TWI313467B - Methods and systems for writing non-volatile memories for increased endurance - Google Patents

Description

1313467 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to a large number of digital data storage systems, more clearly, to the use of memory with limited durability in situations where higher durability levels are required. System and method of body. [Prior Art] The use of non-volatile memory systems (such as 'EEPRC> M memory storage systems or flash memory storage systems) is increasing because these memory systems have a compact physical size and are non-volatile. Memory has the ability to repeatedly reprogram. The compact physical size of the flash memory storage system facilitates the use of such storage systems in increasingly popular devices. Devices that use the flash memory system include, but are not limited to, digital cameras, digital video cameras, digital music players, handheld personal computers, and global positioning devices. The function of repeatedly reprogramming the non-volatile memory contained in the flash memory storage system allows the flash memory storage system to be used and reused. Although non-volatile memory (or more specifically non-volatile memory cells, such as EEPI10M or non-volatile memory cells in flash memory systems) is repeatedly programmed and erased, each A memory cell or entity location can only be erased a certain number of times before it is consumed. In a particular system, a memory cell can be erased up to about 10,000 times before the cell is considered unusable. In other systems, a memory cell can be erased up to about 100,000 times, or even up to one million times, before the "Hai unit is considered to be wasted. When a memory cell is depleted to cause a loss of use or a significant decrease in performance in a segment of the memory volume of the flash memory system 117594.doc 1313467, the user of the beta flash memory system May be negatively affected, for example, 'will lose stored data or can not store data. The loss of memory cells or physical locations within the flash memory system will vary depending on the frequency at which each of the memory cells is programmed. If the right: memory unit, or more generally the system-memory component, is only programmed and then not reprogrammed, then it is related to the memory unit. (4) The consumption is usually very low. If the memory

If the body unit is written and erased repeatedly, then the loss associated with the memory unit is usually very high. When a host (for example, a system that accesses or uses a flash memory system) uses a logical block address (lba) to access data stored in a flash memory system, if a host repeatedly If the same LBA is used to write and rewrite the data, then the same physical location or memory single read in the flash memory system will be written and erased repeatedly, as will be appreciated by those skilled in the art. The existence of a body unit is usually. In addition to the memory 鹘 flash memory system that has been lost and lost, when in a flash memory, the flash memory 遡 memory system still has an effective loss of the segment memory cell. In the case of loss, then the performance of the lossy memory that is involved in the overall performance of the flash memory system is reduced. If the number of elements is insufficient to store the data, the performance may also be affected. Negative impact. Usually, a large number of lost memory cells in the system can be regarded as unusable, even if the flash is more than other memory cells are relatively not worn out. 117594.doc 1313467 (4) Limitations may limit non-volatile properties with similar properties Sexual memory is used in applications where the required financial level exceeds the safe life of the memory. For example, it is often desirable to have a controller in a memory card system in the form of a non-volatile memory for use as a counter to monitor the operation of the system. In this regard, the write or erase/write cycle performed by the non-volatile memory on the controller may be much higher than other memory cells in the memory segment. As a result, if the same record as the memory is used

If the memory technology is formed, then the non-volatile memory on the controller can be quickly depleted, so that the memory system is terminated or limited before the main flash memory segment is worn out. Operation. Further, because any non-volatile memory on the controller can be very small, the tolerance of 'and' for remapping and other defect management techniques for increased lifetime will be lower. Therefore, there is a need for a method for improving the lifetime of non-volatile memory of non-volatile memory with ax. While the evolution of technology has improved the typical durability of these memory components, the further increase in the safe life of such memory has resulted in a number of applications that have benefited. SUMMARY OF THE INVENTION The present invention is directed to a system and method for storing data (e.g., count or scratchpad values) on a non-volatile memory in a manner that increases the durability of a memory technology. The count (or scratchpad value) is encoded into a binary count consisting of several fields. When the count is incremented, only a single stop will change. Depending on the particular embodiment, the field may be a single bit or a larger granularity, such as a one-tuple or a very small write that can access the 117594.doc 1313467 alpha body there. fine. It is possible to access a larger number of bits to access the "hiddenly updated segments will be overwritten m only those that are evenly dispersed by the changes until the complete loss. By - will - knife to the field (For example, write it in a loop (4). If _ such columns (4), each block will only change every N-person increment. Then you can store the blocks in n One of the corresponding groups of non-volatile memory segments that can be individually accessed.

To do this, the given memory segment will only be overwritten every N counts, so the lifetime of the counter will be N times longer than the inherent lifetime of the particular memory technology. For example, an exemplary embodiment would use a set of memory segments having a plurality of individually accessible byte sizes, each byte (or just a segment thereof) being used for the Each block is counted by the code. Another set of specific embodiments uses a one-dimensional access to the EEpR〇M memory. Then the 'count will be encoded in the individually accessible blocks' so that when the count is incremented, the overwriting of the blocks will be evenly spread. This technique can be used in a variety of applications, such as control data maintained in small non-volatile EEPROM memory used to form a controller on a non-volatile memory such as a flash memory card. Counter. This control data may be updated frequently, so it may quickly damage the memory unit compared to the user data stored in the flash memory. Using the techniques of the present invention, the lifetime of the memory used to store this frequently updated material can be extended while still using the same techniques as the memory unit used to store the user data. 117594.doc 1313467 The exemplary embodiment of the present invention is as follows: one: =:=: the declaration, the text, the other patent publications, and all of them are cited by way of all purposes, in the [embodiment]. Α·MEMORY ORGANIZATION AND BASIC DEFINITIONS The present invention relates to increasing durability in a memory genre that may have a reduced performance over time due to an increase in the number of write cycles of P ^ y , ' / , although described herein. The specific embodiments are described as non-volatile (IV) based on non-volatile EEPROM: "But the views of the present invention are still applicable to the easy "loss of any type of storage medium. For example, the novel type of non-swinging technology is phase change memory. By changing the phase t of a given material, it is possible to store the #f signal. Several other examples of such systems are presented in U.S. Patent No. 4 U79. Such systems will still have a "loss of loss". As the number of cycles of the storage medium increases, the ability of the medium to store information will be lower. The present invention can be readily applied to such techniques. In one embodiment, 'fast Non-volatile memory in the flash memory storage system, the memory unit can be repeatedly programmed and erased, (4), each individual unit can only be erased a certain number of times before its loss. When a memory unit is lost The performance associated with the segments in the entire storage volume of the flash memory storage system containing the secret memory cells can be severe: data stored in the segment may be lost 'or it may be a ..., to store the bait in this section. There are several ways to know 117594.doc 10- 1313467: Improve memory life 'eg '(four) " milder, operational values or algorithms (eg smart wipes) In addition to or used in the stylization process, the loss leveling method (for example, as described in the U.S. Patent Application Serial No. 10/686,399, which is incorporated herein by reference) Boundary values (for example, as described in the context of the complete and esoteric (4) No. 5, 532, 962), or in a binary mode to operate multiple levels of quasi-memory (for example, The method is fully incorporated in U.S. Patent No. 6,456,528, which is incorporated herein by reference. Although these and other techniques are capable of <RTI ID=0.0>> A segment is particularly useful in applications where it is required to be frequently overwritten by other memory cells of the memory system formed by the same technique. First, a non-volatile memory device is described with reference to FIG. A general purpose host system such as a Compact Flash memory card. A host or computer system 100 typically includes a system bus 1 〇 4 that allows a microprocessor 1 〇 8, a random access memory (RAM) 112, And the input/output circuits, 116 for communication. It should be understood that the host system 1〇〇 may typically contain other components, for example, display devices and network devices, however, The purpose of the explanation is not shown in the figure. Generally speaking, the host system can capture or store information, including but not limited to: still image information, audio information, and video image information. This information can be captured instantly. And can be transmitted to the host system 100 in a wireless manner. Although the host system 1 may be essentially any system 'however, the host system 100 is usually the following system, for example, a digital camera, a video camera, a cellular communication device, Portable computing device, sound 117594.doc -11 - 1313467 frequency player, or video player. However, it should be understood that the host system 100 can be generally used for storing data or information and full funding. Any system. It can also be a system that only captures data or only collects funds. The system is also a system that can be used to store data, or the host system 100 may be read. The exclusive system of information. For example, host system 100 may be a memory writer configured to write or store only data. Alternatively, host system 100 may also be a device such as a 35-series MP3 player that is typically configured to read or grab material rather than capture data. A non-volatile memory device 12 is configured to interface with the bus bar 104 for storing information. An optional interface circuit block allows non-volatile memory device 120 to communicate with bus 1()4. For example, interface circuit block 130 (e.g., and interface), if present, can be used to mitigate the load on bus bar 104. The non-volatile memory device 12A includes a non-volatile memory 124 and a memory control system 128. In one embodiment, the non-volatile memory device 120 can be implemented on a single wafer or a die or the non-volatile memory device 120 can also be designed on a multi-chip module. Or implemented as multiple discrete components. One of the specific embodiments of a non-volatile memory device 12A will be described in more detail below with reference to FIG. The non-volatile memory device 12" can be substantially any suitable non-volatile memory device', for example, a removable memory card or an embedded subsystem. The non-volatile memory 124 is configured to store data so that the data can be accessed and read as necessary. The process of storing data, reading data, and erasing data with 117594.doc -12-1313467 is generally controlled by memory control system 128. In one embodiment, the memory control system 128 manages the operation of the non-volatile memory 124 to substantially maximize its loss by substantially causing the segments of the non-volatile memory 124 to be substantially equally lost. life.

The non-volatile memory device 12A will generally be described as including a memory control system 128, i.e., a controller. In particular, the non-volatile memory device 120 may include a plurality of discrete wafers to function as the non-volatile memory 124 and the controller 128. For example, although non-volatile memory devices include, but are not limited to, 可 that can be implemented on a discrete wafer

Externally, the controller may also be located on the host system, while - non-volatile cards, CompactFlash cards, MultiMedia cards, and Seeure cards, but other non-volatile memory devices may not be designed to be included in one Controller on discrete wafers. In a specific embodiment in which the non-volatile memory device 12 does not include a discrete memory chip and a controller chip, the memory device 120 is coupled to the host system via a connector or other type of interface. Controller. In any event, the scope of the present invention encompasses all different forms and combinations of memory systems in which loss bit criteria within a memory medium are controlled by a control system. For example, the controller can be implemented in a soft body on the microprocessor of the host system. An example of a non-volatile memory device 12A will now be described in more detail with reference to Figure (4). It should be understood that the embodiment shown in Figure lb contains a single flash memory chip i 24 and a non-volatile memory device 12G of a discrete controller i 28 . The memory 124 may be an array of memory cells 117594.doc - 13-1313467 and a suitable addressing and control circuitry 'on which is formed on a semiconductor substrate by storing two or more charge levels therein Among the individual memory elements of the memory cell, such as cough, one or more data bits are stored in the individual memory cells by dispersing charges among the individual memory elements of the memory cells. A non-volatile flash eraseable stylized read-only memory (EEPR0M) is an example of a common memory type used in such systems. In the particular embodiment described, controller 128 communicates with a host computer or other system using the memory system on a bus 15 for storing data. The busbar 15 is typically a section of the busbar 〇4 of FIG. Control system 128 also controls the operation of memory 124 (which may include a memory cell array 11) for writing data provided by the host, reading the data required by the host, and implementing various internal management functions. To operate the memory 124. Control system 128 may include a general purpose microprocessor or microcontroller with associated memory, various logic circuits, or the like. It usually also contains one or more state machines to control the performance of the routine. The suffix cell array 11 is typically addressed by the control system 128 via the address decoder 丨7. The decoder 17 can apply the correct voltage to the byte and bit line array 11 to program the data into a group of memory cells addressed from the control system 128 to a group of memory cells addressed by the control system 128. The data is read or erased by a group of memory cells addressed by the control system 128. The additional circuitry 19 may include: a data register to temporarily store the data to be read or written; a stylized driver that depends on the data to be programmed into the addressed memory cell group. Control 117594.doc -14- 1313467

The circuitry is applied to the components of the array; and the faces are used to control the sequencing of the various electrical dust and control signals. The support and control circuitry 19 may also include a specific amount of non-volatile memory for counters or other control information. Circuit 19 may also include sense sink A|| and circuitry necessary for reading data from an address memory cell group. The data to be programmed into the array 11 or the data recently read from the array corrections is typically stored in a buffer memory 21 in the control system 128. Control system 128 also often contains various registers for temporarily storing command and status data and similar data. Control system 128 may also include a specific amount of non-volatile memory 25 in which various control data that are desired to be maintained even when power is turned off can be stored. In other cases, control system 128 can maintain any such permanent record in non-volatile memory 124. In a particular embodiment, array u is divided into a plurality of memory cells BLOCKO through N. In the preferred embodiment, a block is a minimum number of memory cells to be erased together. Each block is usually divided into several memory pages, as shown in Figure lb. A memory page is the smallest stylized unit, and one or more user data segments are typically stored in each memory page. A segment is the smallest logical data unit that the host addresses or transmits to/from the non-volatile memory. In a disc drive application, this is typically 5 12 bytes. Specific non-volatile memory allows for segment memory page stylization, where individual bits remaining in the erased state after the first stylization can be programmed in subsequent memory page stylization jobs. Instead of first erasing the memory page. The segment multi-state memory can even stylize the bits that have been programmed into the lower stylized state to a higher state in the subsequent memory page stylization 117594.doc -15· 1313467 job. In these memories, a plurality of sections or even sections can be programmed at different times. However, a memory page will maintain a basic stylized unit; it will be a specific bit that can be masked and later programmed. The invention is applicable to any suitable memory system, regardless of the physical implementation of the units of such erase, read and/or write. As shown in Figure 1b of the specific embodiment, a memory page may contain both user data and management data. The management profile typically contains an error correction code (ECC) calculated from the user profile contained in the memory page, and the ECC may contain specific or all management data. A section 23 of the control system 128 calculates the ECC when the data is to be programmed into the array 11, and also checks the ECC when reading data from the array. The management data may also contain : logical address of the user data, physical address of the memory page and/or block, address mapping information, number of erase cycles experienced by the physical area, block, encrypted information, and/or other statistical information or data. Sections or all management data can be stored in each memory page as shown in Figure lb. Alternatively, the section or all of the management data may be stored in a particular location within each block or even in a separate block from the user profile. A bedding segment is mostly contained in each memory page, however, two or more segments may also constitute a memory page, or a memory page may also be a month t* J in the region #又. For example, U.S. Patent Nos. I. and No. 5,430,859 describe the programming and reading of data in units of chunks, in which a block of memory is a segment. a part of. In a particular S memory system, a sector is contained in a memory page, and a page forms a block. More commonly, in a NAND memory system, one or more segments are contained in each memory page, and 8, 16, or 32 memory pages form a block. In other memory systems, 'blocks are formed by a very large number of memory pages, such as 5 12,

1024, or even more memory pages. The number of blocks is selected to provide the data storage capacity for the memory system. The array 丨丨 is usually divided into sub-arrays (not shown), each of which contains a proportion of the blocks that operate independently of each other to improve when performing various δ mnemonics Parallelism. An example of the use of a multi-sub-array is described in U.S. Patent No. 5,890,192, which is incorporated herein by reference. Β·Writing method for increasing durability As described above, even if there is a technique of increasing the life of EEpR〇M, a flash-form non-volatile memory, the upper life is still limited. This may limit the use of such memory in applications that require the durability of the number of full-replication jobs. In the exemplary embodiment, which can be used to explain the various aspects of the present disclosure, the non-volatile memory 25 on the controller or the branch on the memory 12 can be discussed as having a small (four) volatility retention. - a temporary value, _ = _ used to track the counter of an event on a memory), or 1 where it encodes data. In this regard, its : recall == is updated more frequently. As a result, even if the storage element of the array 11 of the special-purpose 'non-volatile # memory 124 is the same as the technique of 117594.doc 1313467, it still experiences a large number of write/erase cycles and is rapidly depleted. Therefore, even if the array 11 still has a long residual life, it still renders the memory system inoperable. In addition, in this regard, a counter or similar special purpose memory is also relatively small, which may not have much margin to use the special techniques (loss leveling or remapping, etc.) that are often used to extend the usability of the array 11. Lifetime Although the invention is not limited to use in a counter, this is a convenient example for explaining the various aspects of the invention. More broadly, it can be applied to other forms of data, since most of the main points of the section are about re-encoding data in a way that is suitable for encoding data according to Gray code. Therefore, it can be written separately. On the accessible memory segment. For example, the "counter" discussed below may generally be considered only as a register for storing a particular type of material encoded using the techniques, so that the register contains, The "count" is usually only a specific encoded data that is inversely proportional to the sequential increment value of a counter. For example, the register may be storing a difference. Therefore, in addition to storing a set of random numbers for generating a plurality of encryption keys.

In the specific embodiment of the bit) or in the 117594.doc 1313467 兀 field. Because each bit is erased only when it is overwritten, this reduces the change in the numbering of the bits. Exemplary embodiments of the present invention include a single bit accessible specific embodiment and a octet (e.g., a one-tuple) accessible specific embodiment. Which access granularity level is preferred depends on the particular application and considerations (eg, the amount of durability required) (the amount of durability required can exceed the durability of the individual memory cells) The multiple of the level is expressed in terms of X and the technical limitations of the 5 memory cells or array technology used. Single bit access provides a large lifetime magnification; however, such single bit 70 access to non-volatile memory is not commonly used. The reason is that a single bit is not accessible; a complex and f is a large area, which may be a limiting factor. Another way to increase the durability of the counter is to use standard, full-grain non-volatile memory, but only use a few discrete data writes scattered across several modules. However, with twice the improved durability by spreading the counters across two full-capacity modules, even a very limited counter would still require a very large amount of ticks. In a particular point of view, the present invention has a two-dimensional approach to the idea of introducing a new method that utilizes the advantages of the new counting method to allow the use of low-durability non-volatile memory. Indeed, according to one aspect, in a specific embodiment, Ben Yuming: uses non-volatile memory that can be accessed at a small granularity, such as 'has early access, or has more Bit access, but only for meta-memory can be at the same level as this granularity. (IV) Generally speaking, it can be accessed through a larger number of bits, 117594.doc •19- 1313467 The updated segment is only +. The other slices accessed during this process will have the same loss level as the nested segment. The following will discuss -a. - one but multiple bits (example For example, the memory of the '8-bit 存取) access _ may have - a small amount, 256: ::!. For example, 256 bits of το non-volatile memory 25, beans

There are 32 aforementioned 8-bit segments that are individually accessible. According to another point of view, the encoding of the data (here the count) is similar to that of the Gray count, but the encoded count can be spread across multiple of the 8-bit accessible memory fragments. On the snippet, if you use _ one of these snippets, the 'one' given snippet will only be rewritten every second. The typical motivation for Gray code is to reduce power or make data less damaging; although these have always been important considerations, the motivation for this article is to spread the replication more evenly. Thereby, the life of the counter can be increased by a factor of 0. Fig. 2 is a schematic diagram showing an example of the memory used in the present invention. As discussed, this is a small non-volatile memory (NVM 25 in Figure lb) in the controller (128) or may be a state machine (in 19) on the memory (124). The special example in FIG. 2 is a 256-bit memory formed by 32 columns (having corresponding word lines WL1 to WL32) fX and 8 rows (bit lines BL1 to BL8), and the memory shown schematically in the figure. The unit is located at the intersection of the bit line and the word line. For example, the 's memory cells M C1, 8, 215 are located on the word line 1 at the bit line 8. In the exemplary embodiment, the memory cells are EEPROM cells' because the formation of such memory cells can be easily integrated into the flash of the exemplary mass storage memory 11 117594.doc • 20-

1313467 The memory of the flash memory system. More generally, the memory cells can be formed by any of a variety of non-volatile memory technologies, such as those described in U.S. Patent Publication No. US-2005-0251617-A1. Figure 2 shows only the particular selection elements of memory 25, and a more detailed description of such memory structures can be found in the various patents and other documents described herein. The features shown in the figure include row circuit 210 and column circuit 220 for reading, writing, erasing, and generally decoding each memory cell address to access the array. In this non-standard embodiment, four columns (e.g., wu to WL4) are dedicated to the counter, and the remaining segments of memory 25 are available to the controller for use as discrete counters or for other purposes. In a specific embodiment of a multi-bit write segment, the '4-writer segments can be composed of-columns. Therefore, each of the first four columns can be stored on the plurality of individual counts. Access the K group in the byte. In a single-bit write segment, in a particular embodiment, each memory cell can be individually overwritten. The encoding of the count is the same as the Gray counter, but it is not exactly the same. The conventional Gray counter is not used in the present invention because the 'minimum significance byte' does not need to be overwritten when performing a large segment counter update. For example, in an 8-bit counter or higher counter i, only the other-bit tuple is updated on the 256th count. Because &, the entire counter is only slightly energized for a long time to spread the writer on the non-volatile memory unit, and a new counting method will be used. This (4) is only possible not to rewrite each byte too often. This article will make use of

An example of a counter to explain the concept, 117594.doc 1313467

One of the two bits in the bit is retained in one of the individually accessible multi-bit accessible memory segments ("ws" or "write segment #1") Medium, and the other two bits are kept in the other ("WS α"). The granularity of the memory access, or the size of the written fragments, can be The two bits used in ; or it may be larger (for example, a byte) 'However, only two bits in each tuple are used here. Whenever __ When writing a human fragment, only two bytes are used to store the count. This example can be easily extended to a 16-bit counter, and this 4-bit paradigm is used to simplify the explanation. And only the value of the last two digits of each 7L group is displayed. The equivalent count of the byte of the 4-bit counter of the non-standard embodiment (the encoded 4-bit count) and the corresponding Write as follows: Equivalent count value is encoded by 4-bit count

#0 # 1 #2 #3 #4 #5 #6 #7 #8 #9 0000 0001 0101 0110 1010 1011 1111 1101 1001 1000 Write order of counts (value on reset) Write to WS#1 : 01 Write To WS#2 : 01 Write to WS#1 : 10 Write to WS#2 : 10 Write to WS#1 : 11 Write to WS#2 : 11 Write to WS#1 : 01 Write to WS#2 : 10 Write to WS#1 : 00 117594.doc -22- 1313467 Write to WS#2 : 01 Write to WS#1 : 11 Write to WS#2 : 00 Write to WS#1 : 10 Write to WS#2 : 11 Write to WS #1 : 00 The count of this coded

In the case of τ, the first two elements are stored in the value written in the fragment #1, and the latter two bits are stored in the value written in the fragment #2. It can be seen that all of the 16 possible counter states (here) have been smashed, but the order of the conventional counts has changed 'causing each helmet + Α 7 甘> U. Only one write segment will change when the number of turns is reached.

#10 0100 #11 0111 #12 0011 #13 0010 # 14 1110 #15 1100 So 'this is a known type of Gray's expansion type, but it is used in different applications and will be configured for each Only one first pair or second pair of bits in a count will change in an alternating manner. It is assumed in this example that each of the two bytes can be erased separately, and only the bytes to be updated/written before each write are erased. In this way, by shifting the write between the write segment #1 and the write segment #2, a memory having half the necessary durability can be used; that is, the durability is doubled. For example, a non-volatile delta-resonance with 50K safety durability can be used in applications requiring 1 〇〇K reliable counts. Similarly, for a pair of 32-bit counters, by using four segments with 8-bit το access, only one quarter of the necessary durability can be used; or, in other words, the lifetime will increase. Four times. (For example, - 117594.doc -23- 1313467 Non-volatile memory with 25K write endurance can be used for the expected maximum total value of 100K writes) In the case of 32-bit, for the front For a number of counts, the equivalent count of the three-bit counter of the 32-bit counter that can be individually accessed (the encoded 32-bit count) and the corresponding write are as follows: Encoded 32 Bit equivalent count value count (hexadecimal) Count write order #0 0000 0000 # 1 0000 0001 Write to byte #1 : 0000 0001 #2 0000 0101 Write to byte #2 : 00000001 #3 0001 0101 Write to byte #3 : 0000 0001 #4 0101 0101 Write to byte #4 : 0000 0001 #5 0101 0102 _ -3 Ο . . . . Write to byte # 1 : 0000 0010 For an equivalent count with (232-1), the process is performed in the same way as the above 4-bit counter example, until all combinations of the 32-bit bits are used, and such Each of the four bytes is equally accessed. As a result, the durability of the memory is increased by four times. The access sequence shown in this table is cyclic. More generally, other sequences can be used to evenly distribute the replications across the different fields, and the looping sequence is merely a simple implementation. For example, the access sequence of the write segments, the write order within each write segment, or both may use a balanced Gray code of the type described below. The above can be further extended to increase the durability of a memory. Use the 32-bit counter as an example to explore the need to increase life expectancy by more than four times; or, as a technique that is less durable than the 117594.doc -24-1313467, which is less durable than the counter, . For example, according to the following algorithm, for a total of 96-bit non-volatile memory to explore the use of three 32-bit accessible fields, one byte can be accessed at a time: 1) Suppose there are three blocks #1, #2, and #3, each field is formed by a 32-bit counter. The 32-bit counter has four individual access bits as used above. Tuple. 2) The writers are numbered for the lowest value from the three counters

The 'lower block number has priority (if both blocks have the same value). The reading of the highest value of these three counters 3) must be done from time to time. 4) The counting method for each block is the same as above. Each write job will be performed on all (four) of the < tuples in the positioning tuple. So, this situation + number of writes) / 12. The necessary durability will be (, 纟 = 'for example' - has the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ · 5 brothers, the counter can be γ, +, &" ^, state is described by several (one) phantom access, copy of the non-volatile record. ° hidden body section Or "write a piece, month. In the example of shai, etc., each can be a ^ + ! - -, each of the individual access write segments are named a group of bits. Then, count,

Am Jsb jj. $ is exhausted into a corresponding j-block, in which, when counting the number of Tai, the N fields will be updated in a knife-like manner; that is, in the presence of /, 匕With the same H7594.doc -25-1313467, one of the blocks will not be overwritten a second time. Since the object of the present invention is to increase the durability by reducing the number of times of rewriting, as described below with respect to the specific embodiments, the rewriting is not necessarily completely uniform, but only a substantially uniform sentence. Disperse; that is, in the specific embodiment of the _ ^, the update of the blocks only requires a substantially uniform splitting, which results in a significant reduction in the number of times of copying 5 or a number of registers. Yes, ', alpha fruit, when the count is incremented, the N memory segments are evenly and repeatedly rewritten. This will maximize this durability and increase it by a factor of N. In the example of a 4-bit counter, 'this count will protect the bits (each from each write g-age, Gan + break)' where each of these 2-bit fields corresponds to the two Among the ones written in the fragment. For a 32-bit counter, four 8-bit blocks are used, corresponding to bits #1 through #4 in this example. Coding in this way, the count will only change a single block in the n field... and thus change its corresponding individually accessible segment in the memory... and its implementation will cause the bit to be The access of the group is uniformly dispersed. This will reduce the loss rate to 1/N. Although other configurations may be used, 'all of these exemplary embodiments assign the same number of bits to the parent one (4 bit count φ ancient a μ ^ state with two two bits) Bits, there are four in the 32-bit S-number device, and the number is a multiple of the number of memory segments. Figure 3 is a schematic illustration of a particular point of view of a particular embodiment of a particular embodiment using a plurality of multi-bit write breaks having a loop left and right side access pattern. As shown in this figure, the -count (4) is encoded as a hard-to-element count scattered over the two blocks, which is such that the count is incremented by 117594.doc • 26 · 1313467 (or decremented) each time the count is incremented. Only the single-barrier will be changed. (This is different from the standard Gray code. In the standard Gray code, each time the count is incremented, only the single-bit' is changed, but it usually falls within the same field as when the count collapses.) Each of these counting blocks will be stored in the corresponding area & (here, byte #1 to fine) of nvm(4). When the count is incremented, 'bytes #1 to Saki will be overwritten according to the new values they correspond to in the cyclic sequence shown in the figure. Although the arrows in the figure only show when the meter

How to encode and write the count when the number is incremented, and reading the count is basically the reverse process. It should be noted that Fig. 3 merely explains a particular embodiment (having a plurality of snippet segments with % access) and the actual implementation can be changed. For example, the bytes #1 to (the count block will be entered into the figure) shown in the figure are placed next to the (4) NVM 25 or placed in sequence, but it is not necessary. And can usually be configured in other ways. In addition, all of the blocks are not necessarily the same size, and are not necessarily written in the cyclic order of the (four) embodiment, however, = is the simplest way and will optimize the life of the counter. In the specific embodiment of the gossip, as shown in Fig. 3, for example, the first one access, the balanced gray code and the body embodiment, the corresponding change is made to Fig. 3. Next, a specific embodiment with single-bit access will be proposed. As mentioned above, it is not commonly used to 'but' a single bit access but provides a larger: life magnification. In this example, the memory (eg, NVM25 units can be individually accessed and overwritten. In this exemplary implementation, the same PROP unit will be used, but as mentioned above, also 117594.doc • 27-1313467 can be used The gossip-dual stealth technique described in US Patent Publication No. US-2005-025 161 7-A1, because this example allows the writes to be dispersed at a finer granularity as the count is incremented. The lifetime will be increased accordingly. For example, in the case of the 32-bit counter of Figure 2, only - (or sometimes two) bits are overwritten for each increment of the counter and the other bits remain unchanged. If you live, the life will increase - the level of amplification. As mentioned above, the encoding of the count is slightly the same as the 袼 code;

However, in the Gray code, the target is injured __ ▲ know that there will be only a minimum number of bit changes when the 垓 count is incremented. This can enchant $Pa, and the encoded data is less prone to errors, and there is minimal power consumption when writing the capital name ^, ft, ^ n A #枓 in this order; however, the present invention In other words, it is not α. . , , a . ^ ^ M糸攱佳, because the goal here is to minimize and equalize every bit example to read, and reduce the loss. Bottom: ^ For the number of devices, the standard Gray code such as the equivalent count #〇#1 #2 #3 #4 #5 #6 #7 #8 ^The Gray code 0000 0001 0011 0010 0110 0111 0101 0100 1100 117594.doc -28- 1313467 #9 1101 #10 1111 #11 1110 #12 1010 #13 1011 #14 1001 #15 1000 It can be seen that the smallest meaning bit (bit 〇) changes every other write. Or it will change 23 = 8 times, and the number of writes per bit on the left will be halved: bit 1 will change 4 times, bit 2 will be 2 times, and bit 3 will be 1 time. More generally, for a η-bit counter, the least significant bit will change by 2 (η·υ, and the largest significant bit will only change once, compared to LSB, which changes 2η-1 The standard binary count of the second, this practice is only slightly improved (about 2 times improvement). This is different from the purpose of the present invention. Instead, the following will discuss the more uniform distribution of these changes: Equivalent counts are evenly dispersed Change #0 0000 #1 0001 #2 0011 #3 0111 #4 0110 #5 1110 #6 0010 117594.doc -29- #71313467 #8 #9 #10 #11 loio 1000 0101 〇1〇〇1100 #12 #13 #14

Π〇ιHU l〇ll 1001

In this case, 'every increment is only one bit (the formula β & 4 months, only two digits) will change, where bits 0 and 3 will be revamped /, and then Bits 1 and 2 are overwritten four times (including from 15 to 0). This gs _ , .", and the code is only one of many examples that can be used, where the number of columns that are changed each time the person can be incremented is minimized. (The minimum meaning here is that we are as much as possible compared to the conventional implementation. 4 may not necessarily be the absolute minimum that can be achieved.) More generally, 'others can be used. Code, or balanced Gray code. (This balanced Gray code is developed in Gs. Bhat and CD. The Electr〇nic J〇urnal 〇f c(10)3 (1996) '#R25, published on pages 1 to 11, in the US patent case A special example of a circular Gray code is proposed in No. 2, 632, 〇 58. It is used in a special example of using a single-bit write unit and using equal or balanced access. The 32-bit counter of Figure 2, the Dongzimu/, with a memory technology of 15 K times, provides a safe count value of 117594.doc -30· 1313467 about 15 Κχ 32 = 480 K times. (The actual values will be slightly lower 'because some increments may change to two bits.) Another alternative way is to 'if the system requires 1 ο 的 guarantee of safe counting By using a 17-bit counter, the memory cells will reach these memory cells and will be safely required within approximately 130 Κ/17=~7.6 '. 'Completely match each memory cell 丨5 κ times of safe copying times. As with the multi-bit access specific embodiment, by uniformly distributing the overwrites on the write units, a single bit embodiment can achieve a non-volatile durability with a known number of repetitions. The memory is used in a counter with a high increase in durability. Therefore, the present invention is to be construed as illustrative and not restrictive, and the invention is not limited to the details disclosed herein, and may be modified within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be more fully understood from the following description, in which: FIG. 1a is a schematic representation of a general-purpose host system including a non-volatile memory device. Figure 1 is a schematic representation of a "memory system", for example, the memory device 120 of Figure u. Figure 2 is a block diagram of a particular element in an exemplary non-volatile memory. Figure 3 is a schematic diagram of a particular principal aspect of one of the main embodiments. [Key element symbol description] 11 Memory cell array 15 bus 117594.doc •31 - 1313467

17 address decoder 19 support and control circuit 21 buffer memory 23 ECC sector 25 non-volatile memory 100 host system 104 bus 108 microprocessor 112 random access memory 116 input / output circuit 120 non-volatile Memory device 124 Non-volatile memory 128 Memory control system 130 Interface circuit block 210 Row circuit 215 Memory unit 220 Column circuit BL1 Bit line BL2 Bit line BL3 Bit line BL4 Bit line BL5 Bit line BL6 Bit Line BL7 Bit Line 117594.doc -32- 1313467 BL8 Bit Line WL1 Word Line WL2 Word Line WL3 Word Line WL4 Word Line WL32 Word Line

117594.doc •33

Claims (1)

Patent application No. d [Chinese patent application scope replacement (April 1998) - '10, patent application scope·· A method for storing a value in a memory system comprising a plurality of N individually accessible segments consisting of a plurality of erasable and reprogrammed non-volatile memory cells, comprising: The edge value is encoded into a binary value consisting of ^^ blocks, so that for the parent to increment, the value only changes the single block in the block, and when the value is incremented, The changes of the N fields are substantially evenly dispersed among the N fields; and when the value is incremented, the changes of the single block in the N blocks are stored in the N areas. Among the corresponding segments in the segment, the other of the N interceptors remain unchanged. 2. The method of claim 1, wherein when the value is incremented, the changes of the n blocks are cyclically dispersed among the N blocks. 3. The method of claiming, wherein each of the individually accessible segments has a storage capacity of one byte. The method of claim 1, wherein the storing comprises storing the blocks in binary form in the memory cells of the segments. 5. The method of printing the item, wherein each of the blocks has the same number of bits. 6. The method of claim ,, where the value is a Μ bit value, where μ is a multiple of Ν. 7. The method of claim 1, wherein the memory system comprises a controller portion and a memory portion, and the individually accessible segments are formed in the control 117594-980417.doc 1313467, such as 4 item 7 The party, - the event. The value of 4 in the 对应 corresponds to the 9. on the memory. The method of the item 1 is where the 与 掊 掊 ” ” ” ” ” ” ” ” ” ” ” ” Take a section of the state machine above the body. (4) Becoming (4) 10. If the request item 1 s, the land ^ broadcasts the crypto cell units of the EEPROM memory cells in which the individually accessible segments are located. ° I slice H - a method in a memory system having a plurality of individually accessible, replicable fragments, comprising: incrementing a register value; encoding the register value into a complex number Each binary position, such as a binary position, corresponds to one of the four (48) individually accessible and rewritable fragments;; = the fragment 'where' the code will cause #. The register value will be incremented = every count will change The number of blocks, and the changes in the fields are substantially evenly dispersed; and the increment register value is overwritten in the segment where the individual booth values have changed. 12. The method of claim u, wherein the programming mother uses a method of balancing alpha, such as claim η, wherein each of the individually readable and rewritable segments is comprised of a plurality of memory cells. 14. The method of claim 13, wherein when the register value is incremented, the changes in the ones of the blocks are cyclically dispersed among the fields. 15. The method of claim 3, wherein each of the individual accesses: the rewritable fragment contains a storage capacity of a byte. 117594-980417.doc 1313467. The method of claim 11, wherein N is greater than or equal to three, and ― is individually readable, rewritable, and parental. If you have a method of claim 16, the method in claim 18 uses the balanced gray #. If the method of U is not selected, it should be a code. One, each of the individually stored segments has the same number of bits. 19. The method of claim 11, wherein the register value _ where Μ is a multiple of N. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> The formation of a beer system 21 • The method of claim 2, wherein the event is continued. The value of the temporary storage value corresponds to the memory 22. The method of claim (4), wherein the memory system includes a control and a memory portion, and the plurality of memory segments can be formed. Is a segment of a state machine above the memory portion. 23. The method of claim U, wherein the individual pbPPDDA has an individual access, and the rewritable fragment is composed of an EEPROM memory unit. 24. A memory system comprising: a plurality of erasable and reprogrammable non-evaluation. a plurality of N individually accessible segments consisting of the first το; the second register 'which encodes the value into a number 2 consisting of the closing bits,' causes each value of the value to be incremented Only the early-field of the seats will be changed, and when the value is incremented, the changes of the N-blocks will be substantially evenly distributed among the N fields. And a replication circuit connectable to the individually accessible segments and for receiving the encoded register values, whereby the encoded register value changes as the value is incremented The one-block in the (10) field in the corresponding section of the two sections will be stored while leaving the other of the N intercepts unchanged. For example, the memory system of claim 24, wherein when the value is incremented, the server cyclically spreads the changes of the one of the blocks in the ν blocks. 26. The memory system of claim 24, wherein each of said individually accessible segments comprises a byte of storage capability. 27. The memory system of claim 24, wherein the encoded counts are stored in the fields of the memory cells of the segments in a binary form. 8. As claimed in claim 24, each of the blocks has &gt; the same number of bits. For example, the delta-recall system of claim 24, wherein the value is a multi-counter count 'where Μ is a multiple of Ν. The monthly memory system of the month member 24, wherein the memory system includes a control unit and a memory unit and the individually accessible sections are formed on the controller. 31. If the clarification of the item is ambiguous, the value corresponds to an event on the memory. For example, the δ hexa memory system of claim 24, wherein the memory system includes a control portion 117594-980417.doc 1313467 a profit portion and a memory portion, and the individually accessible segments are formed into the memory A section of a state machine above the department. The memory system of claim 24 is such that the memory cells of the individually accessible segments are EEPR0M memory cells. 34. A memory system comprising: a plurality of N individually accessible, rewritable non-volatile segments, a register, the register comprising: - a logic circuit for encoding a value into a plurality N binary intercepts, each of which corresponds to the - individual fragment of the individually readable, rewritable fragments, wherein the encoding causes the value to be incremented to minimize the value every time - The number of blocks that are changed in increment, and the changes in the booths are substantially evenly dispersed; and, the writes are connectable to the biasable access, rewritable segments, and are received from the The encoded register values of the register 'by this, the changes in the programmed register values are stored in the segments in which the individual block values have changed. 35. The memory system of claim 34, wherein the access order of the blocks is encoded according to a balanced Gray code. A: The memory system of item 34, wherein each of the individually rewritable segments is composed of a plurality of memory cells. 37. The memory system of claim 36 wherein the changes in the N blocks are cyclically dispersed among the n blocks as the value is incremented. 〆 I: Clear: The memory system of item 36, wherein each of the individually readable and rewritable fragments contains a storage capacity of one byte. 117594-980417.doc 1313467 39. The memory system of claim 34, wherein N is greater than or equal to three, and each of the individually accessible and one-replicated fragments is composed of a single memory. . 4. The memory system of item 39, wherein the count values are encoded in accordance with a balanced Gray code. 41. In the memory system of claim 34, ― ', first, one of the mothers can be individually stored, and the rewritable fragments have the same number of bits. 42. The memory system of claim 34, wherein the temporary value of the temporary value is - a value of 70, where Μ is a multiple of Ν. 43. The memory system of claim 34, wherein the memory system includes a control and a memory portion and the plurality of individually accessible, reconfigurable forms are formed on the controller. 44. An event on the body of the memory system of claim 43. , , the temporary storage &quot; corresponds to the memory For example, in the memory system of claim 34, wherein the memory system is a thief and a memory portion, and the individually accessible and steerable controls are formed as one of a state machine above the memory portion. Section. Write a fragment 6. A memory system such as the β-item 34, wherein the individual access ports and the write segments are composed of EEPROM memory cells. Recoverable 117594-980417.doc