1311283 九、發明說明： 【發明所屬之技術領域】 本發明係一種多訊號源共用訊號輸入電路，尤其係一種多訊號源共用的 訊號輸入電路。 【先前技術】 電子産品中，往往出現要求多種輸入産生相同效果的情況。此時，該多 種輸入由複數不同的訊號源産生，並共同經由一訊號輸入電路連接至同—處 理裝置的同一中斷訊號輸入介面。處理裝置從該中斷訊號輸入介面接收中斷 輸入後即執行預定的處理程式。習知技術中，利用鍵盤滑鼠等輸入裝置將電 子産品（例如電腦）從睡眠模式喚醒即爲一典型例子。 習知技術中，雖存在有利用複數門電路與開關電路來使複數訊號源的輸 出産生同樣中斷效果的例子，但其電路結構較複雜。 【發明内容】 有鑒於此，提供一多訊號源共用訊號輸入電路，其利用一三態緩衝器根 據多訊號源輸出的訊號產生一中斷訊號，並利用該中斷訊號執行預定的操作。 有鑒於此，還提供一種多訊號源共用喚醒訊號輸入電路，其利用一三態 緩衝器根據多訊號源輸出的訊號産生一喚醒訊號，並另用該唤醒訊號喚醒處 於睡眠狀態中的電子部件。 一種多訊號源共用訊號輸入電路，包括複數訊號源，每一訊號源具有至 少一類輸出訊號，與一處理早元，具有複數訊號輸入介面與至少·—個中斷輸 入介面’所述複數訊號輸入介面中每一訊號輸入介面連接一個或複數訊號 源。其中，所述多訊號源共用訊號輸入電路還包括一三態緩衝器，所述三態 缓衝器具有一使能控制端、複數輸入口及與複數輸入口相對應的複數輸出 口；所述使能控制端接收一使能控制訊號；所述複數輸入口中每一輸入口連 接所述一個或複數訊號源；及所述複數輸出口共同連接至所述處理單元的中 斷輸入介面。 在所述使能控制訊號的控制下，所述訊號源輸出訊號至三態緩衝器的輸 入口時，所述三態緩衝器的輸出口輸出一中斷訊號至所述處理單元的中斷輸 1311283 入介面，所述處理單元根據所述中斷訊號執行中斷處理。 一種多訊號源共用唤醒訊號輸入電路，包括：複數訊號源，每一訊號源 具有至少一類輸出訊號；與一處理單元，具有一喚醒模組、複數訊號輸入介 面與至少一個喚醒訊號輸入介面，所述複數訊號輸入介面中每一訊號輸入介 面連接一個或複數訊號源，所述喚醒模組根據所述喚醒訊號輸入介面輸入的 喚醒訊號執行喚醒操作。其中，所述多訊號源共用喚醒訊號輸入電路還包括： 一三態缓衝器，所述三態緩衝器具有一使能控制端、複數輸入口及與複數輸 入口相對應的複數輸出口；所述使能控制端接收一使能控制訊號；所述複數 輸入口中每一輸入口連接所述一個或複數訊號源；及所述複數輸出口共同連 接至所述處理單元的喚醒訊號輸入介面。 所述訊號源包括按鍵輸入電路、滑鼠輸入電路。 在所述使能控制訊號的控制下’所述訊號源輸出輸出訊號至三態緩衝器 的輸入口時，所述二態緩衝器的輸出口輸出一喚醒訊號至所述處理單元的喚 醒訊號輸入介面，所述處理單元的喚醒模組根據所述中斷訊號執行喚醒操作。 所提供的多訊號源共用訊號輸入電路與多訊號源共用嗔醒訊號輸入電路 具有簡單清晰的電路結構。 【實施方式】 請參閱第一圖，係多訊號源共用訊號輸入電路一具體實施方式的電路框 圖。第一圖中，一訊號源組20分別與一處理單元10 (如cpu)及一三熊緩 衝器30連接，以發送訊號至處理單元10與三態緩衝器3〇中。該訊號g組 20包括複數訊號源（未圖示），每一訊號源具有至少一類訊號輸出。處^單 元10具有複數訊號輸入介面（Ιη) η與至少一個中斷輸入介面（Inte^ret) 12。其中該複數訊號輸入介面u中每一訊號輸入介面分別與訊號源組2〇中 的一個或複數訊號源相連’該中斷輸入介面12與三態緩衝器3〇的"輸出相連。 該二態緩衝器30亦具有複數輸入口（Al~An) 31與複數輪出口 32。該複數輸入口 31中每一輸入口分別連接訊號源組2〇中—個 % 源’複數輸出口 32分別經由一單向導通部件（如第一圖所示的二極體 連接至處理單元10的中斷輸入介面12。此外，三態緩衝器3〇輪出口 = ，單向導通部件後還經由—阻性元件（如第一圖所示的電阻R)連接至、、5 壓源vDD。三態緩衝器30的使能控制端（G)33連接至一控制裝置（未圖示)電 1311283 _ l ' ·_ · 以從該控制裝置處接收低電平訊號的控制’從而使該三態緩衝器3〇處於正常 工作狀態。在本實施方式中，當三態緩衝器30處於正常工作狀態下時，若訊 ， 號源組20處有訊號輸出，則三態缓衝器30接收該訊號後與其後續電路（單 向導通部件、電壓源Vdd以及阻性元件的組合）産生一中斷訊號輸出至處理 單元10的中斷訊號輸入介面12。處理單元1〇根據該中斷訊號執行預定的操 作。 請參閱第二圖，係第一圖所示多訊號源共用訊號輸入電路一具體應用圖。 其中所述具體應用例舉爲根據按鍵訊號喚醒處於睡眠模式中的電腦系統的情 形。在該具體應用中，訊號源組20具體化爲一按鍵電路2〇〇 (包括鍵盤電路 與/或滑鼠電路），處理單元10具體化爲一 CPU 100。其中CPU 100内包含有 鲁 一唤醒模組130 ’在接收到從中斷訊號輸入介面120輸入的中斷訊號（此處 根據其功能稱呼爲“喚醒訊號”）後，CPU 100利用該喚醒模組130喚醒處 於睡眠狀態的自身與其他部件，以恢復至正常工作狀態。在電腦系統進入睡 眠狀態後，用戶需重新使用該電腦系統時，其可經由按鍵電路2〇〇發送按鍵 訊號，該按鍵訊號一方面經由CPU 100上的訊號輸入介面（In) 110輸入至 CPU100,另一方面經由三態緩衝器3〇與其後續電路産生一喚醒訊號輸出至 中斷訊號輸入介面120。CPU 100讀取該喚醒訊號後即喚醒該電腦系統，使 其進入正常使用狀態。 综上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上 • 所述者僅為本創作之較佳實施例，舉凡熟悉本案技藝之人士，在爰依本發明 精神所作之等效修飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 第一圖係多訊號源共用訊號輸入電路一具體實施方式的電路框圖。 第一圖係第一圖所示多訊號源共用訊號輸入電路一具體應用圖。 【主要元件符號說明】 11、 110 處理單元 訊號源組 三態緩衝器 5凡號輸入介面 8 1311283 中斷訊號輸入介面 12、 120 輸入口 31 輸出口 32 使能控制端 33 CPU 100 喚醒模組 130 按鍵電路 200 電壓源 Vdd 二極體 Dl~Dn1311283 IX. Description of the Invention: [Technical Field] The present invention relates to a multi-signal source shared signal input circuit, and more particularly to a signal input circuit shared by a multi-signal source. [Prior Art] In electronic products, there are often cases where multiple inputs are required to produce the same effect. At this time, the plurality of inputs are generated by a plurality of different signal sources, and are commonly connected to the same interrupt signal input interface of the same processing device via a signal input circuit. The processing device executes the predetermined processing program after receiving the interrupt input from the interrupt signal input interface. In the prior art, waking up an electronic product (e.g., a computer) from a sleep mode using an input device such as a keyboard mouse is a typical example. In the prior art, although there are examples in which a plurality of gate circuits and switching circuits are used to cause the same interrupt effect to be outputted from a plurality of signal sources, the circuit configuration is complicated. SUMMARY OF THE INVENTION In view of the above, a multi-signal source shared signal input circuit is provided, which uses a tri-state buffer to generate an interrupt signal according to a signal output from a multi-signal source, and uses the interrupt signal to perform a predetermined operation. In view of this, a multi-signal source shared wake-up signal input circuit is further provided, which uses a tri-state buffer to generate a wake-up signal according to the signal output from the multi-signal source, and additionally uses the wake-up signal to wake up the electronic component in the sleep state. A multi-signal source shared signal input circuit includes a plurality of signal sources, each signal source having at least one type of output signal, and a processing early element having a complex signal input interface and at least one interrupt input interface 'the complex signal input interface Each signal input interface is connected to one or a plurality of signal sources. The multi-signal source shared signal input circuit further includes a tri-state buffer, the tri-state buffer having an enable control end, a plurality of input ports, and a plurality of output ports corresponding to the plurality of input ports; The control terminal receives an enable control signal; each of the plurality of input ports is connected to the one or more signal sources; and the plurality of output ports are commonly connected to the interrupt input interface of the processing unit. Under the control of the enable control signal, when the signal source outputs a signal to the input port of the tristate buffer, the output port of the tristate buffer outputs an interrupt signal to the interrupt input of the processing unit 1311283. The processing unit performs an interrupt process according to the interrupt signal. A multi-signal source sharing wake-up signal input circuit includes: a plurality of signal sources each having at least one type of output signal; and a processing unit having a wake-up module, a complex signal input interface, and at least one wake-up signal input interface Each of the signal input interfaces of the plurality of signal input interfaces is connected to one or a plurality of signal sources, and the wake-up module performs a wake-up operation according to the wake-up signal input by the wake-up signal input interface. The multi-signal source shared wake-up signal input circuit further includes: a tri-state buffer, the tri-state buffer having an enable control end, a plurality of input ports, and a plurality of output ports corresponding to the plurality of input ports; The enable control terminal receives an enable control signal; each input port of the plurality of input ports is connected to the one or more signal sources; and the plurality of output ports are commonly connected to the wake-up signal input interface of the processing unit. The signal source includes a key input circuit and a mouse input circuit. When the signal source outputs an output signal to the input port of the tristate buffer under the control of the enable control signal, the output port of the binary buffer outputs a wake-up signal to the wake-up signal input of the processing unit. The wake-up module of the processing unit performs a wake-up operation according to the interrupt signal. The multi-signal source shared signal input circuit and the multi-signal source are provided to share the wake-up signal input circuit with a simple and clear circuit structure. [Embodiment] Please refer to the first figure, which is a circuit block diagram of a specific embodiment of a multi-signal source shared signal input circuit. In the first figure, a signal source group 20 is connected to a processing unit 10 (e.g., cpu) and a three-branch buffer 30 to transmit signals to the processing unit 10 and the tristate buffer 3. The signal g group 20 includes a plurality of signal sources (not shown), each of which has at least one type of signal output. The unit 10 has a complex signal input interface (?n) η and at least one interrupt input interface (Inte^ret) 12. Each of the signal input interfaces of the plurality of signal input interfaces u is respectively connected to one or a plurality of signal sources of the signal source group 2'. The interrupt input interface 12 is connected to the " output of the tristate buffer 3'. The binary buffer 30 also has a plurality of input ports (Al~An) 31 and a plurality of wheel outlets 32. Each input port of the plurality of input ports 31 is respectively connected to the signal source group 2 — - % source 'the plurality of output ports 32 are respectively connected to the processing unit 10 via a single-conducting component (such as the diode shown in the first figure) Interrupt input interface 12. In addition, tristate buffer 3 〇 wheel outlet =, after the unidirectional conduction component is also connected to the , 5 voltage source vDD via a resistive component (such as the resistor R shown in the first figure). The enable control terminal (G) 33 of the state buffer 30 is connected to a control device (not shown) for the power 1311283 _ l ' · _ · to receive the control of the low level signal from the control device to make the tristate The buffer 3 is in a normal working state. In the present embodiment, when the tristate buffer 30 is in a normal working state, if the signal source is output at the source group 20, the tristate buffer 30 receives the signal. Then, an interrupt signal is outputted to the interrupt signal input interface 12 of the processing unit 10 by the subsequent circuit (the combination of the single-pass component, the voltage source Vdd, and the resistive component). The processing unit 1 performs a predetermined operation according to the interrupt signal. See the second picture, the first A specific application diagram of the multi-signal source shared signal input circuit is shown in the figure. The specific application example is a case of waking up a computer system in a sleep mode according to a button signal. In this specific application, the signal source group 20 is embodied as A button circuit 2 (including a keyboard circuit and/or a mouse circuit), the processing unit 10 is embodied as a CPU 100. The CPU 100 includes a Luyi wake-up module 130' receiving the slave interrupt signal input interface 120. After the input interrupt signal (herein referred to as "wake-up signal" according to its function), the CPU 100 uses the wake-up module 130 to wake up the sleeping self and other components to return to the normal working state. The computer system enters the sleep state. After the user needs to re-use the computer system, the button signal can be sent via the button circuit 2, and the button signal is input to the CPU 100 via the signal input interface (In) 110 on the CPU 100, and via the three states. The buffer 3 and its subsequent circuits generate a wake-up signal output to the interrupt signal input interface 120. The CPU 100 reads the wake-up signal and then calls Wake up the computer system and put it into normal use. In summary, the present invention complies with the invention patent requirements, and patents are filed according to law. However, the above is only a preferred embodiment of the present creation, and is familiar with the case. The equivalent modifications or variations made by the skilled person in the spirit of the present invention should be covered by the following patent application. [Simplified description of the drawings] The first figure is a multi-signal source shared signal input circuit. The first diagram is a specific application diagram of the multi-signal source shared signal input circuit shown in the first figure. [Main component symbol description] 11, 110 processing unit signal source group tristate buffer 5 number input interface 8 1311283 Interrupt signal input interface 12, 120 Input port 31 Output port 32 Enable control terminal 33 CPU 100 Wake-up module 130 Key circuit 200 Voltage source Vdd Dipole D1~Dn