200815973 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電源啟動電路，特別是指一種應 用於ATCA系統之CPU電源啟動控制電路。 ‘ 【先前技術】 • PICMG(全球工業電腦製造組織）訂定一個滿足高呑吐量 及高可靠性的電腦平台標準，並發佈了 PICMG3.0規範—先 進的通訊電腦架構（ATCA)。根據PICMG3.0規範，每個 馨 ATCA系統之前板（front board)的耗電量必須小於200W，輸 入電壓範圍須在-36V到-72V之間。因此，降低前板之處理 器電源消耗和電源管理成為系統設計時主要考量問題之一。 如圖1所示，是習知一種ATCA系統之前板的電源管 理機制，前板（電路板）11具有雙CPU(下稱CPU0及CPU1) ，且根據ATCA Zonel電源連接器的時序，當前板u經由 Zonel電源連接器（圖未示）與系統之機箱12連接時，來自 系統機箱的-48V電源電壓P48V經由Zonel電源連接器（圖 ® 未示）輸入前板11之一電壓轉換單元13中，由電壓轉換單 ’ 元13根據電路元件適用之電源，進行適當的電壓降壓轉換 ，以產生多種不同電壓源輸出，並輸出一電源正常通知訊號 VTT一PG00D給控制CPU電源啟動的一可程式邏輯電路 (FPGA 或 CPLD)14 〇 可程式邏輯電路14其透過内部之邏輯電路偵測來自兩 個CPU的第一滙流排選擇訊號cPUO_BSELO_3P3及 CPU1JBSEL0 一 3P3 ，及第二滙流排選擇訊號 200815973 CPUOJBSEL1—3P3 及 CPU1-BSEL1—3P3，並根據訊號 CPU1—SKTOCC_N決定是否分別輸出致能訊號VRDO JEN及 VRD1—EN給後端的兩個電壓調整器15、16，使根據致能訊 號VRD0_EN及VRD1—EN分別輸出電源P_VCCP0及 P_VCCP1給CPUO及CPU1，即完成CPU的電源開啟動作 〇 然而，由於前板11使用習知的可程式邏輯電路（FPGA 或CPLD)14進行電源管理控制，需要先進行程式規劃，再 將程式燒錄到FPGA或CPLD晶片中，使得生產線必須增加 程式化（programming)可程式邏輯電路14的流程，此外， 由於可程式邏輯電路14除了電路結構複雜，體積龐大，需 佔用電路板較大的面積外’並且具有1¾零件成本。 【發明内容】 本發明之目的，係在提供一種可減少電路板的使用面 積、免除程式化流程並簡化控制線路之CPU電源啟動控制 電路。 於是，本發明CPU電源啟動控制電路，設在一電路板 上，以根據電路板上之CPU滙流排選擇訊號及一電源轉換 單元輸出之一電源正常通知訊號，控制一電壓調整器，使 適時供電給電路板上之CPU，該控制電路包括一第一邏輯 單元，——第二邏輯單元、一第三邏輯單元及一第四邏輯單 元。該第一邏輯單元接受至少一 CPU的一第一滙流排選擇 訊號，及一第二滙流排選擇訊號，並分別對該第一及第二 滙流排選擇訊號進行邏輯”互斥或”運算，以對應輸出一第一 6 200815973 訊號及一第二訊號。該第二邏輯單元接受該第一及第二訊 號，並對該第一及第二訊號進行邏輯”及”運算，以輸出一符 合訊號。該第三邏輯單元連接該第二邏輯單元，並受一外 部訊號控制，以決定是否輸出該符合訊號。該第四邏輯單 元連接該第三邏輯單元並接收該電源正常通知訊號，並對 該符合訊號及該電源正常通知訊號進行邏輯”及”運算，以輸 出一致能訊號控制該電壓調整器供電給CPU。 藉由以硬體邏輯閘組成CPU電源啟動控制電路3，取 代習知需要程式化的可程式邏輯電路（FPGA或CPLD)，不 但能免除生產線對可程式邏輯電路進行程式化的製程，而 且使用價廉體體小之邏輯閘元件，除了可降低製造成本， 更能減少電路板面積的佔用。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例的詳細說明中，將可 清楚的呈現。 參閱圖2及圖3所示，是本發明CPU電源啟動控制電 路的一較佳實施例，其應用在ATCA系統之電源管理機制 中，以達成CPU電源順序地啟動。 ATCA系統主要包括一機箱21及一透過一背板（圖未示 )與機箱21電連接之前板一電路板（前板）22,且本實施例之 電路板22設有兩個中央處理器CPU0及CPU1 (以下簡稱 CPU0及CPU1)，以及兩個提供電源給CPU0及〔卩1；1的電 壓調整器211、212。 7 200815973 且根據設在背板之ATCA Zonel電源連接器的時序，來 自系統機箱21的一電壓訊號P48V(-48V)經由Zonel電源連 ' 接器（圖未示）輸入電路板22之一電壓調整單元20中，且該 電壓調整單元20包含進行下列功能的裝置： ' 電壓訊號P48V送入一電源控制器200中，當電壓訊號 • P48V輸入正常，機箱21輸出一致能訊號PS—ENABLE令電 源控制器200輸出電壓訊號P48V及另一致能訊號 ENABLE—P5V一STBY給一電壓轉換單元201(其中包含 φ 48V轉5V的電壓轉換器，及一 5V轉3.3V的電壓調整器和 一 5V轉1.5V的電壓調整器），並輸出一待機電壓訊號 P3V3-STBY(即3.3V電壓）給一電源管理器（BMC，Baseboard Management Controller ， 一晶片 ）202 和系統（ESB6300 、SUPER I/O，圖未示）。200815973 IX. Description of the Invention: [Technical Field] The present invention relates to a power supply starting circuit, and more particularly to a CPU power supply starting control circuit applied to an ATCA system. ‘ 【Prior Art】 • PICMG (Global Industrial Computer Manufacturing Organization) has set a standard for computer platforms that meet high throughput and high reliability, and has released the PICMG 3.0 specification, Advanced Communications Computer Architecture (ATCA). According to the PICMG 3.0 specification, each front of the ATCA system must consume less than 200W of power and the input voltage must range from -36V to -72V. Therefore, reducing the processor power consumption and power management of the front panel has become one of the main considerations in system design. As shown in FIG. 1 , it is a power management mechanism of a pre-board of an ATCA system. The front board (board) 11 has dual CPUs (hereinafter referred to as CPU0 and CPU1), and according to the timing of the ATCA Zonel power connector, the current board u When the Zonel power connector (not shown) is connected to the chassis 12 of the system, the -48V power supply voltage P48V from the system chassis is input to the voltage conversion unit 13 of the front panel 11 via a Zonel power connector (not shown). The voltage conversion unit 'unit 13 performs appropriate voltage step-down conversion according to the power source applicable to the circuit component to generate a plurality of different voltage source outputs, and outputs a power supply normal notification signal VTT-PG00D to control the CPU power to start a programmable logic. Circuit (FPGA or CPLD) 14 The programmable logic circuit 14 detects the first bus selection signals cPUO_BSELO_3P3 and CPU1JBSEL0-3P3 from the two CPUs through the internal logic circuit, and the second bus selection signal 200815973 CPUOJBSEL1 - 3P3 and CPU1-BSEL1—3P3, and according to the signal CPU1—SKTOCC_N, decide whether to output the enable voltages VRDO JEN and VRD1—EN respectively to the two voltages of the back end. The devices 15 and 16 respectively output the power sources P_VCCP0 and P_VCCP1 to the CPU0 and the CPU1 according to the enable signals VRD0_EN and VRD1_EN, that is, complete the power-on operation of the CPU. However, since the front board 11 uses a conventional programmable logic circuit (FPGA) Or CPLD) 14 for power management control, the program planning is required, and then the program is burned into the FPGA or CPLD chip, so that the production line must increase the flow of the programmable logic circuit 14 and, in addition, due to the programmable logic In addition to the complicated circuit structure and large size, the circuit 14 needs to occupy a large area of the circuit board and has a component cost of 13⁄4. SUMMARY OF THE INVENTION An object of the present invention is to provide a CPU power supply start control circuit which can reduce the use area of a circuit board, eliminate a stylized flow, and simplify a control line. Therefore, the CPU power-on control circuit of the present invention is disposed on a circuit board to control a voltage regulator according to a CPU bus selection signal on the circuit board and a power supply normal notification signal of the power conversion unit to enable timely power supply. To the CPU on the circuit board, the control circuit includes a first logic unit, a second logic unit, a third logic unit, and a fourth logic unit. The first logic unit receives a first bus selection signal of at least one CPU, and a second bus selection signal, and performs a logical “mutual exclusion” operation on the first and second bus selection signals respectively. Corresponding to output a first 6 200815973 signal and a second signal. The second logic unit receives the first and second signals and performs a logical AND operation on the first and second signals to output a coincidence signal. The third logic unit is connected to the second logic unit and is controlled by an external signal to determine whether to output the coincidence signal. The fourth logic unit is connected to the third logic unit and receives the power normal notification signal, and performs a logical AND operation on the compliance signal and the power normal notification signal to output a uniform energy signal to control the voltage regulator to supply power to the CPU. . By using the hardware logic gate to form the CPU power start control circuit 3, instead of the conventional programmable logic circuit (FPGA or CPLD), the production line can not be programmed to program the programmable logic circuit, and the price is used. In addition to reducing the manufacturing cost, it can reduce the occupation of the board area. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Referring to Figures 2 and 3, a preferred embodiment of the CPU power-on control circuit of the present invention is applied to the power management mechanism of the ATCA system to achieve sequential activation of the CPU power. The ATCA system mainly includes a chassis 21 and a front board (a front board) 22 electrically connected to the chassis 21 through a backplane (not shown), and the circuit board 22 of the embodiment is provided with two central processing units CPU0. And CPU1 (hereinafter referred to as CPU0 and CPU1), and two voltage regulators 211, 212 that supply power to CPU0 and [卩1;1. 7 200815973 And according to the timing of the ATCA Zonel power connector provided on the backplane, a voltage signal P48V (-48V) from the system chassis 21 is adjusted via a voltage of a Zonel power supply connector (not shown) input circuit board 22. In the unit 20, the voltage adjusting unit 20 includes a device for performing the following functions: 'The voltage signal P48V is sent to a power controller 200. When the voltage signal • P48V input is normal, the chassis 21 outputs a uniform energy signal PS-ENABLE to enable power control. The device 200 outputs a voltage signal P48V and another enable signal ENABLE_P5V-STBY to a voltage conversion unit 201 (including a voltage converter of φ 48V to 5V, and a voltage regulator of 5V to 3.3V and a 5V to 1.5V) Voltage regulator), and output a standby voltage signal P3V3-STBY (ie 3.3V voltage) to a power manager (BMC, Baseboard Management Controller, a chip) 202 and system (ESB6300, SUPER I / O, the figure is not shown ).
然後’電源管理器202與Shell Management Board溝通 (Shell Management Board，簡稱SMB，是管理機箱用的，設 於外部機箱21，使機箱21可透過SMB與BMC溝通）；同 _ 時，電源控制器200輸出電壓訊號P48V給一-48 V ^12V r 之電壓轉換器203，當電源管理器202讀取來自機箱21之Then, the power manager 202 communicates with the Shell Management Board (SMB, which is used for managing the chassis, and is disposed in the external chassis 21, so that the chassis 21 can communicate with the BMC through the SMB); The output voltage signal P48V is given to a voltage converter 203 of -48 V ^12V r when the power manager 202 reads from the chassis 21
Shell Management Board 之一 IMPI 命令時，即送出一 POWER-ON訊號給電壓轉換器203，使將-48V轉成12V炎 輸出給四組電壓轉換器204(型號ISL6525)、205(型號 ISL6525)、206(型號 RT9214)及 207(型號 RT9214)，使分別 產生電壓訊號 P5V(5V)、P3V3(3.3V)、P1V5(1.5V)及 PI V8(L8V)輸出。 8 200815973 其中電壓轉換器204、205在輸出電壓訊號P5V及 P3 V3後，會分別輸出一電源正常通知訊號P5 V^PWRGD及 P3V3一PWRGD給一反及閘（NAND)208，使進行邏輯 ”NAND”運算後，輸出一電源正常通知訊號 P3V3一P5VJPWRGD控制電壓轉換器206輸出電壓訊號 • P1V5(1.5V)給一處理CPU電源的電壓轉換器210，並送出 一電源正常通知訊號P1V5—PWRGD給電壓轉換器207和一 反及閘（NAND)209，以令電壓轉換器207輸出電壓訊號 # P1V8(1.8V)，並送出一電源正常通知訊號ριν8一PWRGD給 反及閘（NAND)209，當電壓轉換器206及207分別送出電源 正常通知訊號P1V5一PWRGD、P1V8一PWRGD給反及閘209 後，反及閘209輸出一電源正常通知訊號 CPU一VTTEN一OK—N 給 1.5V 轉 1.05V 的電 Μ轉換器 210, 使輸出一電壓訊號VCCP( 1·05 V)給電壓調整器211及212, 並送出一電源正常通知訊號VTTJPGOOD給本實施例之 CPU電源啟動控制電路3。 ® 如圖3所示，CPU電源啟動控制電路3包括一第一邏 ' 輯單元31、一第二邏輯單元300、一第三邏輯單元301、 一第四邏輯單元37及一第五邏輯單元38。 第一邏輯單元31是使用一包含有六顆互斥或閘（x〇r) 的積體電路（1C)之其中兩顆互斥或閘，其中一顆互斥或閘的 輸入端分別連接CPU0及CPU1的一第一滙流排選擇訊號 CPU0一BSEL0一3P3、CPU1JBSEL0-3P3，其中另一顆互斥或 閘的輸入端分別連接CPU0及CPU1的一第二滙流排選擇訊 9 200815973 號 CPUO—BSELl—3P3、CPU1JBSEL1—3P3。而該二互斥或閘 的輸出端分別連接第二邏輯單元300。 第二邏輯單元300包括兩反相器32、33及一及閘34。 兩反相器32、33的輸入端分別與兩互斥或閘的輸出端連接 。當 CPU0 及 CPU1 的第一滙流排選擇訊號 CPUC^BSELO—3P3、CPU1_BSEL0—3P3 相同（同為 0 或同為 1)時，互斥或閘輸出訊號BSELO_OK_N(邏輯”〇”）給反相器 32，使輸出訊號BSELO—OK(邏輯”1”）；同樣地，當CPU0 及CPU1的第二滙流排選擇訊號CPUO—BSEL1_3P3、 CPU1-BSEL1_3P3相同（同為0或同為1)時，互斥或閘輸出 訊號BSELl_OK—N(邏輯”0”）給反相器33，使輸出訊號 BSELl—OK(邏輯”1”）。 及閘34連接反相器32、33的輸出端，並於反相器32 、33輸出訊號BSELO—OK及BSELl—OK時，輸出一符合訊 號BSEL—MATCH(邏輯”1”）給第三邏輯電路301。 第三邏輯單元301包括串接之一第一開關35及一第二 開關36，其皆為一三態開關。第一開關35與及閘34之輸 出端連接，並受一外部訊號CPUl_SKTOCC—N(.是一偵測 CPU有無安裝的信號，來自於CPU)控制，以決定是否將符 合訊號BSELJS4ATCH(邏輯”1”)輸出至第二開關36。第二開 關36受一跳線器（Jumper)39控制，以決定是否將其輸入端 訊號（符合訊號BSEL-MATCH)輸出至第四邏輯單元37。 在本實施例中，第四邏輯單元37是一及閘，當第二開 關36輸出符合訊號BSEL一MATCH(邏輯”1”)及閘37，且及 10 200815973 閘37收到來自上述電壓轉換器210之電源正常通知訊號 VTT JPGOOD時，即輸出一致能訊號VRDO—EN給電壓調整 器211，使輸出一電壓訊號P—VCCP0給CPU0 ;同時，致能 訊號VRD0_EN給第五邏輯單元38。 第五邏輯單元38是一三態開關，其輸入端連接及閘37 ，輸出端連接另一電壓調整器212，並受外部訊號 CPU1_SKT0CC_N控制，以決定是否送出致能訊號 VRD1—EN給電壓調整器212，使輸出電壓訊號P—VCCP1給 CPU1 〇 此外，如圖2所示，電壓調整器211、212在輸出電壓 訊號P_VCCP0、P—VCCP1的同時，會分別輸出一電源正常 通知訊號 CPUO—VRD—PWRGD、CPU1—VRDJPWRGD 給一 反及閘213，使對訊號進行邏輯運算後，輸入電路板22上 之南橋晶片214，即完成了整體系統的電源開啟動作。 當然本實施例除了可對上述雙CPU進行電源控制之外 ，亦可對單一 CPU進行電源控制，亦即當電路板只設有 CPU0 時，只需將 CPU0之第一滙流排選擇訊號 CPU0_BSEL0_3P3同時輸入第一邏輯單元31之同一互斥或 閘的兩輸入端，並將CPU0之第二滙流排選擇訊號 CPU0JBSEL1—3P3同時輸入第一邏輯單元31之另一互斥或 閘的兩輸入端，即可對CPU0進行如同上述之CPU電源啟 動控制。 由上述說明可知，本發明藉由以硬體邏輯閘組成CPU 電源啟動控制電路3，取代習知需要程式化的可程式邏輯電 11 200815973 路（FPGA s CPLD)，不但能免除生產線對可喊邏輯電路 進仃程式化流程，簡化製程’而且使用價廉之邏輯閉元件 ’製造成本亦較可程式邏輯電路相對減少，並能減少電路 板面積的佔用。 ^惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發㈣請專利 祀圍及發明說明内容所作之簡單的等效變化與修飾，皆仍When one of the Shell Management Boards is commanded by the IMPI, a POWER-ON signal is sent to the voltage converter 203, which converts the -48V into a 12V output to the four sets of voltage converters 204 (model ISL6525), 205 (model ISL6525), 206. (Model RT9214) and 207 (Model RT9214) enable voltage signals P5V (5V), P3V3 (3.3V), P1V5 (1.5V), and PI V8 (L8V) output. 8 200815973 The voltage converters 204 and 205 respectively output a power normal notification signal P5 V^PWRGD and P3V3-PWRGD to a NAND 208 after outputting the voltage signals P5V and P3 V3, so as to perform logic "NAND". After the operation, the output power supply normal notification signal P3V3-P5VJPWRGD control voltage converter 206 output voltage signal • P1V5 (1.5V) to a voltage converter 210 for processing the CPU power supply, and sends a power supply normal notification signal P1V5-PWRGD to the voltage The converter 207 and a NAND 209 are used to cause the voltage converter 207 to output a voltage signal #P1V8 (1.8V), and send a power supply normal notification signal ριν8-PWRGD to the NAND gate 209 when the voltage The converters 206 and 207 respectively send the power supply normal notification signal P1V5-PWRGD, P1V8-PWRGD to the reverse gate 209, and the gate 209 outputs a power supply normal notification signal CPU-VTTEN-OK-N to 1.5V to 1.05V. The Μ converter 210 causes a voltage signal VCCP (1·05 V) to be output to the voltage regulators 211 and 212, and sends a power normal notification signal VTTJPGOOD to the CPU power supply start control circuit 3 of the present embodiment. As shown in FIG. 3, the CPU power start control circuit 3 includes a first logic unit 31, a second logic unit 300, a third logic unit 301, a fourth logic unit 37, and a fifth logic unit 38. . The first logic unit 31 uses two mutually exclusive or gates of an integrated circuit (1C) including six mutually exclusive or gates (x〇r), wherein one of the mutually exclusive or gate inputs is respectively connected to the CPU0. And a first bus selection signal CPU0-BSEL0-3P3, CPU1JBSEL0-3P3 of the CPU1, wherein the input terminals of the other mutually exclusive or gate are respectively connected to a second bus selection of the CPU0 and the CPU1. 9200815973 CPUO_BSELl —3P3, CPU1JBSEL1—3P3. The outputs of the two mutually exclusive or gates are respectively connected to the second logic unit 300. The second logic unit 300 includes two inverters 32, 33 and a gate 34. The inputs of the two inverters 32, 33 are respectively connected to the outputs of the two mutually exclusive or gates. When the first bus selection signals CPUC^BSELO-3P3 and CPU1_BSEL0-3P3 of CPU0 and CPU1 are the same (the same as 0 or the same 1), the mutex or gate output signal BSELO_OK_N (logic "〇") is given to the inverter 32. , so that the output signal BSELO_OK (logic "1"); similarly, when CPU0 and CPU1's second bus selection signals CPUO_BSEL1_3P3, CPU1-BSEL1_3P3 are the same (same as 0 or the same 1), mutually exclusive or The gate output signal BSEL1_OK_N (logic "0") is supplied to the inverter 33 to cause the output signal BSEL1 - OK (logic "1"). The gate 34 is connected to the output terminals of the inverters 32 and 33, and outputs a coincidence signal BSEL_MATCH (logic "1") to the third logic when the inverters 32, 33 output the signals BSELO_OK and BSEL1_OK. Circuit 301. The third logic unit 301 includes a first switch 35 and a second switch 36, all of which are a three-state switch. The first switch 35 is connected to the output end of the AND gate 34, and is controlled by an external signal CPU1_SKTOCC-N (. is a signal detecting whether the CPU is installed, from the CPU) to determine whether the signal BSELJS4ATCH (logic) 1 is met. ") is output to the second switch 36. The second switch 36 is controlled by a jumper 39 to determine whether or not to output its input signal (according to the signal BSEL-MATCH) to the fourth logic unit 37. In this embodiment, the fourth logic unit 37 is a NAND gate. When the second switch 36 outputs the coincidence signal BSEL-MATCH (logic "1") and the gate 37, and 10 200815973, the gate 37 receives the voltage converter from the above. When the power supply normal notification signal VTT JPGOOD of 210, the output of the coincidence signal VRDO_EN is given to the voltage regulator 211, so that a voltage signal P_VCCP0 is output to the CPU0; and the enable signal VRD0_EN is given to the fifth logic unit 38. The fifth logic unit 38 is a three-state switch, the input terminal is connected to the gate 37, the output terminal is connected to another voltage regulator 212, and is controlled by the external signal CPU1_SKT0CC_N to determine whether to send the enable signal VRD1_EN to the voltage regulator. 212, the output voltage signal P-VCCP1 is given to the CPU1. In addition, as shown in FIG. 2, the voltage regulators 211, 212 output a power normal notification signal CPUO-VRD at the same time as the output voltage signals P_VCCP0, P-VCCP1. PWRGD, CPU1 - VRDJPWRGD gives a reverse gate 213, after the logical operation of the signal, the south bridge wafer 214 on the circuit board 22, the power-on operation of the overall system is completed. Of course, in this embodiment, in addition to the power control of the dual CPUs, power control can be performed on a single CPU, that is, when only the CPU0 is provided on the circuit board, only the first bus selection signal CPU0_BSEL0_3P3 of the CPU0 is simultaneously input. The two input ends of the same mutual exclusion or gate of the first logic unit 31, and the second bus selection signals CPU0JBSEL1 - 3P3 of the CPU0 are simultaneously input to the two inputs of the other mutual exclusion or gate of the first logic unit 31, The CPU 0 is subjected to the CPU power start control as described above. As can be seen from the above description, the present invention replaces the programmable logic logic 11 200815973 (FPGA s CPLD) by forming a CPU power supply start control circuit 3 with a hardware logic gate, which can eliminate the production line pair shout logic. The circuit enters the stylization process, simplifies the process 'and uses inexpensive logic off-components' manufacturing cost, which is relatively less than the programmable logic circuit, and can reduce the board area. However, the above is only the preferred embodiment of the present invention, and the scope of the present invention cannot be limited thereto, that is, the simple equivalent change of the patent and the description of the invention according to the present invention. And the decoration, all still
屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 電源管理電路 圖1是習知一種使用可程式邏輯電路的 方塊示意圖； 圖2是本發明 ’其中顯示一應用 的電路方塊圖；及 CPU電源啟動控制電 J敎佳實施例 CPU電源啟動控制電路 <I源f理電路 圖3是本實施例CPU電源啟動控制It is within the scope of the patent of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a conventional circuit using a programmable logic circuit; FIG. 2 is a circuit block diagram showing an application of the present invention; and a CPU power supply start control system. Power start control circuit <I source f circuit FIG. 3 is the CPU power start control of this embodiment
黾路的詳細電路圖 12Detailed circuit diagram of Kushiro 12
200815973 【主要元件符號說明】 20電壓調整單元 22電路板 201電壓轉換單元 203〜207、210電壓轉換器 211、212電壓調整器 4 CPU電源啟動控制電路 32、33反相器 35第一開關 37第四邏輯單元 39跳線器 301第三邏輯單元 21機箱 200電源控制器 202電源管理器 208、209、213 反及閘 214南橋晶片 3 1第一邏輯單元 34及閘 36第二開關 38第五邏輯單元 300第二邏輯單元 13200815973 [Description of main component symbols] 20 voltage adjustment unit 22 circuit board 201 voltage conversion unit 203 to 207, 210 voltage converter 211, 212 voltage regulator 4 CPU power supply start control circuit 32, 33 inverter 35 first switch 37 Four logic unit 39 jumper 301 third logic unit 21 chassis 200 power controller 202 power manager 208, 209, 213 reverse gate 214 south bridge wafer 3 1 first logic unit 34 and gate 36 second switch 38 fifth logic Unit 300 second logic unit 13