TWI310560B - Semiconductor memory device with multi-port - Google Patents

Semiconductor memory device with multi-port Download PDF

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TWI310560B
TWI310560B TW095136053A TW95136053A TWI310560B TW I310560 B TWI310560 B TW I310560B TW 095136053 A TW095136053 A TW 095136053A TW 95136053 A TW95136053 A TW 95136053A TW I310560 B TWI310560 B TW I310560B
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data
write
signal
read
unit
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TW095136053A
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TW200729220A (en
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Hwang Hur
Chang-Ho Do
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry

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  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Description

1310560 九、發明說明： 【發明所屬之技術領域】 本發明係關於半導體記憶體裝置，且更特定言之’係關 於多埠記憶體裝置中之測試周邊電路。 【先前技術】 通常，包括動態隨機存取記憶體（DRAM)裝置的大部分記 憶體裝置係用於諸如高清晰度電視（HDTV)及液晶顯示器 (LCD)TV之音§孔及視訊用家電裝置（appHance deviCe)，以及 諸如桌上型電腦、筆記型電腦及伺服器的習知領域中。鑒 於以下所闡述之原因，存在對於可滿足不同於習知輸入/輸 出（I/O)方法之I/O方法之記憶體裝置的需要。習知1/0方法 可為使用具有複數個輸入/輸出插腳組之單一埠（意即，並列 I/O介面）的資料傳輸方法。 考慮到並列I/O介面的缺點，已進行多次嘗試以將並列1/0 介面變為串列I/O介面。串列1/0介面經由小數目之匯流排線 而串列接收外部資料並在内部並列化所接收之資料。 因此，因為串列1/0介面使用小數目之匯流排線，所以其 製造成本減少。另外’因為_列1/0介面不需要具有複數個 輸入/輸出插腳組的單一埠，所以其可適用於多埠記憶體裝 置。 多埠記憶體裝置包括複數個埠，每一淳執行—獨立操 作。因此，多埠記憶體裝置可同時處理多媒體所需要的大 量視訊及音訊資料。 習知DRAM裝置歸因於單一 埠而可處理單一操作 且因 0:\114\114529-980204.doc 1310560 此其僅可能在完成先前操作之後執 欠矾仃另一操作。多埠記憶 體裝置可克服習知DRAM裝置的上述 J工迎限制，以使得多埠記 憶體裝置的應用得到進一步擴展。 在上述多埠記憶體裝置中，高骟咨 n鴻S枓處理邏輯對於並列 化串列資料及串列化並列資料而言為必需的。 當執行用於高頻資料處理的操作時’在與dram裝置中 所包括之記憶體單元有關的故障出現時，難以驗證高頻資 料處理邏輯的操作。另外，當高 。 田π頻貝枓處理邏輯之邏輯信 號之間的時間容限經設定為緊率聋 瓦在時與該時間容限有關的 故障可出現。因此，需要一测古古番 利忒電路來驗證一特定故障是 與dram裝置中所包括之_橋辦留-士 β 。隐體早凡有關還是與高頻資料 處理邏輯之時間容限有關。 【發明内容】 ”因此IU之-目的為提供—種用於在高頻狀況下測 忒周邊裝置而不考慮記憶體單元之缺陷的半導體記憶體裝 置。 本發月之另—目的為提供一種用於在高頻狀況下測試一 2於執订絲操作之電路而不考慮記憶體單元之缺陷的半 導體記憶體裝置。 本發明之另一目的Α Μ 的為知供一種用於在高頻狀況下測試— 用於執行寫入接作夕垂·功Τ 、 電路而不考慮記憶體單元之缺陷的主 導體記憶體裝置。 、康本發明之一態樣，提供一種半導體記憶體裝置，該 、…己itH置包括：_讀取匯流排線，其用於傳送讀 O:\114\114529-980204.doc 1310560 取貝料，-寫入匯流排線，其用於傳送寫入資料；及 時資料儲存早凡’其連接於該讀取薩流排線與該寫入匿流 :線之間且受控於在測試模式期間被啟狀測試模式： 根據本發明之另-態樣’提供—種多埠記憶體裝置其 包括：複數個記憶組（bank);及用於控制全域1/〇線與該等 記憶組之間的信號傳輸之複數個記憶組控制邏輯電路，其 中記憶組控制邏輯電路之數目對應於記憶組及多埠記憶體 裝置之數目且該等記憶組控制邏輯電路經組態以在高頻狀 況下測試周邊電路而不考慮記憶體單元之缺陷。 【實施方式】 以下將參看隨附圖式詳細描述根據本發明之例示性實施 例之用於測試半導體記憶體裝置中的周邊電路之測試電 路。 圖1為根據本發明之多埠記憶體裝置的方塊圖。為了便於 解釋，說明具有四個埠及八個記憶組的多埠記憶體裝置。 特定s之’假定多埠記憶體裝置具有16位元之資料框且執 行64位元之預提取操作。 如圖所示’根據本發明之多埠記憶體裝置包括第一至第 四埠PORTO至PORT3、第一至第八記憶組ΒΑΝΚ0至 B ANK7、第一及第二全域輸入/輸出（I/O)線GIO—OUT及 GIOJN、第一至第八記憶組控制邏輯電路BCL0至BCL7及 一鎖相迴路PLL。 第一至第四埠PORTO至PORT3之每一者獨立地執行與外 O:\114\114529-980204.doc 1310560 部裝置之串列通信。第一至第八記憶組Β ΑΝΚ0至BANK7經 劃分為上部記憶組Β ΑΝΚ0至B ANK3及下部記憶組B ANK4 至Β ANK7，該等記憶組由第一至第四埠PORTO至PORT3劃 分且排列於列方向中。 第一全域I/O線GIO—OUT係在上部記憶組ΒΑΝΚ0至 BANK3與第一至第四埠PORTO至PORT3之間排列於列方向 中，且並列傳輸輸出資料。第二全域I/O線GIO_IN係在下部 記憶組BANK4至BANK7與第一至第四埠PORTO至PORT3之 ® 間排列於列方向中，且並列傳輸輸入資料。 第一至第八記憶組控制邏輯電路BCL0至BCL7控制第一 及第二全域I/O線GIO_OUT及GIO_IN與第一至第八記憶組 ΒΑΝΚ0至BANK7之間的信號傳輸。鎖相迴路PLL係位於第 二埠PORT1與第三埠PORT2之間且產生内部時脈。回應於 内部時脈，將内部命令以及輸入及輸出資料輸入至第一至 第四埠PORTO至PORT3。 ^ 圖2為圖1中所說明之第一記憶組ΒΑΝΚ0及第一記憶組控 制邏輯BCL0的詳細方塊圖。其他記憶組BANK1至BANK7 及其他記憶組控制邏輯電路BCL1至BCL7具有與第一記憶 組ΒΑΝΚ0及第一記憶組控制邏輯BCL0之結構相同的結構。 如圖所示，第一記憶組控制邏輯BCL0包括一測試模式定 義電路415及一命令解碼器417。該命令解碼器41 7接收一内 部命令（諸如，一啟用命令（active command)、一讀取命令及 一寫入命令），且產生一讀取旗標信號RDEN及一寫入旗標 信號WDEN。該測試模式定義電路41 5基於用於驗證高頻資 O:\114\114529-980204.doc 1310560 料處理邏輯之操作的測試模式設定而產生一定義一測試模 式的測試模式信號TLCHECK。 第一記憶組ΒΑΝΚ0包括複數個資料匯流排感測放大器 (DBSA)405、複數個寫入驅動器407、一暫時資料儲存單元 409、一解碼單元410及一讀取/寫入控制單元411。 解碼單元4 10解碼自命令解碼器417輸出的讀取旗標信號 RDEN及寫入旗標信號WDEN，以驅動記憶體單元413之一 特定字線WL，並產生一用於驅動一特定YI電晶體的信號。 該YI電晶體連接一位元線BL及一區段輸入/輸出（I/O)線（諸 如，資料傳送線）。 寫入驅動器407執行寫入資料之寫入操作。DBS A 405放 大自筘憶體單元413輸出之讀取資料且輸出具有64位元輸 出資料之已放大資料。 讀取/寫入控制單元411考慮到與寫入資料之時間容限， 而將寫入旗標信號WDEN延遲一預定時間，以產生一用於 控制寫入驅動器407之寫入信號WDRV，並接收讀取旗標信 號RDEN’以產生一用於控制DBSA 405的讀取信號IOSTBP。 暫時資料儲存單元409共用讀取匯流排線Q_BIO與寫入 匯流排線Q_WTD之間的資料，並基於測試模式信號 TLCHECK暫時地保存該等資料。讀取匯流排線Q—BIO共用 第一記憶組控制邏輯BCL0與DBS A 405之間的資料及複數 個DBSA之間的資料，且寫入匯流排線Q_WTD共用第一記 憶組控制邏輯BCL0與寫入驅動器407之間的資料及複數個 寫入驅動器之間的資料。詳言之，在測試模式期間，暫時 O:\114\114529-980204.doc -10· 1310560 資料儲存單元409將來自外部源之寫入資料保存為讀取資 料，且使用所保存之資料作為用於驗證高頻資料處理邏輯 的讀取/寫入資料。 圖3為圖2中所展示之根據本發明之第一實施例的暫時資 料儲存單元409之電路圖。本文中，信號RX_D表示來自第 一記憶組控制邏輯BCL0的寫入資料，且信號DSTRBP表示 信號RX_D的資料旗標信號。 如圖所示，暫時資料儲存單元409包括一資料輸入單元 5 05、一共用控制單元507及第一鎖存單元501及第二鎖存單 元 503。 資料輸入單元505接收寫入資料RX_D且將所接收之信號 施加於寫入匯流排線Q_WTD。第一鎖存單元501係位於寫 入匯流排線Q_WTD上且鎖存寫入資料RX_D作為資料輸入 單元505之輸出。共用控制單元507與讀取匯流排線(^_：810 共用施加於寫入匯流排線Q_WTD上的寫入資料RX_D。第 二鎖存單元503係位於讀取匯流排線Q_BIO上且鎖存施加 於讀取匯流排線Q_BIO上的寫入資料RX—D。 詳言之，資料輸入單元505包括一第一反相器INV卜第一 PMOS電晶體P1及第二PMOS電晶體P2，以及第一 NMOS電 晶體N1及第二NMOS電晶體N2。 第一反相器INV1使告知輸入該寫入資料RX_Di點的資 料旗標信號DSTRBP反相。第一NMOS電晶體N1具有一接收 資料旗標信號DSTRBP的閘極。連接至第一NMOS電晶體N1 的第二PMOS電晶體P2具有一接收第一反相器INV1之輸出 O:\114\114529-980204.doc 11 1310560 的閘極。連接於第一NMOS電晶體N1與接地電壓（VSS)端子 之間的第二NMOS電晶體N2具有一接收寫入資料RX_D的 閘極。連接於第二PMOS電晶體P2與源電壓（VDD)端子之間 的第一PMOS電晶體P1具有一接收寫入資料RX—D的閘極。 共用控制單元507包括一.第二反相器INV2及一傳送閘 TG1。第二反相器INV2使測試模式信號TLCHECK反相。傳 送閘TG1回應於測試模式信號TLCHECK而將施加於寫入匯 流排線Q_WTD上的寫入資料RX_D傳送至讀取匯流排線 Q—BIO。 第一鎖存單元501及第二鎖存單元503之每一者包括一包 括複數個反相器的反相器鎖存單元。 當測試模式信號TLCHECK為邏輯位準”低”時，意即，在 正常模式期間，僅將寫入資料RX_D施加於寫入匯流排線 Q一WTD。 當測試模式信號TLCHECK為邏輯位準"高”時，意即，在 測試模式期間，傳送閘TG1運作以便與讀取匯流排線Q_BIO 共用施加於寫入匯流排線Q_WTD的寫入資料RX_D。此 時，若自外部源輸入讀取命令，則第一記憶組控制邏輯 BCL0將讀取旗標信號RDEN輸出至讀取/寫入控制單元 411。讀取/寫入控制單元411停用作為DBSA 405的啟用信號 之讀取信號IOSTBP。因此，不輸出來自記憶體單元41 3之 寫入資料，而是輸出保存於暫時資料儲存單元409中之寫入 資料RX_D。 O:\114\I14529-980204.doc -12- 1310560 如圖3中所示，當啟動測試模式信號TLCHECK時，根據 本發明之第一實施例的暫時資料儲存單元409在多埠記憶 體裝置中執行單一寫入操作。 圖4為圖2中所說明之讀取/寫入控制411單元的電路圖。 如圖所示，讀取/寫入控制411包括一寫入信號輸出單元 601及一讀取信號輸出單元603。 寫入信號輸出單元601可用一延遲單元DELAY1來實施， 該延遲單元DELAY1使寫入旗標信號WDEN延遲一預定時 間以輸出已延遲之信號作為寫入信號WDRV。 讀取信號輸出單元603基於測試模式信號TLCHECK輸出 讀取信號IOSTBP。詳言之，讀取信號輸出單元603包括第 一反相器INV3及第二反相器INV4，以及一反及（NAND)閘 極NAND1。第一反相器INV3使測試模式信號TLCHECK反 相。NAND閘NAND1執行對第一反相器INV3之輸出及讀取 旗標信號RDEN的NAND運算。第二反相器INV4使NAND閘 NAND1之輸出反相以輸出讀取信號IOSTBP。 如以上所描述，當用邏輯位準"高"啟動測試模式信號 TLCHECK時’讀取信號輸出單元603不輸出讀取信號 IOSTBP，且當用邏輯位準”低"停用測試模式信號TLCHECK 時，輸出讀取信號IOSTBP。因此，當用邏輯位準"高"啟動 測試模式信號TLCHECK時，讀取/寫入控制411防止在讀取 期間記憶體單元之資料被放大及輸出。此時，若輸入寫入 命令，則正常地將寫入資料RX_D寫入至記憶體單元，因為 寫入資料RX_D係施加於寫入匯流排線Q_WTD以及讀取匯 0:\114\114529-980204.doc - 13 - 1310560 流排線Q_BIO。藉由比較在測試模式期間的讀取資料與在 正常模式期間的讀取資料，可能找到DBS A 405中的故障。 圖5為圖2中所展示之根據本發明之第二實施例的暫時資 料儲存單元409之電路圖。舉例而言，當啟動測試模式信號 TLCHECK時，根據本發明之第二實施例的暫時資料儲存單 元409在多埠記憶體裝置中執行多個寫入操作。特定言之， 基於來自外部的位址信號執行多個寫入操作。本文中，位 址信號之數目對應於待進行之寫入操作的數目，且暫時資 料儲存單元409中之鎖存單元的數目亦對應於待進行之寫 入操作的數目。 如圖所示，暫時資料儲存單元409包括一資料輸入單元 7(H、第一共用控制單元703及第二共用控制單元705以及一 寫入匯流排線鎖存單元707。資料輸入單元701接收寫入資 料RX_D以將所接收之資料施加於寫入匯流排線Q_WTD。 寫入匯流排線鎖存單元707係位於寫入匯流排線Q_WTD上 且鎖存寫入資料RX_D。第一共用控制單元703及第二共用 控制單元705與讀取匯流排線Q_BIO共用施加於寫入匯流 排線Q_WTD的寫入資料RX—D。 詳言之，資料輸入單元701包括第一反相器INV5、第一 NOMS電晶體N3及第二NMOS電晶體N4以及第一 POMS電 晶體P3及第二PMOS電晶體P4。 第一反相器INV5使告知輸入寫入資料RX_D之點的資料 旗標信號DSTRBP反相。第一NMOS電晶體N3具有一接收資 料旗標信號DSTRBP的閘極。連接至第一 NMOS電晶體N3 O:\114\114529-980204.doc •14- 1310560 的第二PMOS電晶體P4具有一接收第一反相器INV5之輸出 的閘極。連接於第一 NM0S電晶體N3與接地電壓（VSS)端子 之間的第二NM0S電晶體N4具有一接收寫入資料rx_D的 閘極。連接於第二PMOS電晶體P4與源電壓（VDD)端子之間 的第一 PM0S電晶體P3具有一接收寫入資料rx_d的閘極。 寫入匯流排線鎖存單元707為一包括複數個反相器的反 相器鎖存單元。 第一共用控制單元703包括第一 NAND閘NAND2及第二 NAND閘NAND3、第一傳送閘TG2及第二傳送閘TG3，以及 第一鎖存單元709及第二鎖存單元711。第一 NAND閘 NAND2執行測試模式信號TLCHECK及第一測試位址信號 ΤΑ—0的NAND運算。第二NAND閘NAND3執行測試模式信 號TLCHECK及第二測試位址信號ΤΑ_1的NAND運算。第一 傳送閘TG2回應於第一 NAND閘NAND2之輸出而傳送由寫 入匯流排線鎖存單元707鎖存的寫入資料RX_D。第二傳送 閘TG3回應於第二NAND閘NAND3之輸出而傳送由寫入匯 流排線鎖存單元707鎖存的寫入資料RX_D。第一鎖存單元 709鎖存連接至第一傳送閘TG2的寫入資料RX_D。第二鎖存 單元711鎖存連接至第二傳送閘TG3的寫入資料RX_D。 第二共用控制單元705包括第二反相器INV6及第三反相 器INV7、第三NAND閘NAND4及第四NAND閘NAND5，以 及第三傳送閘TG4及第四傳送閘TG5。 第二反相器INV6使自測試模式定義電路輸出之第一測試 O:\ll4\114529-980204.doc -15- 1310560 模式信號TLCHECK0反相。第三NAND閘NAND4執行對第 二反相器INV6之輸出及讀取旗標信號RDEN的NAND運 算。第三傳送閘TG4回應於第三NAND閘NAND4之輸出而將 由第一鎖存單元709鎖存之寫入資料10^_0傳送至讀取匯流 排線Q_BI〇。 第三反相器INV7使自測試模式定義電路輸出之第二測試 模式信號TLCHECK1反相。第四NAND閘NAND5執行對第 三反相器INV7之輸出及讀取旗標信號RDEN的NAND運 算。第四傳送閘TG5回應於第四NAND閘NAND5之輸出而將 由第二鎖存單元711鎖存之寫入資料10(_0傳送至讀取匯流 排線Q_BIO。 圖5中所展示之暫時資料儲存單元409為一用於將寫入操 作執行兩次之例示性電路，且因此鎖存單元之數目（意即， 兩個）對應於待進行之寫入操作的數目。熟習此項技術者應 明白，傳送閘、鎖存單元及測試位址之數目對應於待進行 之寫入操作之數目。 在測試模式期間，基於測試位址信號ΤΑ_0及TA_1而接通 第一傳送閘TG2及第二傳送閘TG3中之對應一者，使得對應 之鎖存單元保存寫入資料RX_D «此外，當第一測試模式信 號TLCHECK0及第二測試模式信號TLCHECK1根據測試位 址信號ΤΑ_0及TA_1而為邏輯位準"低"時，接通第三傳送閘 TG4及第四傳送閘TG5中之對應一者，使得將已鎖存之寫入 資料RX_D傳送至讀取匯流排線Q_BIO。 如以上所描述，在本發明中，來自外部之寫入資料係儲 O:\114\114529-980204.doc 16- 1310560 存於連接於寫入匯流排線Q-Wtd與讀取匯流排線Q_BI〇之 間的暫時資料儲存單元中，且隨後在用於測試除記憶體單 兀之外的周邊裝置的測試模式期間，所儲存之資料係用作 讀取及寫入資料。因此，在高頻狀況下而不考慮記憶體單 7L之缺陷’可能找到周邊裝置的錯誤操作。 根據本發明，藉由將高頻資料處理邏輯作為周邊裝置（與 。己隐體單元無關）驗證來有效分析故障並保證半導體記憶 體裝置之穩疋操係可能的。另外，可縮短用於開發半導體 記憶體裝置（具體言之，多土皐記憶體裳置）的期限，藉此增加 其競争性。 本申請案含有與在2005年9月28日及2〇〇6年5月8日在韓 國智慧財產局中請的韓國專财請案第聽肩857號及第 6-4U90號有關之標的物，該等中請案之全文以引用的 方式併入本文中。 雖然已參考特定較佳實施例描述了本發明，但是對於熟1310560 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor memory device, and more particularly to a test peripheral circuit in a multi-turn memory device. [Prior Art] In general, most memory devices including dynamic random access memory (DRAM) devices are used for audio § holes and video home appliances such as high definition television (HDTV) and liquid crystal display (LCD) TVs. (appHance deviCe), as well as in the customary fields such as desktops, notebooks, and servers. For the reasons set forth below, there is a need for a memory device that can satisfy an I/O method other than the conventional input/output (I/O) method. The conventional 1/0 method can be a data transmission method using a single 埠 (ie, a parallel I/O interface) having a plurality of input/output pin groups. In view of the shortcomings of the parallel I/O interface, several attempts have been made to change the parallel 1/0 interface to the serial I/O interface. The serial 1/0 interface serially receives external data via a small number of bus lines and internally parallelizes the received data. Therefore, since the serial 1/0 interface uses a small number of bus bars, its manufacturing cost is reduced. In addition, since the _column 1/0 interface does not require a single 埠 having a plurality of input/output pin sets, it can be applied to a multi-turn memory device. Multiple memory devices include a plurality of ports, each performing an independent operation. Therefore, multiple memory devices can simultaneously process a large amount of video and audio data required for multimedia. Conventional DRAM devices can handle a single operation due to a single defect and because of 0:\114\114529-980204.doc 1310560 it is only possible to owe another operation after completing the previous operation. The multi-turn memory device can overcome the above-mentioned J-Watt limit of the conventional DRAM device, so that the application of the multi-stream memory device is further expanded. In the above-mentioned multi-stream memory device, the processing logic of the high-level data processing is necessary for parallelizing the serial data and the serialized parallel data. When an operation for high frequency data processing is performed 'when a failure associated with a memory unit included in the dram device occurs, it is difficult to verify the operation of the high frequency data processing logic. Also, when high. The time margin between the logical signals of the π-frequency 枓 processing logic is set to a tight rate 聋 watts at which time a fault associated with the time tolerance can occur. Therefore, it is necessary to test the Gu Gufan circuit to verify that a specific fault is associated with the bridge included in the dram device. The hidden body is still related to the time tolerance of the high-frequency data processing logic. SUMMARY OF THE INVENTION "Therefore, the purpose of the IU is to provide a semiconductor memory device for measuring peripheral devices under high frequency conditions without regard to defects of the memory cells. Another purpose of this month is to provide a use. A semiconductor memory device that tests a circuit for performing a wire operation without considering a defect of a memory cell under high frequency conditions. Another object of the present invention is to provide a method for use in a high frequency condition. Test - a main body memory device for performing a write connection, a circuit, and a circuit without considering a defect of a memory cell. In one aspect of the invention, a semiconductor memory device is provided, ... The itH set includes: _ read bus line, which is used to transfer read O:\114\114529-980204.doc 1310560 to take the material, - write bus line, which is used to transfer the written data; timely data storage As long as it is connected to the read-stream line and the write stream: line and controlled by the test mode during the test mode: according to the other aspect of the present invention埠Memory device includes: plural a memory bank control bank and a plurality of memory group control logic circuits for controlling signal transmission between the global 1/〇 line and the memory groups, wherein the number of memory group control logic circuits corresponds to a memory group and a plurality of memories The number of body devices and the memory group control logic circuits are configured to test peripheral circuits under high frequency conditions without regard to the defects of the memory cells. [Embodiment] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. A test circuit for testing peripheral circuits in a semiconductor memory device of the exemplary embodiment. Figure 1 is a block diagram of a multi-turn memory device in accordance with the present invention. For ease of explanation, the description has four ports and eight memory groups. Multiple memory devices. The specific s 'hypothetical memory device has a 16-bit data frame and performs a 64-bit pre-fetch operation. As shown in the 'multiple memory device according to the present invention includes the first One to fourth ports PORTO to PORT3, first to eighth memory groups ΒΑΝΚ0 to B ANK7, first and second global input/output (I/O) lines GIO-OUT and GIOJN, first to eighth The memory group control logic circuits BCL0 to BCL7 and a phase-locked loop PLL. Each of the first to fourth ports PORTO to PORT3 independently performs serial communication with the external O:\114\114529-980204.doc 1310560 device The first to eighth memory groups ΑΝΚ0 to BANK7 are divided into an upper memory group ΑΝΚ0 to B ANK3 and a lower memory group B ANK4 to ΒANK7, and the memory groups are divided and arranged by the first to fourth ports PORTO to PORT3. In the column direction, the first global I/O line GIO_OUT is arranged in the column direction between the upper memory group ΒΑΝΚ0 to BANK3 and the first to fourth ports PORTO to PORT3, and the output data is transmitted in parallel. The second global I/O line GIO_IN is arranged in the column direction between the lower memory groups BANK4 to BANK7 and the first to fourth ports PORTO to PORT3, and the input data is transmitted in parallel. The first to eighth memory group control logic circuits BCL0 to BCL7 control signal transmission between the first and second global I/O lines GIO_OUT and GIO_IN and the first to eighth memory groups ΒΑΝΚ0 to BANK7. The phase-locked loop PLL is located between the second port PORT1 and the third port PORT2 and generates an internal clock. In response to the internal clock, internal commands and input and output data are input to the first to fourth ports PORTO to PORT3. ^ Fig. 2 is a detailed block diagram of the first memory group ΒΑΝΚ0 and the first memory group control logic BCL0 illustrated in Fig. 1. The other memory banks BANK1 to BANK7 and other memory group control logic circuits BCL1 to BCL7 have the same structure as the first memory group ΒΑΝΚ0 and the first memory group control logic BCL0. As shown, the first memory set control logic BCL0 includes a test mode definition circuit 415 and a command decoder 417. The command decoder 41 7 receives an internal command (such as an active command, a read command, and a write command) and generates a read flag signal RDEN and a write flag signal WDEN. The test mode definition circuit 415 generates a test mode signal TLCHECK defining a test mode based on the test mode setting for verifying the operation of the high frequency resource O:\114\114529-980204.doc 1310560 processing logic. The first memory group ΒΑΝΚ0 includes a plurality of data bus sense amplifiers (DBSA) 405, a plurality of write drivers 407, a temporary data storage unit 409, a decoding unit 410, and a read/write control unit 411. The decoding unit 4 10 decodes the read flag signal RDEN and the write flag signal WDEN output from the command decoder 417 to drive a specific word line WL of the memory unit 413, and generates a signal for driving a specific YI transistor. signal of. The YI transistor is connected to a bit line BL and a sector input/output (I/O) line (e.g., a data transfer line). The write driver 407 performs a write operation of writing data. The DBS A 405 expands the read data output from the memory unit 413 and outputs the amplified data having the 64-bit output data. The read/write control unit 411 delays the write flag signal WDEN by a predetermined time in consideration of the time tolerance with the write data to generate a write signal WDRV for controlling the write driver 407, and receives The flag signal RDEN' is read to generate a read signal IOSTBP for controlling the DBSA 405. The temporary data storage unit 409 shares the data between the read bus line Q_BIO and the write bus line Q_WTD, and temporarily stores the data based on the test mode signal TLCHECK. The read bus line Q-BIO shares the data between the first memory group control logic BCL0 and DBS A 405 and the data between the plurality of DBSAs, and the write bus line Q_WTD shares the first memory group control logic BCL0 and write The data entered between the drives 407 and the data written between the plurality of write drivers. In detail, during the test mode, the temporary O:\114\114529-980204.doc -10· 1310560 data storage unit 409 saves the written data from the external source as the read data, and uses the saved data as the data. Verify the read/write data of the high frequency data processing logic. Figure 3 is a circuit diagram of the temporary data storage unit 409 of the first embodiment of the present invention shown in Figure 2 . Herein, the signal RX_D represents the write data from the first memory group control logic BCL0, and the signal DSTRBP represents the data flag signal of the signal RX_D. As shown, the temporary data storage unit 409 includes a data input unit 505, a shared control unit 507, and a first latch unit 501 and a second latch unit 503. The data input unit 505 receives the write data RX_D and applies the received signal to the write bus line Q_WTD. The first latch unit 501 is located on the write bus line Q_WTD and latches the write data RX_D as the output of the data input unit 505. The shared control unit 507 shares the write data RX_D applied to the write bus line Q_WTD with the read bus line (^_: 810. The second latch unit 503 is located on the read bus line Q_BIO and is latch applied. For reading the write data RX_D on the bus line Q_BIO. In detail, the data input unit 505 includes a first inverter INV, a first PMOS transistor P1 and a second PMOS transistor P2, and the first The NMOS transistor N1 and the second NMOS transistor N2. The first inverter INV1 inverts the data flag signal DSTRBP that is input to the write data RX_Di point. The first NMOS transistor N1 has a received data flag signal DSTRBP. The gate of the second PMOS transistor P2 connected to the first NMOS transistor N1 has a gate that receives the output of the first inverter INV1 O:\114\114529-980204.doc 11 1310560. The second NMOS transistor N2 between the NMOS transistor N1 and the ground voltage (VSS) terminal has a gate receiving the write data RX_D, and is connected between the second PMOS transistor P2 and the source voltage (VDD) terminal. A PMOS transistor P1 has a gate that receives the write data RX-D. The unit 507 includes a second inverter INV2 and a transfer gate TG1. The second inverter INV2 inverts the test mode signal TLCHECK. The transfer gate TG1 is applied to the write bus line Q_WTD in response to the test mode signal TLCHECK. The upper write data RX_D is transferred to the read bus line Q_BIO. Each of the first latch unit 501 and the second latch unit 503 includes an inverter latch unit including a plurality of inverters. When the test mode signal TLCHECK is logic level "low", that is, during the normal mode, only the write data RX_D is applied to the write bus line Q-WTD. When the test mode signal TLCHECK is logic level " When "high", that is, during the test mode, the transfer gate TG1 operates to share the write data RX_D applied to the write bus line Q_WTD with the read bus line Q_BIO. At this time, if a read command is input from an external source Then, the first memory group control logic BCL0 outputs the read flag signal RDEN to the read/write control unit 411. The read/write control unit 411 deactivates the read signal IOSTBP which is the enable signal of the DBSA 405. , not output The memory unit 41 3 writes the data, but outputs the write data RX_D stored in the temporary data storage unit 409. O:\114\I14529-980204.doc -12- 1310560 As shown in FIG. When the mode signal TLCHECK is tested, the temporary material storage unit 409 according to the first embodiment of the present invention performs a single write operation in the multi-stream memory device. 4 is a circuit diagram of the read/write control 411 unit illustrated in FIG. 2. As shown, the read/write control 411 includes a write signal output unit 601 and a read signal output unit 603. The write signal output unit 601 can be implemented by a delay unit DELAY1 which delays the write flag signal WDEN by a predetermined time to output the delayed signal as the write signal WDRV. The read signal output unit 603 outputs the read signal IOSTBP based on the test mode signal TLCHECK. In detail, the read signal output unit 603 includes a first inverter INV3 and a second inverter INV4, and a reverse (NAND) gate NAND1. The first inverter INV3 inverts the test mode signal TLCHECK. The NAND gate NAND1 performs a NAND operation on the output of the first inverter INV3 and the reading of the flag signal RDEN. The second inverter INV4 inverts the output of the NAND gate NAND1 to output the read signal IOSTBP. As described above, when the logic level "high" is used to start the test mode signal TLCHECK, the read signal output unit 603 does not output the read signal IOSTBP, and when the logic level is low, the test mode signal is deactivated. At the time of TLCHECK, the read signal IOSTBP is output. Therefore, when the test mode signal TLCHECK is started with the logic level "high", the read/write control 411 prevents the data of the memory cell from being amplified and output during the reading. At this time, if a write command is input, the write data RX_D is normally written to the memory unit because the write data RX_D is applied to the write bus line Q_WTD and the read sink 0:\114\114529-980204 .doc - 13 - 1310560 Streaming line Q_BIO. By comparing the reading data during the test mode with the reading data during the normal mode, it is possible to find the fault in DBS A 405. Figure 5 shows the Figure 2 A circuit diagram of a temporary data storage unit 409 according to a second embodiment of the present invention. For example, when the test mode signal TLCHECK is activated, the temporary data storage unit 409 according to the second embodiment of the present invention is A plurality of write operations are performed in the memory device. Specifically, a plurality of write operations are performed based on an address signal from the outside. Here, the number of address signals corresponds to the number of write operations to be performed, and is temporarily The number of latch units in the data storage unit 409 also corresponds to the number of write operations to be performed. As shown, the temporary data storage unit 409 includes a data input unit 7 (H, the first shared control unit 703 and the The second shared control unit 705 and a write bus line latch unit 707. The data input unit 701 receives the write data RX_D to apply the received data to the write bus line Q_WTD. The write bus line latch unit 707 It is located on the write bus line Q_WTD and latches the write data RX_D. The first shared control unit 703 and the second shared control unit 705 share the write data applied to the write bus line Q_WTD with the read bus line Q_BIO. RX-D. In detail, the data input unit 701 includes a first inverter INV5, a first NOMS transistor N3 and a second NMOS transistor N4, and a first POMS transistor P3 and a second PMOS transistor P4. The first inverter INV5 inverts the data flag signal DSTRBP that informs the input of the data RX_D. The first NMOS transistor N3 has a gate receiving the data flag signal DSTRBP. It is connected to the first NMOS transistor N3. O:\114\114529-980204.doc • The second PMOS transistor P4 of 14-1310560 has a gate that receives the output of the first inverter INV5. The second NMOS transistor N4 connected between the first NMOS transistor N3 and the ground voltage (VSS) terminal has a gate receiving the write data rx_D. The first PMOS transistor P3 connected between the second PMOS transistor P4 and the source voltage (VDD) terminal has a gate receiving the write data rx_d. The write bus line latch unit 707 is a phase inverter latch unit including a plurality of inverters. The first shared control unit 703 includes a first NAND gate NAND2 and a second NAND gate NAND3, a first transfer gate TG2 and a second transfer gate TG3, and a first latch unit 709 and a second latch unit 711. The first NAND gate NAND2 performs a NAND operation of the test mode signal TLCHECK and the first test address signal ΤΑ-0. The second NAND gate NAND3 performs a NAND operation of the test mode signal TLCHECK and the second test address signal ΤΑ_1. The first transfer gate TG2 transfers the write data RX_D latched by the write bus line latch unit 707 in response to the output of the first NAND gate NAND2. The second transfer gate TG3 transfers the write data RX_D latched by the write bus line latch unit 707 in response to the output of the second NAND gate NAND3. The first latch unit 709 latches the write data RX_D connected to the first transfer gate TG2. The second latch unit 711 latches the write data RX_D connected to the second transfer gate TG3. The second shared control unit 705 includes a second inverter INV6 and a third inverter INV7, a third NAND gate NAND4 and a fourth NAND gate NAND5, and a third transfer gate TG4 and a fourth transfer gate TG5. The second inverter INV6 inverts the first test O:\ll4\114529-980204.doc -15- 1310560 mode signal TLCHECK0 of the self test mode definition circuit output. The third NAND gate NAND4 performs a NAND operation on the output of the second inverter INV6 and the read flag signal RDEN. The third transfer gate TG4 transfers the write data 10^_0 latched by the first latch unit 709 to the read bus line Q_BI〇 in response to the output of the third NAND gate NAND4. The third inverter INV7 inverts the second test mode signal TLCHECK1 outputted from the test mode definition circuit. The fourth NAND gate NAND5 performs the NAND operation on the output of the third inverter INV7 and the read flag signal RDEN. The fourth transfer gate TG5 transmits the write data 10 (_0) latched by the second latch unit 711 to the read bus line Q_BIO in response to the output of the fourth NAND gate NAND5. The temporary data storage unit shown in FIG. 409 is an exemplary circuit for performing a write operation twice, and thus the number of latch units (ie, two) corresponds to the number of write operations to be performed. Those skilled in the art will appreciate that The number of transfer gates, latch units, and test addresses corresponds to the number of write operations to be performed. During the test mode, the first transfer gate TG2 and the second transfer gate TG3 are turned on based on the test address signals ΤΑ_0 and TA_1. Corresponding to one, so that the corresponding latch unit holds the write data RX_D « In addition, when the first test mode signal TLCHECK0 and the second test mode signal TLCHECK1 are logic level according to the test address signals ΤΑ_0 and TA_1, "low" ", the corresponding one of the third transfer gate TG4 and the fourth transfer gate TG5 is turned on, so that the latched write data RX_D is transferred to the read bus line Q_BIO. As described above, in the present invention in The externally written data storage O:\114\114529-980204.doc 16-1310560 is stored in a temporary data storage unit connected between the write bus line Q-Wtd and the read bus line Q_BI〇. And then during the test mode for testing peripheral devices other than memory cells, the stored data is used to read and write data. Therefore, in the high frequency condition, regardless of the memory single 7L The defect 'may find the wrong operation of the peripheral device. According to the present invention, the high frequency data processing logic is used as a peripheral device (independent of the hidden unit) to effectively analyze the fault and ensure the stability of the semiconductor memory device. In addition, the duration for developing semiconductor memory devices (specifically, multi-soil memory) can be shortened, thereby increasing its competitiveness. This application contains and on September 28, 2005 and On May 8th, 6th, in the Korean Intellectual Property Office, please contact the Korean Special Funding Request No. 857 and No. 6-4U90. The full text of the case is cited by reference. Into this article. Although it has been The invention has been described in connection with certain preferred embodiments, but

習此項技術者而言，在不偏離以下中請專利範討所定義 之本發明之精神及範相情況下可進行各種改變及修正將 為顯而易見的。 【圖式簡單說明】 圖1為根據本發明之多埠記Μ裝置的方塊圖； 圖2為圖1中所s兒明的第—記憶組及第一記憶組控制邏 的詳細方塊圖； 两 圖3為圖2中所展示之根播士政αη 很據本發明之第一實施例之暫 料儲存單元的電路圖； 貝 O:\114\114529-980204.doc 1310560 圖4為圖2中所說明之讀取/寫入控制單元的電路圖；及 圖5為圖2中所展示之根據本發明之第二實施例之暫時資 料儲存單元的電路圖。 【主要元件符號說明】It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a multi-channel recording device according to the present invention; FIG. 2 is a detailed block diagram of a first memory group and a first memory group control logic of FIG. Figure 3 is a circuit diagram of the temporary storage unit according to the first embodiment of the present invention shown in Figure 2; Bay O:\114\114529-980204.doc 1310560 Figure 4 is shown in Figure 2. A circuit diagram of a read/write control unit is illustrated; and FIG. 5 is a circuit diagram of the temporary data storage unit of the second embodiment of the present invention shown in FIG. [Main component symbol description]

405 資料匯流排感測放大器（DBSA) 407 寫入驅動器 409 暫時資料儲存單元 410 解碼單元 411 讀取/寫入控制單元 413 記憶體單元 415 測試模式定義電路 417 命令解碼器 501 第一鎖存單元 503 第二鎖存單元 505 資料輸入單元 507 共用控制單元 601 寫入信號輸出單元 603 讀取信號輸出單元 701 資料輸入單元 703 第一共用控制單元 705 第二共用控制單元 707 寫入匯流排線鎖存單元 709 第一鎖存單元 711 第二鎖存單元 O:\114\114529-980204.doc -18-405 Data Bus Sense Amplifier (DBSA) 407 Write Driver 409 Temporary Data Storage Unit 410 Decoding Unit 411 Read/Write Control Unit 413 Memory Unit 415 Test Mode Definition Circuit 417 Command Decoder 501 First Latch Unit 503 Second latch unit 505 data input unit 507 common control unit 601 write signal output unit 603 read signal output unit 701 data input unit 703 first common control unit 705 second common control unit 707 write bus line latch unit 709 first latch unit 711 second latch unit O: \114\114529-980204.doc -18-

Claims (1)

1310560 --- %年&gt;月·/日修正本 、申請專利範圍： 1. 2.1310560 --- % year> month/day revision, patent application scope: 1. 2. 一種半導體記憶體裝置，其包含： 一讀取匯流排線，其用於傳送讀取資料丨 一寫入匯流排線，其用於傳送寫入資料；及 一暫時資㈣存單元，其連接於該讀取匯流排線騎 寫入匯流排線之間且受控於一在一測試模式期間 的測試模式信號。 如請求項1之半導體記憶體裝置，盆中 八甲°亥暫時資料儲存單 元包括： 且基於一 而將該所 ，用於鎖 一資料輸入單元，其用於接收該寫入資料， 指示一輸入該寫入資料之點的資料旗標信號， 接收之寫入資料施加於該寫入匯流排線； 一第一鎖存單元，其位於該寫入匯流排線上 存施加於該寫入匯流排線上的該寫入資料； 一資料傳送單元，其用於回應於該測試模式信號，而 將由該第-鎖存單元鎖存之該寫入資料傳送至；讀取: 流排線；及 ’ 一第二鎖存單元，其位於該讀取匯流排線上，用於鎖 存施加於該讀取匯流排線上的該寫入資料。 3.如請求項2之半導體記憶體裝置，其中該資料輸入單 括： t 一第一反相器，其用於使該資料旗標信號反相； 一第一NMOS電晶體，其具有—接收該資料旗標信號的 閘極； ^ O:\114\114529-980204.doc 1310560 —第一 P刪電晶體，其連接至N刪電晶體， 且具有—接收該第—反相器之—輸出的閉極； -第二麵”晶體，其連接於該第—刪巧晶體血 :接地電壓端子之間’且具有-接收該寫入資料的閑 極；及 $ -第二_s電晶體’其連接於該第一 ρΜ〇&quot;晶體與 一源電壓端子之間，且具有—接收該寫人資料的閑極。 # 4. b請求項2之半導體記憶體裝置’其中該資料傳送單元包 括-傳送閘，該傳送閘係用於回應於該測試模式信號， 而將施加於該寫入匯流排線上的該寫入資料傳送至該讀 取匯流排線。 5·如請求…之半導體記憶體裝置，其中該暫時資料健 元包括： 一資料輸入單元，其用於接收該寫入資料，以基於一 告知一輸入該寫入資料之點的資料旗標信號，而將該所 • 接收之寫入資料施加於該寫入匯流排線； 一第一鎖存單元，其位於該寫入匯流排線上，用於鎖 存施加於該寫入匯流排線的該寫入資料； 複數個第一資料傳送單元，其用於基於該測試模式信 號及來自一外部源之複數個測試位址信號，而將由該第° 一鎖存單元鎖存之該寫入資料傳送至一中間讀取匯流排 線； 複數個第二鎖存單元，其位於該中間讀取匯流排線 上，用於鎖存自該等第一資料傳送單元傳送的該寫入資 O:\114\114529-980204.doc -2- 1310560 料；及 號 第 線 個第二資料傳送單i其用於基於該測試模式信 、该等測試位址信號及一讀取旗標信號，而將由該等 -鎖存單元鎖存之該寫入資料傳送至該讀取匯流排 6.A semiconductor memory device comprising: a read bus line for transmitting read data, a write bus line for transmitting write data, and a temporary capital (four) memory unit connected to The read bus bar rides between the write bus bars and is controlled by a test mode signal during a test mode. The semiconductor memory device of claim 1, the temporary data storage unit of the occupant in the basin includes: and based on the one for the lock data input unit, for receiving the write data, indicating an input The data flag signal of the point at which the data is written, the received write data is applied to the write bus line; a first latch unit located on the write bus line and applied to the write bus line The data transfer unit is configured to transmit the write data latched by the first latch unit to the test mode signal; read: stream line; and And a second latch unit located on the read bus line for latching the write data applied to the read bus line. 3. The semiconductor memory device of claim 2, wherein the data input unit comprises: t a first inverter for inverting the data flag signal; a first NMOS transistor having - receiving The gate of the data flag signal; ^ O:\114\114529-980204.doc 1310560 - the first P-cut transistor, which is connected to the N-cut transistor, and has - receives the first-inverter - output a closed-end; - a second-sided crystal connected to the first-deleted crystal blood: between the ground voltage terminals 'and having - the idle pole receiving the written data; and $ - the second_s transistor It is connected between the first pixel and a source voltage terminal, and has a idle electrode for receiving the data of the writer. # 4. b The semiconductor memory device of claim 2, wherein the data transfer unit includes a transfer gate for transmitting the write data applied to the write bus line to the read bus line in response to the test mode signal. 5. A semiconductor memory as claimed The device, wherein the temporary data element comprises: a unit for receiving the write data to apply the received write data to the write bus line based on a data flag signal indicating a point at which the write data is input; a latch unit located on the write bus line for latching the write data applied to the write bus line; a plurality of first data transfer units for generating signals based on the test mode a plurality of test address signals of an external source, and the write data latched by the first latch unit is transferred to an intermediate read bus line; a plurality of second latch units located in the middle read Taking the bus line for latching the write resource O:\114\114529-980204.doc -2- 1310560 material transmitted from the first data transfer unit; and the second line data transfer form i The method for transmitting the write data latched by the latch unit to the read bus 6 based on the test mode signal, the test address signal, and a read flag signal. 如請求項5之半導體記憶雜裝置，其中第一及第二資料傳 1早心X及第二鎖存單元的數目制於待進行之寫入操 作的數目。 如請求項6之半導體記憶體裝置，其中該資料輸入單元包 括： -第-反相器’其用於使該資料旗標信號反相； -第-NMOS電晶體’其具有—接收該資料旗標信號的 閘極； 一第一 PMOS電晶體，其連接至該第一 NM0S電晶體， 且具有一接收該第一反相器之一輸出的閘極； 一第二NMOS電晶體，其連接於該第一 ^^厘〇8電晶體與 一接地電壓端子之間，且具有一接收該寫入資料的閘 極；及 一第二PMOS電晶體，其連接於該第一 1)河〇8電晶體與 一源電壓端子之間，且具有一接收該寫入資料的閘極。 8.如請求項6之半導體記憶體裝置’其中該等第一資料傳送 單元之每一者包括·· 一第一邏輯閘，其用於執行對該測試模式信號及該等 測試位址信號之一對應測試位址信號的一NAND運算；及 O:\114\114529-980204.doc 13l〇56〇 9. 出，而傳送由誃第.、；战弟一邏輯閘之一輸 亥第-鎖存早元鎖存的該寫入眘料。 °月’項8之半導體記憶體女’、、,、 單元之每—者包括：W其中该等第二資料傳送 反相器，其用於使該等第__眘 第—資料傳送單元傳送單元之—對應 —筮 兀之s玄苐—邏輯閘的輪出反相； —弟二邏輯閑，其用於執行該反 取旗標信號的_NAND運算；及 之輸出及該讀 —第二傳送閘，其用於 出，而傳送由該等第1存單/邏輯閘之-輸 鎖存的該寫入資料。 t應第一鎖存早疋 如凊求項1之半導體記憶 寫入批制H_ 具進—步包含一讀取/ 冩入控制早兀，該讀取/ 模式信號，而產生…Γ 用於基於該測試 義一寫入以一讀取操作的讀取信號及-定 義寫入細作的寫入信號。 請之半導體記憶體裝置’其中該讀取，寫入控制 早元包括： -寫入信號輪出單元，其用於將一寫入旗標信號延遲一 預定時間，並輸出該所延遲之信號作為該寫人信號’及 一讀取信號輪出罝 Λ ，”用於基於該蜊試模式信號及 -tn取旗標信號而輪出該讀取信號。 12_如請求項U之半導體記慢體裝置，其中該讀取旗標信號 及該寫入旗標信號係由—内部命令產生，該内部命令係 選自一具有以下命令之群：一啟用命令、-讀取命令、 O:\114\114529-980204.doc 1310560 一寫入命令及其一記憶組。 13.如請求項丨丨之半導體記憶體裝置，其中該讀取信號輪出 單元包括： 一第一反相器，其用於使該測試模式信號反相； 一邏輯閘，其用於執行該第一反相器之—輸出及該讀 取旗標信號的一NAND運算；及The semiconductor memory device of claim 5, wherein the number of the first and second data transmissions 1 and the number of second latch units is determined by the number of write operations to be performed. The semiconductor memory device of claim 6, wherein the data input unit comprises: - a first-inverter 'for inverting the data flag signal; - a first-NMOS transistor' having - receiving the data flag a gate of the target signal; a first PMOS transistor connected to the first NMOS transistor and having a gate receiving an output of one of the first inverters; a second NMOS transistor connected to Between the first transistor and a ground voltage terminal, and having a gate for receiving the write data; and a second PMOS transistor connected to the first 1) river 8 The crystal is between a source voltage terminal and has a gate for receiving the written data. 8. The semiconductor memory device of claim 6, wherein each of the first data transfer units comprises a first logic gate for performing the test mode signal and the test address signals a NAND operation corresponding to the test address signal; and O:\114\114529-980204.doc 13l〇56〇9. Out, and transmitted by 誃第.,;战弟一逻辑闸一输海第-锁The write of the early meta-lock is intentional. Each of the semiconductor memory female ', ', , and units of the item 8 includes: wherein the second data transfer inverters are configured to transmit the first data transmission unit Unit-correspondence-筮兀 s 苐 苐 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 逻辑 逻辑 ; ; ; ; ; ; ; ; ; ; ; A transfer gate is used for outputting the write data latched by the first deposit/logic gate-transfer. t should be the first latch as early as the request 1 of the semiconductor memory write batch H_ step-by-step includes a read / break control early, the read / mode signal, and generate ... Γ for The test writes a read signal with a read operation and a write signal that defines a write operation. The semiconductor memory device is configured to include: - a write signal rounding unit for delaying a write flag signal for a predetermined time and outputting the delayed signal as The write signal 'and a read signal round out 罝Λ , ' is used to rotate the read signal based on the test mode signal and the -tn flag signal. 12_The semiconductor record body of claim U The device, wherein the read flag signal and the write flag signal are generated by an internal command selected from the group consisting of: an enable command, a read command, an O:\114\ 114529-980204.doc 1310560 A write command and a memory group thereof. 13. The semiconductor memory device of claim 1, wherein the read signal turn-out unit comprises: a first inverter for making The test mode signal is inverted; a logic gate is configured to perform an output of the first inverter and a NAND operation of the read flag signal; and 一第二反相器，其用於使該邏輯閘之一輸出反相以輸 出該讀取信號。 如請求項11之半導體記憶體裝置，其中該寫入信號輸出 單元包括一延遲電路，該延遲電路包括偶數個反相器。 如請求項1之半導體記憶體裝置，其中該讀取匯流排線係 連接於複數個資料匯流排感測放大器之間，該複數個放 大器放大該讀取資料且將該已放大之資料輸出至一外部 裝置。 16.如請求…之半導體記憶體裝置’其中該寫入匯流排線係 連接於複數個寫入驅動器之間，該複數個寫入驅動器將 該寫入資料傳送至一記憶體單元。 Π.如請求項1之半導體記憶體裝置，其中該測試模式信號係 由一定義測試模式的測試模式定義電路基於—外部測試 模式設定所產生。 18. —種多埠記憶體裝置，其包括複數個埠，每—淳執行一 獨立操作，該多埠記憶體裝置包含： 複數個記憶組；及 複數個記憶組控制邏輯電路’其用於控制介於全域ι/〇 O:\114\114529-980204.doc 1310560 …亥等記憶組之間的一信號傳輸， 目其中記憶組控制邏輯電路之數目對應於記憶組之數 邊電跃~夕埠。己1*體裝置經組態以在高頻狀況下測試周 过、，而不考慮-記憶體單元之缺陷。 項18之多埠記憶體裝置，其中該等記憶組控制邏 輯電路之每一者包括：A second inverter for inverting one of the logic gate outputs to output the read signal. The semiconductor memory device of claim 11, wherein the write signal output unit comprises a delay circuit comprising an even number of inverters. The semiconductor memory device of claim 1, wherein the read bus line is connected between a plurality of data bus sense amplifiers, the plurality of amplifiers amplify the read data and output the amplified data to a External device. 16. A semiconductor memory device as claimed in claim </ RTI> wherein the write bus line is coupled between a plurality of write drivers, the plurality of write drivers transferring the write data to a memory unit. The semiconductor memory device of claim 1, wherein the test mode signal is generated by a test mode definition circuit defining a test mode based on an external test mode setting. 18. A multi-layer memory device comprising a plurality of ports, each performing an independent operation, the multi-turn memory device comprising: a plurality of memory groups; and a plurality of memory group control logic circuits for controlling A signal transmission between memory groups such as the global ι/〇O:\114\114529-980204.doc 1310560 ..., where the number of memory group control logic circuits corresponds to the number of memory groups of the memory group . The 1* device is configured to test the cycle under high frequency conditions without regard to the defect of the memory cell. The memory device of item 18, wherein each of the memory group control logic circuits comprises: 命令解碼器，其用於接收—内部命令，並產生―言志 旗‘ t5虎及一寫入旗標信號；及 a柳試模歧義電路，其用於基於—外部測試模式設 疋而產生-定義-測試模式之測試模式信號。 2〇.如請求項18之多埠記憶體裝置，其中該等記憶組之每一 者包括： 複數個資料匯流排感測放大器，其連接至一讀取匯流 排線，用於放大並輸出自該記憶體單元輸出之讀取資料； 複數個寫入驅動器，其連接至一寫入匯流排線，用於 執行一寫入操作； 一暫時資料儲存單元，其用於共用該讀取匯流排線與 該寫入匯流排線之間的資料，並基於該測試模式信號暫 時地保存該資料；及 一讀取/寫入控制單元，其用於將該寫入旗標信號延遲 一預定時間，以產生一用於控制該等寫入驅動器的寫入 ^被並接收該讀取旗標信號’以產生—用於控制該等 貢料匯流排感測放大器的讀取信號。 21.如請求項20之多埠記憶體裝置，其中該等記憶組之每一 O:\114\114529-980204.doc l3l〇56〇 步包括一解竭單元，該解碼單元係用於解碼該讀 一旗標信號及該寫入旗標信號，以驅動該記憶體單元之 特定字線，並產生—用於酿私 ^ 用於驅動一特定行電晶體的信 5亥特定行電晶體係用於遠接一a - ^ ^, 巾於運接位兀線與一區段輸入/ 輸出（I/O)線。 一月求項20之多埠δ己憶體裝置，其中該暫時資料儲存單 元包括： t—資料輸人單元’其用於接收—寫人資料，以基於_ 心--輪入該寫入資料之點的資料旗標信號，而將該所 接收之寫入資料施加於該寫入匯流排線； -第-鎖存單元’其位於該寫入匯流排線上，用於鎖 存施加於該寫入匯流排線上的該寫入資料； 一資料傳送單元，其用於回應於該測試模式信號，而 將由該第一鎖存單元鎖存之該寫入資料傳送至該讀取匯 流排線；及 -第二鎖存單元’其位於該讀取匯流排線上，用於鎖 存施加於该項取匯流排線上的該寫入資料。 23.如請求項22之多埠記憶體裝置，其中該資料輸入單元包 括： 一第-反相器’其用於使該資料旗標信號反相； -第-NMOS電晶體，其具有—接收該資料旗標信 閘極； 一第一 PMOS電晶體，其連接至該第一 NM〇s，晶體， 且具有一接收該第一反相器之一輸出的閘極； O:\114\114529-980204.doc 1310560 一第二NM0S電晶體，其連接於該第一NM〇S電晶體鱼 一接地電壓端子之間，且具有—接收該寫人資料的間 極；及 一第二PMOS電晶體，其連接於該第一PMOS電晶體邀 -源電壓端子之間’且具有一接收該寫入資料的閑極。、 24. 如請求項22之多埠記憶體裝置，其中該資料傳送單元包 括一傳送閘，該傳送閘制於回應於該測試模式信號， # 而將施加於該寫入匯流排線上的該寫入資料傳送至該讀 取匯流排線。 25. 如請求項20之多埠記憶體褒置，其中該暫時資料 元包括： 一資料輸入單元’其用於接收該寫入資料，以基於一 輸入該寫入資料之點的資料旗標信號，而將該所 之寫入資料施加於該寫入匯流排線； 帛鎖存單兀’其位於該寫入匯流排線上 •存施加於該寫入匯流排線的該寫入資料； 、鎖 ::個第-資料傳送單元，其用於基於該測 號及來自-外部源之複數個測試位址信號、； 線；…鎖存之該寫入資料傳送至一中間讀取匯流排 複數個第-ϋ七 上，用』二元，其位於該中間讀取匯流排線 料；及、存自該等第一資料傳送單元傳送的該寫入資 複數個第二資料傳送單元，其用於基於該測試模式信 O:\114\114529-980204.doc !310560 號、該等測試位址信號及一讀取旗標信號，而將由該等 第二鎖存單元鎖存之該寫入資料傳送至該讀取匯流排 線。a command decoder for receiving an internal command and generating a "word" flag and a write flag signal; and a test mode ambiguity circuit for generating based on an external test mode setting - Defines the test mode signal for the test mode. 2. The memory device of claim 18, wherein each of the memory groups comprises: a plurality of data bus sense amplifiers coupled to a read bus line for amplifying and outputting The memory unit outputs read data; a plurality of write drivers connected to a write bus line for performing a write operation; and a temporary data storage unit for sharing the read bus line And the data written between the bus bars, and temporarily storing the data based on the test mode signal; and a read/write control unit for delaying the write flag signal for a predetermined time to A write signal is generated for controlling the write drivers and the read flag signal 'is generated to generate a read signal for controlling the tributary bus sense amplifiers. 21. The memory device of claim 20, wherein each of the memory groups of the memory group comprises a depletion unit, the decoding unit is for decoding the Reading a flag signal and the write flag signal to drive a specific word line of the memory unit, and generating a signal for driving a specific row of transistors In the distance of a - ^ ^, the towel is connected to the line and an input/output (I/O) line. In the first month of the present invention, the temporary data storage unit comprises: t-data input unit 'for receiving-writing data, based on _ heart--taking the written data a data flag signal of the point, and applying the received write data to the write bus line; - a first latch unit located on the write bus line for latching the write The write data on the incoming bus line; a data transfer unit for transmitting the write data latched by the first latch unit to the read bus line in response to the test mode signal; and a second latch unit 'which is located on the read bus line for latching the write data applied to the bus bar. 23. The memory device of claim 22, wherein the data input unit comprises: a first-inverter 'for inverting the data flag signal; - a first-NMOS transistor having - receiving The data flag signal gate; a first PMOS transistor connected to the first NM〇s, crystal, and having a gate receiving an output of one of the first inverters; O:\114\114529 - 980204.doc 1310560 a second NMOS transistor connected between the first NM 〇S transistor fish-ground voltage terminal and having a terminal for receiving the write data; and a second PMOS transistor It is connected between the first PMOS transistor invite-source voltage terminal 'and has a idle pole for receiving the write data. 24. The memory device of claim 22, wherein the data transfer unit includes a transfer gate that is responsive to the test mode signal, and wherein the write is applied to the write bus line The incoming data is transferred to the read bus. 25. The memory device of claim 20, wherein the temporary data element comprises: a data input unit for receiving the write data based on a data flag signal inputting a point at which the data is written And writing the written data to the write bus line; 帛 latching unit 其 'which is located on the write bus line □ storing the write data applied to the write bus line; a data transmission unit for transmitting a plurality of test address signals based on the measurement number and from the external source, the line; the latch, the write data to an intermediate read bus, and the plurality of - on the seventh, using "dual", which is located in the middle to read the bus bar material; and the plurality of second data transfer units stored in the first data transfer unit, which are used for The test mode letter O:\114\114529-980204.doc !310560, the test address signal and a read flag signal, and the write data latched by the second latch unit is transmitted to The read bus line. 如請求項25之多埠記憶體裝置，其中第一及第二資料傳 送單元以及第二鎖存單元的數目之每一者對應於待進行 之寫入操作的數目。 如請求項26之多埠記憶體裝置，其中該資料輸入單元包 括： 一第一反相器，其用於使該資料旗標信號反相； 一第一NMOS電晶體，其具有一接收該資料旗標信號的 閘極； —第一PMOS電晶體，其連接至該第一 NM〇s電晶體， 且具有—接收該第一反相器之一輸出的閘極； 第一 NMOS電晶體，其連接於該第一 nm〇s電晶體與 接地電壓端子之間，且具有一接收該寫入資料的閘 極；及 第一 PMOS電晶體，其連接於該第一 pM〇s電晶體與 源電壓端子之間，且具有一接收該寫入資料的閘極。 28·如》青求項26之多埠記憶體裝置，其中該等第一資料傳送 單元之每一者包括： 一第一邏輯閘，其用於執行對該測試模式信號及該等 測試位址信號之一對應測試位址信號的一 nand運算；及 一第一傳送閘，其用於回應於該第一邏輯閘之一輸 出，而傳送由該第一鎖存單元鎖存的該寫入資料。 O:\114\114529-980204.doc -9- 1310560 29.如請求項28之多埠記憶體裝置，其 單元之每一者包括： 第一貝料傳送 -反相ϋ ’其用於使料第―f料傳送 第-資料傳送單元之第一邏輯間的該輸出反相.對應 邏輯閘’其用於執行減心之—輸出及 取旗才示#號的一 NAND運算，·及 〆。賣 一第二傳送閉’其用於回應於該第二邏輯間之 出，而傳送由該等第-雜左〇β - Λ m 牙疋w ^寻弟—鎖存早兀之一對應第二 鎖存的該寫入資料。 早7 3〇·如請求項20之多埠記憶體裝置，其中該讀取/寫入控 元包括： -寫入信號輸出單元’其用於將該寫入旗標信號延遲該 預定時間，並輸出該所延遲之信號作為該寫人信號；及 一讀取信號輸出單元，其用於基於該測試模式信號及 該蟥取旗標信號而輸出該讀取信號。 31. 如請求項30之多埠記憶體裝置，其中該讀取信號輸出單 元包括： 一第一反相器，其用於使該測試模式信號反相； 邏輯閘，其用於執行該第一反相器之一輸出及該讀 取旗標信號的一NAND運算；及 一第二反相器，其用於使該邏輯閘之一輸出反相以輸 出該讀取信號。 32. 如請求項30之多埠記憶體裝置，其中該寫入信號輸出單 元包括一延遲電路，該延遲電路包括偶數個反相器。 O:\114\114529-980204.doc •10· 1310560 如咕求項20之多埠記憶體裝置，其中該讀取匯流排線係 連，於複數個資料匯流排感測放大器之間，該複數個放 大器放大该讀取資料且將該所放大之資料輸出至一外部 裝置。 34.如4求項2〇之多蟑記憶體裝置，其中該寫人匯流排線係 連接於該複數個寫入驅動器之間，該複數個“驅動器 將该寫入資料傳送至該記憶體單元。The memory device of claim 25, wherein each of the number of the first and second data transfer units and the second latch unit corresponds to the number of write operations to be performed. The memory device of claim 26, wherein the data input unit comprises: a first inverter for inverting the data flag signal; a first NMOS transistor having a receiving the data a gate of the flag signal; a first PMOS transistor connected to the first NM〇s transistor and having a gate receiving an output of one of the first inverters; a first NMOS transistor Connected between the first nm 〇s transistor and the ground voltage terminal, and has a gate for receiving the write data; and a first PMOS transistor connected to the first pM 〇s transistor and the source voltage Between the terminals, and having a gate for receiving the written data. 28. The memory device of claim 26, wherein each of the first data transfer units comprises: a first logic gate for performing the test mode signal and the test addresses One of the signals corresponds to an nand operation of the test address signal; and a first transfer gate for transmitting the write data latched by the first latch unit in response to an output of the first logic gate . O:\114\114529-980204.doc -9- 1310560 29. The multi-chassis memory device of claim 28, each of the units comprising: a first beech transfer-reverse ϋ 'which is used to make a material The output of the first logic of the first-data transfer unit is inverted. The corresponding logic gate is used to perform a NAND operation of the subtraction-output and the flag-out ##. Selling a second transmission closed' for responding to the second logical interval, and transmitting by the first-hetero-left 〇β - Λ m 疋 w ^ seeking brother - latching one of the early 对应 corresponds to the second The written data is latched. 7. The memory device of claim 20, wherein the read/write control element comprises: - a write signal output unit for delaying the write flag signal by the predetermined time, and And outputting the delayed signal as the write signal; and a read signal output unit for outputting the read signal based on the test mode signal and the captured flag signal. 31. The memory device of claim 30, wherein the read signal output unit comprises: a first inverter for inverting the test mode signal; and a logic gate for performing the first One of the inverter outputs and a NAND operation of the read flag signal; and a second inverter for inverting one of the logic gate outputs to output the read signal. 32. The memory device of claim 30, wherein the write signal output unit comprises a delay circuit comprising an even number of inverters. O:\114\114529-980204.doc •10· 1310560 For example, the memory device of the item 20, wherein the read bus line is connected, between the plurality of data bus sense amplifiers, the plural The amplifier amplifies the read data and outputs the amplified data to an external device. 34. The memory device of claim 4, wherein the write bus is connected between the plurality of write drivers, and the plurality of "drivers transfer the write data to the memory unit . O:\I14\114529-980204.doc 1310560 七、 指定代表圖： (一) 本案指定代表圖為：第（2 )圖。 (二) 本代表圖之元件符號簡單說明： 405 資料匯流排感測放大器（DBSA) 407 寫入驅動器 409 暫時資料儲存單元 410 解碼單元 411 讀取/寫入控制單元 φ 413 記憶體單元 415 測試模式定義電路 417 命令解碼器 八、 本案若有化學式時，請揭示最能顯示發明特徵的化學式： (無）O:\I14\114529-980204.doc 1310560 VII. Designated representative map: (1) The representative representative of the case is: (2). (2) A brief description of the component symbols of this representative diagram: 405 Data Bus Sense Amplifier (DBSA) 407 Write Driver 409 Temporary Data Storage Unit 410 Decoding Unit 411 Read/Write Control Unit φ 413 Memory Unit 415 Test Mode Definition Circuit 417 Command Decoder 8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: (none) O:\114\114529-980204.docO:\114\114529-980204.doc
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