1310227 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體裝置及其製造方法，詳言之， 係一種具有凸起氧化阻絕層及自我對準閘極之半導體裝置 及其製作方法。 【先前技術】 為了達到尚積集畨度、尚速度以及低成本，傳統金氧半 鲁％效電晶體已進入了奈米世代，然而傳統金氧半場效電晶 體會遭遇到嚴重的超短通道效應（ultra_sh〇rtchannei effect，USCE)，也就是所謂的門梭電壓（thresh〇ld讀age) roll-off以及汲極感應的能障下降（drain induced ba^ier 1〇wering，mBL)效應。此外傳統bulk_cmos亦有PN接面 . I生電容過大以及嚴重的漏電流問題m緣（Silicon_ cm-insulator，S0I)技術似乎可同時改善傳統bulk_cm〇s 所遭遇的問題。然:而傳統妙覆絕緣卻也面臨了嚴重的超短 • 通道效應，以及各種元件所面臨的自我對準（self-aligned) 問題。若要進-步取得較佳的元件次臨界特性，傳統石夕覆 絕緣之本體厚度必要進-步的縮小，否則會造成嚴重超短 通道效應。 國内關於傳統矽覆絕緣的專利於同時解決諸如：超短通 道效應與自我對準的方法並不多。如台灣專利申請號第 9123110號’其係採用逆增式濃度通道掺雜法，來抑制短 —mit效應，此法是用摻雜方法來改f通道濃度；台灣專利 .巾請號第86115832號’其雖可克服超短通道效應，然而卻 111440.doc 1310227 無法解決自我對淮es ^ 宁罕問通；及美國專利申請號第10/989,639 :Ί用自我調整好的薄膜碎化物，可減少短 應’卻沒有自我對準的閉極。 因此有必要提供一種創新且具進步性之具有凸起氧 我對準開極之半導體裝置及其製造方法，以解 決上述問題。 【發明内容】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a raised oxide barrier layer and a self-aligned gate and a method of fabricating the same . [Prior Art] In order to achieve the enthusiasm, speed and low cost, the traditional MOS-semiconductor has entered the nano generation, but the traditional MOS half-effect transistor will encounter severe ultra-short channels. The effect (ultra_sh〇rtchannei effect, USCE), also known as the threshold-voltage (thresh〇ld read) roll-off and the drain induced ba^ier 1〇wering (mBL) effect. In addition, the traditional bulk_cmos also has a PN junction. The excessive capacitance of the I and the serious leakage current problem (Silicon_cm-insulator, S0I) technology seem to improve the problems encountered by the traditional bulk_cm〇s. However, traditional insulation is also faced with severe ultra-short • channel effects and self-aligned problems faced by various components. In order to achieve better subcritical characteristics of the component, the thickness of the body of the traditional Shihua overlying insulation must be reduced in steps, otherwise it will cause severe ultra-short channel effects. Domestic patents on traditional enamel insulation have not solved many methods such as ultra-short channel effects and self-alignment. For example, Taiwan Patent Application No. 9123110's adopts a reverse-increasing concentration channel doping method to suppress the short-mit effect. This method uses a doping method to change the f channel concentration; Taiwan Patent No. 86115832 'Although it can overcome the ultra-short channel effect, yet 111440.doc 1310227 can't solve the self-to-Huai es ^ Ninghan Wentong; and US Patent Application No. 10/989,639: Using self-adjusting film shreds, can reduce Short should be 'there is no self-aligned closed pole. It is therefore necessary to provide an innovative and progressive semiconductor device with raised oxygen that is aligned with open electrodes and a method of manufacturing the same to solve the above problems. [Summary of the Invention]
本發明之目的在於提供—種具有凸起氧化阻絕層及自我 對準閘極之半導體裝置。該半導體裝置包括一基板、一氧 邑：-矽覆絕緣層、一矽層、一閘極氧化層及一閘 極。該氣化阻絕層形成於該基板上，該氧化阻絕層係為_ 凸起結構。該石夕覆絕緣層具有一源極及-没極，且分別形 成於該乳化阻絕層之二側邊，該石夕覆絕緣層及該氧化阻絕 層形成一凹陷部。該矽層形成於該氧化阻絕層及該矽覆絕 緣層上。_極氧化層形成於㈣層上。該閘極形成於該 閘極氧化層上，且位於該凹陷部上方之相對位置。 本發明之另—目的在於提供—種具有凸起氧化阻絕層及 自我對準閘極之半導體裝置之製造方法。該製造方法包 括.（a)提供一基板；（b)形成—第一氧化層於該基板上；（匀 形成一矽覆絕緣層於該第一氧化層上，該矽覆絕緣層具有 一槽口；⑷形成一第二氧化層於該槽口 β，相對於垂直 該基板表面方向，該第二氧化層係為一凸起結構，該第一 氧化層及該第二氧化層形成—氧化阻絕層，該氧化阻絕層 及該矽覆絕緣層形成一凹陷部；（句形成一矽層於該第二氧 lll440.doc 1310227 匕層及該矽覆絕緣層± ; (f)形&一閘極氧化層於該矽層 上；（g)形成一閘極於該閘極氧化層上，該閘極位於該凹陷 部上方之相對位置；及（h)形成一源極及 一汲極。 本發明該半導體裝置之製造方法，可利用職【 CMOS、S0I、TFT等傳統技術製造，本發明之該半導體裝 置可藉由該氧化阻絕層之該第二氧化層，同時阻隔源極部 及汲極部PN接面寄生電容及接面漏電流。並且，該矽層之 φ 厚度可非常薄，故可有效抑制超短通道效應。再者，該矽 層與材質為單晶矽之源極部及汲極部’在高溫製程中會自 動以固相再結晶，故品質較為可靠。另外，本發明之該閘 極氧化層具有一微凹區域，以使該閘極具有完全自我對準 - <功效。因此，本發明之該半導體裝置不只克服元件微縮 • 化所面臨的超短通道效應，且可達成完全自我對準之功 效，故可使得該半導體裝置之性能及穩定性大幅的提升。 【實施方式】 _ 配合參考圖1至圖9，其顯示本發明具有凸起氧化阻絕層 及自我對準閘極之半導體裝置之製造方法之示意圖。參考 圖1，首先k供一基板11，在該實施例中，該基板11係選 自石夕（Si)、錯（Ge)、玻璃、塑膠或ΠΙ_ν族晶圓基板。接 著’形成一第一氧化層12於該基板11上。接著，形成一石夕 覆絕緣層13於該第一氧化層12上。參考圖2，於該矽覆絕 緣層13形成一槽口 130 ’該槽口 130暴露部分該第一氧化層 - 12。在該實施例中，該槽口 130係利用光罩方法或以邊襯 ' (spACER )技術形成硬光罩再蝕刻而成。 111440.doc 1310227 參考圖3，地毯式沉積一第二氧化層14於該第一氧化層 12及該矽覆絕緣層13上。參考圖4，以化學機械研磨方法 移除部分該第二氧化層14，在該實施例中係以該矽覆絕緣 層13當化學機械研磨之終止層，使得該第二氧化層14大略 與該矽覆絕緣層13等高並暴露出該矽覆絕緣層丨3。移除部 /7該第一氧化層14後，該第二氧化層存在於該槽口 130 内’且相對於垂直該基板11表面方向，該第二氧化層14係 φ 為一凸起之結構。 參考圖5至圖7’於該第一氧化層14之頂部形成一凹陷部 141 ’該凹陷部141係形成於該槽口 n〇上之相對位置。在 該實施例中，該凹陷部141係利用溼式蝕刻方法將該第二 氧化層14往下蝕刻，再地毯式沈積一第三氧化層22於該矽 • 覆絕緣層13及該第二氧化層14上，接著再以活性離子蝕刻 该第三氧化層22，直到暴露出該矽覆絕緣層13及部分該第 二氧化層14而形成。該第一氧化層12、該第二氧化層14及 _ 該第—氧化層22形成-氧化阻絕層} 5。該氧化阻絕層} 5係 為一 β起結構。 參考圖8,形成一矽層丨6於該第二氧化層14、該矽覆絕 緣層13及該第三氧化層22上。該矽層16之材質可選自非晶 矽或多晶矽。在該實施例中，該矽層16係利用化學氣相沉 積方法形成，且所沉積之該石夕層16之厚度可非常薄。該矽 層16具有一第一微凹區域161，該第—微㈣⑹㈣位於 該凹陷部141上方之相對位置。 參考圖9,形成1極氧化層17於财㈣上，在該實 U\440.doc 1310227 施例中’遠閘極氧化層17係利熱氧化方法或化學沈積法形 成。該閘極氧化層17係選自由二氧化矽、氮化矽、氧氮 氧、空氣腔或其他高介電係數材質所組成之群組。該閘極 氧化層17具有一第二微凹區域m，該第二微凹區域171係 形成於該第一微凹區域161上。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having a raised oxide barrier layer and a self-aligned gate. The semiconductor device includes a substrate, an oxide: a germanium insulating layer, a germanium layer, a gate oxide layer, and a gate. The gasification barrier layer is formed on the substrate, and the oxidation barrier layer is a _ convex structure. The stellite insulating layer has a source and a finite electrode, and is respectively formed on two sides of the emulsification barrier layer, and the stellite insulating layer and the oxidative barrier layer form a depressed portion. The tantalum layer is formed on the oxide barrier layer and the overlying insulating layer. The _ pole oxide layer is formed on the (four) layer. The gate is formed on the gate oxide layer and is located at a relative position above the recess. Another object of the present invention is to provide a method of fabricating a semiconductor device having a raised oxide barrier layer and a self-aligned gate. The manufacturing method includes: (a) providing a substrate; (b) forming a first oxide layer on the substrate; (forming a blanket insulating layer on the first oxide layer, the buffer insulating layer having a groove (4) forming a second oxide layer in the notch β, the second oxide layer is a convex structure with respect to a direction perpendicular to the surface of the substrate, and the first oxide layer and the second oxide layer form an oxidation block a layer, the oxidized barrier layer and the ruthenium-clad insulating layer form a depressed portion; (the sentence forms a 矽 layer in the second oxidized layer ll 440.doc 1310227 匕 layer and the 矽 绝缘 insulating layer ±; (f) shape & a pole oxide layer is on the germanium layer; (g) a gate is formed on the gate oxide layer, the gate is located at a position above the recess; and (h) a source and a drain are formed. The method for fabricating the semiconductor device can be manufactured by using a conventional technology such as CMOS, SOI, or TFT. The semiconductor device of the present invention can block the source portion and the drain electrode by the second oxide layer of the oxidation barrier layer. The parasitic capacitance of the PN junction and the leakage current of the junction, and the φ of the 矽 layer The thickness can be very thin, so it can effectively suppress the ultra-short channel effect. Moreover, the enamel layer and the material of the single-crystal 矽 source and the drain portion will automatically recrystallize in the high-temperature process, so the quality is relatively high. Further, the gate oxide layer of the present invention has a dimpled region to make the gate fully self-aligned - <Efficacy. Therefore, the semiconductor device of the present invention not only overcomes the component shrinkage The ultra-short channel effect and the self-alignment effect can be achieved, so that the performance and stability of the semiconductor device can be greatly improved. [Embodiment] _ With reference to FIGS. 1 to 9, it is shown that the present invention has a bump. A schematic diagram of a method of fabricating an oxide device and a semiconductor device for self-aligned gates. Referring to FIG. 1, first, a substrate 11 is provided, and in this embodiment, the substrate 11 is selected from the group consisting of Shi Xi (Si) and Ge (Ge). a glass, plastic or germanium-based wafer substrate. Then a first oxide layer 12 is formed on the substrate 11. Next, a layer of insulating layer 13 is formed on the first oxide layer 12. Referring to Figure 2, The cover The edge layer 13 defines a notch 130' that exposes a portion of the first oxide layer-12. In this embodiment, the notch 130 is formed using a photomask method or a side liner (spACER) technique to form a hard light. The cover is etched again. 111440.doc 1310227 Referring to Figure 3, a second oxide layer 14 is deposited on the first oxide layer 12 and the overlying insulating layer 13. Referring to Figure 4, the chemical mechanical polishing method is used to remove a portion of the second oxide layer 14, in this embodiment, the termination layer of the chemically mechanically grounded insulating layer 13 such that the second oxide layer 14 is substantially equal to the insulating layer 13 and exposes the layer After the insulating layer 丨3 is removed. After the first oxide layer 14 is removed, the second oxide layer is present in the notch 130 and is opposite to the surface of the substrate 11. The second oxide layer 14 is φ is a raised structure. A recessed portion 141' is formed on the top of the first oxide layer 14 with reference to FIG. 5 to FIG. 7'. The recessed portion 141 is formed at a position opposite to the notch n〇. In this embodiment, the recessed portion 141 is etched down by the wet etching method, and a third oxide layer 22 is deposited on the insulating layer 13 and the second oxide. On the layer 14, the third oxide layer 22 is then etched with active ions until the overlying insulating layer 13 and a portion of the second oxide layer 14 are exposed. The first oxide layer 12, the second oxide layer 14, and the first oxide layer 22 form an oxidized barrier layer. The oxidized barrier layer 5 is a β-structure. Referring to Fig. 8, a tantalum layer 6 is formed on the second oxide layer 14, the overlying insulating layer 13, and the third oxide layer 22. The material of the germanium layer 16 may be selected from amorphous germanium or polycrystalline germanium. In this embodiment, the tantalum layer 16 is formed by a chemical vapor deposition method, and the thickness of the deposited layer 16 can be very thin. The ruthenium layer 16 has a first dimple region 161, the first micro (four) (6) (four) being located at a relative position above the recess portion 141. Referring to Fig. 9, a 1-pole oxide layer 17 is formed on the fourth (fourth), and in the embodiment of the U.S. Patent Application Serial No. 4,102,227, the remote gate oxide layer 17 is formed by a thermal oxidation method or a chemical deposition method. The gate oxide layer 17 is selected from the group consisting of cerium oxide, cerium nitride, oxynitride, air chambers or other high dielectric constant materials. The gate oxide layer 17 has a second dimple region m formed on the first dimple region 161.
參考圖10，形成一多晶矽層18於該閘極氧化層17上。參 考圖11，利用活性離子蝕刻方法蝕刻多晶矽層丨8，以形成 一殘餘晶種19。該晶種19形成於該閘極氧化層π之該第二 微凹區域171之角落或中間上（在該實施例為形成於該第 二微凹區域171之二角落）。參考圖12，利用選擇性磊晶成 長製程（selective epitaxial growth)成長該晶種19，以形成 一閘極20。因為該閘極氧化層17具有該第二微凹區域 171，故在磊晶成長製程形成該閘極2〇時，該閘極2〇即可 於該第二微凹區域171中成長，因此不需要再一額外光罩 之步驟，即可達到完全自我對準之功效。 參考圖13，形成一離子佈植用散射氧化層21於該閘極2〇 ，該閘極氧化層17上。在該實施例中，該離子佈植用散射 氧化層21係利用化學氣相沉積方法形成。最後，再以離子 佈植方式於該⑦覆絕緣層13和㈣層16上形成—源極ΐ3ι 阻絕層 及一汲極132,以製作完成本發明之具有Λ起氧化 及自我對準開極之半導體I置1。該源極131及該沒極132 覆蓋該槽σ13_之部分該第三氧化層22。該源極ΐ3ι及該 沒極132之間界定—本體133，且該源極ΐ3ι與該本體⑴里 有-源極ΡΝ接面134’且該波極132與該本體134具有一： 111440.doc 1310227 極PN接面135。其中，該㈣16與材f為單晶該源極 131及該汲極132密合，在高溫製程中會自動固相再結晶， 故品質較為可靠。 要/〜的;I:在孩具有凸起氧化阻絕層及自我對準閘極 之半導體裝置1之後，亦可依不同應用之需求選擇性地 將該離子佈植用散射氧化層21移除。 再參考圖13 ’其顯示本發明第—實施例具有凸起氧化阻 _ ，絕層及自我對準閘極之半導體裝置之示意圖。該第一實施 例之半導體裝置1包括—基板U、一氧化阻絕層。、一矽 覆絕緣層13、一石夕層16、—閘極氧化層17、—閘極2〇及— 離子佈植用散射氧化層21。該基板丨丨係選自矽（si)、鍺 (Ge)、玻璃、塑膠或爪-v族晶圓。該氧化阻絕層^形成於 該基板11上，該氧化阻絕層15係為一凸起結構。該氧化阻 絕層15由下而上具有一第—氧化層12及—第二氧化層14及 一第三氧化層22。相對於垂直該基板丨丨表面方向，該第二 _ I化層14係為-凸起之結構’該第三氧化層22形成於該第 二氧化層14上，且暴露部分該第二氧化層14，以形成一凹 陷部14 h 該矽覆絕緣層13及該矽覆絕緣層13上相對位置之部分該 矽層16界定一源極131及一汲極132，亦即，該源極131及 該汲極132分別形成於該第二氧化層14之二側邊，且覆蓋 部分該第三氧化層14。該源極π!及該汲極132間之該矽層 16界疋一本體133，該源極131與該本體133具有一源極pn 接面134，且該汲極132與該本體133具有一汲極1>1^接面 111440.doc • 11 - 1310227 135。在該實施例中，該矽覆絕緣層13之高度略高且大略 相同於該氧化阻絕層15之該第三氧化層22之高度。該石夕居 16形成於該第二氧化層14、該碎覆絕緣心及該第三氧二 層22上。該石夕層16係為非晶石夕，或該矽層16亦可：多晶 矽。在該實施例中’該矽層16係利用化學氣相沉積方：: 成，且所沉積之該矽層16之厚度可非常薄。該矽層“具有Referring to FIG. 10, a polysilicon layer 18 is formed on the gate oxide layer 17. Referring to Fig. 11, the polysilicon layer 8 is etched by a reactive ion etching method to form a residual seed crystal 19. The seed crystal 19 is formed at a corner or an intermediate portion of the second dimple region 171 of the gate oxide layer π (in this embodiment, formed at two corners of the second dimple region 171). Referring to Fig. 12, the seed crystal 19 is grown by selective epitaxial growth to form a gate 20. Since the gate oxide layer 17 has the second dimple region 171, when the gate electrode 2 is formed by the epitaxial growth process, the gate electrode 2 can grow in the second dimple region 171, so A further reticle step is required to achieve full self-alignment. Referring to Fig. 13, an ion implantation scattering oxide layer 21 is formed on the gate electrode 2, the gate oxide layer 17. In this embodiment, the ion implantation scattering oxide layer 21 is formed by a chemical vapor deposition method. Finally, a source ΐ3ι barrier layer and a drain 132 are formed on the 7-insulating layer 13 and the (4) layer 16 by ion implantation to form the oxidized and self-aligned opening of the present invention. The semiconductor I is set to 1. The source 131 and the dipole 132 cover a portion of the third oxide layer 22 of the trench σ13_. The source ΐ3ι and the immersion 132 define a body 133, and the source ΐ3ι has a source-source junction 134' in the body (1) and the wave 132 and the body 134 have a: 111440.doc 1310227 Pole PN junction 135. Wherein, the (four) 16 and the material f are single crystals, the source electrode 131 and the drain electrode 132 are closely adhered, and the solid phase is recrystallized automatically in a high temperature process, so that the quality is relatively reliable. I/O; I: After the semiconductor device 1 having a raised oxide barrier layer and a self-aligned gate, the ion implantation scattering oxide layer 21 can be selectively removed according to the needs of different applications. Referring again to Fig. 13', there is shown a schematic view of a semiconductor device having a raised oxidation resistance, a gate layer and a self-aligned gate in accordance with a first embodiment of the present invention. The semiconductor device 1 of the first embodiment includes a substrate U and an oxidation barrier layer. An insulating layer 13, a layer 16, a gate oxide layer 17, a gate electrode 2, and a scattering oxide layer 21 for ion implantation. The substrate is selected from the group consisting of bismuth (si), germanium (Ge), glass, plastic or claw-v wafers. The oxidative barrier layer is formed on the substrate 11, and the oxidized barrier layer 15 is a convex structure. The oxidized barrier layer 15 has a first oxide layer 12 and a second oxide layer 14 and a third oxide layer 22 from bottom to top. The second oxidized layer 14 is a bulged structure with respect to a direction perpendicular to the surface of the substrate, and the third oxide layer 22 is formed on the second oxide layer 14 and exposes a portion of the second oxide layer. And forming a source portion 131 and a drain electrode 132, that is, the source electrode 131 and the portion of the insulating layer 13 and the opposite portion of the insulating layer 13 The drain electrodes 132 are respectively formed on two sides of the second oxide layer 14 and cover a portion of the third oxide layer 14. The source layer π! and the germanium layer 16 between the drain electrodes 132 are bounded by a body 133. The source electrode 131 and the body 133 have a source pn junction 134, and the drain 132 and the body 133 have a Bungee 1>1^ junction 111440.doc • 11 - 1310227 135. In this embodiment, the height of the insulating insulating layer 13 is slightly higher and substantially the same as the height of the third oxide layer 22 of the oxidized barrier layer 15. The Shishiju 16 is formed on the second oxide layer 14, the broken insulating core, and the third oxygen double layer 22. The layer 16 is amorphous, or the layer 16 may be polycrystalline germanium. In this embodiment, the ruthenium layer 16 is formed by chemical vapor deposition, and the thickness of the ruthenium layer 16 deposited can be very thin. The layer "has
-第-微凹區域161 ’該第一微凹區域161係位於該凹陷部 14 1上方之相對位置。 該閘極氧化層17形成於财層16上。該閘極氧化層㈣ 選自由二氧化石夕、氮化石夕、氧氮氧、空氣腔或其他高介電 係數材質所組成之群組。該閘極氧化層17具有一第二微凹 區域171 ’該第二微凹區域171係形成於該第一微凹區域 161上。該閘極20形成於該閘極氧化層17之該第二微凹區 域171上。該閘極氧化層17之該第二微凹區域ΐ7ι ,可使該 閘極20自然地形成於該第二微凹區域171中，故具有完全 自我對準之功效。該離子佈植用散射氧化層21形成於該閘 極20及該間極氧化層17上。要注意的是，依不同應用之需 求，亦可選擇性地將該離子佈植用散射氧化層21移除。 本發明該半導體裝置之製造方法，可利用bulk_ CMOS、SOI、TFT等傳統技術製造，本發明之該半導體裝 置1可藉由該氧化阻絕層15，同時阻隔該源極PN接面！ 34及 該汲極PN接面135寄生電容及接面漏電流。並且，該矽層 Μ之厚度可非常薄，故可有效抑制超短通道效應。 再者’該石夕層16與材質為單晶矽之該源極131及該汲極 111440.doc 1310227 132密合，在高溫製程中會自動固相.再結晶，故品質較為 可靠。另夕卜’本發明之該閘極氧化層17具有該第二微凹區 域17卜故可使該閘極具有完全自我對準之功效。因此， 本發明之該半導體裝置1不只克服元件微縮化所面臨的超 短通道效應’且可達成完全自我對準之功效，故可使得該 半導體裝置1之性能及穩定性大幅的提升。 二實施例具有凸起氧化阻絕 置之示意圖。該第二實施例The first dimple region 161' is located at a relative position above the recess portion 141. The gate oxide layer 17 is formed on the financial layer 16. The gate oxide layer (4) is selected from the group consisting of sulphur dioxide, nitrite, oxygen, nitrogen, air, or other high dielectric material. The gate oxide layer 17 has a second dimple region 171' which is formed on the first dimple region 161. The gate 20 is formed on the second dimple region 171 of the gate oxide layer 17. The second dimple region ΐ7ι of the gate oxide layer 17 allows the gate 20 to be naturally formed in the second dimple region 171, thereby providing full self-alignment. The ion implantation scattering oxide layer 21 is formed on the gate 20 and the inter-electrode oxide layer 17. It is to be noted that the ion implantation scattering oxide layer 21 can also be selectively removed depending on the needs of the different applications. The method for fabricating the semiconductor device of the present invention can be fabricated by conventional techniques such as bulk_CMOS, SOI, TFT, etc., and the semiconductor device 1 of the present invention can block the source PN junction by the oxidation blocking layer 15 at the same time! 34 and the drain PN junction 135 parasitic capacitance and junction leakage current. Moreover, the thickness of the tantalum layer can be very thin, so that the ultrashort channel effect can be effectively suppressed. Furthermore, the stone layer 16 is closely adhered to the source 131 of the single crystal germanium and the drain 111440.doc 1310227 132, and is automatically solid phased and recrystallized in a high temperature process, so that the quality is relatively reliable. Further, the gate oxide layer 17 of the present invention has the second dimple region 17 so that the gate electrode has a completely self-aligned effect. Therefore, the semiconductor device 1 of the present invention can overcome the ultra-short channel effect faced by the device miniaturization and achieve full self-alignment effect, so that the performance and stability of the semiconductor device 1 can be greatly improved. The second embodiment has a schematic diagram of a convex oxidative barrier. This second embodiment
參考圖14’其顯示本發明第 層及自我對準閘極之半導體裝 之半導體裝置3包括一基板31、—氧化阻絕層& 一矽覆 絕緣層33、-石夕層34、一閘極氧化層35、—閘極^及一離 子佈植用散射氧化層37。該第二實施例之半導體裝置3與 上述該第一實施例之半導體裝置〖不同之處在於，在該第 二實施射，係僅制澄絲刻方法直接㈣該氧化阻絕 層32，蝕刻後之該氧化阻絕層32之高度低於二侧邊之該矽 覆絕緣層33之高度，使該氧化阻絕層32及該矽覆絕緣層^ 形成一凹陷部。其餘步驟與上述該第一實施例㈣，在此 不加以贅述。 該第二實施例之半導體裝置3同樣具有上述該第一實施 例之半導體裝置1所具有之功效。另外，因為未來之半導 體兀*件之體積越趨微小，故欲在氧化阻絕層形成一凹陷部 更加困難。該第二實施例之半導體裝置3之氧化阻絕層係 直接利用蝕刻方式，使蝕刻後之該氧化阻絕層3 2之高度低 於忒矽覆絕緣層3 3之高度，以形成一凹陷部，因此更可因 應於未來更微小化之半導體元件之需求。 H1440.doc -13- 1310227 惟上述實施例僅為說明本發明之原理及其功效，而非用 以限制本發明。因此，習於此技術之人士對上述實施例進 行修改及變化仍不脫本發明H本發明之權利範圍應 如後述之申請專利範圍所列。 【圖式簡單說明】 圖1顯示本發明矽覆絕緣基板之示意圖； 圖2顯示本發明於矽覆絕緣基板形成一槽口之示意圖； 圖3顯示本發明形成一第二氧化層之示意圖； 圖4顯示本發明移除部分該第二氧化層之示意圖； 圖5顯示本發明再蝕刻部分該第二氧化層之示意圖； 圖6顯示本發明形成一第三氧化層之示意圖； 圖7顯示本發明移除部分該第三氧化層之示意圖； 圖8顯示本發明形成一矽層於該矽覆絕緣基板及該第二 氧化層上之示意圖； 圖9顯示本發明形成一閘極氧化層於該矽層上之示竟 圖， 圖10顯示本發明形成一多晶矽層於該閘極氧化層上之示 意圖， 圖11顯示本發明形成一晶種之示意圖； 圖12顯示本發明形成一閘極之示意圖； 圖13顯不本發明帛-實施例具有凸起氧化i絕層及自我 對準閘極之半導體裝置之示意圖；及 圖14顧示本發明第二實施例具有凸起氧化阻絕層及自我 對準閘極之半導體裝置之示意圖。 111440.doc •14- 1310227 【主要元件符號說明】Referring to FIG. 14', a semiconductor device 3 including a first layer and a self-aligned gate of the present invention includes a substrate 31, an oxide barrier layer, an insulating layer 33, a layer 34, and a gate. The oxide layer 35, the gate electrode, and the scattering oxide layer 37 for ion implantation. The semiconductor device 3 of the second embodiment is different from the semiconductor device of the first embodiment described above in that, in the second embodiment, only the wire-cutting method is directly performed (four) the oxidation-resistant layer 32, after etching The height of the oxidized barrier layer 32 is lower than the height of the insulating layer 33 on the two sides, so that the oxidized barrier layer 32 and the smear insulating layer are formed into a depressed portion. The remaining steps are the same as the first embodiment (4) described above, and are not described herein. The semiconductor device 3 of the second embodiment also has the effects of the semiconductor device 1 of the first embodiment described above. In addition, since the volume of the future semiconductor 兀* is becoming smaller, it is more difficult to form a depressed portion in the oxidized barrier layer. The oxidation blocking layer of the semiconductor device 3 of the second embodiment is directly etched so that the height of the oxidized barrier layer 3 2 after etching is lower than the height of the insulating layer 33 to form a depressed portion. It can also meet the needs of semiconductor components that are more miniaturized in the future. H1440.doc -13- 1310227 The above examples are merely illustrative of the principles of the invention and its utility, and are not intended to limit the invention. Therefore, those skilled in the art will be able to modify and change the above-described embodiments without departing from the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a covered insulating substrate of the present invention; FIG. 2 is a schematic view showing a notch formed on a covered insulating substrate of the present invention; FIG. 3 is a schematic view showing the formation of a second oxide layer according to the present invention; 4 is a schematic view showing a portion of the second oxide layer removed by the present invention; FIG. 5 is a schematic view showing a second etching layer of the present invention; FIG. 6 is a schematic view showing the formation of a third oxide layer of the present invention; FIG. 8 is a schematic view showing the formation of a germanium layer on the insulating substrate and the second oxide layer; FIG. 9 is a view showing the formation of a gate oxide layer on the germanium layer. FIG. 10 is a schematic view showing the formation of a polycrystalline germanium layer on the gate oxide layer of the present invention, FIG. 11 is a schematic view showing the formation of a seed crystal of the present invention; FIG. 12 is a schematic view showing the formation of a gate according to the present invention; Figure 13 is a schematic view showing a semiconductor device having a bump oxide layer and a self-aligned gate; and Figure 14 shows a second embodiment of the present invention having a convex oxidation barrier Self semiconductor device and a schematic diagram of aligned gate electrode. 111440.doc •14- 1310227 [Main component symbol description]
1 本發明第一實施例具有凸起氧化阻絕層及自 我對準閘極之半導體裝置 3 本發明第二實施例具有凸起氧化阻絕層及自 我對準閘極之半導體裝置 11 基板 12 第一氧化層 13 石夕覆絕緣層 14 第一氧化層 15 氧化阻絕層 16 層 17 閘極氧化層 18 多晶$夕層 19 晶種 20 閘極 21 離子佈植用散射氧化層 22 第三氧化層 31 基板 32 氧化阻絕層 33 矽覆絕緣層 34 石夕層 35 閘極氧化層 36 閘植 37 離子佈植用散射氧化層 111440.doc •】5_ 1310227 130 槽口 131 源極 132 汲極 133 本體 134 汲極部與本體間之PN接面 135 源極部與本體間之PN接面 141 凹陷部 161 第一微凹區域1 A semiconductor device having a bump oxide barrier layer and a self-aligned gate according to a first embodiment of the present invention. A second embodiment of the present invention has a bump oxide barrier layer and a self-aligned gate semiconductor device 11 substrate 12 first oxidation Layer 13 Insulation layer 14 First oxide layer 15 Oxidation barrier layer 16 Layer 17 Gate oxide layer 18 Polycrystalline layer 19 Seed crystal 20 Gate 21 Ion implantation scattering oxide layer 22 Third oxide layer 31 substrate 32 Oxidation barrier layer 33 矽 insulation layer 34 Shixi layer 35 gate oxide layer 36 sluice 37 ion scattering scattering oxide layer 111440.doc •] 5_ 1310227 130 notch 131 source 132 bungee 133 body 134 bungee PN junction 135 between the body and the body PN junction 141 between the source and the body, the recess 161, the first dimple
171 第二微凹區域171 second dimple area
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