TWI310187B - Semiconductor memory device - Google Patents

Description

1310187 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor memory device, and more particularly to a method for controlling a row decoder for use in a memory bank The technique of body bias, a large amount of open leakage current (〇ff_leakage current) appears in the row decoder. [Prior Art] Since the dynamic random access memory (DRAm) device employs a memory cell each constructed of an electric B body and a capacitor, it has a great integration advantage over other memory device devices. In addition, DRAM devices have advanced in terms of operating speed because various technologies have been proposed in accordance with recent high speed requirements. Therefore, a dram device having advanced driving capability even at a low voltage has been developed, and in addition, the DRAM device has been gradually extended to applications such as electric devices for consuming lower power and main memory of automobiles and computers. However, due to the high level of integration of semiconductor memory devices, it has become increasingly difficult to implement low standby currents, where ensuring low standby current means minimizing the off leakage current of each device. 1 is a diagram showing the break of each component calculated by summing the widths of transistors present in each of the components of a semiconductor memory device (eg, a memory bank, a voltage generator, and peripheral circuits). A table of open drain current values. The open leakage currents appearing in the memory group, the voltage generator, and the peripheral circuits are 40.2 μΑ, 6 2 μΑ && _, respectively. In short, the total width of the transistor and therefore the off-leakage current in the semiconductor memory device is mostly occupied by the transistor assigned to the memory group. The maximum width and maximum of the memory group are occupied by the decoder. The leakage current is disconnected, and in addition, as can be seen from Figure 2, the open drive current of one of the final drive units of the row decoder and one of the first 觝 觝 山 山 鈪42 8% of the off leakage current that appears in this memory group. Figure 2 shows a simulation result of the off-leakage current level of each element obtained by generating an off-leakage current in each element of the memory group. # From the simulation results, it can be seen that the off-leakage current generated by the row decoder occupies more than the above. Figure 3 illustrates a detailed circuit diagram of a conventional row decoder 5 in a semiconductor memory device. The conventional row decoder 5 includes a pre-drive unit 丨 and a drive unit 2. The pre-drive unit i has a PMOS transistor pi & nm 〇s transistors N1 to N3 connected in series between a power supply terminal vdd and a ground voltage terminal VSS. The PMOS transistor 卩1 and the 电8 transistor have a common gate, and a control signal Βγρ is provided via the common gate, and the control signal 脉冲 is a pulse signal containing memory group information. In addition, it has a common drain which acts as an output node of the pre-drive unit 以 to output a status output nickname to the drive unit 2. The NM〇s transistors Ν2 and Ν3 respectively receive code signals yc〇d1 and YC〇D2 via their gates, wherein each of the code numbers YCOD1 and YCOD2 has a memory cell containing a semiconductor memory device A row of corresponding memory cells of a plurality of memory cells in the matrix 3 is exhausted. 114725.doc 1310187 The driving unit 2 has a PMOS transistor P2 and an NMOS transistor N4 connected in series between the power voltage terminal vdd and the ground voltage terminal VSS. The PMOS transistor P2 and the NMOS transistor N4 have a common gate serving as an input node of the driving unit 2 and a common gate serving as a wheel node of the driving unit 2. The input node of the drive unit 2 is coupled to the output node of the pre-drive unit 以 to receive a status output signal from the pre-drive unit 1. If a certain condition is satisfied as described later, the drive unit 2 generates a corresponding row selection signal (e.g., γί〇) to the memory cell matrix 3. The row selection signal Yi 〇 indicates the address of the corresponding cell in the memory cell matrix 3 which is jointly represented by the two code signals YCOD1 and YCOD2. The PMOS transistors P1 & P2 receive the power supply voltage via their bodies and the NMOS transistors N1 to N4 receive the ground voltage vss via their bodies. In order to form a memory bank, a plurality of the above-described assembled row decoders are required and thus a plurality of row selection signals (e.g., TM to Yin) are outputted to the memory cell matrix 3, η being a positive integer. The pre-drive unit 1 receives the code signals YC〇D 1 and YCOD2 required for row selection and selects the row decoders, and the input signals of the enabled state (10), such as logic high level, YCOD i and YC〇D2 To the one, a corresponding row select signal is enabled thereby, for example, Yi. When the row access operation for row selection is not performed, the control L number 6丫1> has a disabled state 'for example, a logic low level, thereby setting the row selection signal Yi to the disabled state. For example, the logic is low. On the other hand, 'Tian Zhixuan' is used to enable the control signal BYP to the logic high level when the row access operation is selected. When the (4) signal Βγρ is enabled, if the code signal corresponding to the line decoding 114725.doc 1310187 D„ has an enabled state, then the certain line decodes the pre-drive single-open!, a few i' so that the drive unit 2 is turned on. The PMOS transistor P2, enables the row select signal Yi0 and outputs it to the memory cell matrix 3. : In the row decoder by controlling the occurrence of a substantial amount of open leakage current therein, the disconnection in the semiconductor § memory device The present invention provides a method for reducing and total disconnecting @current by controlling a decoder in which a maximum amount of % open leakage occurs. Semiconductor Memory Body Device - Embodiments of the Invention - Embodiments - A semiconductor memory device for selectively controlling the voltage level of the source voltage of a row of decoders, thereby improving the operating speed. In one aspect of the invention, a semiconductor memory device is provided, comprising: a memory cell matrix comprising a plurality of memory cells; φ - < D decoding unit 纟 having a row position for responding to a memory cell containing material Selecting a plurality of lines of the memory cells to selectively activate the plurality of lines of the memory information, wherein each of the four decoders includes - for returning the equal code signal to provide a power supply voltage and a source a pre-drive unit for outputting a signal between voltage transitions, and a drive unit for returning a state turn-off signal and rotating a row of select signals to activate one of the memory cells, wherein the pre-drive unit and the Each of the driving units includes at least one PMOS transistor and at least one NMOS transistor, respectively receiving a pumping voltage and a reverse bias via a body thereof, the pumping voltage having a height of 114725.doc 1310187 a voltage level at a voltage level of the power supply voltage, and the reverse bias voltage has a voltage level lower than a voltage level of a ground voltage. According to another aspect of the present invention, a semiconductor memory device is provided The basin comprises: 〃 a plurality of memory groups, each of the plurality of memory groups having: a memory cell matrix having a plurality of memory cells, and having a row position for responding to the memory cells a code signal of the address information to selectively activate a row decoding unit of the plurality of row decoders of the memory cells, wherein each of the row decoders includes - for returning an equal code signal to provide a a pre-drive unit for outputting a state between the power supply dust and a source voltage, and a drive unit for outputting a row of selection signals for responding to the status output signal to activate the unit: the corresponding drive unit, wherein Each of the pre-drive unit and the driver unit includes at least one PMOS transistor and at least a -nm 〇s transistor. The transistors receive a pumping voltage and a reversed dust through their bodies respectively. The electric iridium has a higher electric Φ Μ level than the electric power level of the power supply I and the reverse bias M has a voltage level lower than the electromigration level of the grounding electric rush; The source unit of the source pole a is provided to the plurality of memory groups, and the power level of the source voltage changes in accordance with an operation mode of the memory groups. According to still another aspect of the present invention, a semiconductor memory device is provided, comprising: a plurality of memory groups, each of the plurality of memory groups having: a memory cell matrix having a plurality of memory cells, one having Each of the memory cells is selectively activated in response to a code signal containing the address information of 114725.doc -9- 131.0187:: the read code (four) line decoding unit, each of the towel row decoders a pre-drive unit for returning a status signal output between a supply voltage and a source, and an output-line selection signal for starting the memory cell The driver's single drive 70', the pre-driver single s and the drive unit package 3 to J__PM〇S transistor and at least one transistor,

The electric body cutter receives a pumping voltage through its body and a reverse bias voltage having a voltage level higher than a voltage level of the power supply voltage and the reverse bias has a lower than a ground The voltage level of the voltage level of the voltage; and providing a plurality of primal voltage control units & corresponding to the source voltage to the plurality of memory groups, the voltage levels of the source voltages are regarded as the memory groups The mode of operation varies from place to place. [Embodiment] A semiconductor memory device according to a specific embodiment of the present invention includes a line decoding early and a memory cell matrix, wherein the row decoding unit includes a plurality of row decoders. Figure 4 provides a circuit diagram of a row of decoders 1 and a memory cell matrix. The row decoder 10 includes a pre-drive unit u and a drive unit 12. The pre-drive unit 丨丨 has a pM 〇s transistor P3 and NMOS transistors N5 to N7 connected in series between a supply voltage terminal vdd and a node receiving the voltage source control signal NSRC. The voltage source control signal NSR(: has a voltage level of a ground voltage VSS or a reverse bias voltage VBB, wherein the reverse bias 114725.doc -10- 1310187 voltage VBB voltage level is lower than the ground voltage VSS The PMOS transistor P3 and the NMOS transistor N5 have a common gate receiving a control signal BYP, and the control signal BYP is a pulse signal containing memory group information. In addition, it has a common drain. The common drain serves as an output node of the pre-drive unit 11 to output a state output signal to the drive unit 12. The NMOS transistors N6 and N7 are coupled to the code signals YCOD1 and YCOD2 via their gates, respectively, and the code signals are YCOD1 and YCOD2 have a code containing a row address information of a corresponding memory cell of a plurality of memory cells in the memory cell matrix 20. The driving unit 12 has a series connection between the power supply voltage terminal VDD and a ground voltage terminal VSS. a PMOS transistor P4 and an NMOS transistor N8. The PMOS transistor P4 and the NMOS transistor N8 have a common gate serving as an input node of the driving unit 12 and an output node serving as the driving unit 12. The driving unit 12 receives the status output signal via the input node connected to the output node of the pre-drive unit 11 and outputs a row of selection signals Yi to the memory cell matrix 20. The row selection signal Yi is used to select the memory cell matrix. Corresponding memory cells represented by two code signals YCOD1 and YCOD2 in 20. The pumping voltage VPP is supplied to the main body of the PMOS transistors P3 and P4, and the NMOS transistors N5 to N8 receive the reverse bias voltage VBB via their bodies, The voltage level of the pumping voltage VPP is higher than the electric power level of the power supply voltage VDD.

In order to form a memory bank, a plurality of the above-described assembled row decoders are required, and in addition, one or more row selection signals YiO 114725.doc 11 - 1310187 to Yin to the memory cell matrix 20 are supplied from the plurality of row decoders. The activation of the pre-drive unit 11 is determined based on whether the codes of the code signals YCOD1 and YCOD2 required for the row selection are identical to each other and have an enabled state. If the codes of the two code signals YCOD1 and YCOD2 are identical to each other and are at a logic high level, the pre-drive unit 11 is activated. A corresponding row decoder (e.g., 10) is then selected from the plurality of row decoders such that a corresponding row select signal (e.g., YiO) is enabled and output from the drive unit 12. In particular, when the row access operation for row selection is not performed, the control signal BYP is disabled to a logic low level, thereby setting the row selection signal Yi to the logic low level. On the other hand, when the row access operation for row selection is performed, the control signal BYP is enabled to a logic high level. Under the condition that the control signal BYP is enabled, if the codes of the code signals YCOD1 and YCOD2 of the row decoder 10 have a logic high level, the pre-drive unit 11 is activated, so that the PMOS transistor P4 of the driving unit 12 is turned on, and row selection is enabled. Signal YiO is provided to the memory cell matrix 20. In the row decoder 10 of the present invention, the PMOS transistors P3 and P4 receive the pumping voltage VPP as the body bias voltage, the voltage level of the pumping voltage VPP is higher than the voltage level of the power source voltage VDD, and the NMOS transistor N5 The reverse bias voltage VBB is received as a body bias to N8, and the voltage level of the reverse bias voltage VBB is lower than the voltage level of the ground voltage VSS. Further, the NMOS transistor N7 receives the source voltage control signal NSRC having the voltage level of the ground voltage VSS or the reverse bias voltage VBB via its source. Figure 5 provides a comparison chart of the off leakage currents present in one example of the inventive row decoder 10 and the conventional row decoder 5. 114725.doc •12· The Zhixing decoder exhibits a drop in leakage as a power supply and has an off-leakage current of approximately -540 pA at approximately 1.8V.

1310187 As can be seen from the comparison chart, the off-leakage current supply voltage VDD as a function of the voltage VDD has a decoding J per line. For the inventive row decoder i Q, the source voltage control signal NSRC is assumed to have a grounding Mvss The voltage level, the pumping voltage vpp represents 33 V ' and the fox has a high temperature of 85 C. The characteristic of the leakage current in the 纟 is obviously compared with the Bai Zhixing decoder as a function of the power supply voltage. The off-leakage current is sufficiently reduced and the variation in the characteristics of the off-leakage current is minimal. Therefore, it should be understood that the present invention can advantageously control the body bias of the row decoder ig by using the pumping voltage vpp and the reverse bias voltage, so that the characteristics of the off leakage current can be improved. 6 shows a diagram of a memory group of a semiconductor memory device including an Av rs on - ding decoding early 兀 、 ', the memory cell matrix 20 and a source voltage control unit 70 30 'where the line is depleted Single heart, with multiple line decoders. The source voltage control single i 3G receives the column active signal (10) machine to provide the source voltage control signal lobes to the row decoding unit 1 〇 |, according to the column signal ROWb ^ inactive mode (aetive mGde) or standby mode The source voltage control signal NSRC has a ground state or a reverse bias MB. The source voltage control unit 30 is disposed on the wires of the ground voltage VSS and the reverse bias voltage VBB. In the case of inputting to the logic low level in the memory group 1 , the action signal R 〇 Wb of the action of the s sell or write face has, for example, indicating that a certain column is selected to perform the normal mode; In another condition in which the column signal R 〇 Wb has, for example, a logic high level, this indicates a standby mode in which the precharge 114725.doc -13 - 1310187 electrical operation is performed. In the active mode or the source voltage is to be controlled, as shown in FIG. 4, the state of the signal ROWb (ie, in the mode), the switching source voltage control unit 3 is fed by the signal NSRC. In the row decoding unit 10, for example, in the source of the NMOS transistor 1^7 of the pre-drive unit 11 of the row decoder 10.

The source of the NMOS transistor N7 of the pre-drive unit u is controlled based on the source voltage control signal NSRC, and the pumping voltage vpp and the bias voltage VBB are respectively applied to the body of the PMOS transistor P3 and the NM 〇s transistor ns to Μ? In each subject. Then, if the row decoding unit 1 〇, a certain row decoder, such as the 'row decoder 10', is enabled, the row selection signal γ 〇 指示 indicating the address of the corresponding memory cell represented by the two code signal generations (10) and YCOD2 is enabled. And coupled to the memory cell matrix 20. Figure 7 depicts a circuit diagram of the source voltage control unit 3 of Figure 6 including a bit shifter 〇evei shifter 3i and a voltage select unit 32. The level shifter 3 1 performs a level shift on the column active signal R 〇 Wb to generate an active signal ACTb. The voltage level of the active signal ACTb is alternately at the power supply voltage VDD and the reverse bias voltage VBB. Swing between. The voltage selection unit 32 has NMOS transistors N9 and N10 and - an inverter ινι and a capacitor (::1 and (:2;; ^^〇8 transistor N9 connected to the ground voltage terminal VSS and an output of the source voltage control) An active signal ACTb is received between the output nodes of the signal NSRC and via its gate. The NMOS transistor N1 is coupled between a reverse bias terminal that provides the reverse bias voltage VBB and the output node, and The gate receives an inactive active signal iACTb output from the inverter IV1. The capacitor (: is a parasitic capacitor between the reverse bias terminal and the ground terminal 114725.doc • 14· 131.0187 voltage terminal, and the capacitor IIC2 is a parasitic capacitor existing between the output node and the ground voltage terminal, wherein the capacitor ^ is generally selected to have a capacitance greater than several hundred to several thousand times the capacitance of the capacitor C2. The source is described with reference to the operation timing diagram of FIG. The operation of the voltage control unit 3. First, in the standby mode, both the column active signal R〇wb and the active signal ACTb have the voltage level of the power supply voltage VDD. Therefore, the NMOS transistor is turned on. N9 and disconnecting the NM〇s transistor N1 〇, thereby outputting the source electrical control signal NSR having the voltage level of the power supply voltage VDD (:. As a result, the input mode wipes the input power with the ground voltage vss The source voltage of the M level is controlled by the NSRC to the row decoder 〇 in the pre-drive unit 。. On the other hand, in the active mode, the level shifter 3 1 performs the ## ROWb in the column action The level shifts to output the active signal ACTb, wherein the column active signal ROWb has a voltage level of the ground voltage vss, and thus the active signal ACTb becomes the voltage level of the reverse bias voltage VBB. At this time, because the capacitor C1 The capacitance is greater than the capacitance of the capacitor (^ is hundreds to thousands of times, so the level offset may be ignored. Thereafter, the NM〇s transistor N9 is turned off and the NMOS transistor Nio is turned on, whereby the output has a reverse bias The source voltage control signal NSRC of the voltage level of VBB is pressed. As a result, in the active mode, the source voltage control signal NSRC having the voltage level of the reverse bias voltage VBB is input to the pre-drive unit of the row decoder 1 11. In the case, when the row decoder 10 is changed When the body bias is applied to reduce the off-leakage current, the threshold voltage of each of the connected transistors in the row decoder 10 becomes high, and thus the driving force thereof is lowered, resulting in a decrease in the operating speed. To overcome this problem 114725.doc 15 In the problem of 1310187, the present invention uses the source voltage control signal NSRC, so that when the column SELb is enabled to the logic low level in the column action, that is, in the active mode, the input source has the reverse bias VBB source control signal NSRc Up to the source of the NMOS transistor N7 in the pre-drive unit 11. As a result, the PMOS transistor P4 of the drive unit 12 receives a selective negative (four) via its gate, that is, grounded „vss or reverse biased, And therefore there can be sufficient driving force to improve the operating speed due to the deterioration of the open leakage current.

Thus, according to the present invention, it is possible to achieve a low power in the standby mode and a high operating speed in the active mode. Fig. 9 is a view showing a comparison chart of the row selection signals generated by the inventive row decoder 1 and the conventional row decoder source based on the source of the NSRC. Referring to Fig. 9, wherein the horizontal axis refers to time, and the vertical axis refers to the lamp selection signal voltage 'should be noted that when the source mode is controlled in the active mode, i5 i^NSRC: has a reverse bias voltage VBB When the voltage level is normal, the row selection signal has the fastest rising characteristic. Figure 4 - Figure 4 - A diagram of a semiconductor memory device for a source electrostatic dust control soap element in accordance with a particular embodiment of the present invention. The circuit of Figure 6 has only the source voltage control unit for the memory bank 10G and the circuit of the ® I 1G includes a plurality of source voltage control units 30A for a plurality of memory banks. Multiple source (four) control unit 胤 output source voltage control signal NS song G: 3 > m access to all memory groups 2 〇〇 A. Figure U is a diagram of a semiconductor memory device with a source voltage control unit in accordance with another particular embodiment of the present invention. The circuit of Figure U is similar to the circuit of Figure 1 except that there is a single source lH725.doc -16-1310187 voltage control unit 3OB for several memory banks 200B. Therefore, a logic gate AND (and) is used, so that when at least one of the column active signals R 〇 wb < 0: 3 > 2 is enabled, the source voltage control signal NSRC is level shifted to the voltage of the reverse bias voltage VBB. Level and coupled to all memory groups 2〇〇b. In the exemplary configuration of Fig. 11, since the circuit is constructed only by a source voltage control unit 3B which is structurally identical to the source voltage control unit of Fig. 7, it is possible to minimize the layout size. In particular, the circuit of Figure n is advantageously used in the case where the capacitor C1 employed has a capacitance greater than several hundred to several thousand times the capacitance of the capacitor C2. Figure 12 shows a block diagram of a reverse bias generator connected to a source voltage control unit in accordance with the present invention. The reverse bias generator 60 includes a reverse bias (VBB) detecting unit such as a VBB generating unit 50. The VBB detecting unit 40 receives the reverse bias voltage fed back from the VBB generating unit 5, and detects the voltage level of the feedback vbb based on a reference voltage VRC, thereby rotating an enable signal VEN, wherein the reference The voltage vrc has a voltage level that is substantially opposite to an ideal reverse bias. The VBB generates a single turn 50 to generate a reverse bias voltage VBB whose voltage level is adjusted to be enabled by the enable signal VEN. The side generating unit 5() outputs the reverse dusting VBB to the source voltage control unit 3'. The reverse bias generator 60 is used to prevent the voltage level of the reverse bias voltage VBB from changing. As can be seen from the above description, the present invention controls the body bias for the row decoder in which the maximum amount of off-leak current occurs, resulting in an open leakage current occurring in the semiconductor device 114725.doc 17 1310187 u body 4 The total amount is reduced, and in addition, the voltage level of the voltage source control signal applied to the pre-driver unit of the row decoder is selectively applied to improve the access operation speed. Although the present invention has been shown and described with respect to the preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the following claims. . [Simple description of the map]

=1 is a table showing the breaking leakage current of each memory component calculated by summing the widths of the transistors present in each of several components used in a semiconductor memory device; Breaking the leakage current simulation result; Figure 2 shows the breaking leakage current level of each component obtained by each of the memory groups. Figure 3 is a circuit diagram of a conventional row decoder; Figure 5 provides a comparison chart of the off-leakage currents present in a row decoder and a conventional row decoder in accordance with an embodiment of the present invention. Figure 6 shows an inventive line of the solution. A block diagram of a source voltage control unit in accordance with another embodiment of the present invention; FIG. 7 depicts a circuit diagram of the source voltage control unit of FIG.

Figure 8 shows a source voltage control unit according to the present invention. Figure 9 provides a comparative diagram of the inventive solution (4) with a #一^J number; a selection of Figure 10 depicts a source using a specific embodiment according to the present invention. Electrical 114725.doc -18· 1310187 The semiconductor memristor of the pressure control unit is a diagram of a semiconductor memory device using a re-specific embodiment according to the invention; and FIG. 12 shows a method according to the invention - Block diagram. The side of the reverse bias generator of the π Court example [Main component symbol description]

1 Pre-emphasis area early element 2 drive unit 3 memory cell matrix 5 conventional line decoder 10 (inventive) row decoder 10 · row decoding unit 11 pre-drive unit 12 drive unit 20 memory cell matrix 30 source voltage control unit 30 Source voltage control unit 30 Β source voltage control unit 31 level shifter 32 voltage selection unit 40 reverse bias (VBB) detection single 50 VBB generation unit 60 reverse bias generator 100 memory group 114725.doc 19 · 1310187 2 0 0 A Memory Group 200B Memory Group

114725.doc -20-

Claims (1)

1310187 X. Patent application scope: 1 . A semiconductor memory device, comprising: a memory cell matrix comprising a plurality of memory cells; a row of decoding units having a code signal responsive to information of row address information of the memory cells; Selectively activating a plurality of row decoders of the memory cells, wherein each of the row decoders comprises: a state in which a code signal should be equalized to provide a transition between a supply voltage and a source voltage a pre-drive unit for outputting a signal; and a drive output unit that outputs a row of select signals to activate a corresponding one of the memory cells, wherein each of the pre-drive unit and the drive unit includes at least one PMOS a transistor and at least one NM0S transistor for receiving a pumping voltage and a reverse bias via a body thereof, the pumping voltage having a voltage level higher than a voltage level of the power source voltage And the reverse bias has a voltage level lower than a voltage level of a ground voltage. 2. The semiconductor memory device of claim 1, wherein the pre-drive unit comprises: a first PMOS transistor connected between a terminal of the power supply voltage and a first wheel-out node, the state output signal system And outputting through the first output node; and a plurality of NMOS transistors connected in series between the first output node and one of the source voltage terminals, wherein the first PMOS transistor and the NM〇s transistors One of them receives a control signal from its common gate via H4725.doc 1310187 to activate the row of decoding units, and the remaining NMOS transistors receive the code signals via their gates, respectively. 3. The semiconductor memory device of claim 2, wherein the driving unit comprises: a second PMOS transistor connected between the terminal of the power supply voltage and a second output node, the row selection signal is via the Two output nodes output; and An NMOS transistor connected between the second output node and one of the ground voltage terminals, wherein the second PMOS transistor and the NMOS transistor receive the state output signal via their common gate. 4. The semiconductor memory device of claim 3, wherein the source voltage has a level of the ground voltage. 5. The semiconductor memory device of claim 3, further comprising: a source M control unit for providing the source voltage, wherein the source of the electric gate is aligned with the operation of the semiconductor memory device a mode in which the source voltage control unit is level-shifted to produce the column-effect t-signal indicating the semiconductor memory device as claimed in π, wherein the element comprises: - for receiving a column of active signals and generating The level shifter of the active signal, the operating mode; and the choice of the Φ i for the source of the electric dust, the electric power to 4 冤靥, the early 兀, the source 麈 7. The active signal is determined. The semiconductor memory device of the item 6 of the month, the middle of the 广 广 广 赵 衣 衣 该 该 电压 电压 电压 电压 电压 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 a first transistor connected between the terminal of the source voltage and the terminal of the ground voltage and controlled by the active signal; and the terminal connected to the source voltage and one of the reverse bias A second transistor between the terminals and controlled by a signal in the opposite phase. 8. The semiconductor memory device of claim 7, wherein the first transistor is turned on to provide the ground to the terminal of the source voltage when the signal is in the mode. 9. The semiconductor memory device of claim 8, wherein when the signal is in the active mode, the second transistor is turned on to provide the reverse bias to the terminal of the source voltage . 10. The semiconductor memory device of claim 7, further comprising: a reverse bias generator comprising: a voltage tilting unit for receiving the reverse bias and based on a reference reverse bias And detecting a voltage level of the reverse bias, thereby outputting an enable signal; and an electric dust generating unit for the reverse bias of the production line and outputting the reverse bias to the source voltage control The unit, the voltage level of the reverse bias is adjusted back to the enable signal. The semiconductor memory device of claim 7, wherein the voltage selection unit further comprises: a first capacitor, which is a parasitic capacitor existing between the terminal of the reverse bias and the terminal of the ground voltage And 114725.doc 1310187 a second capacitor, a double helmet exists between the terminal of the source voltage and the terminal of the ground voltage" wherein one of the first capacitors is larger than the second capacitor The capacitor 13 is π. The semiconductor memory of the request item η is set, wherein the capacitance of the first capacitor number is greater than the capacitance of the second capacitor by several hundred to several thousand times. A semiconductor memory device comprising: φ a plurality of memory groups, each of the plurality of memory groups comprising: a memory cell matrix having a plurality of memory cells; - a lamp decoding early element having a code for responding to row address information containing the memory cells And selectively driving a plurality of row decoders of the memory cells, wherein each of the row decoders comprises: - a back should be equal to the code signal provided - in - power supply a pre-drive unit that outputs a signal with a source voltage transition, and a signal output signal that outputs a row of select signals to activate a drive unit corresponding to one of the memory cells, wherein the pre-drive unit And each of the driving units includes at least one PMOS transistor and at least a __NM〇s transistor, and the transistors respectively receive a pumping voltage and a reverse bias via the main body thereof, and the pumping voltage has a high voltage a voltage level at a voltage level of the power supply voltage, wherein the reverse bias voltage has a voltage level level lower than a ground voltage; and a source voltage is provided to the plurality of memory groups The source voltage control unit, the voltage level of the source voltage changes according to the operation of the memory group 114725.doc 1310187 volts rf 〇疋 。 14 · · · · · · · · · · · · · · 半导体 半导体 半导体 半导体 半导体 半导体 半导体a terminal of the power supply voltage and a first PMOS transistor of a first-out node, the state output signal is output through the one-node node; and the first output is connected in series to the first output section a plurality of NMOS transistors between the source voltage and the ^Q, wherein the first PMOS transistor and the first of the NM〇S transistors have a correspondence with a common gate A control signal for the information of the memory group, and the remaining NM 〇s transistors respectively pass the code signals via their gates. 15. The semiconductor memory device of claim 14, wherein the driving unit comprises: a connection to the power supply voltage a second PMOS transistor between the terminal and a second output node, the row selection signal is outputted through the second output node; and is connected between the second output node of the shai and one of the ground voltage terminals NMOS transistor, β wherein the second PMOS transistor and the NM 〇s transistor receive the state turn-out signal via their common gate. 6. The semiconductor memory device of claim 13, wherein the source voltage control unit comprises: logic closed 'which is used to AND the signals in the column action indicating the respective modes of operation of the memory groups, respectively (and Operation; 114725.doc 1310187 - "offset" which is used to level shift the output signal of the logic (4) to produce an active signal; and - to provide the source to a corresponding memory bank Voltage selection list of voltage: 'The voltage level of the source voltage is returned to the active signal. The semiconductor memory device of claim 16, wherein the voltage selection unit has: An inverter in which the signal is inverted; a first transistor connected between the terminal of the source voltage and the terminal of the ground voltage and controlled by the active signal; and / is connected to the source a second transistor between the terminal of the pole voltage and one of the terminals of the reverse bias and controlled by an inactive signal. 18. The semiconductor memory device of claim 17, wherein in the column function Signal indication - standby In the formula, the first transistor is turned on to provide the ground voltage to the terminal of the source voltage. 19. The semiconductor memory device of claim 18, wherein when the signal indicates the active mode in the column action The second transistor is turned on to provide the reverse bias to the terminal of the source voltage. 20. The semiconductor memory device of claim 17, further comprising: a reverse bias generator The method includes: a voltage detecting unit configured to receive the reverse bias voltage and detect a voltage level of the reverse bias based on a reference reverse bias, and output an enable signal; and The voltage is generated early, which is used to generate the reverse bias and rotates the counter 114725.doc 1310187 to the source voltage control unit, and the voltage level of the reverse bias is back to the enable signal 21. The semiconductor memory device of claim 17, wherein the voltage selection unit further comprises: a first capacitor between the terminal of the reverse bias and the terminal of the ground voltage Parasitic capacitance And a first capacitor, which is a parasitic capacitor between the terminal of the source voltage and the terminal of the ground voltage, wherein a capacitance of one of the first capacitors is greater than a capacitance of the second capacitor. The semiconductor memory device of claim 21, wherein the capacitance of the first capacitor is greater than a capacitance of the second capacitor by hundreds to thousands of times. 23. A semiconductor memory device comprising: a plurality of memory banks Each of the plurality of memory groups includes: a memory cell matrix having a plurality of memory cells; and a row of decoding units having a code signal for responding to information of the row address of the memory cells and being selectively Generating a plurality of row decoders of the memory cells, wherein each of the row decoders comprises: a state for returning an equal code signal to provide a transition between a supply voltage and a source voltage a pre-drive unit that rotates a signal; and a drive unit that outputs a line of selection signals for responding to the status output signal to activate one of the memory cells, Each of the pre-drive unit and the drive unit includes at least 114725.doc 1310187 a PMOS transistor and at least one NM〇s transistor for receiving a pump voltage and a reverse via their bodies, respectively. a bias voltage, the pump voltage having a voltage level higher than a voltage level of the power voltage, and the reverse bias having a voltage level lower than a voltage level of a ground voltage; The plurality of memory groups provide a plurality of source voltage control units corresponding to the source voltages, and the voltage levels of the source voltages vary depending on the operation modes of the φ s groups. The semiconductor memory device of claim 23, wherein the pre-drive unit comprises: a first PMOS transistor connected between a terminal of the power supply voltage and a first output node, wherein the state is rotated by the signal a first round of the output node; and a plurality of NM0S transistors connected in series between the first output node and one of the source voltage terminals, wherein the first PM0S transistor and the NM0S transistor are The information is controlled by a corresponding memory group coupled to its common gate = control 彳5唬, and the remaining NMOS transistors receive the weight signals via their gates, respectively. The conductor memory device of claim 24, wherein the driving unit comprises: a second PMOS transistor connected between the terminal of the power supply voltage and 3 of a second output node, the row selection The signal is rotated through the first point; and the NMOS transistor connected to the second output node and the terminal of the ground voltage 114725.doc 1310187, wherein the first: PMOS transistor and the NMOS transistor are Its common gate receives the status output signal. 26. The semiconductor memory device of claim 23, wherein each of said source voltage control early elements comprises: - a level shifter for receiving a column of active signals and for level shifting thereof Generating an active signal, wherein the column active signal indicates an operation mode of the corresponding suffix group; and a voltage selection unit for supplying the corresponding source voltage to the corresponding memory group, the source voltage The voltage level is determined by returning to the active signal. The semiconductor memory device of claim 26, wherein the voltage selection unit has: an inverter for inverting the active signal; a terminal connected to the source voltage and the ground voltage a first transistor between the terminals and controlled by the active signal; and a signal connected between the terminal of the source voltage and one of the terminals of the reverse bias and controlled by a reverse phase active signal The second transistor. 28. The semiconductor memory device of claim 27, wherein when the signal in the column indicates a no-standby mode, the first transistor is turned on to provide the ground voltage to the terminal of the source voltage. The semiconductor memory device of claim 28, wherein, in the column function, the second transistor is turned on to raise (4) reverse bias to the source device Cough the terminal. The semiconductor memory device of claim 27, further comprising: a reverse bias generator comprising: a voltage extraction unit for receiving the reverse bias and based on a Detecting a voltage level of the reverse bias voltage with reference to a reverse bias voltage, thereby outputting an enable signal; and a voltage generating unit for generating the reverse bias voltage and outputting the reverse bias voltage to the The source voltage control unit, the voltage level of the reverse bias is adjusted to be enabled by the enable signal. The semiconductor memory device of claim 27, wherein the voltage selection unit further comprises: a second valley device, wherein the parasitic capacitor is present between the terminal of the reverse bias and the terminal of the ground voltage And the first electric thief, which is a parasitic capacitor existing between the terminal of the source and the ground voltage, the ... Wherein the capacity of the first capacitor. The capacitor is larger than the power of the second capacitor. The semiconductor memory device of claim 31, wherein the capacitance of the first container is greater than the capacitance of the second capacitor by hundreds to thousands of times. ° 114725.doc