1307962 16854twf.doc/006 .. 九、發明說明： 【發明所屬之技術領域】 / « 本發明是有關於一種圖案的形成方法，且特別是有關 於一種能夠降低膜層應力之圖案的形成方法與應用其之薄 膜電晶體的製作方法。 【先前技術】 顯示器為人與資訊的溝通界面，目前以平面顯示器為 φ 發展之趨勢。平面顯示器主要有以下幾種：有機電激發光 顯示器（Organic Electro-Luminescence Display, OELD)、電 漿顯示器(Plasma Display Panel, PDP)以及薄膜電晶體液晶 顯示器等（Thin Film Transistor Liquid Crystal Display， TFT-LCD)。其中，又以薄膜電晶體液晶顯示器的應用最為 廣泛。 薄膜電晶體液晶顯示器主要由薄膜電晶體陣列基板 (Thm Film Transistor Array Substrate, TFT array - Substrate )、彩色濾光陣列基板（Color Filter Array substrate， —CF array substrate )和液晶層（Liquid Crystal, LC )所構成， ' ，中薄膜電晶體陣列基板是由多個以陣列方式棑列的晝素 . 單元(pixel unit)所組成。而每一晝素單元係由薄膜電晶體 Film Tmnsistor, TFT)以及與薄膜電晶體電性連接 之資料配線:掃瞄配線及晝素電極(Pixel Electrode)所組 ^。上述之薄膜電晶體包括閑極、通道層、源極/沒極，且 薄膜電晶體是用來作為晝素單元（Pixel滅）的開關元件。 習知的薄膜電晶體的製作，會利用到成膜（Film 1307962 16854twf.d〇c/〇〇6 方法例如包括下列步驟’首先’了二T:: ,uvn 其覆蓋閑極與間絕緣層。接J，3=成:介電層’ 第開口與一第二開口。繼之，逸— 声中形驟’以移除第-開口底下的介電層，而於：電 層宁形成一凹陷圖案。再央， 从一 叩電 第二開口底下的介電層=—弟一钱刻步驟以移除 來，且同時去除位於二9 ’以使源極/汲極暴露出 除圖案化光阻層。严扣底下的間絕緣層。之後，去 在本發明之一實施例中， 是使_半透光 之前，例如更包括::::驟上=:進行第， 露出介電層。 Ka〜）以使第二開口暴 在本發明之一實施例中， 之^列如更包括在基板上形成-緩衝‘成:::夕島狀物 一非連續膜層。 对層且此緩衝層是 在本發明之一實施例中，上 膜層。 之閘、纟巴緣層是一非連續 在本發明之一實施例中，上求 <、 方法例如是先在基板上形成：：成多晶矽島狀物之 2連續之膜層。接著，進行—二i程其中非晶石夕層是 轉變成多晶石夕層。之後，圖安 、王，以使非晶石夕層 -化夕曰曰矽層以形成多晶矽島 1307962 16854twf.doc/006 狀物 在基薄膜電晶體的製作方法，其例如先 閘i。、紅二閘絕:上;成間絕緣層以覆蓋 後，於通道層上J成=:極2形成-通道層。之 成方法。 < 之万法疋使用上述之圖案的形 前，=本=月ί—、實施例中’上述之在形成源極/没極之 觸㈣如在通逼層上形成—歐姆接觸層，且歐姆接 觸層例如疋_上述之_的形成方法而形成。 連續ΐί發明之一實施财，上述之間絕緣層例如是一非 後，一實施例中’上述之在形成源極/沒極之 層例如是糊上述之職的形成方法而形成。”隻 法，n明m可形成非連續膜層之圖案的形成方 板-以==除因應力不均所造成之基 的形成方法製作;= 二::昇=發_ 為讓本發明之上、“ ：：了“其製作良率。 易懂，下文特;^、目的、特徵和優點能更明顯 明:下特舉較佳貫施例，並配合所附圖式，作詳細說 【實施方式】 1307962 36854twf.doc/006 第一實施例 /圖1A〜圖ic纟會示為本發明之較佳實施例中—種圖案 =形成方紅步驟流㈣面示意圖，首先，請參照圖1Α， 提供一基板100。接著，請參照圖lB，於基板1〇〇上形成 —非L層U0 ’以降低此膜層u〇之應力。之後，請 蒼照圖ic，對非連續膜層11〇進行一圖案化製程以形成一 圖案120。 在本發明之一實施例中，如圖1Β所繪示之製程，即 於基板1GG场成非連續膜層UQ之方法例如是利用一隱 遮罩130以進行一沈積製程H0 (緣示於圖2中），且此 沈積製程140例如是化學氣相沈積製程乂啊1307962 16854twf.doc/006 .. IX. Description of the invention: [Technical field to which the invention pertains] / « The present invention relates to a method for forming a pattern, and more particularly to a method for forming a pattern capable of reducing stress of a film layer and A method of fabricating a thin film transistor using the same. [Prior Art] The display is a communication interface between people and information. At present, the development trend of flat display is φ. The main types of flat panel displays are: Organic Electro-Luminescence Display (OELD), Plasma Display Panel (PDP), and Thin Film Transistor Liquid Crystal Display (TFT-). LCD). Among them, thin film transistor liquid crystal displays are the most widely used. The thin film transistor liquid crystal display mainly comprises a thin film transistor array substrate (TFT array-substrate), a color filter array substrate (CF array substrate), and a liquid crystal layer (Liquid Crystal, LC). The thin film transistor array substrate is composed of a plurality of pixel units arranged in an array. Each of the pixel units is composed of a thin film transistor (TFT) and a data wiring electrically connected to the thin film transistor: a scanning wiring and a Pixel Electrode. The above-mentioned thin film transistor includes a dummy electrode, a channel layer, a source/drain, and a thin film transistor is used as a switching element of a pixel unit. The fabrication of conventional thin film transistors utilizes film formation (Film 1307962 16854 twf.d〇c/〇〇6 method includes, for example, the following steps 'first' of two T::, uvn which covers the idle and inter-insulating layers. Connect J, 3 = into: the dielectric layer 'the first opening and the second opening. Then, the sound-in-sound shape is used to remove the dielectric layer under the first opening, and the electric layer is formed into a depression. Pattern. From the bottom, the dielectric layer under the second opening of the second electric power = the younger one engraved step to remove, and at the same time remove the second 9' to expose the source/drain to the patterned resist The interlayer insulating layer is tightly buckled. Thereafter, in an embodiment of the present invention, before the _ semi-light transmission, for example, the method further includes:::: 上上=: performing the first, exposing the dielectric layer. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The layer and the buffer layer are in the embodiment of the invention, the upper film layer. In the embodiment of the present invention, the method is as follows: The method is first formed on the substrate: a continuous film layer of polycrystalline germanium. Then, the process is carried out, wherein the amorphous layer is transformed into a polycrystalline layer. After that, Tuan and Wang, in order to form a polycrystalline enamel layer to form a polycrystalline iridium island 1307962 16854 twf.doc / 006 in the method of fabricating a base film transistor, for example, the gate i. , the second gate of the red: upper; after the insulation layer is covered, on the channel layer J = = pole 2 form - channel layer. The method of making. < 万 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋The ohmic contact layer is formed, for example, by the method of forming the above. In one embodiment of the invention, the insulating layer is formed, for example, in a first embodiment. In the embodiment, the layer forming the source/drain electrode is formed by a method of forming the paste. "Only, n can form a square plate of a pattern of discontinuous film layers - by == except for the formation of the base due to uneven stress; = 2:: liter = hair _ for the purpose of the present invention On, "::" its production yield. Easy to understand, the following special; ^, purpose, features and advantages can be more obvious: the next special case is better than the example, and with the drawings, for details EMBODIMENT] 1307962 36854twf.doc/006 The first embodiment / FIG. 1A to FIG. 1 is a schematic diagram of a pattern of forming a square red flow in the preferred embodiment of the present invention. First, please refer to FIG. A substrate 100 is provided. Next, referring to FIG. 1B, a non-L layer U0' is formed on the substrate 1 to reduce the stress of the film layer. After that, please view the ic, the discontinuous film layer 11 〇 performing a patterning process to form a pattern 120. In one embodiment of the invention, the process illustrated in FIG. 1A, that is, the method of forming the discontinuous film layer UQ on the substrate 1GG, for example, utilizes a hidden mask. 130 to perform a deposition process H0 (shown in FIG. 2), and the deposition process 140 is, for example, a chemical vapor deposition process what
Deposition, CVD)或是物理氣相沈積製程（脚Deposition, CVD) or physical vapor deposition process (foot)
Deposition, PVD )。 圖2繪示為本發明之較佳實施例中利用_罩以進行 沈積製程的側視示意圖。請參照圖2，_罩13()具有遮 ，區132與開口區134,而遮蔽區132會阻措沈積製程⑽ 中的離子束，且開口區134會使沈積製程⑽中的離子束 通過、，^一來，將在基板100上形成非連續膜層110， Θ連、’、膜層110具有—非連續區m與多^^膜塊叫。 此:卜蔭遮罩130之遮蔽區132與開口區134的排列 二：可f據所欲形成的元件形狀’而設計成柵攔形狀 Ϊ 並制續配合沈積製程14〇而形成柵攔形 狀與棋盤形狀之非連續膜層110。圖3A與圖3B _為呈 柵攔形狀與祺盤形狀之非連續膜層的俯视示意圖。請先參 1307962 16854twf.doc/0〇6 =⑶其中被非連續 或資料線等。請再參照圖“後績可以圖案化成掃目苗線 110，1中被非、’、 ’具有棋盤形狀的非連續薄膜 形成各個多個魏…其可用以 源極/沒轉中之轉結構’例如晝素電極、閑極與 即上述另—貫施例中，如圖1Β情示的製程， Ρ上k之於基板1〇〇上形 、 也可進行如圖从與圖㈣示之=⑽之方如例如 的步層形祕連續膜層 上形成-圖案化底層210。接著二:;二二於f板200 ^ 侵考5月參,¾圖4B，進行一沈 ^程220以於基板上形成非連續膜層230。其中， ，、：210之方法例如為習知中之微影蝕刻方 式，熟=技勢者應可_實施，在此將不予以費述。 值付注意的是’在本發明之—較佳實施例中，圖案化 底層210例如是多個凸起圖案或多個凹陷圖案。圖5A與 圖5B緣示顧案化底狀剖面示錢。請先參照圖5a，、 圖案化底層210可以是一凸起圖案雇，且凸起圖案2i如 之頂部寬度dl大於其底部寬度们。藉由此寬度的差里， 而可較佳地形成非連續膜層230。請再參照圖5B，圖幸化 底層210也可以是-凹陷圖案21%，且凹陷圖案2滿之 頂部寬度dl’小於其底部寬度d2,。地，藉由此寬度的 差異，而可較佳地形成非連續膜層230。 ^U/962 16854twf.doc/006 在利用上述蔭遮罩或是 膜層23〇後，將會繼續對於此非卞連匕鋒底層之方式形成非連續 f會示之圖案化製程，而形成®層230進行如圖1C 疋閘極圖案、源極㈣圖案：20。此圖案U0可以 以及晝素電極圖案等。在明二、'、圖案、掃瞒線的圖案 如包括-微影製程此圖案化 者應可據以實施，在此將衫jL，熟知技藝 總之’利用上述之圖幸 = 續膜層，並顯將此非連續膜可以先形成非連 由於是形成非連續膜層，所以二案化_成元件圖案。 =問題，並可消除因膜層應力不^解應力不均 象。特別是，在製作大面_層時，現 麵曲現象將更嚴重，因此， :力不均引起的基板 法將大面積連續薄膜轉變成許多非成的方 而有效地解決㈣之仏冰，的小面積溥膜，進 與曝光偏移等問▲。’’、： ’以及其所引發的對位不良 弟一貫施例 施你丨由 '第+％例中之圖案形成的方法，可應用在本實 “ 膜電晶體的製作。此薄膜電晶體例如是一低溫 LTPS專膜電晶體（L〇W 丁⑽柯站職P〇lySiliC〇n TFT, + 。圖6A到圖6G繪示為本發明之較佳實施例 5丨同厚膜電晶體的製作流程剖面示意圖，請共同參照圖6A 到圖6G。 12 1307962 16SMtwf.doc/006 如圖6A所綠示，本發明之薄膜電晶體的製作方法其 先提供-基板3GG。此基板例如‘玻璃基板、一石夕 基板或是一可撓式基板。 接著，於基板300上形成一多晶石夕島狀物34〇 (如圖 仍所繪示）。在本發明之—實施例中，上述之形成多晶石夕 島狀物340之方法例如是圖6B到圖6D所繪示。請先參照 圖6B，f先在基板3〇〇上形成一非晶石夕層32〇，其电非晶 矽層320疋一非連續之膜層。接著，請參照圖6c，進行一 回火製程’以使非晶發層32()轉變成多晶砍層33()。此回 火製程例如是準分子雷射退火製程（Exdmer Laser Annealing，ELA)或是快速熱退火製程（Rapid Thermd Annealing，RTA)。之後，請參照圖，圖案化多晶矽層 330以形成多晶矽島狀物34〇。在本發明之一實施例中，上 述之於形成多晶矽島狀物340之前，例如更包括在基板300 上形成一緩衝層310(繪示於圖65中），丘此缓衝層31〇 是一非連續膜層，其例如是利用第一實施例中之形成非連 續膜層的方法而達成其製作。 再來，請繼續參照圖6E，形成一閘絕緣層350以覆蓋 多晶矽島狀物340。在本發明之一實施例中，此閘絕緣層 350例如是一非連續膜層，其例如是利用第一實施例中之 形成非連縯膜層的方法而達成其製作，以消除其應力不均 的問題。 繼之，請參照圖6F，於閘絕緣層35〇上形成一閘極 360。之後，請麥照圖6G，於閘極36〇兩側下方之多晶矽 13 ic/006 島狀物 34Θ 中形成一4¾ 07η 印…w 而源極，汲極370之間 P疋〇。形成源極/汲極370之方法例如I以η 極360為自行對準罩幕，進行一離子推雜疋= 多晶石夕島狀物340之兩側形成源極/汲極37() 進行一回火製程，以修復多_島狀物34()_^二=再 至少形成多晶嫌物細與閘細 方法:也就是說，在=之圖案的形成 甘I成用來製作多晶矽島狀物340盥閘 非連續膜層後，繼續再進行圖案化製程而將其非 連、，膜層形成多晶發島狀物340與閉極360。所以，可降 低膜層的應力不均’並進而增進_電晶體的製作良率。 此外，上述之薄膜電晶體的製作方法，例如更包括如 圖7Α到圖7Β所緣示之步驟以形成源極/汲極導體層偏。 首先，請參照圖7Α，在基板上形成一圖案化介電層 450 ’其中圖案化介電層45()暴露出部分源極/汲極wo。 之後、:請參照圖7B，在圖案化介電層㈣上形成一源極/ 及極^^層460’而源極/汲極導體層働分別與源極/沒極 370電性連接，其中形成圖案化介電層45〇與源極/汲極導 體層460至少其中之—之方法是使用第一實施例中之圖案 的形成方法。 、為更詳細說明上述之形成圖案化介電層450與源極/ /及極$體層460至少其中之一之方法是使用第一實施例中 之圖案的形成方法，以下將以形成源極/汲極導體層460為 例而進行說明。請繼續參照圖7B，源極/汲極導體層460 14 1307嫩 twf.doc/006 可利用第一實施例中利用蔭遮罩配合沈積製程的方式進行 製作。也就是說，利用一具有遮蔽區132與開口區134的 隱遮罩130配合沈積製程140，而形成具有非連續區462 的源極/汲極導體層460。特別是在進行大面積膜層的製作 時，非連續區462可以將大面積膜層轉變為多個小面積的 臈層，進而降低膜層之應力不均現象。因此，可消 :及極導體層46〇的應力不均。之後，再 及極導體層460進行圖案化製程，以形成具有預定 源極/汲極導體層460。 /、 另外，上述於形成圖案化介電層45〇時可以同 =如第-實施例中所述圖案化底層，以消除後續所形成 々源極/汲極導體層_之賴應力不均，_ 到圖8Ε所繪示。 ，、衣私如圖8Α 其覆在基板獅上形成—介電層棚， 介電層35〇。接著，請參，於 層400上形成—圖案化光阻層410,苴農右狄0日 口 412與一第二開口 4M。^二、有—弟一開 光阻，以雜出介電層_^是完全去除 y法例如是使料有半透光阻層410 罩_來進行曝光製程，此丰、|二圖案610之光 D 414之上方。 切先圖案61G是位於第二開 降第^明爹照圖8C ’進行一第一银刻步輝430梦 除弟-開口 412底下 430,以移 層伽，而於介電層400中形 130 環— ，办凹fe圖案402。值得注意的是，此凹陷圖案4〇2之頂 部f度di’小於其底部寬度d2，。再來，請參照圖8d，進 行一第二蝕刻步驟44〇以移除第二開口 414底下的介 400與間絕緣層35G，以使源極/沒極370暴露出來，且^ ^去除位於第—開口 412底下的閘絕緣層350，因而形成 如圖8E所緣示之圖案化介電層45〇。在本發明之一實施例 =，上述之於進行第二蝕刻步驟44〇之前，例如更包括進 行-灰化步驟（ashing)以使第二開口 414暴露出介電居 400 ^之後，睛參照圖8E，去除圖案化光阻層410。 ，繼續參照圖8E，繼續於基板上形成一源極/沒 虽¥體層460,在具有凹陷圖案4〇2處，此源極/汲極 而形成非連續膜層。因此，可降低咖及極 i-厣二#不均的問題。之後，對非連續的源極/汲極 ==圖案一形成具有預定圖案的二 門日貞，甘、佳而担θ 、電日日脰，將可解決膜層之應力不均的 越並進而&升薄膜電晶體之製作良率。 第三實施例 圖9Α到圖9Ε絡+劣丄，々 '9不為本發明較佳實施例中又一種巷聪 、日面示意圖，請共同參照圖9A到圖9E。 ^ 51° ° 土板500上形成閘絕緣層520以覆 16 13079®tw,doc/ 006 蓋閘極510。繼之，請參照圖9c ,於閘絕緣層52〇上及閘 極510上方形成—通道層53〇。之後，請參照圖9D，於通 道層530上形成—源極/没極550，其中形成閘極510、通 道層530與源極/汲極550至少其中之一之方法是使用第一 實施例中之圖案的形成方法。Deposition, PVD ). 2 is a side elevational view showing the use of a hood to perform a deposition process in accordance with a preferred embodiment of the present invention. Referring to FIG. 2, the hood 13 () has a mask, a region 132 and an open region 134, and the mask region 132 blocks the ion beam in the deposition process (10), and the open region 134 passes the ion beam in the deposition process (10). A non-continuous film layer 110 is formed on the substrate 100, and the film layer 110 has a discontinuous region m and a plurality of film blocks. Therefore, the arrangement of the shielding area 132 and the opening area 134 of the shadow mask 130 is: the shape of the element can be formed according to the shape of the element to be formed, and the deposition process 14 制 is formed to form the barrier shape and A discontinuous film layer 110 in the shape of a checkerboard. 3A and 3B are top plan views of a discontinuous film layer in the shape of a barrier and a disk. Please refer to 1307962 16854twf.doc/0〇6 = (3) where it is discontinuous or data line. Please refer to the figure again. "After the performance can be patterned into a sweeping line 110, a non-continuous film with a checkerboard shape in the 1st, ', and a plurality of non-continuous films having a checkerboard shape can be used to form a source/non-transfer structure. For example, in the case of the halogen electrode, the idle electrode and the above-mentioned other embodiment, as shown in FIG. 1 , the process of the upper surface of the substrate 1 can also be performed as shown in the figure (4). The method is as follows, for example, forming a patterned underlayer 210 on a layer of a continuous layer of film, followed by two:; two on the f plate 200 ^ invading the May parameter, 3⁄4 in FIG. 4B, performing a sinking process 220 on the substrate The discontinuous film layer 230 is formed thereon. The method of:, : 210 is, for example, a conventional lithography etching method, and the skilled person should be able to implement it, which will not be described here. In the preferred embodiment of the present invention, the patterned bottom layer 210 is, for example, a plurality of raised patterns or a plurality of concave patterns. Figures 5A and 5B show the bottom view of the substrate. Please refer to Figure 5a first. The patterned bottom layer 210 may be a raised pattern, and the raised pattern 2i has a top width dl greater than its bottom width. In the difference of the width, the discontinuous film layer 230 can be preferably formed. Referring again to FIG. 5B, the underlayer 210 can also be a recessed pattern of 21%, and the recessed pattern 2 is full of the top width dl' is smaller than the bottom thereof. Width d2, ground, by the difference in width, the discontinuous film layer 230 can be preferably formed. ^U/962 16854twf.doc/006 After using the above-mentioned shadow mask or film layer 23, Continuing to form a non-continuous f-patterning process for the non-continuous Bottom layer, the ® layer 230 is formed as shown in FIG. 1C, the gate pattern, and the source (four) pattern: 20. This pattern U0 and the pixel electrode pattern Etc. In the second, ', pattern, broom line pattern, such as including - lithography process, this pattern should be implemented according to the implementation, here will be the shirt jL, well-known skills in general 'Using the above picture lucky = continuous film And it is obvious that the discontinuous film can be formed first as a non-continuous film layer, so that the second film is formed into a component pattern. The problem is solved, and the stress unevenness due to the film stress is not eliminated. When making a large surface _ layer, the phenomenon of the surface music will be more serious, therefore, : The substrate method caused by unevenness converts a large-area continuous film into many non-formed sides and effectively solves the problem of (4) ice, small area enamel film, exposure and exposure shift, etc. '',: 'and its The resulting mismatched brother has always applied the method of forming the pattern in the '+% of the case, which can be applied to the production of the film transistor. The thin film transistor is, for example, a low temperature LTPS film transistor (L〇W butyl (10) Ke station, P〇lySiliC〇n TFT, +. Fig. 6A to Fig. 6G show the preferred embodiment of the present invention. For a cross-sectional view of the fabrication process of the film transistor, please refer to FIG. 6A to FIG. 6G together. 12 1307962 16SMtwf.doc/006 As shown in FIG. 6A, the method for fabricating the thin film transistor of the present invention first provides a substrate 3GG. For example, a 'glass substrate, a slab substrate or a flexible substrate. Next, a polycrystalline slab 34 〇 is formed on the substrate 300 (as still shown). In the embodiment of the present invention - The method for forming the polycrystalline stone island 340 is as shown in FIG. 6B to FIG. 6D. Referring first to FIG. 6B, f first forms an amorphous layer 32 on the substrate 3? The electrically amorphous layer 320 is a discontinuous film layer. Next, referring to FIG. 6c, a tempering process is performed to convert the amorphous layer 32() into a polycrystalline layer 33 (). This tempering process For example, Exdmer Laser Annealing (ELA) or Rapid Thermal Annealing (Rapid Thermd Annealing) Afterwards, referring to the figure, the polysilicon layer 330 is patterned to form a polycrystalline germanium 34. In one embodiment of the invention, the foregoing is further included in the substrate 300 before forming the polysilicon island 340. A buffer layer 310 (shown in FIG. 65) is formed thereon, and the buffer layer 31 is a discontinuous film layer, which is formed by, for example, forming a discontinuous film layer in the first embodiment. Referring again to FIG. 6E, a gate insulating layer 350 is formed to cover the polysilicon island 340. In one embodiment of the invention, the gate insulating layer 350 is, for example, a discontinuous film layer, which is utilized, for example. The method of forming a non-continuous film layer in the first embodiment achieves its fabrication to eliminate the problem of uneven stress. Next, referring to FIG. 6F, a gate 360 is formed on the gate insulating layer 35. Please take photo of 6G, forming a 43⁄4 07η print...w in the polycrystalline 矽13 ic/006 island 34Θ below the two sides of the gate 36〇 and the source, the drain 370 between P疋〇. Form the source/ The method of the bungee 370 is performed, for example, by using the η pole 360 as a self-aligning mask. Ion push enthalpy = the source/drain 37 () is formed on both sides of the polycrystalline stone island 340 to perform a tempering process to repair the multi-island 34 () _ ^ two = at least form polycrystalline The method of thinning the smear and the sluice method: that is, after the formation of the pattern of = is used to make the polycrystalline 矽 状物 非 非 非 非 非 continuation of the non-continuous film layer, the patterning process continues to be non-connected, The film layer forms the polycrystalline island 340 and the closed electrode 360. Therefore, the stress unevenness of the film layer can be reduced and the yield of the transistor can be improved. Further, the above-described method of fabricating the thin film transistor, for example, further includes the steps as shown in Figs. 7A to 7B to form the source/drain conductor layer. First, referring to FIG. 7A, a patterned dielectric layer 450' is formed on the substrate, wherein the patterned dielectric layer 45() exposes a portion of the source/drain electrodes wo. Thereafter, referring to FIG. 7B, a source/drain layer 460' is formed on the patterned dielectric layer (4) and the source/drain conductor layer 电 is electrically connected to the source/drain 370, respectively. The method of forming at least one of the patterned dielectric layer 45A and the source/drain conductor layer 460 is to use the formation method of the pattern in the first embodiment. The method for forming at least one of the patterned dielectric layer 450 and the source//and the body layer 460 described above in more detail is to use the method of forming the pattern in the first embodiment, which will be used to form the source/ The gate conductor layer 460 will be described as an example. Continuing to refer to FIG. 7B, the source/drain conductor layer 460 14 1307 twf.doc/006 can be fabricated by using the shadow mask in conjunction with the deposition process in the first embodiment. That is, the deposition process 140 is utilized with a hidden mask 130 having a masking region 132 and an open region 134 to form a source/drain conductor layer 460 having a discontinuous region 462. In particular, in the fabrication of a large-area film layer, the discontinuous region 462 can transform a large-area film layer into a plurality of small-area germanium layers, thereby reducing the stress unevenness of the film layer. Therefore, it is possible to eliminate the stress unevenness of the pole conductor layer 46. Thereafter, the epitaxial conductor layer 460 is patterned to form a predetermined source/drain conductor layer 460. In addition, when the patterned dielectric layer 45 is formed, the underlayer can be patterned as described in the first embodiment to eliminate the uneven stress of the subsequently formed germanium source/drain conductor layer. _ to Figure 8Ε. , clothing private as shown in Figure 8 Α covered on the substrate lion formed - dielectric layer shed, dielectric layer 35 〇. Next, please refer to the formation of a patterned photoresist layer 410 on the layer 400, the 右农右迪0日口 412 and a second opening 4M. ^ Second, there is a brother to open the photoresist, to make the dielectric layer _ ^ is completely removed y method, for example, the material has a semi-transparent resistive layer 410 cover _ to carry out the exposure process, this Feng, | two pattern 610 light Above D 414. The first pattern 61G is located at the second opening and lowering, and the first silver etching step 430 is performed by a first silver engraving step 430, and the opening 412 is bottom 430 to shift the layer gamma, and the dielectric layer 400 is shaped 130. Ring -, do concave fe pattern 402. It is to be noted that the top portion f degree di' of the recess pattern 4〇2 is smaller than the bottom width d2 thereof. Referring to FIG. 8d, a second etching step 44 is performed to remove the dielectric 400 and the interlayer insulating layer 35G under the second opening 414 to expose the source/drain 370, and the removal is located at the first The gate insulating layer 350 under the opening 412 thus forming a patterned dielectric layer 45A as shown in Figure 8E. In an embodiment of the present invention, before the second etching step 44 is performed, for example, the ashing step is further included to expose the second opening 414 to a dielectric level of 400 ^. 8E, the patterned photoresist layer 410 is removed. Continuing to refer to FIG. 8E, a source/non-body layer 460 is formed on the substrate, and the source/drain is formed to form a discontinuous film layer at the recess pattern 4〇2. Therefore, the problem of unevenness of the coffee and the extreme i-厣二# can be reduced. After that, the non-continuous source/drainage== pattern forms a two-door corona with a predetermined pattern, and the symmetry of the film layer can be solved by the two-door corona with a predetermined pattern. The yield of the film transistor is increased. THIRD EMBODIMENT Fig. 9 Α to Fig. 9 丄 + 丄 丄 丄 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 ^ 51 ° ° The gate insulating layer 520 is formed on the earth plate 500 to cover the 16 13079® tw, doc / 006 cover gate 510. Next, referring to Fig. 9c, a channel layer 53 is formed on the gate insulating layer 52 and over the gate 510. Thereafter, referring to FIG. 9D, a source/drain 550 is formed on the channel layer 530, wherein a method of forming at least one of the gate 510, the channel layer 530 and the source/drain 550 is used in the first embodiment. The method of forming the pattern.
請繼續參照圖9C，在本發明之一實施例中，上述之 在形成源極/汲極550之前，例如更包括在通道層53〇上形 成一歐姆接觸層540，且歐姆接觸層540也可以是利用第 一貫施例中之圖案的形成方法而形成。且閘絕緣層52〇也 可以是一非連續膜層，其也可以利用第一實施例中之圖案 的形成方法而形成。 一 明參知圖9E，在形成源極/汲極550之後，可以再形 成-保護層560以覆蓋源極/汲極55G，其中保護層56〇例 如是利用第-實施例中之圖案的形成方法而形成。如圖％ 中所緣示，形成保護層例如是第-實施例中之降Continuing to refer to FIG. 9C, in an embodiment of the present invention, before forming the source/drain 550, for example, an ohmic contact layer 540 is formed on the channel layer 53A, and the ohmic contact layer 540 can also be formed. It is formed by the formation method of the pattern in the first embodiment. Further, the gate insulating layer 52A may be a discontinuous film layer, which may also be formed by the formation method of the pattern in the first embodiment. Referring to FIG. 9E, after forming the source/drain 550, a protective layer 560 may be formed to cover the source/drain 55G, wherein the protective layer 56 is formed, for example, by using the pattern in the first embodiment. Formed by the method. As shown in the figure %, the formation of the protective layer is, for example, the drop in the first embodiment.
==配合沈積製程140的方法，而將原本連續的保i 層560轉變成一非連續膜層，其中非連續區尬會 的=層_區分成多個膜塊’因此，可降低保護層⑽ 的之後可再將此非連續的保護層560進 订圖案化，而製作出所需之圖案。當然，也可用第 =之圖案化底相方式來形成非連續的保護層56〇，、在 此將不再予以贊述。 圖案，可以利用第一實 作，其可以形成非連續 承上述’薄膜電晶體中的各個 細*例中之圖案的形成方法來加以製 17 13079揣 twf.d〇c/〇〇6 的膜層，而降低膜層之應力不均現象。所以，可消除因為 應力不均現象而引起之基板Μ曲，並進而消除微影時產生 所之偏移與對位不良等問題。因此，可以提昇薄膜 雕 的製作良率。 3曰妝 綜上所述’本發明之圖案的形成方法以及薄膜電晶體 的製作方法具有下列優點： 妝 (1) 本發明之圖案的形成方法’其所形成的非連續 膜層可消除因應力不均所造成之基板輕曲的現象。特別是 在大尺寸面積膜層的情形下，更能有效地降低膜層之應力。 (2) 利用本發明之圖案的形成方法製作薄膜^曰曰 體，可以得到應力較為平均之非連續膜層，所以可消除= 應力不均而弓丨起之基板翹曲以及其所引發的問題，如在微 影時之對位不良與曝光偏移等。因此，將可提昇薄膜雷曰 體之製作良率。 、罨日曰 雖然本發明已以較佳實施例揭露如上，然其並非用以 限^本發明’任何熟習此技藝者，在我離本發明之精 和範圍内，當可作些許之更動與潤飾，因此本發明之 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A〜圖1(：緣示為本發明之較佳實施例中—種 的形成方法之步驟流程剖面示意圖。 木 圖2綠示為本發明之較佳實施例中利用_罩 沈積製程的側視示意圖。 订 圖3 A與圖3 B緣示為呈柵攔形狀與棋盤形狀之非連續 B079欲 f.doc/〇〇6 膜層的俯視示意圖。 的步湘酸喊細祕連續膜層 與圖犯繪示為圖案化底層之剖面示意圖。 電‘的制ϋ 6G綠示為本發明之較佳實施例中的薄膜 電日日虹的衣作流程剖面示意圖。 到圖7B!會示為本發明之薄膜電晶體的製作方法 中，形成源極/汲極導體層的步驟流 圖8A到圖8E綸干盍户士政。口 」田回 法中，料_電晶體的製作方 形成圖木化；|電層的步驟流程剖面圖。 圖9 A到圖9 E綠示為本發明較佳實施例中又 電晶體的製作流程剖面示意圖。 ' 【主要元件符號說明】 100、200、300、500 :基板 110、230 :非連續膜層 112、462、562 .非連續區== In conjunction with the deposition process 140, the original continuous ii layer 560 is converted into a discontinuous film layer, wherein the non-continuous zone = = layer _ is divided into a plurality of film blocks 'thus, the protective layer (10) can be lowered The discontinuous protective layer 560 can then be patterned further to produce the desired pattern. Of course, the non-continuous protective layer 56〇 can also be formed by patterning the bottom phase of the =, which will not be described here. The pattern can be formed by a first implementation, which can form a film of 17 13079 揣twf.d〇c/〇〇6 by forming a pattern of each of the above-mentioned thin film transistors. And reduce the stress unevenness of the film layer. Therefore, the distortion of the substrate due to the uneven stress phenomenon can be eliminated, and the problems such as the offset and the misalignment which occur when the lithography is eliminated can be eliminated. Therefore, the production yield of the film engraving can be improved. The method for forming the pattern of the present invention and the method for producing the film transistor have the following advantages: makeup (1) The method for forming the pattern of the present invention, which forms a discontinuous film layer to eliminate stress The unevenness of the substrate caused by unevenness. Especially in the case of a large-sized film layer, the stress of the film layer can be more effectively reduced. (2) By forming a thin film by using the pattern forming method of the present invention, a discontinuous film layer having a relatively uniform stress can be obtained, so that the warpage of the substrate caused by the uneven stress and the problem caused by the substrate can be eliminated. , such as misalignment and exposure shift in lithography. Therefore, the production yield of the film thunder body will be improved. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention to anyone skilled in the art, and it is within the spirit and scope of the invention. The scope of the invention is therefore defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1 are schematic cross-sectional views showing the steps of a method for forming a preferred embodiment of the present invention. The green figure 2 is shown in the preferred embodiment of the present invention. A side view of the hood deposition process. Figure 3 A and Figure 3 B are shown as a schematic view of the non-continuous B079 shape of the gate and the shape of the checkerboard. The schematic view of the f.doc/〇〇6 film layer. The detailed continuous film layer and the figure are shown as a schematic cross-sectional view of the patterned bottom layer. The electric 的 6G green is shown as a schematic cross-sectional view of the filming process of the thin film electric day xihong in the preferred embodiment of the invention. 7B! In the method for fabricating the thin film transistor of the present invention, the step of forming the source/drain conductor layer is shown in FIG. 8A to FIG. 8E, and the 盍 」 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Fig. 9A to Fig. 9 E is a schematic cross-sectional view showing the manufacturing process of the transistor in the preferred embodiment of the present invention. ' [Main component symbol description] 100, 200, 300, 500: substrates 110, 230: discontinuous film layers 112, 462, 562. Continuum
114 :膜塊 120 :圖案 130 :蔭遮罩 132 ··遮敗區 134 :開口區 140、220 ··沈積製程 210 ··圖案化底層 210a :凸起圖案 19 13〇7糧 :wf.doc/006 210b :凹陷圖案 310 :緩衝層 320 :非晶矽層 330 :多晶矽層 340 :多晶矽島狀物 350、520 :閘絕緣層 360、510 :閘極 370 :源極/汲極 372 :離子摻雜製程 380 :通道區 400 :介電層 402 :凹陷圖案 410 :圖案化光阻層 412 :第一開口 414 :第二開口 430 :第一蝕刻步驟 440 :第二蝕刻步驟 450 :圖案化介電層 460 :源極/汲極導體層 530 :通道層 540 :歐姆接觸層 550 :源極/汲極 560 :保護層 600 :光罩 20 I3〇7962d〇c/006 610 :半透光圖案 dl、dl’ ：頂部寬度 d2、d2’ ：底部寬度 21114: film block 120: pattern 130: shadow mask 132 · shading area 134: opening area 140, 220 · · deposition process 210 · · patterned bottom layer 210a: raised pattern 19 13 〇 7 grain: wf.doc / 006 210b: recess pattern 310: buffer layer 320: amorphous germanium layer 330: polysilicon layer 340: polysilicon island 350, 520: gate insulating layer 360, 510: gate 370: source/drain 372: ion doping Process 380: channel region 400: dielectric layer 402: recess pattern 410: patterned photoresist layer 412: first opening 414: second opening 430: first etching step 440: second etching step 450: patterning the dielectric layer 460: source/drain conductor layer 530: channel layer 540: ohmic contact layer 550: source/drain 560: protective layer 600: photomask 20 I3〇7962d〇c/006 610: semi-transmissive pattern dl, dl ' : Top width d2, d2': bottom width 21