TWI307554B - A thin film transistor and method of fabrication the same - Google Patents
A thin film transistor and method of fabrication the same Download PDFInfo
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- TWI307554B TWI307554B TW93102583A TW93102583A TWI307554B TW I307554 B TWI307554 B TW I307554B TW 93102583 A TW93102583 A TW 93102583A TW 93102583 A TW93102583 A TW 93102583A TW I307554 B TWI307554 B TW I307554B
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- dielectric layer
- thin film
- gate dielectric
- film transistor
- gate
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- 239000010409 thin film Substances 0.000 title claims description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 29
- 238000005468 ion implantation Methods 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052684 Cerium Inorganic materials 0.000 claims description 6
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000011651 chromium Substances 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- 229910003828 SiH3 Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 230000004048 modification Effects 0.000 claims description 3
- 238000012986 modification Methods 0.000 claims description 3
- OLRJXMHANKMLTD-UHFFFAOYSA-N silyl Chemical compound [SiH3] OLRJXMHANKMLTD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- DIOQZVSQGTUSAI-UHFFFAOYSA-N decane Chemical compound CCCCCCCCCC DIOQZVSQGTUSAI-UHFFFAOYSA-N 0.000 claims 2
- 150000004767 nitrides Chemical class 0.000 claims 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims 1
- UOUJSJZBMCDAEU-UHFFFAOYSA-N chromium(3+);oxygen(2-) Chemical class [O-2].[O-2].[O-2].[Cr+3].[Cr+3] UOUJSJZBMCDAEU-UHFFFAOYSA-N 0.000 claims 1
- QDOXWKRWXJOMAK-UHFFFAOYSA-N dichromium trioxide Chemical compound O=[Cr]O[Cr]=O QDOXWKRWXJOMAK-UHFFFAOYSA-N 0.000 claims 1
- 239000000839 emulsion Substances 0.000 claims 1
- 239000011888 foil Substances 0.000 claims 1
- 230000005660 hydrophilic surface Effects 0.000 claims 1
- 150000003949 imides Chemical class 0.000 claims 1
- 229910052738 indium Inorganic materials 0.000 claims 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- SOQBVABWOPYFQZ-UHFFFAOYSA-N oxygen(2-);titanium(4+) Chemical class [O-2].[O-2].[Ti+4] SOQBVABWOPYFQZ-UHFFFAOYSA-N 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 150000003431 steroids Chemical class 0.000 claims 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 100
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 9
- 229910052732 germanium Inorganic materials 0.000 description 8
- 238000001459 lithography Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- XMIJDTGORVPYLW-UHFFFAOYSA-N [SiH2] Chemical compound [SiH2] XMIJDTGORVPYLW-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- AWOORJZBKBDNCP-UHFFFAOYSA-N molybdenum;oxotungsten Chemical compound [Mo].[W]=O AWOORJZBKBDNCP-UHFFFAOYSA-N 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- -1 oxides Chemical compound 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Description
【發明所屬之技術領域】 本發明係有關於一種薄膜電晶體(thin-film transi stor ; TFT )的結構和製造方法,特別是有關於一 種主動區域為微結晶結構(micr〇cryStaiiine)之薄膜晶 體結構和製造方法。 、 【先前技術】 薄膜電晶體為液晶顯示器常用的主動元件(active e 1 emen t ),藉由薄膜電晶體的使用,使得在影像的資料 寫入期間(address period),使薄膜電晶體的半導體層 成為低電阻狀態(ON狀態),將影像資料(image data ) 傳達寫入至一電容中進而改變液晶的角度;而在保持期間 (sustain period),能夠使半導體層成為高電阻狀態 (OFF狀態)’而將該電容上所儲存的影像資料保持一 定0 常見的應用於薄膜電晶體平面顯示器的薄膜電晶體結 構如第1圖所示,其製造流程如下所述。在基板10上具有 一電晶體區,在電晶體區中形成第一金屬層,利用第一道 微影姓刻製程將第一金屬層定義成橫向配置之閘極線1 2。 接著於其上方依序沈積絕緣層1 4、半導體層(通常指非晶 石夕層,amorphous silicon layer) 16、η型摻雜石夕層18和[Technical Field] The present invention relates to a structure and a manufacturing method of a thin film-transistor (TFT), and more particularly to a thin film crystal in which an active region is a microcrystalline structure (micr〇cryStaiiine) Structure and manufacturing method. [Prior Art] A thin film transistor is an active element (active e 1 emen t ) commonly used in liquid crystal displays. By using a thin film transistor, a semiconductor of a thin film transistor is made during an address period of an image. The layer is in a low-resistance state (ON state), and the image data is written into a capacitor to change the angle of the liquid crystal; and in the sustain period, the semiconductor layer can be made into a high-resistance state (OFF state) 'And the image data stored on the capacitor is kept constant. A common thin film transistor structure applied to a thin film transistor flat panel display is shown in Fig. 1, and the manufacturing process is as follows. There is a transistor region on the substrate 10, a first metal layer is formed in the transistor region, and the first metal layer is defined as a laterally disposed gate line 12 by a first lithography process. Then, an insulating layer 14 is sequentially deposited thereon, a semiconductor layer (generally referred to as an amorphous silicon layer) 16, an n-type doped layer 18 and
0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc 第4頁0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc Page 4
1307554 案號 93102583 五、發明說明(2) 第二金屬層20 ’並進行第二道微影蝕刻製程,定義電晶體 中非晶矽層16、η型摻雜矽層18和第二金屬層2〇的圖案, 直至暴露出絕緣層1 4的表面,並在電晶體區外使第二金屬 廣20在基板10上特定位置形成縱向配置之信號線(未圖 示)°接著’進行第二道微影ϋ刻製程’以於^電晶體區内 將第二金屬層20和η型摻雜石夕層18中定義一通道 (channel ) 1 9 ’並使非晶矽層1 6的表面暴露於通道i 9 中,藉以將非晶矽層16與第二金屬層20更進—步定義形成 源極和汲極電極。 為增加非晶矽薄膜電晶體之载子在主動區域半導體層 之移動速度’現已開發出一種以氫化微結晶結構 (hydrogenated microcrystalline)之妙(一 si.jj)作為 主動區域半導體層之薄膜電晶體。此種氫化微結晶結構”之 技術具有容易和現有生產線整合的優點,此外在其結構内 電子的移動速度也較一般的非晶石夕為快。但此種氫化微择 晶結構技術因為所形成之矽層在頂部具有較大且較完整^ 結晶結構,也因此,此種氫化微結晶結構技術一般較適用 在頂部閘極(ΐ 〇 p - g a t e)結構之薄膜電晶體。 底部閘極(bottom-gate)結構之薄膜電晶體之通道區 域是半導體層鄰接閘極介電層之介面。而此技術所形成之 矽結構,在底部尤其是鄰接閘極介電層之介面是接近非晶 發之結構’也因此在通道區域電子移動速度較慢,進而景<1307554 Case No. 93102583 V. DESCRIPTION OF THE INVENTION (2) Second metal layer 20' and performing a second lithography process to define an amorphous germanium layer 16, an n-type doped germanium layer 18 and a second metal layer 2 in the transistor a pattern of germanium until the surface of the insulating layer 14 is exposed, and a second metal strip 20 is formed outside the transistor region to form a longitudinally disposed signal line (not shown) at a specific position on the substrate 10. The lithography engraving process defines a channel 1 9 ' in the second metal layer 20 and the n-type doped layer 18 in the transistor region and exposes the surface of the amorphous germanium layer 16 to In the channel i9, the amorphous germanium layer 16 and the second metal layer 20 are further stepwise defined to form a source and a drain electrode. In order to increase the moving speed of the carrier of the amorphous germanium thin film transistor in the active region semiconductor layer, a thin film of hydrogenated microcrystalline (a si.jj) has been developed as the active region semiconductor layer. Crystal. The technique of such a hydrogenated microcrystalline structure has the advantage of being easily integrated with an existing production line, and in addition, the movement speed of electrons in the structure is also faster than that of a general amorphous stone. However, such a hydrogenated micro-selective structure technique is formed. The ruthenium layer has a large and relatively complete crystal structure at the top, and therefore, such a hydrogenated microcrystalline structure technique is generally applicable to a thin film transistor of a top gate (ΐ - p - gate) structure. The channel region of the thin film transistor of the structure is the interface of the semiconductor layer adjacent to the gate dielectric layer, and the germanium structure formed by the technique has an interface at the bottom, especially adjacent to the gate dielectric layer, which is close to amorphous. The structure 'is therefore slower in the channel area, and then the scene<
.J307554 ^93ΐ〇^83 五、發明說明(3) 響薄膜電晶體之效 【發明内容】 有鑑於此,為了解決上述問豸 供種薄膜電晶體的製造方法 目的在於提 ;體之開極介電層上進行一離子佈植;m吉構薄膜電 八;排以从介電層表面之之表面狀態例如:表面处县 UHgned)的接:疋/jm = Zati〇n) 1成排列一致 體層時,可在δ也因此在後續形成微結晶、结構之半導 在通道區域的接面形成具有較整赛 結晶顆粒較大之I #接 取八有較整齊結晶排列I. 速度,改進進而增加電子在其中的移動 及没汉進涛犋電晶體的效能。 ’’’、勺上述目的,本發明提供一種薄膜電晶體的製造 ^法丄匕括下列步驟:首先,提供一基板,其中基板上形 有閘極’及一閘極介電層覆蓋閘極及基板。接下來, 對閘極介電層進行一離子佈植步驟,及形成一半導體層於 閘極介電層上。 .一為達成上述目的,本發明提供一種薄膜電晶體,包括 :一基板、一閘極介電層於基板上,其中閘極介電層具有 親矽表面、一半導體層位於閘極介電層上,其中半導體層 在鄰接閘極介電層的部分為近結晶狀結構,另一部分為近.J307554 ^93ΐ〇^83 V. DESCRIPTION OF THE INVENTION (3) Effect of the thin film transistor [Invention] In view of the above, in order to solve the above problem, the method for manufacturing the thin film transistor is aimed at improving the body An ion implantation is performed on the electric layer; the m-shaped thin film is electrically arranged; the surface state from the surface of the dielectric layer is, for example, the surface of the UHgned surface: 疋/jm = Zati〇n) In the case of δ, and thus in the subsequent formation of microcrystals, the semiconducting of the structure is formed in the junction region of the channel region, and the larger the crystal grains are, the larger the crystal grain is arranged. I have a more uniform crystal arrangement I. Speed, improvement and increase The movement of electrons in it and the performance of the crystals without Hanjintao. For the above purpose, the present invention provides a method for fabricating a thin film transistor, comprising the steps of: firstly, providing a substrate having a gate electrode and a gate dielectric layer covering the gate and Substrate. Next, an ion implantation step is performed on the gate dielectric layer, and a semiconductor layer is formed on the gate dielectric layer. In order to achieve the above object, the present invention provides a thin film transistor comprising: a substrate and a gate dielectric layer on the substrate, wherein the gate dielectric layer has a relative surface and a semiconductor layer is located at the gate dielectric layer Above, wherein the semiconductor layer is in a nearly crystalline structure in a portion adjacent to the gate dielectric layer, and the other portion is near
1307554魏93撤娜 五、發明說明(4) 非晶狀結構。 所附圖示,作 明頻和其他目的、特徵、和優點能更 月顯易廋,下文特舉一較佳實施例,並配合 詳細說明如下: 【實施方式】 實施例 首先,b第2A圖所示,以一沉積方法,例如減鍵法, 形成一閘極層於一基板2 0 〇上,其基板2 〇 〇較佳為一玻璃基 板’且其閘極層較佳為一金屬層,其可由纽(τ a'')、鶴 (W)、鉬(Mo)、鈦(Ti)、鉻(Cr)、鋁(A1)或其合金所組 成。之後,以一般的微影蝕刻方法,圖形化閘極層,'以 成一閘極202於基板200上。 曰 接下來,如第2Β圖所示,以一沉積方法,例如化學氣 相沉積方法(chemi cal vapor depos i t ion),形成一閘極 介電層204覆蓋閘極202及基板2 0 0,其閘極介電層2〇4 為擇自下列分子所組成之族群:钽的氧化物、鎢的氧化 鉬的氧化物、鈦的氧化物、鉻的氧化物、鋁的氧化物、 的氧化物、矽的氮化物、矽的氮氧化物和其組合。 之後,如第2C圖所示,對閘極介電層204進行一表面 改質步驟’例如:離子佈植步驟2〇6,以改變閘極介電層1307554 Wei 93 withdrawal Na V. Invention description (4) Amorphous structure. The accompanying drawings, as well as other objects, features, and advantages, will be more readily apparent, and a preferred embodiment will be described below with reference to the detailed description as follows: [Embodiment] First, b, Figure 2A As shown, a gate layer is formed on a substrate 20 by a deposition method, such as a subtractive bonding method. The substrate 2 is preferably a glass substrate and the gate layer is preferably a metal layer. It may be composed of New Zealand (τ a''), crane (W), molybdenum (Mo), titanium (Ti), chromium (Cr), aluminum (A1) or alloys thereof. Thereafter, the gate layer is patterned in a general lithography process to form a gate 202 on the substrate 200. Next, as shown in FIG. 2, a gate dielectric layer 204 is formed to cover the gate 202 and the substrate 200 by a deposition method such as a chemical vapor deposition method. The gate dielectric layer 2〇4 is a group selected from the group consisting of oxides of cerium, oxides of tungsten molybdenum oxide, oxides of titanium, oxides of chromium, oxides of aluminum, oxides, Niobium nitride, niobium oxynitride and combinations thereof. Thereafter, as shown in FIG. 2C, a surface modification step is performed on the gate dielectric layer 204, for example, an ion implantation step 2〇6 to change the gate dielectric layer.
五、發明說明(5) 204严面之表面狀態,例如:表面能4,分子排列結構, 或疋極性(P〇larization),形成排列一致Uligned)的接 面。其離子佈植步驟2〇6可以一次單一角度佈植,或是數 次不同角度佈植。易言之’其可在一次單一方向佈植之 後,轉換一角度再一次進行離子佈植2〇6。為使佈植之元 素不和閘極介電層204產生化學反應,其佈植之原子較 2 =氣體之原子,例如:m氪或^此 佈植步驟20 6主要目的是改變閘極介電層2()4表面之狀離, 用不同的元素、佈植能[佈植角度和摻雜;'重 複進仃試驗,並於之後檢驗閘極介電層2〇6表面之狀態。 其檢驗之方法,可以是形成一液晶層3〇2於閘極介電 層204上,藉由顯微鏡觀察液晶層3〇2之長條形液晶分子 304為垂直排列,如第3Α圖所示之局部放大圖,或是水平 排列’如第3Β圖所示之局部放大圖,檢驗開極介電層2〇4 之表面狀態是否改變。例如:若是其離子佈植2Q6前長條 形液晶分子304為垂直排列’離子佈植2〇6後長條形液晶分 子304改變為水平排列,即可得知其閘極介電層2〇4表面之 極性改變’使其上的液晶分子3〇4從傾向垂直排列變更為 傾向水平排列。在此需注意的是,其離子佈植2〇6之步驟 可以是在形成閘極介電層204後,於沉積室内進行離子佈 植’或是於沉積室外在破真空後進行離子佈植2〇6,其目 的為找到一閘極介電層2 04之表面狀態之最佳條件以進行 後續之主動區域半導體層20 8之 接者,如第2D圖所示,以— (PECVD),形成一半導體層2=:例如電漿化學氣相沉積法 =體層208可以為石夕或鍺,較佳於^極介電層204上。其半 (S i & )和氫氣,以Α Γ為導引 馬在 >儿積室内通入矽烷 反應室中將矽烷(S i札)分解為=沉積室輔以電漿反應,在 閘極介電層上。更佳為—層二听有電荷之S i扎和S i扎沉積在 方式形成,以達到微結晶化二by layer)堆疊的 206步驟’改變閘極介電層2〇曰的。經由上述之離子佈植 半導體208,在長晶之過程 之表面狀態,使此步驟形成 形之SiHs或Si I分子210由原太^極介電層204表面之長條 204表面,改變為長軸傾向'平〜長輛傾向垂直於閘極介電層 言之,閘極介電層具有親石夕订於閑極介電層20 4表面。易 狀態經由離子佈植步驟後,# = a 介電層表面2〇4之 之矽肩早。 後較傾向吸引Sil和SiH2分子210 如第4A和4B圖所示,在a 電層表面204之SiH3 *Siii八n i過程中,若是閘極介 電層204表面進行^積;;此軸傾向垂直於問極介 形成之半導體層208,'在接】= :::=(Seeding layer)所 域2 12會形成較接近非晶狀之二” :204表面之通道區 且曰, 、电層表面之心札和Sih分子21〇作為 長晶層(Seeding Uyer)所形成之半導體層2〇8,在接近問 極介電層204表面之通道^^會形成……V. INSTRUCTIONS (5) 204 Surface states of the surface, such as surface energy 4, molecular arrangement, or P〇larization, forming a uniform Uligned joint. The ion implantation step 2〇6 can be planted at a single angle or at several different angles. It is easy to say that it can be ion-implanted 2〇6 after one angle of implantation in one direction. In order to prevent the implanted elements from chemically reacting with the gate dielectric layer 204, the implanted atoms are more than 2 = gas atoms, for example: m氪 or ^. The implantation step 20 6 is mainly to change the gate dielectric. Layer 2 () 4 surface separation, with different elements, planting energy [planting angle and doping; 'repeated enthalpy test, and then verify the state of the gate dielectric layer 2 〇 6 surface. The method for inspecting may be to form a liquid crystal layer 3〇2 on the gate dielectric layer 204, and the long liquid crystal molecules 304 of the liquid crystal layer 3〇2 are vertically aligned by a microscope, as shown in FIG. A partial enlargement, or a horizontal arrangement of a partial enlargement as shown in Fig. 3, verifies whether the surface state of the open dielectric layer 2〇4 is changed. For example, if the ion-plated 2Q6 long strip-shaped liquid crystal molecules 304 are vertically aligned, after the ion-plated liquid crystal molecules 304 are changed to a horizontal arrangement, the gate dielectric layer 2〇4 can be known. The change in the polarity of the surface is such that the liquid crystal molecules 3〇4 on the surface are changed from a tendency to a vertical arrangement to a tendency to be horizontally aligned. It should be noted that the step of ion implantation 2〇6 may be ion implantation in the deposition chamber after forming the gate dielectric layer 204 or ion implantation after vacuuming outside the deposition chamber 2 〇6, the purpose of which is to find the optimum condition of the surface state of a gate dielectric layer 408 for subsequent contact of the active region semiconductor layer 20, as shown in FIG. 2D, by - (PECVD) A semiconductor layer 2 =: for example, a plasma chemical vapor deposition method = the bulk layer 208 may be a stone or germanium, preferably on the dielectric layer 204. The half (S i & ) and hydrogen are guided by Α 马 in the 积 积 通 通 通 反应 反应 反应 反应 反应 反应 反应 = = = = = = = = = = = = = = = = = = = = = = = = 沉积 沉积 沉积 沉积 沉积On the dielectric layer. More preferably, the layer 2 listens to the charge of the Si and the S i is deposited in a manner to achieve the microcrystallization of the second layer of the step 206 of the step of changing the gate dielectric layer 2'. Through the above-described ion implantation semiconductor 208, the SiHs or Si I molecules 210 formed in this step are changed from the surface of the strip 204 of the surface of the original dielectric layer 204 to the long axis in the surface state of the process of the crystal growth. The tendency to 'flat ~ long vehicle tends to be perpendicular to the gate dielectric layer, and the gate dielectric layer has a lithophile layer disposed on the surface of the dummy dielectric layer 204. Easy state After the ion implantation step, # = a dielectric layer surface 2〇4 of the shoulder is early. Afterwards, it is more inclined to attract the Sil and SiH2 molecules 210, as shown in Figures 4A and 4B, in the SiH3*Siii8 process of the surface 204 of the a layer, if the surface of the gate dielectric layer 204 is formed; In the semiconductor layer 208 formed by the polar interposer, the domain 2 12 of the 'contacting' = ::: = (Seeding layer) region will form a channel region which is closer to the amorphous two": 204 surface and the surface of the electric layer. The core layer and the Sih molecule 21〇 are formed as a semiconductor layer 2〇8 formed by a seeding layer, and a channel close to the surface of the dielectric layer 204 is formed.
0632-A50065TWfl(4.5) ; AU0310005 : Wayne.ptc ~ 1307554 案號 93in?f^i__. 五、發明說明(7) ' ^—且 _ ’ (crystalline)且晶格大之結構, 率。 有較快之電子移動速 接下來,如第2E圖所示,於 積摻雜半導體層220和導電層222 體層2〇8上方依序沉 定義摻雜半導體層220和導4展2 ’並進行微影蝕刻製程, 外使導電層222在基板t胳定:22的圖案,並在電晶體區 (未圖示)。接著,進行微影餘也成縱向配置之信號線 將導電層2 2和摻雜半導 體層220中Λ程’以於電晶體區内 (channel),以使半導體層2〇8中又義一通道224 中,藉以將半導體層2〇8與導 的表面暴露於通道224 極和汲極電極。 ” θ 22 2更進~~步定義形成源 【本發明之特徵和優點】 本發明之特徵在於提供 方法’其在底部閘極結構薄 一離子佈植製程,藉由離子 之表面狀態’例如:表面能 (polar ization),形成排列 此在後續形成微結晶結構之 接面形成具有較整齊結晶排 構,進而增加電子在其中的 效能。 種薄骐電晶體的結構和製造 媒電晶體之閘極介電層上進行 ,植製程改變閘極介電層表面 量’分子排列結構,或是極性 一致(aligned)的接面,也因 半導體層時’可在通道區域的 列且結晶顆粒較大之半導體結 移動速度,增進薄膜電晶體的0632-A50065TWfl(4.5) ; AU0310005 : Wayne.ptc ~ 1307554 Case No. 93in?f^i__. V. Description of invention (7) ' ^ - and _ ' (crystalline) and large lattice structure, rate. There is a faster electron moving speed. Next, as shown in FIG. 2E, the doped semiconductor layer 220 and the conductive layer 220 are sequentially defined over the bulk layer 2〇8 of the conductive doped semiconductor layer 220 and the conductive layer 222. In the lithography process, the conductive layer 222 is patterned on the substrate t: 22 and in the transistor region (not shown). Then, the signal line of the lithography is also arranged in a longitudinal direction to pass the process in the conductive layer 2 2 and the doped semiconductor layer 220 to the channel of the transistor, so that a channel 224 is defined in the semiconductor layer 2 〇 8 The semiconductor layer 2〇8 and the exposed surface are exposed to the channel 224 and the drain electrode. θ 22 2 Further steps to define the source of formation [Features and Advantages of the Invention] The present invention is characterized by providing a method of thinning an ion implantation process at the bottom gate structure by the surface state of ions 'eg: Polarization, forming an arrangement to form a more uniform crystal structure in the subsequent formation of a microcrystalline structure, thereby increasing the efficiency of electrons therein. The structure of the thin germanium transistor and the gate for fabricating the dielectric transistor Conducted on the dielectric layer, the process changes the surface of the gate dielectric layer 'molecular alignment structure, or the aligned junctions, and the semiconductor layer can be in the channel region and the crystal particles are larger. Semiconductor junction moving speed, enhancing thin film transistor
1307554 案號 93102583_年月日__ 五、發明說明(8) 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作些許之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。</ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; In the spirit and scope, the scope of protection of the present invention is defined by the scope of the appended claims.
0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc 第11頁 1307554 案號 93102583_年月日_i±^._ 圖式簡單說明 第1圖係顯示習知薄膜電晶體之製造方法。。 第2 A〜2E圖係顯示本發明較佳實施例薄膜電晶體之製 造方法。 第3 A和3 B圖係顯示檢驗閘極介電層表面狀態方法之局 部放大圖。 第4A圖、第4B圖、第4C圖、第4D圖係顯示本發明半導 體層之局部放大圖。 【符號說明】 習知技術 基板〜1 0 ; 閘極線·~ 1 2 ; 絕緣層〜1 4 ; 半導體層〜16 ; η型摻雜ί夕層〜18 ; 通道〜19 ; 金屬層~ 2 0。 本發明技術 基板〜2 0 0 ; 閘極〜2 0 2 ; 閘極介電層〜2 0 4 ; 離子佈植步驟〜2 0 6 ; 半導體層〜2 08 ;0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc Page 11 1307554 Case No. 93102583_年月日日_i±^._ BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a method of manufacturing a conventional thin film transistor. . 2A to 2E are views showing a method of manufacturing a thin film transistor of a preferred embodiment of the present invention. Figures 3A and 3B show a magnified view of the method for verifying the surface state of the gate dielectric layer. 4A, 4B, 4C, and 4D are partial enlarged views of the semiconductor layer of the present invention. [Description of symbols] Conventional technology substrate ~1 0; gate line ·~1 2 ; insulating layer ~1 4 ; semiconductor layer ~16; n-type doping 夕 夕 layer ~18; channel ~19; metal layer ~ 2 0 . The substrate of the present invention is ~200; the gate is ~2 0 2 ; the gate dielectric layer is ~2 0 4 ; the ion implantation step is ~2 0 6 ; the semiconductor layer is ~2 08 ;
0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc 第12頁 ,1307554 案號93102583_年月日_修正 圖式簡單說明 ' S i H3 或 S i H2 分子〜2 1 0 ; 通道區域~ 2 1 2 ; 摻雜半導體層〜220 ; 導電層〜2 2 2 ; 液晶層〜3 0 2 ; 長條形液晶分子〜304。0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc Page 12, 1307554 Case No. 93102583_Year of the month _ Correct illustration of the simple description 'S i H3 or S i H2 molecule ~ 2 1 0 ; Channel area ~ 2 1 2 Doped semiconductor layer ~220; conductive layer ~2 2 2 ; liquid crystal layer ~3 0 2 ; long strip liquid crystal molecule ~304.
0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc 第13頁0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc Page 13
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