TWI307554B - A thin film transistor and method of fabrication the same - Google Patents

Description

[Technical Field] The present invention relates to a structure and a manufacturing method of a thin film-transistor (TFT), and more particularly to a thin film crystal in which an active region is a microcrystalline structure (micr〇cryStaiiine) Structure and manufacturing method. [Prior Art] A thin film transistor is an active element (active e 1 emen t ) commonly used in liquid crystal displays. By using a thin film transistor, a semiconductor of a thin film transistor is made during an address period of an image. The layer is in a low-resistance state (ON state), and the image data is written into a capacitor to change the angle of the liquid crystal; and in the sustain period, the semiconductor layer can be made into a high-resistance state (OFF state) 'And the image data stored on the capacitor is kept constant. A common thin film transistor structure applied to a thin film transistor flat panel display is shown in Fig. 1, and the manufacturing process is as follows. There is a transistor region on the substrate 10, a first metal layer is formed in the transistor region, and the first metal layer is defined as a laterally disposed gate line 12 by a first lithography process. Then, an insulating layer 14 is sequentially deposited thereon, a semiconductor layer (generally referred to as an amorphous silicon layer) 16, an n-type doped layer 18 and

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1307554 Case No. 93102583 V. DESCRIPTION OF THE INVENTION (2) Second metal layer 20' and performing a second lithography process to define an amorphous germanium layer 16, an n-type doped germanium layer 18 and a second metal layer 2 in the transistor a pattern of germanium until the surface of the insulating layer 14 is exposed, and a second metal strip 20 is formed outside the transistor region to form a longitudinally disposed signal line (not shown) at a specific position on the substrate 10. The lithography engraving process defines a channel 1 9 ' in the second metal layer 20 and the n-type doped layer 18 in the transistor region and exposes the surface of the amorphous germanium layer 16 to In the channel i9, the amorphous germanium layer 16 and the second metal layer 20 are further stepwise defined to form a source and a drain electrode. In order to increase the moving speed of the carrier of the amorphous germanium thin film transistor in the active region semiconductor layer, a thin film of hydrogenated microcrystalline (a si.jj) has been developed as the active region semiconductor layer. Crystal. The technique of such a hydrogenated microcrystalline structure has the advantage of being easily integrated with an existing production line, and in addition, the movement speed of electrons in the structure is also faster than that of a general amorphous stone. However, such a hydrogenated micro-selective structure technique is formed. The ruthenium layer has a large and relatively complete crystal structure at the top, and therefore, such a hydrogenated microcrystalline structure technique is generally applicable to a thin film transistor of a top gate (ΐ - p - gate) structure. The channel region of the thin film transistor of the structure is the interface of the semiconductor layer adjacent to the gate dielectric layer, and the germanium structure formed by the technique has an interface at the bottom, especially adjacent to the gate dielectric layer, which is close to amorphous. The structure 'is therefore slower in the channel area, and then the scene<

.J307554 ^93ΐ〇^83 V. DESCRIPTION OF THE INVENTION (3) Effect of the thin film transistor [Invention] In view of the above, in order to solve the above problem, the method for manufacturing the thin film transistor is aimed at improving the body An ion implantation is performed on the electric layer; the m-shaped thin film is electrically arranged; the surface state from the surface of the dielectric layer is, for example, the surface of the UHgned surface: 疋/jm = Zati〇n) In the case of δ, and thus in the subsequent formation of microcrystals, the semiconducting of the structure is formed in the junction region of the channel region, and the larger the crystal grains are, the larger the crystal grain is arranged. I have a more uniform crystal arrangement I. Speed, improvement and increase The movement of electrons in it and the performance of the crystals without Hanjintao. For the above purpose, the present invention provides a method for fabricating a thin film transistor, comprising the steps of: firstly, providing a substrate having a gate electrode and a gate dielectric layer covering the gate and Substrate. Next, an ion implantation step is performed on the gate dielectric layer, and a semiconductor layer is formed on the gate dielectric layer. In order to achieve the above object, the present invention provides a thin film transistor comprising: a substrate and a gate dielectric layer on the substrate, wherein the gate dielectric layer has a relative surface and a semiconductor layer is located at the gate dielectric layer Above, wherein the semiconductor layer is in a nearly crystalline structure in a portion adjacent to the gate dielectric layer, and the other portion is near

1307554 Wei 93 withdrawal Na V. Invention description (4) Amorphous structure. The accompanying drawings, as well as other objects, features, and advantages, will be more readily apparent, and a preferred embodiment will be described below with reference to the detailed description as follows: [Embodiment] First, b, Figure 2A As shown, a gate layer is formed on a substrate 20 by a deposition method, such as a subtractive bonding method. The substrate 2 is preferably a glass substrate and the gate layer is preferably a metal layer. It may be composed of New Zealand (τ a''), crane (W), molybdenum (Mo), titanium (Ti), chromium (Cr), aluminum (A1) or alloys thereof. Thereafter, the gate layer is patterned in a general lithography process to form a gate 202 on the substrate 200. Next, as shown in FIG. 2, a gate dielectric layer 204 is formed to cover the gate 202 and the substrate 200 by a deposition method such as a chemical vapor deposition method. The gate dielectric layer 2〇4 is a group selected from the group consisting of oxides of cerium, oxides of tungsten molybdenum oxide, oxides of titanium, oxides of chromium, oxides of aluminum, oxides, Niobium nitride, niobium oxynitride and combinations thereof. Thereafter, as shown in FIG. 2C, a surface modification step is performed on the gate dielectric layer 204, for example, an ion implantation step 2〇6 to change the gate dielectric layer.

V. INSTRUCTIONS (5) 204 Surface states of the surface, such as surface energy 4, molecular arrangement, or P〇larization, forming a uniform Uligned joint. The ion implantation step 2〇6 can be planted at a single angle or at several different angles. It is easy to say that it can be ion-implanted 2〇6 after one angle of implantation in one direction. In order to prevent the implanted elements from chemically reacting with the gate dielectric layer 204, the implanted atoms are more than 2 = gas atoms, for example: m氪 or ^. The implantation step 20 6 is mainly to change the gate dielectric. Layer 2 () 4 surface separation, with different elements, planting energy [planting angle and doping; 'repeated enthalpy test, and then verify the state of the gate dielectric layer 2 〇 6 surface. The method for inspecting may be to form a liquid crystal layer 3〇2 on the gate dielectric layer 204, and the long liquid crystal molecules 304 of the liquid crystal layer 3〇2 are vertically aligned by a microscope, as shown in FIG. A partial enlargement, or a horizontal arrangement of a partial enlargement as shown in Fig. 3, verifies whether the surface state of the open dielectric layer 2〇4 is changed. For example, if the ion-plated 2Q6 long strip-shaped liquid crystal molecules 304 are vertically aligned, after the ion-plated liquid crystal molecules 304 are changed to a horizontal arrangement, the gate dielectric layer 2〇4 can be known. The change in the polarity of the surface is such that the liquid crystal molecules 3〇4 on the surface are changed from a tendency to a vertical arrangement to a tendency to be horizontally aligned. It should be noted that the step of ion implantation 2〇6 may be ion implantation in the deposition chamber after forming the gate dielectric layer 204 or ion implantation after vacuuming outside the deposition chamber 2 〇6, the purpose of which is to find the optimum condition of the surface state of a gate dielectric layer 408 for subsequent contact of the active region semiconductor layer 20, as shown in FIG. 2D, by - (PECVD) A semiconductor layer 2 =: for example, a plasma chemical vapor deposition method = the bulk layer 208 may be a stone or germanium, preferably on the dielectric layer 204. The half (S i & ) and hydrogen are guided by Α 马 in the 积 积 通 通 通 反应 反应 反应 反应 反应 反应 反应 = = = = = = = = = = = = = = = = = = = = = = = = 沉积 沉积 沉积 沉积 沉积On the dielectric layer. More preferably, the layer 2 listens to the charge of the Si and the S i is deposited in a manner to achieve the microcrystallization of the second layer of the step 206 of the step of changing the gate dielectric layer 2'. Through the above-described ion implantation semiconductor 208, the SiHs or Si I molecules 210 formed in this step are changed from the surface of the strip 204 of the surface of the original dielectric layer 204 to the long axis in the surface state of the process of the crystal growth. The tendency to 'flat ~ long vehicle tends to be perpendicular to the gate dielectric layer, and the gate dielectric layer has a lithophile layer disposed on the surface of the dummy dielectric layer 204. Easy state After the ion implantation step, # = a dielectric layer surface 2〇4 of the shoulder is early. Afterwards, it is more inclined to attract the Sil and SiH2 molecules 210, as shown in Figures 4A and 4B, in the SiH3*Siii8 process of the surface 204 of the a layer, if the surface of the gate dielectric layer 204 is formed; In the semiconductor layer 208 formed by the polar interposer, the domain 2 12 of the 'contacting' = ::: = (Seeding layer) region will form a channel region which is closer to the amorphous two": 204 surface and the surface of the electric layer. The core layer and the Sih molecule 21〇 are formed as a semiconductor layer 2〇8 formed by a seeding layer, and a channel close to the surface of the dielectric layer 204 is formed.

0632-A50065TWfl(4.5) ; AU0310005 : Wayne.ptc ~ 1307554 Case No. 93in?f^i__. V. Description of invention (7) ' ^ - and _ ' (crystalline) and large lattice structure, rate. There is a faster electron moving speed. Next, as shown in FIG. 2E, the doped semiconductor layer 220 and the conductive layer 220 are sequentially defined over the bulk layer 2〇8 of the conductive doped semiconductor layer 220 and the conductive layer 222. In the lithography process, the conductive layer 222 is patterned on the substrate t: 22 and in the transistor region (not shown). Then, the signal line of the lithography is also arranged in a longitudinal direction to pass the process in the conductive layer 2 2 and the doped semiconductor layer 220 to the channel of the transistor, so that a channel 224 is defined in the semiconductor layer 2 〇 8 The semiconductor layer 2〇8 and the exposed surface are exposed to the channel 224 and the drain electrode. θ 22 2 Further steps to define the source of formation [Features and Advantages of the Invention] The present invention is characterized by providing a method of thinning an ion implantation process at the bottom gate structure by the surface state of ions 'eg: Polarization, forming an arrangement to form a more uniform crystal structure in the subsequent formation of a microcrystalline structure, thereby increasing the efficiency of electrons therein. The structure of the thin germanium transistor and the gate for fabricating the dielectric transistor Conducted on the dielectric layer, the process changes the surface of the gate dielectric layer 'molecular alignment structure, or the aligned junctions, and the semiconductor layer can be in the channel region and the crystal particles are larger. Semiconductor junction moving speed, enhancing thin film transistor

</ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; In the spirit and scope, the scope of protection of the present invention is defined by the scope of the appended claims.

0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc Page 11 1307554 Case No. 93102583_年月日日_i±^._ BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a method of manufacturing a conventional thin film transistor. . 2A to 2E are views showing a method of manufacturing a thin film transistor of a preferred embodiment of the present invention. Figures 3A and 3B show a magnified view of the method for verifying the surface state of the gate dielectric layer. 4A, 4B, 4C, and 4D are partial enlarged views of the semiconductor layer of the present invention. [Description of symbols] Conventional technology substrate ~1 0; gate line ·~1 2 ; insulating layer ~1 4 ; semiconductor layer ~16; n-type doping 夕 夕 layer ~18; channel ~19; metal layer ~ 2 0 . The substrate of the present invention is ~200; the gate is ~2 0 2 ; the gate dielectric layer is ~2 0 4 ; the ion implantation step is ~2 0 6 ; the semiconductor layer is ~2 08 ;

0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc Page 12, 1307554 Case No. 93102583_Year of the month _ Correct illustration of the simple description 'S i H3 or S i H2 molecule ~ 2 1 0 ; Channel area ~ 2 1 2 Doped semiconductor layer ~220; conductive layer ~2 2 2 ; liquid crystal layer ~3 0 2 ; long strip liquid crystal molecule ~304.

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Claims (1)

t « Touching charm 2583_年月日日__ VI. Patent application scope&quot; 1. A method for manufacturing a thin film transistor, comprising the steps of: providing a substrate, wherein a gate is formed on the substrate, and a gate is formed a dielectric layer is disposed on the gate and the substrate; an ion implantation step is performed on the gate dielectric layer; and a semiconductor layer is formed on the gate dielectric layer. 2. The method for producing a thin film transistor according to claim 1, wherein the gate dielectric layer is selected from the group consisting of oxides of cerium, oxides of oxides of cranes, An oxide of titanium, an oxide of chromium, an oxide of aluminum, an oxide of cerium, a nitride of cerium, an oxynitride of cerium, and combinations thereof. 3. The method of producing a thin film transistor according to claim 1, wherein the ion implantation step is performed at the same angle. 4. The method of producing a thin film transistor according to claim 1, wherein the ion implantation step is an atom of a passive gas. 5. The method of producing a thin film transistor according to claim 4, wherein the atomic system of the passive gas is selected from the group consisting of: 氦, 氖, 氪, 氪, 氙. 6. The method of producing a thin film transistor according to claim 1, wherein the semiconductor layer is a micro-crystalline structure. 7. The method of manufacturing a thin film transistor according to claim 6, wherein the microcrystallized structure is a structure closer to the surface of the gate dielectric layer than the crystal (crysta 11 ine). The other part is a structure that is closer to amorphous. 0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc Page 14 &gt; 1307554 Case No. 93102583_年月日日__ VI. Patent Application Scope 8. Manufacturing of thin film transistor as described in claim 1 The method wherein the semiconductor layer is formed by decomposing decane (S i H4 ) into a charged S i H3 and S i H2 deposited on a gate dielectric layer in a reaction chamber. The method for producing a thin film transistor according to the item 8, wherein the SiH3 or 8iH2 molecular system is elongated, and a long axis of the elongated strip tends to be parallel to a surface of the gate dielectric layer during deposition. The method for fabricating a thin film transistor according to claim 1, further comprising forming a doped semiconductor layer covering portion of the semiconductor layer, wherein the semiconductor layer exposes a channel region on the gate, and forms a conductive layer on the doped semiconductor layer and the substrate. 11. A method of fabricating a thin film transistor, comprising the steps of: providing a substrate; forming a gate on the substrate; forming a gate dielectric layer covering the a gate and the substrate; Performing a surface modification step on the gate dielectric layer; forming a semiconductor layer on the gate dielectric layer; forming a doped semiconductor layer on the semiconductor layer and the gate dielectric layer; patterning the blend a semiconductor layer to be exposed on the gate; and a conductive layer formed on the doped semiconductor layer, wherein the method of manufacturing a thin film transistor according to claim 1 is as follows. The substrate is a glass substrate. 1 3. Fabrication of a thin film transistor according to claim 1 0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc Page 15 Month 曰 r^^S54^_g£_93i〇2 VI. Application - Set U. The t-layer is a metal. Method #, as claimed in claim 13 of the invention, wherein the metal system is selected from the group consisting of the following groups: Group (Ta), manufacture of the steroid (1), Road (6), Shao (4), and alloys thereof. .鸪(w), Pin. The thin film electro-technical button of claim 1 wherein the gate dielectric layer is selected from the group consisting of T-column molecules to produce gas::, oxide of the crane Turned oxides, = Essence: J:, Ming's telluride, Shi Xi's oxide "Xue's vapor; chromium's emulsion and its combination. Nitrogen method 16 · Λ ^ profit range 11th The manufacturing process of the thin film transistor and the dry surface modification step are ion implantation of the gate dielectric layer. 7. The method for manufacturing a thin film transistor according to the above application. The implanting atom of the ion implantation step is an atom of a passive gas. The manufacturing method of the thin pancreatic crystal according to the seventh aspect of the patent application, wherein the atomic system of the passive gas is selected from the following atoms The method of manufacturing a thin film transistor according to the above aspect of the invention, wherein the semiconductor layer is a microcrystallized structure. The method for manufacturing a thin film transistor according to claim 19, wherein the microjunction The crystallized structure is a structure close to the surface of the gate dielectric layer, which is relatively close to the crystal. (2) The method for manufacturing the thin circuit transistor according to the first aspect of the patent application. Wherein the semiconductor layer is decomposed by SiH4 in a reaction chamber 0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc Page 16, 1307554 Case No. 93102583_年月日日__. Sixth, the scope of application for the patent is formed by the deposition of charged S i H3 and S i H2 on the gate dielectric layer. 2. The method for producing a thin film transistor according to claim 2, wherein the SiH3 or S i H2 molecular system is elongated, and the long axis of the elongated strip tends to be parallel during deposition. On the surface of the gate dielectric layer. 2 3 . A thin film transistor comprising: a substrate; a gate dielectric layer on the substrate, wherein the gate dielectric layer has a hydrophilic surface; and a semiconductor layer is on the gate dielectric layer The semiconductor layer has a near-crystalline structure in a portion adjacent to the gate dielectric layer, and the other portion is a near-amorphous structure. The thin film transistor according to claim 23, wherein the gate dielectric layer is selected from the group consisting of oxides of cerium, oxides of tungsten, oxides of indium, titanium Oxides, chromium oxides, imides oxides, shixi oxides, shixi nitrides, shixi oxynitrides, and combinations thereof. 0632-A50065TWfl(4.5) ; AU0310005 ; Wayne.ptc Page 17 1307554 Case No. 93] 〇 沾 __年月四, Chinese invention^ Ming name: Lai crystal structure and a thin film transistor manufacturer provide one a substrate on which a blanket gate and a substrate are formed. Next, the step of forming and forming a semiconductor layer in the method comprises the steps of: first, having a gate, and a gate dielectric layer, and a gate dielectric layer after ion implantation on. Wu, (1), the representative of the case is: Figure 2C. Brief description: (b), the representative of the representative figure of the case substrate ~2 0 0; gate ~ 20 2; gate dielectric layer ~ 2 0 4; ion implantation step ~ 206. A thin film transistor and method of fabrication the same, a substrate with a gate is provided, in which both are covered with a gate dielectric layer. Gate dielectric layer is implanted and foil owed by formation of a semi conductor layer 0632-A50065TWfl(4.5) : AU0310005 ; Wayne.ptc Page 2