TWI307128B - - Google Patents

Download PDF

Info

Publication number
TWI307128B
TWI307128B TW95117554A TW95117554A TWI307128B TW I307128 B TWI307128 B TW I307128B TW 95117554 A TW95117554 A TW 95117554A TW 95117554 A TW95117554 A TW 95117554A TW I307128 B TWI307128 B TW I307128B
Authority
TW
Taiwan
Prior art keywords
cover
substrate
metal
wafer
molten
Prior art date
Application number
TW95117554A
Other languages
Chinese (zh)
Other versions
TW200744137A (en
Inventor
qing-fu Zou
hong-zhong Li
Original Assignee
qing-fu Zou
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by qing-fu Zou filed Critical qing-fu Zou
Priority to TW095117554A priority Critical patent/TW200744137A/en
Publication of TW200744137A publication Critical patent/TW200744137A/en
Application granted granted Critical
Publication of TWI307128B publication Critical patent/TWI307128B/zh

Links

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Micromachines (AREA)

Description

1307128 九、發明說明: 【發明所屬之技術領域】 ^發明係有關一種晶圓級真空封裝方法 Ξίίί環境内以熔融金屬材料將貫穿孔填滿且密封之 【先前技術】 按二傳統微結構,如光電元件、射頻元件及微機電元 件專使在縣時係以單顆晶粒之方式封裝,如第8圖所 了 J係在::基座6上設有—微結構6 1,再於該基座6 容:;美:ί6 2 ’該封蓋6 2内具有一空間6 3,以供 二基上之微結構6丄,且該封蓋6 2底端之側邊 開权有一缺口 6 2 1,以供將該封蓋6 2内之空間6 3抽 =空狀態,再㈣膠方式將該缺口621封閉,而 對裝。 由^封蓋6 2之缺口 6 2 1係開在側邊,在點膠時 j刀购作,纽同時师,因此不適用晶該之封裝方 :量其點膠之量非常微小,容易造成點膠 置不易控制,而無法確實封閉住缺口 6 2 1。 =二而有另一種晶圓級之封裝方式,如第9圖所示 糸在一晶圓片7上設置多數之微結構7 1,再以至朵 及㈣製程分別在各微結構7 1上製作出封蓋7 2,1各 ,封蓋72之頂面分別開設有孔洞72 1,以供將封蓋7 2内之”?3抽成真錄態,再以驗法 = 上鍍上-層封裝層74,以封閉該孔洞721,再經^ 1307128 成單顆之晶粒,而完成封裝。 ,前述之封裝方式,雖可以晶圓級方式封裝,以增加封 裝製程之效率,但是在開設該封蓋7 2上之孔洞7 2丄 ,必須將孔洞7 2 1控制在1〜2微米或是更小之尺寸, 否則在蒸鍍封裝層7 4時,其蒸鍍材料之微粒無法填滿該 孔洞7 2 1,造成無法封閉住該孔洞7 2丄,如此一來广 需以高階的製程來開設該微小之孔洞72工',梦 之成本增加。 訶裒 ^在蒸錢封裝層7 4時,係以金屬材料為蒸錢材 4,,、蒸鍍材料之金屬微粒沉積在該封蓋7 2上時,會 些許之金屬微粒由孔洞7 2 1落入封蓋72内,而沉^在 微二構71上,並對其產生污染,進而影響到微結構7 1 .- 之效能,造成品質不良。 除此,在蝕刻製程去除微結構7 i周圍之犧牲層時, 由於封蓋7 2與微結構7 1之間的犧牲層厚度有限,餘刻 ί瓜動f生不佳’造成其#刻之效果不易控制,無法綠實去 除微結構7 1周圍之犧牲層,而影響微結構 造成製程良率之降低。 b 此外’上述利用薄膜沈積以達成真空封裝之方式,並 封裝環境之真空度需達到一定等級,才能讓所欲沈積之乾 材順利沈積至被沈積物上,例如以熱阻絲蒸鍵機進行蒸鐘 沈積時丄其要求之真空度需達標準,始可適用 ’然而高規格設備之要求即意味著高成本之支出。 故,對於習知微結構之封裝方式,無論是在結構上及 6 1307128 ’仍有待改善。 在製程上所產生之缺失 【發明内容】 晶圓===,、在=決上述的問題而提供-種 之方式,可避㈣^ ),其精金屬之溶融材料熔融封裝 染。 《絲朗料齡對各顧結構造成之污1307128 IX. Description of the invention: [Technical field to which the invention pertains] The invention relates to a wafer-level vacuum packaging method in which a through-hole is filled and sealed with a molten metal material. [Prior Art] According to a conventional microstructure, The optoelectronic component, the radio frequency component, and the microelectromechanical component are specifically packaged in a single crystal in the county. As shown in Fig. 8, the J system is provided on the base 6 with a microstructure 6 1 and then Block 6:: US: ί6 2 'The cover 6 2 has a space 6 3 for the microstructure of the second base 6 丄, and the side of the bottom end of the cover 6 2 has a gap 6 2 1, for the space 6 3 in the cover 6 2 is pumped = empty state, and then the gap 621 is closed by the (four) glue method, and is mounted. The notch 6 2 1 of the cover 6 2 is fastened on the side, and the j-knife is purchased at the time of dispensing, so the new one is not suitable for the package of the crystal: the amount of the glue is very small, which is easy to cause The dispensing position is not easy to control, and the gap 6 2 1 cannot be reliably closed. There is another wafer-level packaging method. As shown in FIG. 9, a plurality of microstructures 7 are disposed on a wafer 7, and then a process is performed on each of the microstructures 71. Each of the cover covers 7 2, 1 and the top surface of the cover 72 are respectively provided with a hole 72 1 for drawing the "?3" in the cover 7 2 into a true recording state, and then performing the test = plating on the layer The encapsulation layer 74 is used to close the hole 721 and then form a single die through the ^ 1307128 to complete the encapsulation. The foregoing packaging method can be packaged in a wafer level manner to increase the efficiency of the packaging process, but The hole 7 2 上 on the cover 7 2 must be controlled to a size of 1 to 2 μm or less, otherwise the particles of the evaporation material cannot be filled when the encapsulation layer 74 is vapor-deposited. The hole 7 2 1 makes it impossible to close the hole 7 2丄, so it is necessary to open the tiny hole 72 by a high-order process, and the cost of the dream increases. 诃裒^ When the steaming encapsulation layer is 7 4 The metal material is a steamed material 4, and when the metal particles of the vapor deposition material are deposited on the cover 71, there are some metal particles. The hole 7 2 1 falls into the cover 72, and is deposited on the micro-two structure 71, and pollutes it, thereby affecting the performance of the microstructure 7 1 .-, resulting in poor quality. In addition, the etching process is removed. When the sacrificial layer around the microstructure 7 i is limited, since the thickness of the sacrificial layer between the cover 7 2 and the microstructure 7 1 is limited, the effect of the engraving is not easy to control, and the effect of the engraving is not easy to control, and it is impossible to green. The sacrificial layer around the microstructure 7 1 is removed, and the microstructure is affected to reduce the yield of the process. b In addition, the above-mentioned film deposition is used to achieve vacuum packaging, and the vacuum degree of the package environment needs to reach a certain level. The deposited dry material is deposited smoothly on the sediment, for example, when the steam is deposited by the thermal resistance wire steamer, the required vacuum is required to meet the standard. However, the requirement of high specification equipment means high cost. Therefore, for the conventional micro-structure encapsulation method, both in structure and 6 1307128 'has still to be improved. The lack of production in the process [invention content] wafer ===, in = above Problem with - kind In the way, it can avoid (4)^), and the molten metal of the molten metal is melt-encapsulated and dyed.

在於解決上述的問題而提供一種 ’其係可於較低溫度製程下,進 本發明之再一目的, 晶圓級真空封裝方法(一) 行熔融封裳。 ,達刖述之目的,本發明係包括一種晶圓級真空封裝 ^ ),其包括下列步驟: 封裝結構製程,係提供一基板及一封蓋,其中該基板 參-面係設有數微結構,而贿蓋係可蓋合於該基板設有數 微結構之-面,且該封蓋與該基板對應各該微結構之間係 分別具有-空間,以供分別容納各該微結構,且該封蓋於 其異於蓋·合該基板之一面,在對應各該空間之位置處分別 關設至少一貫穿孔’俾供連通各該空間; 封裝製程,係於該基板與該封蓋之相接處分別設有-金廣之㈣材料,及於各該貫穿孔處分別填人—金屬之溶 融材料,並於該封蓋之金屬之熔融材料上施以-載重,再 將此兩相對準之基板與封蓋所在之環境真空化,續對其施 7 1307128 予一熱源以使該兩金屬之熔融材料同時熔融,俾供同時完 成該基板與該封蓋之接合以及各該貫穿孔之密封,俾使各 該空間内之各微結構處於一真空狀態。 本發明之上述及其他目的與優點,不難從下述所選用 實施例之詳細說明與附圖中,獲得深入了解。 . 當然,本發明在某些另件上,或另件之安排上容許有 所不同,但所選用之實施例,則於本說明書中,予以詳細 說明,並於附圖中展示其構造。 •【實施方式】 請參閱第1圖至第7圖,圖中所示者為本發明所選用 之實施例結構,此僅供說明之用,在專利申請上並不受此 種結構之限制。 本實施例提供一種晶圓級真空封裝方法(一),其包括 下列步驟: 封裝結構製程1,係提供一基板1 1及一封蓋1 2, 其中該基板1 1與該封蓋1 2係選用矽、玻璃與P C B及 — 其他可應用於IC半導體製程或是微機電製程之耐高溫 材料其中之一材質,而該基板1 1一面係設有數微結構1 3,且各該微結構1 3係以微機電技術與半導體製程其中 之一方法,製作出光電元件、射頻元件及微機電元件其中 之一元件,又該封蓋1 2係可蓋合於該基板1 1設有數微 結構1 3之一面,且該封蓋1 2與該基板1 1對應各該微 結構1 3之間係分別具有一空間1 4,以供分別容納各該 微結構1 3,且該封蓋1 2於其異於蓋合該基板1 1之一In order to solve the above problems, it is provided that it can be further processed in a lower temperature process, and the wafer level vacuum packaging method (1) is melt-sealed. For the purpose of the present invention, the present invention includes a wafer level vacuum package, which comprises the following steps: The package structure process provides a substrate and a cover, wherein the substrate is provided with a plurality of microstructures. The bribe cover can be covered on the substrate with a plurality of microstructures, and the cover and the substrate respectively have a space between the microstructures for respectively accommodating the microstructures, and the seal Covering one surface of the substrate different from the cover and at least one of the spaces corresponding to the space, respectively, is provided to connect the spaces; the packaging process is performed at the interface between the substrate and the cover Do not have - Jin Guangzhi (4) material, and fill the metal-melting material in each of the through-holes, and apply - load on the molten metal of the cover metal, and then the two relative substrates and seals The environment in which the cover is located is vacuumed, and a heat source is continuously applied thereto to apply a heat source to simultaneously melt the molten materials of the two metals, thereby simultaneously completing the bonding of the substrate and the cover and sealing the through holes. The micro within the space Mechanism is in a vacuum state. The above and other objects and advantages of the present invention will be readily understood from Of course, the invention may be different in some of the components, or the arrangement of the components, but the selected embodiments are described in detail in the present specification, and the construction thereof is shown in the drawings. • [Embodiment] Please refer to Fig. 1 to Fig. 7, which show the structure of the embodiment selected for the present invention, which is for illustrative purposes only and is not limited by this structure in the patent application. The present embodiment provides a wafer level vacuum packaging method (1), which includes the following steps: The package structure process 1 provides a substrate 1 1 and a cover 1 2, wherein the substrate 1 1 and the cover 1 2 are One of the materials of the high temperature resistant material which can be applied to the semiconductor semiconductor process or the microelectromechanical process, and the substrate 11 has a plurality of microstructures 13 on one side, and each of the microstructures 1 3 One of the components of the photovoltaic device, the radio frequency component, and the microelectromechanical component is fabricated by one of the microelectromechanical technology and the semiconductor process, and the cover 12 can be covered on the substrate 1 1 to have a plurality of microstructures 1 3 One cover, and the cover 12 and the substrate 1 1 respectively have a space 14 between the microstructures 1 3 for respectively accommodating each of the microstructures 1 3 , and the cover 1 2 is Different from covering one of the substrates 1 1

1307128 面,在對應各該空間1 4之位置處分別開設至少一貫穿孔 1 5,俾供連通各該空間1 4。 封裝製程2,係於該基板1 1與該封蓋1 2之相接處 設有一金屬之熔融材料2 1 A,及於各該貫穿孔1 5處設 有與其相對應之至少一金屬之炼融材料2 1 B,並於該封 盖1 2之金屬之炼融材料2 1 B上施以一載重3 2,再將 此兩相對準之基板1 1與封蓋1 2所在之環境真空化,續 對其施予一熱源3 3以使該兩金屬之熔融材料2 1 A、2 1 B同時炫融,俾供同時完成該基板1 1與該封蓋1 2之 接合以及各該貫穿孔1 5之密封,俾使各該空間1 4内之 各微結構13處於一真空狀態。 請參見第2圖與第3圖,為本實施例中該封裝結構之 基板1 1與封蓋1 2之相關製程說明,於第2圖中,係選 用片(1〇 〇)單晶矽晶片作為基板11,並於該基板 ^1之頂面與底面各製作有-層二氧化⑦111 ’續於該 ,板1 1之頂面上製作一黏著層i工2,於本實施例中, 於第3圖中 係選用一片 1 0 0 )單晶石夕晶片作為 9 1 1頂面之黏著層1 1 2係—藉蒸鑛製程所製作 光ρ 1層於該黏著層112上利用微影相關製程,由 融二λ定義出該基板1 1與封蓋1 2間之金屬之熔 ^ 1 於此處之設置區域1 1 4,接著再於這些設 A,‘太音1 4上製作出相對應之金屬之熔融材料2 1 電鍍所製作t:此處之金屬之溶融材料2 1 A係-藉 1307128 封蓋1 2 ’並將該封蓋! 2置於爐 〃 於贫射芸乂熱氣化之方式’ ^封盍12之頂面與底面分別製 21,以作為_保護層,再利—層二⑽石夕1 2塗佈、曝光、顯影與去 2 兮抖#1〇 ^ 夺相關步驟,分別於 ㈣112之頂面與底面定義出於該封 面所欲蝕刻之區域,並經由、、晶蝕 2頁面,、底At 1307128, at least a uniform through hole 15 is opened at a position corresponding to each of the spaces 14 to provide communication for each of the spaces 14. The encapsulation process 2 is characterized in that a metal molten material 2 1 A is disposed at the junction of the substrate 11 and the cover 12, and at least one metal corresponding thereto is disposed at each of the through holes 15. The material 2 1 B is melted, and a load 3 2 is applied to the metal smelting material 2 1 B of the cover 12, and the environment of the two opposite substrates 1 1 and the cover 1 2 is vacuumed. And continuing to apply a heat source 3 3 to simultaneously melt the molten metal 2 1 A, 2 1 B of the two metals, and simultaneously complete the bonding of the substrate 1 1 and the cover 12 and the through holes. The sealing of 15 is such that the microstructures 13 in each of the spaces 14 are in a vacuum state. Please refer to FIG. 2 and FIG. 3 , which are related to the process description of the substrate 1 1 and the cover 12 of the package structure in the embodiment. In the second figure, the chip (1 〇〇) single crystal germanium wafer is selected. As the substrate 11, a layer of oxidized layer 7111 is formed on the top surface and the bottom surface of the substrate ^1, and an adhesive layer 2 is formed on the top surface of the substrate 11. In this embodiment, In Fig. 3, a piece of 100) single crystal stone wafer is selected as the adhesive layer of the top surface of the 191 layer. The light pu 1 layer is formed on the adhesive layer 112 by lithography. In the process, the fusion of the metal between the substrate 11 and the cover 12 is defined by the fusion λ, and the set region 1 1 4 is here, and then the phase is formed on the A, 'Taiyin 1 4 Corresponding metal molten material 2 1 Made by electroplating t: Metallic molten material here 2 1 A-borrowing 1307128 Cover 1 2 'and cover it! 2 placed in the furnace 贫 贫 贫 贫 贫 ' ' ^ ^ ^ ^ ^ ^ ^ ^ ^ 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之 之The steps associated with going to 2 兮 # 〇 , , , , , , 112 112 112 112 112 112 112 112 112 相关 相关 相关 相关 相关 112 112 相关 112 112 112 112 112 相关 相关 相关 相关 相关 相关 相关 相关 相关 相关 相关 相关

IFm_^ &丄由/祕刻(Β〇Ε)及乾㈣(R 、 ,方式去除蝕刻區域的保護層,使該封蓋 心刻的區域裸露在外,再利用非等向性濕钱 1 2頂…二Π之區域姓刻至—定深度,俾使該封蓋 穿 /夕貝穿孔15及同時在底面對應各該貫 穿孔^處形成多數凹陷之空間工4 ’再於該封蓋工2頂 面之每一貫穿孔1 5周緣處分別製作-炫接層! 2 3,於 ㈣接層! 2 3係—藉蒸鍍所製作之金屬 曰八係可於各該貝穿孔1 5上之金屬之炫融材料2 1 B 炫融後而與其密接,如第4圖所示’又各該貫穿孔! 5上 之金屬之熔融材料21B係可為-錫球、錫塊與錫片其中 之一者,於本實施例中,係以錫球作說明;且該封蓋工2 底面於各該空間1 4之外圍處係分別製作有一黏著層工 2 4,於本實施例中,各該空間i 4外圍處之黏著層工2 4係一藉蒸鍍所製作之金屬層,其可於該基板工丄與該封 蓋1 2相接處之金屬之熔融材料2 1 A熔融後而與其密 接。 請續參見第4圖,將具有多數微結構1 3之基板1 1 的一面與具有多數空間1 4之封蓋1 2的一面相對準,並 1307128 先將各該金屬之熔融材料2 1 B置於各該貫穿孔1 5 上,之後將該封裝結構置入一真空腔室3 ;[中,續於該封 蓋1 2之頂面置一載重3 2,藉以壓迫各該貫穿孔1 5處 以及該基板11與該封蓋12相接處之兩金屬之熔融材 料2 1 A、2 1 B,又因各該貫穿孔i 5上之金屬之熔融 材料2 1 B (錫球)與各貫穿孔i 5間係相對具有些許間 隙,故可供該真空腔室3丄之真空化,而待其抽真空後, 藉一設置於該真空腔室3 1内之熱源3 3,對該真空腔室 3 1施予-輻射熱3 3 !之加熱,在本實施例中,該熱源 係為-可供該封裝結構置放於其上之加熱器,使各該貫穿 孔15處及該基板11與封蓋12相接處之兩金屬之炼 融材料UA、21B同時炼融,且在該載重^之施=IFm_^ & 丄 by / secret engraved (Β〇Ε) and dry (four) (R, , remove the protective layer of the etched area, so that the area of the engraved heart is exposed, and then use the non-isotropic wet money 1 2 The top of the area is engraved to the depth of the area, so that the cover is worn/infiltrated by the perforation 15 and at the same time the space is formed on the bottom surface corresponding to each of the through holes ^4. Each of the through-holes is formed at the periphery of each of the through-holes 1 5 - a layer of splicing! 2 3, at (4) layers! 2 3 series - a metal made by vapor deposition, which can be used for the metal on each of the shells. The dazzling material 2 1 B is fused with it and is in close contact with it, as shown in Figure 4, and each of the through holes! The molten metal 21B of the metal can be one of - tin balls, tin blocks and tin sheets. In the present embodiment, the solder ball is used as a description; and the bottom surface of the cover 2 is respectively formed with an adhesive layer 2 4 at the periphery of each of the spaces 14 . In this embodiment, each of the spaces The adhesive layer of the periphery of i 4 is a metal layer made by evaporation, which can be used as a molten metal of the metal between the substrate and the cover 12 2 1 A is melted and is in close contact with it. Please continue to refer to Fig. 4, the side of the substrate 1 1 having the majority of the microstructures 1 3 is aligned with the side of the cover 1 2 having the majority of the space 14 , and 1307128 The molten metal 2 1 B of the metal is placed on each of the through holes 15 , and then the package structure is placed in a vacuum chamber 3; [wherein, a load 3 2 is placed on the top surface of the cover 12, The molten material 2 1 A, 2 1 B of the two metals at the through hole 15 and the substrate 11 and the cover 12 are pressed, and the molten material 2 of the metal on the through hole i 5 is further 1 B (the solder ball) has a slight gap with each of the through holes i 5 , so that the vacuum chamber 3 can be vacuumed, and after being evacuated, it is placed in the vacuum chamber 31 The heat source 3 3 applies a heating of the radiant heat 3 3 to the vacuum chamber 31. In the embodiment, the heat source is a heater for the package structure to be placed thereon. The two metal smelting materials UA, 21B at the through hole 15 and at the junction of the substrate 11 and the cover 12 are simultaneously smelted, and the load is applied at the load

該貫穿孔1 5之密封以及供該基板1 1與封蓋 祕接*該兩處之金屬之龍材料2〗A :η:!最佳t方式炼融填滿於各該貫穿孔 同時完成該封裝:構之:2之接合’藉此,以 裝完將經接合與封 口分Α工間1 4之四周切到, 一顆一顆之單顆封裝晶粒。 刀。J以凡成 刖文所述之金屬之熔融材 约為1 8 3度,故於封裝該封心:其炫點 溫度以進行嫁融封裝及接合,故不需要超尚溫之 外,對於該封裝結構内之徵有低溫製程之優點 从結構13,更不會發生因高溫 1307128 之製程而使其發生損壞之情況。 如附件中之照片所示,其中之金屬之熔融材料2工B (錫球)於熔融後係流入各該貫穿孔i 5内,當其流至各 邊貫穿孔1 5底部時’因各該金屬之熔融材料2工B (錫 球)本身係具有一定程度之黏滯張力,故各該金屬之熔融 材料21B(錫球)熔融後其熔融部分係可於各該貫穿孔 1 5底部產生凝聚,並於冷卻後而固化;又其於各該貫穿 '孔1 5内流動時,其可與各該貫穿孔i 5周圍處之熔接層 ► 123因高溫而產生密接,致使最後該封裝結構内之各空 間1 4可形成與外界隔絕之真空狀態。 綜上所述,可知本發明係藉金屬之熔融材料2 i B ( 錫球)進行熔融封裝,當金屬之熔融材料2 i B (錫球) -之炼融部分封閉各該貫穿孔丄5時,因金屬之溶融材料2 1 B (錫球)之黏滯性與表面張力的緣故,使其不會由貫 穿孔1 5滴落至微結構1 3上,故可避免採蒸鍍封裝時微The sealing of the through hole 15 and the metal dragon material 2 for the substrate 1 1 and the cover joint *A: η:! The best t-mode refining fills each of the through holes while completing the Package: structure: 2 joint 'by this, after the installation is completed, the joints and seals are divided into four quarters, one single package crystal. Knife. J. The molten metal of the metal described in the article is about 183 degrees, so the core is encapsulated: the bright point temperature is used for the grafting and joining, so no extra temperature is required. The advantages of the low temperature process in the package structure are from the structure 13, and the damage caused by the high temperature 1307128 process is not caused. As shown in the photo in the attached article, the molten material 2 of the metal (the solder ball) flows into each of the through holes i 5 after being melted, and when it flows to the bottom of each of the through holes 15 5 The molten material 2 of the metal (the solder ball) itself has a certain degree of viscous tension, so that the molten material 21B (the solder ball) of each of the molten metal is melted and the molten portion can be condensed at the bottom of each of the through holes 15 . And solidifying after cooling; and when flowing in each of the through holes 15 5, it can be in close contact with the welded layer ► 123 around the through holes i 5 due to high temperature, so that the package structure is finally Each of the spaces 14 forms a vacuum state that is isolated from the outside world. In summary, it is understood that the present invention is melt-wrapped by a molten metal material 2 i B (tin ball), and when the molten portion of the metal molten material 2 i B (tin ball) is closed to each of the through-holes 5 Due to the viscosity and surface tension of the molten metal material 2 1 B (tin ball), it does not drip from the through hole 15 to the microstructure 1 3, so it is possible to avoid the time of the vapor deposition package.

粒對各該微結構1 3造成之污染外,進而增加製程之良率 W 由於該封蓋1 2頂面具有多數之貫穿孔1 5,並可藉 由器具(圖中未示)將金屬之熔融材料2丄B (錫球)以 陣列之方式,一次整批鋪設於該封蓋1 2之各該貫穿孔1 5上,而於該真空腔室3 1抽真空後,藉由熱輻射3 3 1 之方式可將各該金屬之熔融材料2 1 b (錫球)熔融,俾 供一次封閉該封蓋1 2上之所有貫穿孔1 5,以完成晶圓 級之封裝,故具有製程簡單且可降低成本之優勢。 12 1307128 又,本發明並不要求極高之真空度,即可進行封裝結 構之封裝,故其於真空封裝時所用之真空儀器相對性的具 有較多之選擇性;而在製程設備上更可降低其設備成本之 支出。 且,本發明係採用金屬之熔融材料2 1 B (錫球)進 行熔融封裝,故具有較低封裝溫度之優勢,而對於設備上 之要求亦可同時降低。 當然,本發明仍存在許多例子,請參閱第5圖,其係 本發明上述文中封裝製程同時完成之第二實施例,其特點 係在於:置於各該貫穿孔處之金屬之熔融材料,係可於該 封裝結構已置入該真空腔室内後,始放置於各該貫穿孔上 ,如此可依製程上不同之要求,而進行製程順序之調控。 請參閱第6圖至第7圖本發明係具有另一實施方式 ,其係先進行該封蓋與該基板之接合製程,其後再進行該 封裝結構之封裝製程,其包括步驟如下: 封裝結構製程1 A,係提供一基板1 1A及一封蓋1 2 A,其中該基板1 1 A —面係設有數微結構1 3 A,而 該封蓋1 2 A係可蓋合於該基板1 1 A設有數微結構1 3A之一面,且該封蓋1 2 A與該基板1 1 A對應各該微 結構1 3 A之間係分別具有一空間1 4 A,以供分別容納 各該微結構13A,且該封蓋12 A於其異於蓋合該基板 1 1A之一面,在對應各該空間1 4 A之位置處分別開設 至少一貫穿孔1 5A,俾供連通各該空間1 4 A,在本實 施例中,該封裝結構之基板1 1 A與封蓋1 2 A之相關製 13 1307128 程係與第一實施例之封裝結構製程相同; 接合製程5 1 ’係於該基板1 ία與該封蓋1 2A之 相接處,設有至少一金屬之熔融材料2 2 A,並於該基板The particles cause contamination of each of the microstructures 13, thereby increasing the yield of the process. W. Because the top surface of the cover 12 has a plurality of through holes 15 and can be metal by means of an appliance (not shown). The molten material 2丄B (the solder balls) is laid in an array in each of the through holes 15 of the cover 12 in an array, and after the vacuum chamber 3 1 is evacuated, by heat radiation 3 In the manner of 3 1 , the molten material 2 1 b (tin balls) of each of the metals can be melted, and all the through holes 15 on the cover 12 can be closed once to complete the wafer level packaging, so that the process is simple. And can reduce the cost advantage. 12 1307128 Moreover, the invention does not require a very high degree of vacuum, and can be packaged in a package structure, so that the vacuum instrument used in vacuum packaging has more selectivity, and the process equipment can be more selective. Reduce the cost of equipment costs. Moreover, the present invention employs a molten metal material 2 1 B (tin ball) for melt encapsulation, so that it has the advantage of a lower package temperature, and the requirements on the device can be simultaneously reduced. Of course, there are still many examples of the present invention. Please refer to FIG. 5, which is a second embodiment of the present invention in which the packaging process is completed at the same time, and is characterized in that: the molten material of the metal placed at each of the through holes is After the package structure has been placed in the vacuum chamber, it is placed on each of the through holes, so that the process sequence can be adjusted according to different requirements of the process. Please refer to FIG. 6 to FIG. 7 . The present invention has another embodiment, which first performs a bonding process between the cap and the substrate, and then performs a packaging process of the package structure, including the following steps: The process 1 A provides a substrate 1 1A and a cover 1 2 A, wherein the substrate 1 1 A is provided with a plurality of microstructures 1 3 A, and the cover 1 2 A can be attached to the substrate 1 1 A is provided with one surface of the micro-structure 1 3A, and the cover 1 2 A corresponds to the substrate 1 1 A, and each of the microstructures 1 3 A has a space of 1 4 A for respectively accommodating each of the micro-structures The structure 13A, and the cover 12A is different from the one surface of the substrate 1 1A, and at least a uniform perforation 15A is respectively opened at a position corresponding to each of the spaces 1 4 A, and the space is connected to each of the spaces 1 4 A In this embodiment, the substrate 1 1 A of the package structure and the cover 1 2 A are related to the package structure of the first embodiment; the bonding process 5 1 ' is attached to the substrate 1 ία At the junction with the cover 12A, at least one metal molten material 2 2 A is disposed on the substrate

1 1A與該封蓋1 2A相對準後,對其施予一載重3 2A 及一熱源3 3 A,以使該基板1 1 a與該封蓋1 2A相接 處金屬之熔融材料2 2 A熔融,俾供該基板i i與該封蓋 1 2之接合; 封裝製程5 2,係於各該貫穿孔1 5 A處分別填入一 金屬之熔融材料2 2 B,並將此已接合好之基板i i A與 封蓋1 2A其所在之環境真空化,續對其施予一載重3 2 A及一熱源3 3 A,在本實施例中,係將該封裝結構置入 一真空腔室3 1A中,續於該封蓋1 2A之頂面置一載重 3 2A,藉以壓迫各該貫穿孔1 5A處金屬之熔融材料2 2B,又因各該貫穿孔1 5 a上之金屬之熔融材料2 2 B (錫球)與各貫穿孔1 5間係相對具有些許間隙,故可供 該真空腔室3 1A之真空化,而待其抽真空後,藉由設置 於該真空腔室3 1A内之熱源3 3A,對該真空腔室3 1 施予一輻射熱之加熱,使各該貫穿孔i 5 A處金屬之熔融 材料2 2 B熔融,且在該载重3 2A之施壓下,可供各該 貝穿孔1 5A之雄、封,猎此完成該晶圓級真空封裳,以使 各該空間1 4 A内之各微結構1 3 A處於一真空狀態。在 本實施例中之熱源係位於該真空腔室内,利用幅射熱使貫 穿孔内之熔融材料熔融,當然可利用真空腔室外部之熱 源’例如以外部之雷射聚焦照射在熔融材料上,使其溶融 14 1307128 而密封住該貫穿孔,同樣達到使熔融材料熔融之功效。 本實施例中更包括有一切割製程4 A,係將經接合與 封裝完畢之封裝結構,沿各該空間1 4 A之四周切割,以 完成一顆一顆之單顆封裝晶粒。 上述本發明之另一實施之方式,係在闡明本發明製程 上之多樣性,故可依不同製程之需求而進行調整。 以上所述實施例之揭示係用以說明本發明,並非用以 ' 限制本發明,故舉凡數值之變更或等效元件之置換仍應隸 _ 屬本發明之範_。 由以上詳細說明,可使熟知本項技藝者明瞭本發明的 確可達成前述目的,實已符合專利法之規定,爰提出專利 申請。 附件:熔融材料(錫球)熔融狀態之封蓋正面及背面 照片 【圖式簡單說明】 第1圖係本發明真空封裝方法之流程圖 • 第2圖係本發明之基板製程示意圖 第3圖係本發明之封蓋製程示意圖 第4圖係本發明封裝時之示意圖 第5圖係本發明封裝時另一實施例之示意圖 第6圖係本發明真空封裝方法另一實施方式之流程 圖 第7圖係本發明之接合與封裝製程之示意圖 第8圖係習用之封裝結構之示意圖 15 1307128 第9圖係另一習用封裝結構之示意圖 【主要元件符號說明】 (習用部分) 基座6 封蓋6 2 空間6 3 微結構7 1 孔洞7 2 1 封裝層7 4 (本發明部分) 封裝結構製程1、1 A 二氧化矽1 1 1 光阻1 1 3 封蓋1 2、1 2 A 光阻1 2 2 黏著層1 2 4 空間1 4、1 4 A 金屬之熔融材料2 1 A 金屬之熔融材料2 2 A 真空腔室3 1、3 1 A 熱源3 3、3 3 A 切割製程4、4 A 封裝製程5 2 微結構6 1 缺口 6 2 1 晶圓片7 封蓋7 2 空間7 31 1A is aligned with the cover 1 2A, and a load 3 2A and a heat source 3 3 A are applied thereto to make the molten material 2 2 A of the metal where the substrate 11 a meets the cover 1 2A. Melting, the substrate ii is bonded to the cover 12; the encapsulation process 5 2 is filled with a metal molten material 2 2 B at each of the through holes 15 5 A, and the bonded material is bonded The substrate ii A and the cover 1 2A are vacuumed, and a load 3 2 A and a heat source 3 3 A are continuously applied thereto. In this embodiment, the package structure is placed in a vacuum chamber 3 In 1A, a load 3 2A is placed on the top surface of the cover 1 2A to press the molten material 2 2B of the metal at the through hole 15 5A, and the molten material of the metal on each of the through holes 15 5 a 2 2 B (the solder ball) has a slight gap with each of the through holes 15 , so that the vacuum chamber 3 1A can be vacuumed, and after being evacuated, it is disposed in the vacuum chamber 3 1A. The heat source 3 3A is heated by applying a radiant heat to the vacuum chamber 3 1 to melt the molten metal 2 2 B of the metal at the through hole i 5 A, and under the pressure of the load 3 2A Each of the shells can be pierced with a 1 5A male, sealed, and finished to complete the wafer level vacuum sealing so that the microstructures 1 3 A in each of the spaces 1 4 A are in a vacuum state. The heat source in the embodiment is located in the vacuum chamber, and the molten material in the through hole is melted by the radiation heat. Of course, the heat source outside the vacuum chamber can be used to focus on the molten material, for example, by external laser focusing. It is melted 14 1307128 to seal the through-hole, and the effect of melting the molten material is also achieved. In this embodiment, a dicing process 4 A is further included, in which the packaged structure after bonding and encapsulation is cut along each of the spaces 1 4 A to complete a single package die. The other embodiment of the present invention described above clarifies the diversity of the process of the present invention, and can be adjusted according to the requirements of different processes. The above description of the embodiments is intended to be illustrative of the invention, and is not intended to limit the invention. From the above detailed description, it will be apparent to those skilled in the art that the present invention can achieve the above-mentioned objects, and is in accordance with the provisions of the Patent Law. Attachment: Photograph of the front and back of the cover of molten material (tin ball) in molten state [Simplified illustration of the drawing] Fig. 1 is a flow chart of the vacuum packaging method of the present invention. Fig. 2 is a schematic view of the substrate manufacturing process of the present invention. 4 is a schematic view of a package of the present invention, FIG. 5 is a schematic view of another embodiment of the present invention, and FIG. 6 is a flow chart of another embodiment of the vacuum packaging method of the present invention. FIG. FIG. 8 is a schematic view of a conventional package structure. FIG. 9 is a schematic view of another conventional package structure. [Main component symbol description] (conventional part) Base 6 cover 6 2 Space 6 3 Microstructure 7 1 Hole 7 2 1 Encapsulation layer 7 4 (part of the invention) Package structure process 1, 1 A cerium oxide 1 1 1 photoresist 1 1 3 cover 1 2, 1 2 A photoresist 1 2 2 Adhesive layer 1 2 4 Space 1 4, 1 4 A Metal melt material 2 1 A Metal melt material 2 2 A Vacuum chamber 3 1 , 3 1 A Heat source 3 3, 3 3 A Cutting process 4, 4 A package Process 5 2 Microstructure 6 1 Notch 6 2 1 Wafer 7 Cover 7 2 Space 7 3

基板1 1、1 1 A 黏著層112 設置區域1 1 4 二氧化矽121 熔接層1 2 3 微結構1 3、1 3 A 貫穿孔15、15A 金屬之熔融材料2 1 B 金屬之熔融材料2 2 B 載重3 2、3 2 A 熱輻射3 3 1 接合製程5 1 16Substrate 1 1 , 1 1 A Adhesion layer 112 Setting area 1 1 4 Ceria 121 Fusing layer 1 2 3 Micro structure 1 3, 1 3 A Through hole 15, 15A Metal molten material 2 1 B Metal molten material 2 2 B Load 3 2, 3 2 A Thermal radiation 3 3 1 Bonding process 5 1 16

Claims (1)

1307128 十 1 ,申請專利範圍: 種曰θ圓級真空封裝方法㈠,包括下列步驟: 封I结構製程,係提供—基板及—封蓋,其中該 土=一面係設有數微結構,而該封蓋係可蓋合於該^ 數微結構之一面,且該封蓋與該基板對應各該 :士: ’之間係分別具有一空間’以供分別容納各該微 二兮㈣盍於其異於蓋合該基板之—面’在對應 各°“間之位置處分別開設至少-貫穿孔,俾供連通 各該空間; 通 ^封裝製程,係於該基板與該封蓋之相接處,分別 δ又有一金屬之熔融材料,及於各該貫穿孔處分別填入 一金屬之熔融材料’並於該封蓋之金屬之熔融材料上 ^以一載重’再將此兩相對準之基板與封蓋所在之環 =真二化,續對其施予一熱源以使各該金屬之熔融材 料同時溶融’俾供同時完成該基板與該封蓋之接合以 及各該貫穿狀密封,俾使各該空間内之各微結構處 於一真空狀態。 依申请專利範圍第1項所ϋ之晶圓、級真空封裝方法 (在封裝結構製程中,係提供一晶圓形狀之基板 與封蓋’其中該基板與封蓋係選用矽、玻璃與P c B 及,他可應用於!C半導體製程或是微機電製程之 耐同溫材料其中之—材質’且該微結構係以微機電技 術與半導體f程其中之—製作出光電元件、射頻元件 及微機電元件其中之一。 17 1307128 晶梦晶片作為知·雲 # 早 作出-層二氧切,’以=封蓋之頂面與底面分別製 *程定義該_面=:;=’再利用微影 】=「其'之1方式去除_區域的: 方式==絲挪,制㈣料__的 万式將Ιά刻區域_至 π :f多數貫穿孔及同時在底面對應各皁 :=ΐί!間’再於該封蓋頂面之各貫穿孔周緣 炫二㈣乍一炫接層,其係可與各貫穿孔處之金屬之 融密接,且於該封蓋底面之各空間外圍處 :厶厘4黏著層’其係可與該基板與該封蓋相接處 之金屬之熔融材料熔融密接; 而制S石夕晶片作為基板,並於該基板之頂面與底 二:有一層二氧化發’續於該基板之頂面上製作一 並於該黏著層上利用微影製程定義出該基板 〇、間之金屬之熔融材料的設置區域; 將具有多數微結構之基板的—面與具有多數空 ^之封蓋的-面於對準後置入一真空腔室中,並於抽 真空後’藉一加熱器對該真空腔室施予-輻射熱之熱 源’使各該貫穿孔處及該基板與封蓋相接處之兩金屬 =溶融材料同時熔融’俾供密封各該貫穿孔以及供該 土板與封蓋之密接’以同時完成該封裝結構之接合與 1307128 封裝。 41307128 X1, the scope of application for patent: 曰 θ circular vacuum packaging method (1), including the following steps: Sealing I structural process, providing a substrate and a cover, wherein the soil = one side is provided with a number of micro-structures, and the seal The cover system can be covered on one side of the plurality of micro-structures, and the cover corresponds to the substrate: each of: "there is a space between the two sides" for respectively accommodating each of the micro-two (four) Opening at least a through hole at a position between the corresponding surfaces of the substrate to be connected to each of the spaces; the encapsulation process is at a junction of the substrate and the cover, Each of the δ has a molten metal material, and each of the through holes is filled with a molten metal of metal and is applied to the molten metal of the metal of the cover to carry a load between the two substrates. The ring in which the cover is located = true, and a heat source is continuously applied thereto so that the molten materials of the metal are simultaneously melted, and the joint between the substrate and the cover and the through seals are simultaneously completed, so that each Microstructures within the space In a vacuum state, the wafer and grade vacuum packaging method according to item 1 of the patent application scope (in the package structure process, a wafer-shaped substrate and a cover are provided), wherein the substrate and the cover are selected , glass and P c B and, can be applied to the C semiconductor process or the micro-electromechanical process of the same temperature-resistant material - the material 'and the micro-system is made of micro-electromechanical technology and semiconductor f-making One of the components, RF components and micro-electromechanical components. 17 1307128 Crystal Dream Wafer as Zhiyun # Early-layer dioxotomy, '=================================================================== ;='Reuse lithography】="It's 1 way to remove _ area: mode == silk, system (four) material __ 10,000 type will engrave area _ to π: f most through holes and at the same time on the bottom Corresponding to each soap: = ΐί! between the two sides of each of the through-holes on the top surface of the cover, two (four) 炫 a splicing layer, which can be closely connected with the metal at each through hole At the periphery of each space: 厶 4 adhesive layer 'which can be attached to the substrate and the cover The molten metal of the joint is melted and adhered; and the S-stone wafer is used as the substrate, and the top surface and the bottom of the substrate are: a layer of oxidized hair is formed on the top surface of the substrate and bonded thereto. The lithography process is used to define a region of the molten material of the substrate and the metal between the substrates; the surface of the substrate having the majority of the microstructure is aligned with the surface having the majority of the cover; In the vacuum chamber, after vacuuming, the heat source of the radiant heat is applied to the vacuum chamber by a heater, so that the two metal=melting materials at the through-hole and the junction between the substrate and the cover are simultaneously melted. '俾 for sealing each of the through holes and for the intimate connection of the earth plate to the cover' to complete the bonding of the package structure and the 1307128 package. 4 77 •依申請專利制第3項所述之晶圓級真 )’其中各貫穿孔周緣處之熔接層係一二去( 作之金屬層;各空間外圍處之黏著層係43:斤製 作之金屬層;板頂面之黏著層係_藉#= 斤製 之金屬層。 稽為鍍所製作 •依申請專利範_ 3項所述之晶@級真空封 其中該加熱器係設於該真空裝置内 ^ 結構係置於該加熱器之鄰處。 ~十裴 依申請專·圍第3項所述之晶圓級真”裝 )’其中置於各該貫穿孔處之金屬线融材 於該封裴結構置入該真空腔室前已置於其上。’、 依申請專利範圍第3項所狀晶圓級真空封裝方法 '其中置於各該貫穿孔處之金屬之熔融材料,係 於该封装結構置入該真空腔室後始置於其上。 ” 依申請專利範圍第1項所述之晶圓級真空封裝方法( 一),其中各該貫穿孔處之金屬之熔融材料係一錫球 、錫片與錫塊其中之一者; ' 該基板與封蓋相接處之金屬之熔融材料係一 電鍍所製作之錫。 依申請專利範圍第1項所述之晶圓級真空封裝方法( 一),其更包括有一切割製程,係將經接合與封裝完 之封裝結構’沿各該空間四周切割,以完成—顆一顆 之單顆封裝晶粒。 1307128 1 0 · —種晶圓級真空封裝方法(一),包括下列步驟: 封裝結構製程,係提供一基板及一封蓋,其中該 基板一面係設有數微結構,而該封蓋係可蓋合於該基 板設有數微結構之一面,且該封蓋與該基板對應各該 微結構之間係分別具有一空間,以供分別容納各該微 結構,且該封蓋於其異於蓋合該基板之一面,在對應 各該空間之位置處分別開設至少一貫穿孔,俾供連通 各該空間;• According to the patent level of the patent application, the wafer level is true.] The fusion layer at the periphery of each through hole is one or two (the metal layer; the adhesive layer at the periphery of each space 43: the metal made by the pound) Layer; adhesive layer on the top surface of the board _ borrowing #= metal layer made of jin. Manufactured for plating; according to the application of patent _ 3, the crystal @ grade vacuum seal, wherein the heater is installed in the vacuum device The internal structure is placed adjacent to the heater. ~ The application of the wafer-level true package described in Item 3 of the application The sealing structure has been placed thereon before being placed in the vacuum chamber. ', the wafer-level vacuum packaging method according to the third application of the patent application', wherein the molten material of the metal placed in each of the through holes is tied to The package structure is placed on the vacuum chamber and is placed thereon. The wafer level vacuum packaging method (1) according to claim 1, wherein the molten material of the metal at the through hole is One of tin balls, tin sheets and tin blocks; 'the melting of the metal at the junction of the substrate and the cover The material system produced a tin plating. According to the wafer-level vacuum packaging method (1) of claim 1, further comprising a cutting process for cutting and encapsulating the packaged structure along each of the spaces to complete the A single package of die. 1307128 1 0 · A wafer level vacuum packaging method (1), comprising the following steps: a package structure process, providing a substrate and a cover, wherein the substrate is provided with a micro structure on one side, and the cover can be covered The substrate is provided with one surface of the micro-structure, and the cover and the substrate respectively have a space between the microstructures for respectively accommodating the microstructures, and the cover is different from the cover One surface of the substrate is respectively provided with at least a uniform perforation at a position corresponding to each of the spaces, and is connected to each of the spaces; 接合製程,係於該基板與該封蓋之相接處,設有 一金屬之熔融材料,並於該基板與該封蓋相對準後, 對其施予一熱源及一載重,以使該基板與該封蓋相接 處之金屬之熔融材料熔融,俾供該基板與該封蓋之接 合; 封裝製程,係於各該貫穿孔處分別設有一金屬之 熔融材料,並將此已接合好之基板與封蓋其所在之環 境真空化,續對其施予一熱源及一載重,以使各該貫 穿孔處之金屬之熔融材料熔融,俾供各該貫穿孔之密 封,藉此完成該晶圓級真空封裝,以使各該空間内之 各微結構處於一真空狀態。 1 1 ·依申請專利範圍第1 0項所述之晶圓級真空封裝方 法(一),在封裝結構製程中,係提供一晶圓形狀之基 板與封蓋,其中該基板與封蓋係選用矽、玻璃與P C B其中之一材質,且該微結構係以微機電技術與半導 體製程其中之一製作出光電元件、射頻元件及微機電 20 1307128 A 元件其中之一。 12·依申請專利範圍第10項所述之晶圓級真空封裝方 法(一),其中各該貫穿孔處之金屬之熔融材料係一錫 球與錫塊其中之一者;該基板與封蓋相接處之金屬之 熔融材料係一藉電鍍所製作之錫。 13·依申請專利範圍第10項所述之晶圓級真空封裝方 • 法(一),其更包括有一切割製程,係將經接合與封裝 完之封裝結構,沿各該空間四周切割,以完成一顆一 I 顆之單顆封裝晶粒。 21The bonding process is disposed at a junction of the substrate and the cover, and is provided with a molten metal material, and after the substrate is aligned with the cover, a heat source and a load are applied thereto to make the substrate and the substrate The molten material of the metal at the junction of the cover is melted to be bonded to the cover; the packaging process is respectively provided with a molten metal of metal at each of the through holes, and the bonded substrate is assembled Vacuuming the environment in which the cap is placed, continuously applying a heat source and a load to melt the molten metal of each of the through holes, and sealing the through holes, thereby completing the wafer The stage is vacuum encapsulated so that the microstructures in each of the spaces are in a vacuum state. 1 1 · According to the wafer level vacuum packaging method (1) described in claim 10, in the package structure process, a wafer-shaped substrate and a cover are provided, wherein the substrate and the cover are selected. One of the materials of germanium, glass and PCB, and the microstructure is one of the components of the photovoltaic device, the radio frequency component and the micro-electromechanical 20 1307128 A by one of the microelectromechanical technology and the semiconductor process. The wafer-level vacuum packaging method (1) according to claim 10, wherein the molten material of the metal at the through-hole is one of a solder ball and a tin block; the substrate and the cover The molten material of the metal at the junction is a tin made by electroplating. 13. The wafer level vacuum package method according to claim 10, wherein the method further comprises a cutting process for cutting and encapsulating the package structure along each of the spaces. Complete a single package of one-chip crystal. twenty one
TW095117554A 2006-05-17 2006-05-17 Wafer-level vacuum packaging method TW200744137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW095117554A TW200744137A (en) 2006-05-17 2006-05-17 Wafer-level vacuum packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095117554A TW200744137A (en) 2006-05-17 2006-05-17 Wafer-level vacuum packaging method

Publications (2)

Publication Number Publication Date
TW200744137A TW200744137A (en) 2007-12-01
TWI307128B true TWI307128B (en) 2009-03-01

Family

ID=45071545

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095117554A TW200744137A (en) 2006-05-17 2006-05-17 Wafer-level vacuum packaging method

Country Status (1)

Country Link
TW (1) TW200744137A (en)

Also Published As

Publication number Publication date
TW200744137A (en) 2007-12-01

Similar Documents

Publication Publication Date Title
JP4480939B2 (en) Method for structuring a flat substrate made of a glass-based material
US7981765B2 (en) Substrate bonding with bonding material having rare earth metal
JP2006525133A (en) Vacuum package manufacturing of integrated circuit elements
RU2536076C2 (en) Method of connection, sealed structure made thereby and system of sealed structures
JP2010525558A (en) Electrical interconnect structure and method of forming the same
EP1272422A2 (en) Vacuum package fabrication of microelectromechanical system devices with integrated circuit components
TW201542309A (en) Process for the eutectic bonding of two carrier devices
CN101542702A (en) Bonding method of three dimensional wafer lamination based on silicon through holes
CN101261932A (en) A bonding method for low-temperature round slice
EP1633480B1 (en) Method of bonding microstructured substrates
TWI307128B (en)
KR101637288B1 (en) Method for junction of silver paste
US9718674B2 (en) Thin capping for MEMS devices
JP2012028750A (en) Method for thickness-calibrated bonding between at least two substrates
JP6022065B2 (en) Substrate assembly, method and apparatus for bonding substrates
JP6128566B2 (en) Method of joining material layers together and resulting device
CN104662649B (en) Direct Bonding technique
WO2010031987A2 (en) Encapsulation method
JP4964505B2 (en) Semiconductor device, manufacturing method thereof, and electronic component
JP2005158717A (en) Fluid-based switch and method for manufacturing and sealing fluid-based switch
JP2005158717A5 (en)
US20100308475A1 (en) Composite of at least two semiconductor substrates and a production method
TW200830515A (en) Method for sealing vias in a substrate
KR100944530B1 (en) Wafer Bumping Template Manufactured by Glass Forming and Manufacturing Method Thereof
JP2004318136A5 (en)

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees