TWI306659B - Multi-package module - Google Patents

Multi-package module Download PDF

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TWI306659B
TWI306659B TW95130533A TW95130533A TWI306659B TW I306659 B TWI306659 B TW I306659B TW 95130533 A TW95130533 A TW 95130533A TW 95130533 A TW95130533 A TW 95130533A TW I306659 B TWI306659 B TW I306659B
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package
module
substrate
package module
disposed
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TW95130533A
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TW200812055A (en
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Rong Tai Liu
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Description

1306659 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種多重封裝模組(multi_package m〇dule，MPM)，特別是關於—種包含有複數個封裝體組成 立體多邊形(polygonal prism shaped)結構，並包含有散埶 置設於封裝體上的多重封裝模組。 【先前技術】 由於電子產品之未來演變趨勢為微小化與多功能性，因 此將各種原本獨立之電子科，例如微處理晶片、記憶體 晶片、邏輯晶片、光學晶片以及無線通訊積體電路晶片等 整合於-單-構件的趨勢也日勒要，是以目前各項半導 體裝置皆朝向系統單晶片（system Gn ehip，s〇c)與系統封裝 (system ln package，SIP)兩大類別發展。其中系统單曰片 (S〇C)必須整合各種不同半導體製程於同1时，研^之 時間冗長且費用高昂，而且不同性能之元件均有1適 寺性及製程參數需考量’若不能有效整合並簡併：半 ¥體製造過程中，此方式减會降低製程的 製程的複雜度與困難度。因此，將多吉’均口 于夕種晶片直接整合於單 一封裝模組内便為現今較為可行之方案，例如包含有 曰曰片之多重封裝模組。 請參考第1圖，第1圖為一 習知多重封裝模組 1〇之結 5 1306659 構示意圖。如第1圖所示，習知多重封裝模組10包含有一 . 第—封裝體20與一第二封裝體30,且第一封裝體2〇與第 ， 二封裝體30係以立體堆疊型式(stack-type)封裝。其中，第 一封裝體結構20包含有一第一基板22、—第一晶片24與 第一銲球26，且第一晶片24設於第一基板22之上表面並 電性連接至第一基板22。而第二封裝體30係設於第一封 裝體20之下方，其包含有一第二基板32、一第二晶片34 _ 與第二銲球36，且第二晶片34設於第二基板32之下表面 並電性連接至第二基板32。另外’第一銲球26係設置於 第一基板22與第二基板32之間’電性連接第一基板22與 第一基板32’而第二鲜球36設置於第二基板32之下表面， 如此’第一晶片24與第二晶片34便可透過第一基板22、 第一銲球26、第二基板32與第二銲球36而電性連接至印 刷電路板(printed circuit board, PCB)。 • 由於在目前之封裝構造中，晶片所產生的熱量大多是 經由基板向外逸散，然而封裝構造之基板往往卻是利用雙 馬來醯亞胺·三氮雜笨(Bisnlaleimide Triazine，BT)樹脂等低 熱傳導係數之材質所構成，因而大幅阻礙了封裴體之傳熱 效果。尤其是前述之多重封裝模組晶片，在操作時其所產 生的熱需通過多個含低導熱材質BT樹脂的基板層層下 -傳，才能經由基板之下表面上的銲球傳導至印刷電路板 • 上，因此嚴重影響導致習知多重封裝模組之整體散熱效 6 1306659 能，進而減低晶片的運作效能與使用壽命。 【發明内容】 據此，本發明之主要目的在於提供一種多重封裝模 組，以解決習知技術技術無法克服之難題，進而提升多重 封裝模組之散熱效能。 根據本發明之申請專利範圍，係提供一種多重封裝模 組，包含有一第一封裝體、複數個第二封裝體、複數個電 性連接端分別設置於第一與第二封裝體之接合處、複數個 銲球設於第一封裝體之外侧，以及複數個散熱裝置設置於 第一與第二封裝體之上，其中，第二封裝體與第一封裝體 構成立體多邊形結構，使多重封裝模組具有良好散熱性。 由於本發明之多重封裝模組係利用第二封裝體與第一 封裝體構成立體多邊形結構，因此可以把散熱裝置直接設 置於第一與第二封裝體之上，大幅提升多重封裝模組之散 熱效能’並有效避免晶片過熱專問題。 為了使貴審查委員能更近一步了解本發明之特徵及 技術内容，請參閱以下有關本發明之詳細說明與附圖。然 而所附圖式僅供參考與輔助說明用，並非用來對本發明加 以限制者。 1306659 【實施方式】 清參考第2圖’第2圖為本發明之第一較佳實施例多 重封裝模組40之結構示意圖。如第2圖所示，多重封裝模 組4〇包含有一第一封裝體42、一第二封裝體44、一第二 封裝體46、二個電性連接端48、複數個録球52以及二個 散熱裝置54。第二封裝體44之一側邊、第二封裝體46之 一侧邊分別與第一封裝體42之二侧邊相鄰，且第二封裝體 44之另一側邊與第二封裝體46之另一側邊相鄰，使第— 封裝體42與二第二封裂體44、46構成一三角柱結構之側 壁，並使第一封裝體42與二第二封裝體44、46定義出内 侧及外側。 於此第一較佳實施例中，第一封裝體42包含一第一基 板421、至少一第一晶片422設置於第一基板421之内表 面’以及封膠體423包覆第一晶片422。第二封裝體44包 含一第二基板441、至少一第二晶片442設置於第二基板 441之外側’以及封膠體443包覆第二晶片442。而第二封 褒體46則包含一第二基板461、至少一第二晶片462設置 於第二基板461之外表面，以及封膠體463包覆第二晶片 462 °其中’各晶片422、442、462可利用圖中所示之打線 接合方式電連接至對應之各基板421、441、461，亦可利 用覆晶接合之方式電連接至對應之各基板42卜441、461。 8 1306659 —個電性連接端48分別設置於第一封裝體42鱼第-、0之接合處以及第二封裝體44與第二封裝體46之 接合處’且各電性連接端48可以是可撓性線路板、卷帶自 動&合柔性排線、塑膠排線等導電元件，以電連接第一封 裝體42與一第二封裝體44、46，而第一封裝體42與第二 封裝體44之接合處則可利用黏著劑(glue)56或卡榫加以固 定。複數個銲球52設於第一封裝體42之外側，透過銲球 52使多重封裝模組40中之晶片422、442、462電性連接 至印刷電路板(未顯示）。尤其注意的是，本發明之多重封 裝模組40可包含有複數個散熱裝置54設置於第二封裝體 44、46之内、外侧，且散熱裝置54可為散熱片或散熱風 扇等裝置’例如第2圖中所示之散熱裝置54即為散熱風 扇’且二散熱風扇分別設置於第二封裝體44、46之内侧。 由於多重封裝模組40以三個封裝體42、44、46組成 立體之二角柱結構，並於三角柱結構中裝設散熱裝置54， 故可有效提升多重封裝模組40之散熱效果，因此即使第一 基板421與第二基板441、461仍使用BT樹脂等低熱傳導 係數材質所構成之BT基板，也不會阻礙熱傳效果。尤其 當散熱裝置54為散熱風扇時，風扇運作所產生之強制對 流’更能大幅增加熱量向外散失之速率，避免多重封裝模 組40因過熱而影響效能。 9 1306659 /本發明之多重封裝模組係以多個封裝體組成立體多邊 幵"。構例如二角挺、四面體或立方體，並利用至少一散 ,、、、裝置π於上述封裝體的表面，以形成—散熱效果良好之 多重封裝餘，值不侷限於此。請參考第3®，第3圖為 本發明之第二較佳實施例多重封裝模組6G之結構示意 圖。如第3圖所示，多重封裝模組6〇包含有一第一封裝體 42、:第二封裝體64、一第二封裝體66、至少一散熱模組 62、複數個電性連接端48、複數個銲球52設於第一封裝 體42之外側，以及複數個散熱裝置54。第二封裝體64之 侧邊、第二封裝體66之侧邊分別與第一封裝體42之二侧 邊相鄰，使第一封裝體42與二第二封裝體構64、66成一 二角柱結構之侧壁，而散熱模組62則構成三角柱結構之底 部。 於此第二較佳實施例中，第一封裝體42包含一第一基 板421、至少一第一晶片422設置於第一基板421之内表 面’以及封膝體423包覆第一晶片422。第二封裝體64包 含一第二基板641、至少一第二晶片642設置於第二基板 641之内表面，以及封膠體643包覆第二晶片642。第二封 裝體66包含一第二基板661、至少一第二晶片662設置於 第二基板661之内表面’以及封勝體663包覆第二晶片 662。其中’各晶片422、642、662可利用打線接合方式活 1306659 或覆晶接合方式電連接至對應之各基板421、641、661， 使得各晶片422、642、662可透過銲球52與印刷電路板等 外部裝置進行電連接。 同樣地’本發明第-封裝體42、二$二封震體64、66 與散熱模組62之接合處可視需要㈣μ連接心8或黏 著劑56接合。如第3圖所示，第—封教體42盥第二封裝 體66之接合處以及第二封裝體64與第二封袭體的之接合 處分別利用-電性連接端48結合並且電連接，電性連接端 48可以是可撓性線路板、卷帶自動料紐树、塑膠排 線、異方性導電料導電元件。第—外體42與第二封裝 體64之接合處以及散熱模組62與第1裝體c、二第二 封裝體64、66之接合處則可利用轉剛％或其他方式固 定。尤其注意的是，多重封裝模组60包含有二散赦裝置 μ 封裝體64' 66 κ則，例如第3圖中 所示之散熱裝置54為散熱風扇，且散熱模⑽通常可包 含有散W #裝置’用以w多 之散熱效能。 很像个乐 — · ^却於多重封裝模 包含有散熱裝置54裝設於第二封裝體 祖04、66之外侧 此可增加第二基板641、661之散熱速率 i千。此外，由於 明之多重封裝模組60另包含有散熱模叙62，1306659 IX. Description of the Invention: [Technical Field] The present invention relates to a multi-package module (MPM), and more particularly to a multi-package matrix comprising a plurality of packages to form a polygonal prism shaped The structure includes a plurality of package modules disposed on the package. [Prior Art] Since the future evolution trend of electronic products is miniaturization and versatility, various original electronic departments such as micro processing chips, memory chips, logic chips, optical chips, and wireless communication integrated circuit chips are used. The trend of integration into the single-component is also to be developed. Currently, various semiconductor devices are developed in two major categories: system Gn ehip (s) and system ln package (SIP). Among them, the system single-chip (S〇C) must integrate various semiconductor processes at the same time, the time of research is long and costly, and the components of different performances have a suitable temple and process parameters to be considered. Integration and degeneracy: In the half-body manufacturing process, this method reduces the complexity and difficulty of the process. Therefore, it is now more feasible to integrate Dorje's even-in-one wafers into a single package, such as multiple package modules containing enamel. Please refer to FIG. 1 , which is a schematic diagram of a conventional multi-package module 1 5 5 1306659. As shown in FIG. 1 , the conventional multi-package module 10 includes a first package body 20 and a second package body 30 , and the first package body 2 and the second package body 30 are in a three-dimensional stacked type ( Stack-type) package. The first package structure 20 includes a first substrate 22, a first wafer 24 and a first solder ball 26, and the first wafer 24 is disposed on the upper surface of the first substrate 22 and electrically connected to the first substrate 22 . The second package 30 is disposed under the first package 20 and includes a second substrate 32, a second wafer 34_ and a second solder ball 36, and the second wafer 34 is disposed on the second substrate 32. The lower surface is electrically connected to the second substrate 32. In addition, the first solder ball 26 is disposed between the first substrate 22 and the second substrate 32 to electrically connect the first substrate 22 and the first substrate 32 ′ and the second fresh ball 36 is disposed on the lower surface of the second substrate 32 . Thus, the first wafer 24 and the second wafer 34 can be electrically connected to the printed circuit board (PCB) through the first substrate 22, the first solder ball 26, the second substrate 32, and the second solder ball 36. ). • Since the heat generated by the wafer is mostly dissipated outward through the substrate in the current package construction, the substrate of the package structure is often made of Bisnlaleimide Triazine (BT) resin. It is composed of a material with a low thermal conductivity, which greatly hinders the heat transfer effect of the sealing body. In particular, in the foregoing multi-package module wafer, the heat generated during operation is required to pass through a plurality of substrate layers containing a low thermal conductivity material BT resin, so as to be conducted to the printed circuit via solder balls on the lower surface of the substrate. On the board, it has a serious impact on the overall heat dissipation efficiency of the conventional multi-package module, which can reduce the operating efficiency and service life of the chip. SUMMARY OF THE INVENTION Accordingly, the main object of the present invention is to provide a multi-package module to solve the problem that cannot be overcome by the prior art, thereby improving the heat dissipation performance of the multi-package module. According to the patent application of the present invention, a multi-package module includes a first package, a plurality of second packages, and a plurality of electrical connection ends respectively disposed at a junction of the first and second packages. The plurality of solder balls are disposed on the outer side of the first package body, and the plurality of heat dissipating devices are disposed on the first and second package bodies, wherein the second package body and the first package body form a three-dimensional polygonal structure, so that the multiple package modes The group has good heat dissipation. Since the multiple package module of the present invention utilizes the second package body and the first package body to form a three-dimensional polygonal structure, the heat dissipation device can be directly disposed on the first and second package bodies, thereby greatly improving the heat dissipation of the multiple package modules. Performance' and effectively avoid the problem of wafer overheating. In order to provide a more detailed understanding of the features and technical aspects of the present invention, the following detailed description of the invention and the accompanying drawings. The drawings are for illustrative purposes only and are not intended to limit the invention. 1306659 [Embodiment] Referring to FIG. 2, FIG. 2 is a schematic structural view of a multi-package module 40 according to a first preferred embodiment of the present invention. As shown in FIG. 2 , the multi-package module 4 includes a first package body 42 , a second package body 44 , a second package body 46 , two electrical connection ends 48 , a plurality of recording balls 52 , and two Heat sink 54. One side of the second package body 44 and one side of the second package body 46 are respectively adjacent to the two sides of the first package body 42 , and the other side of the second package body 44 and the second package body 46 . The other side is adjacent to the first package 42 and the second package 44, 46 to define the inner side of the first package 42 and the second package 44, 46. And the outside. In the first preferred embodiment, the first package body 42 includes a first substrate 421, at least one first wafer 422 is disposed on the inner surface of the first substrate 421, and the encapsulant 423 covers the first wafer 422. The second package body 44 includes a second substrate 441, at least one second wafer 442 is disposed on the outer side of the second substrate 441, and the encapsulant 443 covers the second wafer 442. The second body 46 includes a second substrate 461, at least one second wafer 462 is disposed on the outer surface of the second substrate 461, and the sealing body 463 covers the second wafer 462 ° of the respective wafers 422, 442, 462 can be electrically connected to the corresponding substrates 421, 441, 461 by wire bonding as shown in the drawing, or can be electrically connected to the corresponding substrates 42 441, 461 by flip chip bonding. 8 1306659 - an electrical connection end 48 is respectively disposed at the junction of the first package body 42 and the junction of the second package body 44 and the second package body 46 and the electrical connection ends 48 may be Conductive components such as a flexible circuit board, a tape reel, a flexible flexible cable, a plastic cable, etc., to electrically connect the first package 42 and a second package 44, 46, and the first package 42 and the second The junction of the package 44 can be secured by means of a glue 56 or a cassette. A plurality of solder balls 52 are disposed on the outer side of the first package body 42, and the wafers 422, 442, and 462 in the multi-package module 40 are electrically connected to the printed circuit board (not shown) through the solder balls 52. In particular, the multiple package module 40 of the present invention may include a plurality of heat sinks 54 disposed inside and outside the second packages 44, 46, and the heat sink 54 may be a heat sink or a heat sink fan, for example. The heat sink 54 shown in FIG. 2 is a heat dissipating fan', and the two heat dissipating fans are respectively disposed inside the second packages 44 and 46. Since the multi-package module 40 is composed of three packages 42 , 44 , 46 and a three-dimensional column structure and a heat sink 54 is arranged in the triangular column structure, the heat dissipation effect of the multi-package module 40 can be effectively improved, so even The BT substrate composed of a low thermal conductivity material such as a BT resin is still used for the substrate 421 and the second substrates 441 and 461, and the heat transfer effect is not hindered. Especially when the heat sink 54 is a heat dissipating fan, the forced convection generated by the fan operation can greatly increase the rate of heat loss, and the multi-package module 40 can be prevented from being affected by overheating. 9 1306659 / The multi-package module of the present invention is composed of a plurality of packages to form a stereoscopic multilateral 幵". For example, a dihedral, a tetrahedron or a cube is used, and at least one of the devices, π is applied to the surface of the package to form a plurality of packages having a good heat dissipation effect, and the value is not limited thereto. Please refer to FIG. 3®, which is a schematic structural view of a multi-package module 6G according to a second preferred embodiment of the present invention. As shown in FIG. 3 , the multi-package module 6 includes a first package body 42 , a second package body 64 , a second package body 66 , at least one heat dissipation module 62 , and a plurality of electrical connection ends 48 . A plurality of solder balls 52 are disposed on the outer side of the first package body 42 and a plurality of heat sinks 54. The side of the second package body 64 and the side of the second package body 66 are respectively adjacent to the two sides of the first package body 42, so that the first package body 42 and the second package body structure 64, 66 are formed into one or two. The side wall of the corner column structure, and the heat dissipation module 62 constitutes the bottom of the triangular column structure. In the second preferred embodiment, the first package body 42 includes a first substrate 421, at least one first wafer 422 is disposed on the inner surface of the first substrate 421, and the sealing body 423 covers the first wafer 422. The second package body 64 includes a second substrate 641, at least one second wafer 642 is disposed on the inner surface of the second substrate 641, and the encapsulant 643 covers the second wafer 642. The second package 66 includes a second substrate 661, at least one second wafer 662 is disposed on the inner surface ′ of the second substrate 661, and the sealing body 663 covers the second wafer 662. Wherein each of the wafers 422, 642, 662 can be electrically connected to the corresponding substrates 421, 641, 661 by wire bonding, or by flip chip bonding, so that the wafers 422, 642, 662 can pass through the solder balls 52 and the printed circuit. An external device such as a board is electrically connected. Similarly, the junction of the first package 42, the second and second envelopes 64, 66 of the present invention and the heat dissipation module 62 may be joined by (4) the connection core 8 or the adhesive 56. As shown in FIG. 3, the junction of the second encapsulation body 42 and the second encapsulation 66 and the junction of the second encapsulation 64 and the second encapsulation body are respectively combined and electrically connected by the electrical connection end 48. The electrical connection end 48 can be a flexible circuit board, a tape automatic material new tree, a plastic cable, and an anisotropic conductive material conductive element. The junction between the first outer body 42 and the second package 64 and the junction between the heat dissipation module 62 and the first package c and the second package 64, 66 can be fixed by the transfer % or other means. In particular, the multi-package module 60 includes a second diverging device μ package 64' 66 κ. For example, the heat sink 54 shown in FIG. 3 is a cooling fan, and the heat dissipation die (10) may generally include a dispersion W. #装置' is used for more heat dissipation. Much like a piece of music — the multi-package module includes a heat sink 54 mounted on the outside of the second package body 04, 66. This increases the heat dissipation rate of the second substrate 641, 661 by one thousand. In addition, since the multiple package module 60 of the present invention further includes a heat dissipation module 62,

L-l it 匕口J 1306659 一步提升各晶片422、642、662之散熱效果。 • 請參考第4圖，第4圖為本發明之第三較佳實施例多 重封裝模組80之結構示意圖。如第4圖所示，多重封裝模 組80包含有一第一封裝體42、一第二封裝體料、一第二 封裝體46、一第二封裝體82、三個電性連接端48、複數 個鮮球52設於第一封裝體42之外側’以及二個散熱裝置 54。第一封裝體42、第二封裝體44、第二封裝體82與第 ® 二封裝體46分別構成一立方體結構之四個侧壁。 第一封裝體42包含一第一基板421、一第一晶片422 設置於第一基板421之内表面，以及封膠體423包覆第一 晶片422。第二封裝體44包含一第二基板441、一第二晶 片442設置於第二基板441之外表面，以及封膠體443包 覆第二晶片442。第二封裝體46包含一第二基板461、至 鲁 少一第一晶片462設置於第二基板461之外表面，以及封 膠體463包覆第二晶片462。第二封裝體82包含一第二基 板82卜一第二晶片822設置於第二基板821之内表面， 以及封膠體823包覆第二晶片822。其中，各晶片422、442、 462、822可利用打線接合方式活或覆晶接合方式電連接至 對應之各基板421、441、461、821。 " 第一封裝體42與第二封裝體44、46之接合處、第二 12 1306659 封裝體46與第二封裝體82之接合處分別利用一電性連接 端48結合並且電連接。第二封裝體44與第二封裝體82之 接合處則可利用黏著劑56固定。尤其注意的是，多重封裝 模組60包含有二散熱裝置54分別設置於第二封裝體44、 46之内側，例如第4圖中所示之散熱裝置54為散熱風扇。 根據本發明之第三較佳實施例，多重封裝模組40包含 有散熱裝置54裝設於第二封裝體44、46之内侧，因此可 增加第二基板441、461之散熱速率，並提升各晶片422、 442、462、822之散熱效果。 由於本發明係以多個封裝體組成立體多邊形結構，並 利用至少一散熱裝置設於封裝體的表面，因此可形成一散 熱效果良好之多重封裝模組，以大幅提升多重封裝模組之 散熱效能，並有效避免晶片過熱等問題。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為一習知多重封裝模組之結構示意圖。 第2圖為本發明之第一較佳實施例多重封裝模組之結構示 意圖。 13 1306659 第3圖為本發明之第二較佳實施例多重封裝模組之結構示 意圖。 第4圖為本發明之第三較佳實施例多重封裝模組之結構示 意圖。L-l it J口J 1306659 One step to improve the heat dissipation effect of each wafer 422, 642, 662. Please refer to FIG. 4, which is a schematic structural view of a multi-package module 80 according to a third preferred embodiment of the present invention. As shown in FIG. 4 , the multi-package module 80 includes a first package body 42 , a second package body material , a second package body 46 , a second package body 82 , three electrical connection ends 48 , and a plurality of The fresh balls 52 are disposed on the outer side of the first package 42 and the two heat sinks 54. The first package body 42, the second package body 44, the second package body 82 and the second package body 46 respectively form four side walls of a cubic structure. The first package body 42 includes a first substrate 421, a first wafer 422 is disposed on an inner surface of the first substrate 421, and a sealant 423 covers the first wafer 422. The second package body 44 includes a second substrate 441, a second wafer 442 disposed on the outer surface of the second substrate 441, and a sealant 443 covering the second wafer 442. The second package body 46 includes a second substrate 461, and a first wafer 462 is disposed on the outer surface of the second substrate 461, and the sealing body 463 covers the second wafer 462. The second package 82 includes a second substrate 82. The second wafer 822 is disposed on the inner surface of the second substrate 821, and the encapsulant 823 covers the second wafer 822. The wafers 422, 442, 462, and 822 can be electrically connected to the corresponding substrates 421, 441, 461, and 821 by wire bonding or flip chip bonding. < The junction of the first package 42 and the second package 44, 46, the junction of the second 12 1306659 package 46 and the second package 82 are respectively combined and electrically connected by an electrical connection end 48. The junction of the second package 44 and the second package 82 can be fixed by the adhesive 56. In particular, the multiple package module 60 includes two heat sinks 54 disposed inside the second packages 44, 46. For example, the heat sink 54 shown in FIG. 4 is a heat sink fan. According to the third preferred embodiment of the present invention, the multiple package module 40 includes a heat sink 54 disposed on the inner side of the second package 44, 46, thereby increasing the heat dissipation rate of the second substrate 441, 461 and enhancing each The heat dissipation effect of the wafers 422, 442, 462, and 822. Since the present invention comprises a plurality of packages to form a three-dimensional polygonal structure, and at least one heat dissipating device is disposed on the surface of the package body, a plurality of package modules with good heat dissipation effect can be formed, thereby greatly improving the heat dissipation performance of the multiple package modules. And effectively avoid problems such as overheating of the wafer. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. [Simple Description of the Drawing] Fig. 1 is a schematic structural view of a conventional multi-package module. Fig. 2 is a schematic view showing the structure of a multi-package module according to a first preferred embodiment of the present invention. 13 1306659 FIG. 3 is a schematic view showing the structure of a multi-package module according to a second preferred embodiment of the present invention. Figure 4 is a block diagram showing the structure of a multi-package module according to a third preferred embodiment of the present invention.

【主要元件符號說明】 10 多重封裝模組 20 第一封裝體 22 第一基板 24 第一晶片 26 第一銲球 30 第二封裝體 32 第二基板 34 第二晶片 36 第二銲球 40 多重封裝模組 42 第一封裝體 44 第二封裝體 46 第二封裝體 48 電性連接端 52 鲜球 54 散熱裝置 56 黏著劑 60 多重封裝模組 62 散熱模組 64 第二封裝體 66 第二封裝體 80 多重封裝模組 82 第二封裝體 421 第一基板 422 第一晶片 423 封膠體 441 第二基板 442 第二晶片 443 封膠體 461 第二基板 462 第二晶片 463 封膠體 641 第二基板 642 第二晶片 14 1306659 643 1 ' 封膠體 661 第二基板 662 第二晶片 663 封膠體 821 第二基板 822 弟二晶片 823 封膠體 15[Main component symbol description] 10 multi-package module 20 first package 22 first substrate 24 first wafer 26 first solder ball 30 second package 32 second substrate 34 second wafer 36 second solder ball 40 multiple package Module 42 first package body 44 second package body 46 second package body 48 electrical connection end 52 fresh ball 54 heat sink 56 adhesive 60 multiple package module 62 heat dissipation module 64 second package 66 second package 80 multiple package module 82 second package 421 first substrate 422 first wafer 423 sealant 441 second substrate 442 second wafer 443 sealant 461 second substrate 462 second wafer 463 sealant 641 second substrate 642 second Wafer 14 1306659 643 1 ' Sealant 661 Second substrate 662 Second wafer 663 Sealant 821 Second substrate 822 Second wafer 823 Sealant 15

Claims (1)

1306659 十、申請專利範圍： 1. 一種多重封裝模組(multi-package module，MPM)，其包 含有·· 一第一封裝體； 複數個第二封裝體，與該第一封裝體構成一立體多邊 形(polygonal prism shaped)結構，並使該第一與各該第二封 裝體分別定義出一内侧及一外侧； 複數個電性連接端，分別設置於該第一與該等第二封 裝體之接合處； 複數個銲球，設於該第一封裝體之該外側；以及 複數個散熱裝置，設置於該第一與該等第二封裝體之 上。 2. 如申請專利範圍第1項所述之多重封裝模組，其中該第 一封裝體包含一第一基板，且該第一基板係為雙馬來醯亞 胺-三氮雜苯(bismaleimide triazine，BT)基板。 3. 如申請專利範圍第2項所述之多重封裝模組，其中該第 一封裝體包含至少一第一晶片設置於該第一基板表面，並 位於該第一封裝體之該内側。 4. 如申請專利範圍第1項所述之多重封裝模組，其中各該 第二封裝體包含一第二基板，且各該第二基板係為雙馬來 16 1306659 醯亞胺-三氮雜苯基板。 5. 如申請專利範圍第4項所述之多重封裝模組，其中各該 第二封裝體包含至少一第二晶片，設置於各該第二基板表 面，並位於各該第二封裝體之該外側。 6. 如申請專利範圍第5項所述之多重封裝模組，其中各該 散熱裝置係設置於各該第二封裝體之該内側。 7. 如申請專利範圍第6項所述之多重封裝模組，其中該等 散熱裝置包含散熱片或散熱風扇。 8. 如申請專利範圍第4項所述之多重封裝模組，其中各該 第二封裝體包含至少一第二晶片，設置於各該第二基板表 面，並位於各該第二封裝體之該内側。 > 9.如申請專利範圍第8項所述之多重封裝模組，其中各該 散熱裝置係設置於各該第二封裝體之該外側。 10. 如申請專利範圍第9項所述之多重封裝模組，其中該等 散熱裝置包含散熱片或散熱風扇。 11. 如申請專利範圍第1項所述之多重封裝模組，其中該等 電性連接端係為可撓性線路板(FPC)、卷帶自動結合(Tape 17 1306659 Automatic Bonding，TAB)柔性排線或塑膠排線之任一種， 以電連接該第一與各該第二封裝體。 * 12.如申請專利範圍第1項所述之多重封裝模組，另包含至 少一散熱模組，該散熱模組構成該立體多邊形結構之底部。 13. 如申請專利範圍第12項所述之多重封裝模組，其中該 散熱模組包含散熱片或散熱風扇。 參 14. 如申請專利範圍第1項所述之多重封裝模組，其中該立 體多邊形結構係為三角柱、四面體或立方體之任一種。 十一、圖式： 181306659 X. Patent Application Range: 1. A multi-package module (MPM), comprising: a first package; a plurality of second packages, forming a solid with the first package a polygonal prism-shaped structure, wherein the first and the second package respectively define an inner side and an outer side; a plurality of electrical connection ends are respectively disposed on the first and the second package bodies a plurality of solder balls disposed on the outer side of the first package; and a plurality of heat dissipating devices disposed on the first and second package bodies. 2. The multi-package module of claim 1, wherein the first package comprises a first substrate, and the first substrate is bimaleimide-triazabenzene (bismaleimide triazine) , BT) substrate. 3. The multi-package module of claim 2, wherein the first package comprises at least one first wafer disposed on the surface of the first substrate and located on the inner side of the first package. 4. The multi-package module of claim 1, wherein each of the second packages comprises a second substrate, and each of the second substrates is Bismale 16 1306659 quinone imine-triaza Phenyl board. 5. The multi-package module of claim 4, wherein each of the second packages comprises at least one second wafer disposed on each of the second substrate surfaces and located in each of the second packages Outside. 6. The multi-package module of claim 5, wherein each of the heat sinks is disposed on the inner side of each of the second packages. 7. The multiple package module of claim 6, wherein the heat sink comprises a heat sink or a heat sink fan. 8. The multi-package module of claim 4, wherein each of the second packages comprises at least one second wafer disposed on each of the second substrate surfaces and located in each of the second packages Inside. 9. The multi-package module of claim 8, wherein each of the heat sinks is disposed on the outer side of each of the second packages. 10. The multiple package module of claim 9, wherein the heat sink comprises a heat sink or a heat sink fan. 11. The multi-package module of claim 1, wherein the electrical connection ends are flexible circuit board (FPC), tape automatic bonding (Tape 17 1306659 Automatic Bonding, TAB) flexible row Any one of a wire or a plastic wire to electrically connect the first and the second package. The multi-package module of claim 1, further comprising at least one heat dissipation module, the heat dissipation module forming a bottom of the three-dimensional polygonal structure. 13. The multiple package module of claim 12, wherein the heat dissipation module comprises a heat sink or a heat dissipation fan. The multi-package module of claim 1, wherein the stereoscopic structure is any one of a triangular prism, a tetrahedron or a cube. XI. Schema: 18
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