TWI305948B - Non-volatile memory device and method of fabricating the same - Google Patents

Description

130594& '015 20929 twf.doc/e IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a memory element and a method of fabricating the same, and more particularly to a non-volatile memory element and a method of fabricating the same. [Prior Art]

Non-volatile memory (Non_v〇latile memory, "NVM") is a semiconductor memory that can continuously store information after power is removed. NVM includes mask-type read-only memory (Mask ROM), programmable read-only memory (PROM), erasable programmable read-only memory (eprom), electrically erasable programmable read-only memory (EEPROM), and fast Flash memory. Non-volatile memory is widely used in the semiconductor industry and has been developed to prevent loss of programming data. Typically, volatile memory cells can be programmed, read, and/or erased depending on the end use requirements of the component, and the stylized data can be stored for long periods of time. The information technology market has developed in the past two decades, so portable computers and electronic communication X-red have become semiconductor super-large-capacity circuits.

The main direction of (VLSI) and ultra-large integrated circuit (ULSI) design. Therefore, there is a great demand for low power consumption, high density and reprogrammable non-volatile memory cells. These readable and erasable memory cells have become the main components in the industry. As the demand for memory capacity increases, the requirements for semiconductor integration and memory density are relatively increased. The memory of the two-bit unit can be stored in the memory cell, which is an effective memory element. The two-element unit of the snorkeling towel has a type called gas = 5 130594 & 〇 15 ' 20929 twf. doc / e reading (10) (four) conductor elements. ^Generally, §, nitride read-only memory unit includes metal decay visits ^

MOSFET, and 氧化 氧化 pu 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化Sacrifice to set (four): nitride material 嶋 makes the mistakes in contrast, in the knowledge of floating _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _俨 ( (4),) Note the capture layer to perform the nitride thunder, the same ^L, 転 (that is, charge injection). The erase of the nitride read-only memory can be removed between the bands (ie, the charge shift: the stored charge can be reprogrammed, 21 ran or reprogrammed by the known voltage application technique, The charge cell can be captured in the forward or reverse direction to make the county memory cell _) have two independent positions 7^, thus making it possible to double the It cell density. , Feng Zhan, ^ to 1 <: The edge shows that a nitride read-only memory manufacturer: 3⁄4 Mu: ί °] surface. Referring to FIG. 1A, a nitride-reading memory is formed on the substrate 100 to sequentially form a nitrite/oxidized oxide/nitride heap ^^2, a heteropolycrystalline layer 104, and a top cover. Layer 106, afterwards, please refer to "', θ%, for lithography and etching processes to make tantalum nitride/yttria/zinc oxide layer and layer 102, doped polycrystalline stone layer and cap layer The ship is patterned to form a patterned nitridite/oxidized oxide/nitrite stack layer 102a, a doped polysilicon layer l〇4a, and a cap layer 1〇6a. Thereafter, an ion implantation process is performed using the cap layer 1〇6& as a cover ►015 20929 twf.doc/e to form a junction region ιι in the substrate 100 as a bit line. Thereafter, dielectric layer U2 0 is formed on doped region 110 between adjacent doped polysilicon layers 1〇4. Thereafter, referring to FIG. 1C, cap layer 106a is removed. Thereafter, a metal lithology layer is formed on the substrate 100, and the metal lithium layer and the doped polysilicon layer are patterned to form a metal halide layer ι 4 and a doped polysilicon layer 〇4b. As a word line.曰 Referring to FIG. 1B, the polymer 1〇8 is easily formed in the process of forming the nitrogen cut/oxygen cut/nitriding layer stacking layer, the doping multi-(4) layer purchase, and the top test in the above method. If the polymer 1〇8 remains on the nitride rock/oxidized oxide/nitride stack 々1〇2 and the doped polycrystalline slab sidewall, then the deposition process of the metal-lithium layer 114 is formed later. In the middle, it will be replaced by a metal material, so that the substituted metal 11 layer 114a

Directly with the bit line (4) 11G lion's make a miscellaneous road, as shown in Figure 1C. In another aspect, please refer to FIGS. 2A and 2B, in the process of forming a nitride nitride/yttria/tantalum nitride stacked layer 102, a doped polysilicon layer 1〇4, and a cap layer 1〇6, The conditions are not properly controlled, so that the formed doped polycrystalline layer is purchased in an inverted ladder shape, and then in the subsequent formation of the patterned metallization layer 114 and the doped polycrystalline dream layer 1 () 4b, It is easy to have the doping of the daytime 矽 〇 a a a a a a a a a a a a a 而 而 而 而 而 而 而 而 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多SUMMARY OF THE INVENTION 1305m, 20929twf.doc/e According to an embodiment of the present invention, the object of the present invention is to provide a volatile memory member and a method for fabricating the same, which can avoid the polymer residue from directly causing the word line to directly intersect with the bit line. The short circuit problem caused by the contact of the doped regions. A further object of the embodiments of the present invention is to provide a memory device and a method for fabricating the same, which can avoid the improper control of the core, and cause the adjacent wires to be electrically connected to each other through the residual grain crystal beam on the layer (4). The problem. ~

a The present invention proposes a method of manufacturing a non-volatile memory element. In this method, a money ditch is formed in the base towel, and the ditch towel is filled in the first: 1. Next, a charge storage layer # is formed on the substrate to cover the surface of the base wire and the surface of the first conductor layer. After that, on

A second conductor layer is formed on the charge storage layer as a word line. I, in accordance with an embodiment of the present invention, the first conductor layer has a doping, such that a portion of the first conductor layer is doped into the "substrate surrounding" to form a diffusion region, and the first conductor Luqiu is used as a buried bit line.

According to an embodiment of the invention, in the above method, the step of diffusing the upper portion of the first conductor layer into the substrate of the first conductor is performed: performing the step of forming the charge storage layer on the substrate simultaneously, according to the present invention The method of forming the above charge storage Γ ί ί 形成 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑 逑According to the present invention, the bottom oxide layer/nitride layer/1305948 drain 20929twf.doc/e top oxide layer comprises a hafnium oxide layer/tantalum nitride layer/negative according to an embodiment of the invention, The method of forming the first conductor layer of the doping day comprises depositing a polycrystalline 7 layer, and performing doping on the spot, and forming a doped polycrystalline layer. According to an embodiment of the invention, the method for forming the second conductor layer comprises forming a heteropolycrystalline material on the charge storage layer and forming a metal germanide layer on the upper doped polysilicon layer.

• The invention further proposes a non-volatile memory element. The memory component package has a plurality of doped conductor layers, an electroacoustic memory layer and a plurality of second conductor layers. The first conductor layer is buried in the substrate, and the material thereof is different from the material of the substrate, and is used as a plurality of buried bit lines. The charge storage layer is directly overlying the substrate and the first conductor layer. The second conductor layer is directly overlaid on the charge storage layer and is recorded as a word line. According to an embodiment of the invention, the word line of the non-volatile memory element is not parallel to the bit line.

According to an embodiment of the invention, the non-volatile memory element further includes a plurality of diffusion regions respectively located in the substrate around the first conductor layer, and the first conductor layer is used as a buried bit line. According to an embodiment of the invention, the charge storage layer of the non-volatile memory element includes a bottom oxide layer on the substrate, a nitride layer on the bottom oxide layer, and a nitride layer on the nitride layer. Top oxide layer. According to an embodiment of the invention, the bottom oxide layer/nitride layer/top oxide layer comprises a hafnium oxide layer/tantalum nitride layer/yttria layer. 9 130594^015 2〇929twf.d〇c/e According to an embodiment of the invention, the above-described substitution includes a doped polysilicon layer. Having the basket layer according to the embodiment of the invention, the second conductor reed: = doped polycrystal Zheng and the bit on the doped multi-layer on the gold on the first: the bit line is the axis in the substrate, no need The implantation of the underlying conductor layer ' as a bit line can be caused by the _ polymer residual word line, resulting in the contact of the metal layer of the word line directly with the bit line. The problem of short circuit. Moreover, the present invention can avoid the problem that d is improperly controlled, resulting in the residual polycrystalline stone suspension beam on the sidewall of the dielectric layer being adjacent to each other. The other and other objects and features of the present invention are provided. And the advantages can be more obvious, and the preferred embodiments are described below, and in conjunction with the drawings, the details are described. [Embodiment] FIG. 3A is a non-volatile 圮 according to an embodiment of the present invention. Referring to Figure 3A, a substrate 300 is provided. The material of the substrate 300 is, for example, a germanium semiconductor material such as germanium or germanium. In one embodiment, the substrate 3 is a body. In one embodiment, the substrate 3 is There is 矽(s〇i) on the insulating layer. Next, a well region 301 is formed in the substrate 300. When the doping of the substrate 3〇〇 is n-type, the well region 301 is p-type doped; when the substrate 300 is doped In the case of a p-type, the well region 301 is n-type doped. Thereafter, a mask layer I30594S〇〇i 5 20929twf.doc/e is formed on the substrate 3〇〇, preferably formed before the formation of the tantalum nitride layer. A oxidized layer 302. The method of forming the bismuth layer may be a thermal oxidation method. Μ An f Refer to FIG. 3B to perform a lithography and etching process, and the mask θ ® is used to make the county layer 3G4a, and then hard The mask, the side pad oxygen: the enamel layer, and the substrate _, to form a shallow trench in the substrate 3 通 入 入 , , 酬 酬 酬 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离 隔离The mask layer 306a is patterned again to form a mask layer fiber, and then the oxide layer 302a and the substrate 3 are etched with a hard mask to form a trench 31G on the substrate 3. The method can use an anisotropic button engraving method, for example, a fluorine-containing compound such as CF4 or % as a side gas. 'After the 3D' is formed on the substrate_layer The body layer 312' having f is replaced with a cover layer and filled in the trench 31. The doped conductor layer 312 is, for example, a doped polysilicon layer. When the well 301 is p-doped, The conductor layer 312 is, for example, a polysilicon layer doped with a ^ type; when the well region 301 is n-type doped, the conductor layer 312 is, for example, a p-type, a hetero-acoustic Ba layer. The formation method of the doped polycrystalline dream layer is, for example, The polycrystalline stone is deposited by chemical=phase deposition method and deposited at the same time as the deposition, such as _s(4). After that, the conductor layer 312 other than the trench 310 is removed as shown in FIG. 3E'. The removal method can be performed by chemical mechanical polishing. (CMP), using the mask layer 11 I30594S 20 secret 20929twid 〇 c / e = as a polishing stop layer to remove the excess conductor layer 3 〖 2, leaving the conductor layer 3 留 in = 31 () as A part of the buried bit line. ^ ίηή ί The mask layer and the tantalum oxide layer 3G2b are removed to expose the base thickness. Thereafter, a charge storage 曰0 is formed on the surface of the substrate 3〇0. In the embodiment, the charge storage layer is composed of a bottom oxide layer layer 314 and a top oxide layer 316. For example, a oxidized sand layer is formed on the substrate by a dioxane or bismuth method, and then a ruthenium nitride layer is formed on the ruthenium oxide layer by a chemical vapor phase, and then formed on a wet heat layer. Oxidized stone layer. The conductor layer in the charge storage layer trench 310 is formed by heat, and the doping in the diffusion diffuses into the substrate 3 (8) around the trench 31, forming a diffusion region 312b. This diffusion region 312b is in common with the conductor layer M2a in the buried bit line 35 of the memory element of the present invention. After the screen 2, please refer to Fig. 3F' to form a patterned conductor " on the substrate 300 as a word line, which is not parallel to the bit line. The conductor 曰 360, for example, is composed of a doped polysilicon layer 322 and gold. The material of the metal consumable layer 324 is, for example, Wei He: 324, and the top of the line, the line of the hair is formed in the base, and there is no need to form a conductor layer on the base, and then use it as a shape The implantation of the element line = the curtain 'so' can avoid the short circuit problem caused by the (4) polymer residual word line leading to the metallurgical layer of the word line directly contacting the crystal line of the bit line. Moreover, it can be avoided that the conventionally used character control is used to cause the adjacent character lines on the dielectric layer to be mutually conductive. 。 12 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I The invention is modified and refurbished, and therefore, the invention is defined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A to 1C are schematic cross-sectional views showing a conventional method of a tantalum nitride read only memory element.

Figure 2A is a schematic illustration of a conventional nitrided read only memory element. 2B is a schematic cross-sectional view of the Π-Π 线 line of FIG. 2A.

3A to 3F are schematic cross-sectional views showing a process of manufacturing a non-volatile memory element according to an embodiment of the invention. X [Description of main component symbols] 100, 300: substrate 102: charge storage layer 104, l〇4a: doped polysilicon layer

106, l〇6a: cap layer 108: polymer 110: doped region 112: dielectric layer 114, 114a: metal telluride layer 120: polycrystalline germanium suspension beam 301: well region 302, 302a, 302b: pad oxide layer 13 to O 15 20929twf.doc/e 304, 304a '304b: mask layer 306, 310: trench 308: shallow trench isolation structure 312, 312a: conductor layer 312b: diffusion region 313, 316: oxide layer 314: nitride layer 320: Charge storage layer 322: doped polysilicon layer 324: metal germanide layer 350: bit line 360: conductor layer/word line 14

Claims (1)

I30594S 0015 20929twf.doc/e X. Patent application scope: 1. A method for manufacturing non-volatile έ έ 元件 , 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 And a plurality of the plurality of 姊嶋嶋_number of word lines are formed on the charge storage layer. ^ several conductor layers, as a multi-fabrication: the non-volatile memory elements described in item 1 are such that the first-conducting two-doped 'and the method is more surrounded by the cladding 丄3 Two: =: Diffusion to the first-conductor is rarely called a plurality of diffusion regions, and the first conductor layers are collectively used as the buried bit lines. The non-volatile memory element described in the second item of the claim 11 to the 'Tombs' causes the doping of the portions of the first conductor layer to diffuse: the substrate around the layer The step in is performed with the step of forming the charge storage layer on the substrate. The method for forming the charge storage layer of the non-volatile memory element according to claim 1, wherein: forming a bottom oxide layer on the substrate; forming a layer on the oxide layer on the bottom layer a nitride layer; and forming a top oxide layer on the nitride layer. 5. The manufacturing method of the first patented non-volatile memory element 15 130594 mouse '015 ' 20929 twf. doc / e, wherein the ruthenium layer comprises an oxygen cut layer nitride layer / the top oxide layer Shen 2: The non-volatile memory element according to Item 1 of the second aspect includes a method of forming a polycrystalline germanium layer for depositing a polycrystalline layer. (3) Doping in the presence to form a doping system: II: II: Non-volatile recording of the Fandiwei * The method of forming the charge reservoir includes: forming a doped polysilicon layer on θ; A gold-emitting layer is formed on the doped multi-transfer layer. δ. A non-volatile memory component, comprising: a layer embedded in a substrate, wherein the materials of the plurality of buried wires are different, for making a replacement on the substrate and the majority The strips have a layer directly covering the charge storage layer, and the word lines are not parallel to the bit lines as described in claim 8 of the patent application (4). °Concealing elements, 讥As defined in item 8 of the patent application, the =r zone is located in the plurality of elementary common lines and the first layer of the same layer 16 I30594>S〇〇i5 2〇929twf.doc/e U. The non-volatile member of the eighth aspect of the patent scope includes: a bottom oxide layer on the substrate; a nitride layer on the bottom oxide layer; and a top oxide layer a layer on the nitride layer. 12. A non-volatile memory element as described in claim U A memory element wherein the bottom oxide layer / the nitride layer / the top oxide layer comprises a layer of oxidized stone layer / a layer of nitride layer / a layer of oxidized stone. 13. The non-volatile memory element of claim 8, wherein the doped first conductor layer comprises a doped polycrystalline layer. H. The non-volatile memory element of claim 8, wherein each of the second conductor layers comprises: - a doped multi-transfer layer on the charge storage layer; and a metal telluride layer, On the doped polysilicon layer. 17 17