1305481 ASEK1844-NEW.final_tw_2〇〇611〇3 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種線路基板(circuit substrate)，且特 別是有關於一種具有内埋晶片之線路基板。 【先前技術】 隨著電子產品的需求朝向高功能化、訊號傳輸高速化 及電路το件高密度化，積體電路晶片所呈現的功能越強， 而針對肩費性電子產品，搭配的被動元件數量亦隨之遽 增。再者，在電子產品強調輕薄短小之際，如何在有限的 構裝空間巾容納數目龐大的電子元件，已成為電子構褒業 者急待解決與克服的技術瓶頸。為了解決此一問題，構裝 技術逐漸走向單構裝系統(System in Package，SIp)的系統 整合階段’特別是多晶片模組(Multi-Chip Module，MCM) 的構裝。而其中，埋藏式主、被動元件技術(祕咖以 technology)與表面積層技術(buiw叩)成為關鍵技術。藉由 元，的内埋化，可使構裝體積大幅度縮小，能放入更多高 功能性元件，*表面積層技㈣可以提高線路密度、縮小 元件厚度，藉此提高產品整體的構裝密度。 圖1A繪不習知埋藏式晶片封襞結構之晶片上的兩接 墊與το件之電性連接義，*圖1B、㈣當外界提供 繪示之兩接塾時，此兩接整之間的電位 曲線。明參㈣卜在習知埋藏式晶片封裝結構中，盆曰 片之相_料1G、2()之邮有—咖 = 件30配置於錄1G與2G之間，其中元件如例如為t 1305481 ASEKl 844-NEW-FINAL-T W-200611〇3 體（transistor)或其他電子元件。當外界施給接墊1〇及 20 —操作電壓V時，此操作電壓v經過元件3〇後會產生 壓降（voltage difference)。此壓降會消耗能量及產生一熱 區（hot zone) ’進而使元件3〇的電性表現降低。如此一 來，埋藏式晶封裴結構之整體電性效能亦會受到影響。當 然，縮短接墊10與20之間距可以改善此壓降對埋藏式晶 片封裝結構之電性效能的不良影響，但這不是一個可行性 高的解決方案，因為過度縮短接墊1〇與2〇之間距會造成 埋藏式晶片封裝結構之良率下降或接墊10與20間的電性 干擾。 【發明内容】 本發明之目的是提供一種線路基板，其具有多個第一 導電通孔及至少-第二導電通孔。各第一導電通孔是電性 連接至一信號輸入/輸出端子，而第二導電通孔則是電性連 接至兩個以上的信錄人/輸㈣子，以提升祕基板之電 性效能。 本發明之另一目的是提供一種線路基板，直且有多個 第-導電通孔及至少-第二導電通孔。各第—導電通孔且 有:第-尺寸，且電性連接至一信號輸入/輪出端子；而第 電通孔具有-大於上述第—尺寸之第二財，且電性 連接至兩個以上的信號輸入/輸出端子。由 面積’藉此提供較大之導電面積，二充 分地供應至相對應之晶片。 本發明之又-目的是提供一種具有内垣晶片之線路 1305481 ASEKl 844-NEW-FINAL-TW-20061103 基板’其可在不犧牲製程良率的前提下提供較佳電性效能。 本發明的再一目的是提供一種具有内埋晶片之線路 基板’其可使電源充分地供應至晶片。 為達上述或是其他目的，本發明提出一種線路基板， 其包括多數個介電層、多數個内部圖案化線路層（inner patterned circuit layer)、一表層線路層（surface drcuk layer)、多數個第一導電通孔以及至少一第二導電通孔。 其中，各内部圖案化線路層是配置於兩相鄰之介電層之 間。表層線路層配置於最外侧之介電層上，且表層線路層 包括多數個信號輸入/輸出端子（signal input/〇utput terminal)。這些第一導電通孔配置於這些介電層内，用以 導通兩相鄰之㈣贿化線關，且衫—導電通孔電性 連接至其中一信號輸入/輸出端子。第二導電通孔配置於其 中-介電相，肋導通兩婦之__化線路層，且 第二導電通孔電性連接至兩個以上之信號輸人/輸出端子。 在本發明之一實施例中，上述之線路基板可更包括一 焊罩層（passivation layer)，其配置於表層線路層上，並 J露信號輸入/輸出端子。此外，上述之線路基板可 ==多數個焊球(solde⑽），其分別配 層所暴路出之這些信號輸入/輸出端子上。 在本發明之一實施例中，上述電 孔之信號輸入/輸出端子為電源端子。 #導電通 板，二上=線他路：之本:明更提出-種線路基 ^頁上述線路基板之特徵外，其第二導電通孔 1305481 ASEKl 844-NEW-FINAL-TW-20061103 的尺寸大於第一導電通孔的尺寸。 在本發明之一實施例中’上述之第二導電通孔的尺寸 至少為第一導電通孔的尺寸之1ί5倍。 曰曰 B曰 為達上述或是其他目的，本發明更提出一種具有内埋 片之線路基板，其包括一晶片以及一線路基板。其中， 片具有一主動表面，且晶片包括多數個第一接墊、多數 個弟一球底金屬層（under bump metallurgy )、至少一第二 球底金屬層以及多數個凸塊。這些第一接墊配置於主動表 面上，而這些第一球底金屬層分別配置於這些第一接墊 上。第二球底金屬層配置於兩個以上之第一接墊上。這些 凸塊分別配置於這些第一球底金屬層以及第二球底金屬^ 上。線路基板包括多數個介電層、多數個 層、一第-表層線路層一第二表層線路層、多 至:一第二導電通孔。這些介電層所形成之 =口…構具有-上表面以及—下表面，其中叠合結構之 ί於一凹槽’晶片是以主動表面朝向凹槽的方式配 介電圖案化線路層是配置於兩相鄰之這些 曰η表層線路層配置於凹槽所暴露出之介電 層上。第-表層線路層包括多數個第二接墊 應於這些凸塊其中之-，且與其電性連接:ΐ : =路層配置於疊合結構之下表面上，且第二表； 'ίί個信號輸人7輪^端子。這些第—導電通二置二 介:層内，用以導通兩相鄰之内部圖案化線 各第一導電通孔電性連接至其信號輸人/輪^子以 1305481 ASEK1844-NEW-FINAL-TW-20061103 及其中-第二接墊。第二導電通孔配置於其中一介電層 内，且位於凹槽之下方。第二導電通孔電性連接至兩個二 上之^吕说輸入/輸出端子以及其中一第二接塾。 在本發明之-實施例中，上述之具有内埋晶片之線路 基板可更包括-底縣（underflll layer)，其配置於線路 基板與晶片之主動表面之間。 為達上述或是其他目的，本發明更提出一種具有内埋 晶片之線路基板，其除了具有上述具有内埋晶片之線路基 板之特徵外，其第二導電通孔的尺寸大於第一導電通孔的 尺寸。 基於上述，在本發明之具有内埋晶片之線路基板中， 第二導電通孔及第二球底金屬層可電性連接至兩個以上之 4吕號輸入/輸出端子及兩個以上之第一接墊。因此，當這些 信號輸入/輸出端子被施以相同電壓時，晶片上位於這些第 一接墊之間的部分能夠維持與這些第一接墊相同的電壓。 如此一來，具有内埋晶片之線路基板便能在不縮短第一接 墊之間距的情況下，具有較習知埋藏式晶片封裝結構優越 的電性效能。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 圖2為本發明一實施例之線路基板的剖面示意圖。請 參照圖2,本實施例之線路基板1〇〇包括多數個介電層 1305481 844-NEW-FINAL-TW-200611〇3 aseki 多數個内部圖案化線路層120、一第二表層線路層 130、多數個第一導電通孔14〇以及至少一第二導電通^ 150。其中，這些介電層11〇形成一疊合結構，其具有一上 表面112及一下表面114。各内部圖案化線路層12〇是配 置於兩相鄰之介電層110之間。第二表層線路層13〇配置 ，疊合結構之下表面114上，且第二表層線路層13〇包括 多數個信號輸入/輸出端子132。這些第一導電通孔14〇配 • 置於這些介電層110内，用以導通兩相鄰之内部圖案化線 路層120，且各第一導電通孔140電性連接至其中一信號 輪入/輸出端子132。第二導電通孔150配置於其中一介電 層110内，用以導通兩相鄰之内部圖案化線路層12〇，且 第二導電通孔150電性連接至兩個以上之信號輸入/ 端子132。 在本實施例中’線路基板1〇〇可更包括一焊罩層160， 其配置於第二表層線路層13〇上，並暴露出這些信號輸入/ ，出端子132。此外，線路基板100可進一步包括多數個 知球170 ’其分別配置於焊罩層160所暴露出之這些信號 輸入/輸出端子132上。如此一來，内部圖案化線路層12〇 便可以透過焊球170而與外界之電子零件電性連接。 在本實施例中，第一導電通孔140與第二導電通孔15〇 的製作簡易，其中一種製作方法為以雷射鑽孔技術在介電 層110上鑽出多個貫孔，然後再以電鍍法將導電材質電鍍 於這些貫孔中。此外，第一導電通孔14〇具有一第一尺寸， 而第二導電通孔150具有一第二尺寸。在本實施例中，第 11 1305481 ASEK1844-NEW-FINAL-TW-20061103 二尺寸大於第一尺寸。在本發明之一較佳實施例中，第二 尺寸至少為第一尺寸的1，5倍。另外，電性連接至第二導 電通孔150之信號輸入/輸出端子132可為電性連接至電源 之電源端子或電性連接至接地之接地端子，或者可用以傳 輸信號。 圖3為本發明一實施例之具有内埋晶片之線路基板的 剖面示意圖。請參照圖3，本實施例之具有内埋晶片之線 路基板400包括一晶片200及一線路基板3〇〇。晶片2〇〇 具有一主動表面210,且晶片200包括多數個第一接墊 220、多數個第一球底金屬層23〇、至少一第二球底金屬層 240以及多數個凸塊250。這些第一接墊220配置於主動^ 面210上，而這些第一球底金屬層230分別配置於這些第 一接墊220上。第二球底金屬層240配置於兩個以上之第 一接墊220上。這些凸塊250分別配置於這些第一球底金 屬層230以及第二球底金屬層240上。 圖4為圖3中所續'示之晶片在尚未形成凸塊時之朝向 主動表面的下視示意圖。請參照圖4，在本實施例中，第 二球底金屬層240之表面形狀可視實際需求而調整為各種 不同形狀，以使第二球底金屬層240覆蓋於其所須覆蓋的 多個第一接墊220上。 請再參照圖3 ’線路基板300除了具有與圖2之線路 基板100相同之特徵及結構之外，更具有下述特徵及結 構。為了方便讀者對照圖3與圖2,圖3中與圖2相同之 結構將沿用圖2之標號。線路基板3〇〇之介電層1所开多 12 1305481 A 1844-NEW-FINAL-TW-20061103 ，之疊合結構的上表面112,具有一凹槽116,而晶片200 是以其主動表面210朝向凹槽116的方式配置於凹槽U6 中。線路基板300更包括一第一表層線路層31〇，其配置 • 於凹槽U6所暴露出之介電層110上。第一表層線路層310 包括多數個第二接墊312，其中各第二接墊312對應於這 些凸塊250其中之一，且與其電性連接。此外，各第一導 電通孔140除了電性連接至其中一信號輸入/輸出端子 鲁 132,更電性連接至其中一第二接墊312。第二導電通孔15〇 除了電性連接至兩個以上之信號輸入/輸出端子132，更電 陡連接至其中一第二接墊312，且第二導電通孔15〇位於 凹槽116之下方。 在本實施例之具有内埋晶片之線路基板4〇〇中，第二 V電通孔150及第二球底金屬層240可電性連接至兩個以 上之信號輸入/輸出端子132及兩個以上之第一接墊220。 因此，當這些信號輸入/輸出端子132被施以相同電壓時， 晶片200上位於這学第一接墊22〇之間的部分能夠維持與 • 這些第一接墊220相同的電壓。如此一來，具有内埋晶片 之線路基板400便能在不縮短第一接墊22〇、第一導電通 孔/40及第二導電通孔15〇之間距的情況下，具有較習知 埋藏式晶月封裝結構優越的電性效能。並且，由於本實施 例無須縮短第一接塾220、第一導電通孔140及第二導電 通孔150之間距，這會使得第一接墊22〇、第一導電通孔 140及第二導電通孔15〇的製作容易，故具有内埋晶片之 線路基板400能在維持高良率的情況下被製造。此外，當 13 1305481 ASEKl 844-NEW-FINAL-TW-20061103 第二導電通孔150被電性連接至電源時，由於晶片2〇〇上 位於這些第一接墊220之間的部分能夠維持與這些第一接 墊220相同的電壓，因此電源可透過第二導電通孔15〇充 分地供應至晶片200。 在本實施例中，具有内埋晶片之線路基板4〇〇可更包 括一底膠層410,其配置於線路基板3〇〇與晶片2〇〇之主 動表面210之間。底膠層410的主要用途為緩衝晶片2〇〇 與線路基板300之間所產生的熱應力，並增加結構強度。 圖5為圖3所繪示之線路基板的上視示意圖。請參照 圖5，第二接墊312之表面形狀可視實際需求而調整為各 種不同形狀。在本實施例中，第二接墊312的表面形狀與 圖4所繪不之第二球底金屬層24〇的表面形狀相對應。 綜上所述，在本發明之具有内埋晶片之線路基板中， 第二導電通孔及第二球底金屬層可電性連接至兩個以上之 信號輸入/輸出端子及兩個以上之第一接墊。因此，當這些 k號輸入/輪出端子被施以相同電壓時，晶片上位於這些第 一接墊之間的部分能夠維持與這些第一接墊相同的電壓。 如此一來，具有内埋晶片之線路基板便能在不縮短第一接 墊、第一導電通孔及第二導電通孔之間距的情況下，具有 較習知埋藏式晶片封裝結構優越的電性效能。並且，由於 本發明無須縮短第一接墊、第一導電通孔及第二導電通孔 之間距，這會使得第一接墊、第一導電通孔與第二導電通 孔的製作容易，故具有内埋晶片之線路基板能在維持高良 率的情況下被製造。此外，當第二導電通孔被電性連接至 衝 :::此位於這些第一接墊之間的部分能约維 通孔充分地供應至晶片。 等冤 雖然本發明已以較佳實施例揭露如上 限定本㈣’任何㈣技魏域t料财知識 脫離本發明之精神和範_，t可作 I 不 ^明之保護範圍當視後附之申請專利二二 【圖式簡單說明】 替鱼圖=if習知埋藏式晶片封裝結構之晶片上的兩接 墊與7〇件之電性連接關係。 接塾^ lBtHt外界提供—操作電壓至圖1績_示之兩 接墊時，此兩接墊之間的電位曲線。 發明一實施例之線路基板的剖面示意圖。 剖面實施例之具有内埋晶片之線路基板的 主動3中所緣示之晶片在尚未形成凸塊時之朝向 主勤表面的下視示意圖。 圖 圖5為圖3崎示之線路基板的上視示意 【主要元件符號說明】 Η) ' 20 :接墊 30 :元件 100、300 :線路基板 110 ··介電層 15 1305481 ASEKl 844-NE W-FINAL-TW-20061103 112、112’ ：上表面 114 :下表面 116 :凹槽 120 :内部圖案化線路層 130 :第二表層線路層 132 :信號輸入/輸出端子 140 :第一導電通孔 150 :第二導電通孔 160 :焊罩層 170 :焊球 200 :晶片 210 :主動表面 220 :第一接墊 230 :第一球底金屬層 240 :第二球底金屬層 250 :凸塊 310 :第一表層線路層 312 :第二接墊 400 :具有内埋晶片之線路基板 410 :底膠層 161305481 ASEK1844-NEW.final_tw_2〇〇611〇3 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a circuit substrate, and more particularly to a circuit substrate having a buried wafer. [Prior Art] As the demand for electronic products is toward high functionality, high-speed signal transmission, and high density of circuits, the functions of integrated circuit chips are stronger, and passive components for shoulder-emitting electronic products are used. The number has also increased. Moreover, when electronic products emphasize lightness and shortness, how to accommodate a large number of electronic components in a limited configuration space towel has become a technical bottleneck that the electronic structure industry urgently needs to solve and overcome. In order to solve this problem, the packaging technology is gradually moving toward the system integration phase of the System in Package (SIp), especially the Multi-Chip Module (MCM). Among them, buried primary and passive component technology (tech) and surface area technology (buiw叩) become key technologies. By embedding the element, the size of the package can be greatly reduced, and more high-functional components can be placed. * Surface area layer technology (4) can increase the line density and reduce the thickness of the element, thereby improving the overall structure of the product. density. FIG. 1A illustrates the electrical connection between the two pads on the wafer of the buried wafer package structure, and FIG. 1B and (4) when the two interfaces are provided by the outside, the two are connected. Potential curve. Mingshen (4) Bu In the conventional buried chip package structure, the phase of the pots 1G, 2 () of the postal-coffee = 30 is arranged between 1G and 2G, wherein the component is for example t 1305481 ASEKl 844-NEW-FINAL-T W-200611〇3 Transistor or other electronic components. When the externally applied pads 1 and 20 - the operating voltage V, the operating voltage v passes through the element 3 and a voltage difference is generated. This pressure drop consumes energy and creates a hot zone' which in turn reduces the electrical performance of the component 3〇. As a result, the overall electrical performance of the buried crystal sealing structure will also be affected. Of course, shortening the distance between the pads 10 and 20 can improve the adverse effect of this voltage drop on the electrical performance of the buried chip package structure, but this is not a feasible solution because the pads are excessively shortened. The distance between the pads causes a drop in the yield of the buried chip package structure or electrical interference between the pads 10 and 20. SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit substrate having a plurality of first conductive vias and at least a second conductive via. Each of the first conductive vias is electrically connected to a signal input/output terminal, and the second conductive via is electrically connected to two or more sources (four) to improve the electrical performance of the secret substrate. . Another object of the present invention is to provide a circuit substrate having a plurality of first-conducting vias and at least - second conductive vias. Each of the first conductive vias has a first dimension and is electrically connected to a signal input/rounding terminal; and the first electrical via has a second wealth greater than the first dimension and is electrically connected to two or more Signal input/output terminal. By the area ' thereby providing a larger conductive area, the second is sufficiently supplied to the corresponding wafer. It is yet another object of the present invention to provide a circuit 1305481 ASEKl 844-NEW-FINAL-TW-20061103 substrate having an intrinsic wafer that provides better electrical performance without sacrificing process yield. It is still another object of the present invention to provide a wiring substrate having a buried wafer which allows a power supply to be sufficiently supplied to the wafer. To achieve the above or other objects, the present invention provides a circuit substrate including a plurality of dielectric layers, a plurality of inner patterned circuit layers, a surface drcuk layer, and a plurality of a conductive via and at least one second conductive via. Wherein, each internal patterned circuit layer is disposed between two adjacent dielectric layers. The surface circuit layer is disposed on the outermost dielectric layer, and the surface circuit layer includes a plurality of signal input/output terminals. The first conductive vias are disposed in the dielectric layers for conducting two adjacent (four) brittle lines, and the shirt-conductive vias are electrically connected to one of the signal input/output terminals. The second conductive via is disposed in the dielectric phase, the rib conductively connects the two layers, and the second conductive via is electrically connected to the two or more signal input/output terminals. In an embodiment of the invention, the circuit substrate may further include a passivation layer disposed on the surface circuit layer and having a signal input/output terminal. In addition, the above-mentioned circuit substrate can be == a plurality of solder balls (solde (10)) which are respectively disposed on the signal input/output terminals from which the channels are violently discharged. In an embodiment of the invention, the signal input/output terminal of the aperture is a power supply terminal. #通通通板,二上=线他路:本本:明来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来来Greater than the size of the first conductive via. In one embodiment of the invention, the size of the second conductive via is at least 1⁄5 times the size of the first conductive via. In order to achieve the above or other objects, the present invention further provides a wiring substrate having a buried chip including a wafer and a wiring substrate. Wherein, the sheet has an active surface, and the wafer comprises a plurality of first pads, a plurality of under bump metallurgy layers, at least one second ball metal layer and a plurality of bumps. The first pads are disposed on the active surface, and the first ball bottom metal layers are respectively disposed on the first pads. The second ball bottom metal layer is disposed on the two or more first pads. The bumps are respectively disposed on the first ball bottom metal layer and the second ball bottom metal. The circuit substrate includes a plurality of dielectric layers, a plurality of layers, a first-surface layer, a second surface layer, and a second conductive via. The dielectric layer is formed with an upper surface and a lower surface, wherein the laminated structure is formed by disposing a dielectric pattern layer on the surface of the active surface toward the recess. The two adjacent surface layer layers are disposed on the dielectric layer exposed by the recess. The first-surface circuit layer includes a plurality of second pads disposed in the bumps and electrically connected thereto: ΐ: = the road layer is disposed on the lower surface of the stacked structure, and the second table; 'ίί The signal is input to the 7-turn ^ terminal. The first conductive vias are disposed in the layer to electrically connect the first conductive vias of the two adjacent internal patterned lines to each of the signal input/wheels to 1305481 ASEK1844-NEW-FINAL- TW-20061103 and its middle-second pad. The second conductive via is disposed in one of the dielectric layers and below the recess. The second conductive via is electrically connected to the two input/output terminals and one of the second contacts. In an embodiment of the invention, the above-described wiring substrate having a buried wafer may further include an underflll layer disposed between the wiring substrate and the active surface of the wafer. In order to achieve the above or other objects, the present invention further provides a circuit substrate having a buried chip, wherein the second conductive via has a larger size than the first conductive via except for the feature of the circuit substrate having the embedded wafer. size of. Based on the above, in the circuit substrate with a buried chip of the present invention, the second conductive via and the second ball metal layer can be electrically connected to two or more four-number input/output terminals and two or more A pad. Therefore, when these signal input/output terminals are applied with the same voltage, the portion of the wafer between these first pads can maintain the same voltage as these first pads. In this way, the circuit substrate having the embedded wafer can have superior electrical performance than the conventional buried chip package structure without shortening the distance between the first pads. The above and other objects, features, and advantages of the present invention will become more apparent <RTIgt; Embodiments FIG. 2 is a cross-sectional view showing a circuit substrate according to an embodiment of the present invention. Referring to FIG. 2, the circuit substrate 1A of the present embodiment includes a plurality of dielectric layers 1305481 844-NEW-FINAL-TW-200611〇3 aseki, a plurality of internal patterned circuit layers 120, and a second surface layer 130, A plurality of first conductive vias 14 and at least one second conductive via 150. Wherein, the dielectric layers 11A form a stacked structure having an upper surface 112 and a lower surface 114. Each of the internal patterned wiring layers 12 is disposed between two adjacent dielectric layers 110. The second surface layer 13 is disposed on the lower surface 114 of the stacked structure, and the second surface layer 13 includes a plurality of signal input/output terminals 132. The first conductive vias 14 are disposed in the dielectric layers 110 for conducting two adjacent internal patterned circuit layers 120, and each of the first conductive vias 140 is electrically connected to one of the signals. /output terminal 132. The second conductive via 150 is disposed in one of the dielectric layers 110 for conducting two adjacent internal patterned circuit layers 12 , and the second conductive vias 150 are electrically connected to the two or more signal inputs/terminals 132. In the present embodiment, the circuit substrate 1 may further include a solder mask layer 160 disposed on the second surface wiring layer 13 and exposing the signal input/output terminals 132. In addition, the circuit substrate 100 may further include a plurality of known balls 170' disposed on the signal input/output terminals 132 exposed by the solder mask layer 160, respectively. In this way, the internal patterned circuit layer 12 can be electrically connected to the external electronic components through the solder balls 170. In this embodiment, the first conductive vias 140 and the second conductive vias 15 are easily fabricated. One of the fabrication methods is to drill a plurality of through holes on the dielectric layer 110 by laser drilling techniques, and then A conductive material is electroplated into the through holes by electroplating. In addition, the first conductive via 14 〇 has a first size, and the second conductive via 150 has a second size. In the present embodiment, the 111305401 ASEK1844-NEW-FINAL-TW-20061103 two size is larger than the first size. In a preferred embodiment of the invention, the second dimension is at least 1, 5 times the first dimension. In addition, the signal input/output terminal 132 electrically connected to the second conductive via 150 may be a power terminal electrically connected to the power source or a ground terminal electrically connected to the ground, or may be used to transmit a signal. Fig. 3 is a cross-sectional view showing a circuit substrate having a buried wafer in accordance with an embodiment of the present invention. Referring to FIG. 3, the circuit substrate 400 having the embedded wafer of the present embodiment includes a wafer 200 and a circuit substrate 3A. The wafer 2 has an active surface 210, and the wafer 200 includes a plurality of first pads 220, a plurality of first ball bottom metal layers 23, at least one second ball bottom metal layer 240, and a plurality of bumps 250. The first pads 220 are disposed on the active surface 210, and the first ball bottom metal layers 230 are disposed on the first pads 220, respectively. The second ball bottom metal layer 240 is disposed on the two or more first pads 220. These bumps 250 are disposed on the first ball bottom metal layer 230 and the second ball bottom metal layer 240, respectively. Figure 4 is a bottom plan view of the wafer shown in Figure 3 as it is oriented toward the active surface when no bumps have been formed. Referring to FIG. 4, in the embodiment, the surface shape of the second ball bottom metal layer 240 can be adjusted to various shapes according to actual needs, so that the second ball bottom metal layer 240 covers the plurality of layers to be covered. A pad 220 is placed on it. Referring to Fig. 3 again, the circuit board 300 has the following features and structures in addition to the same features and structures as the circuit board 100 of Fig. 2. For the convenience of the reader, referring to Fig. 3 and Fig. 2, the same structure as Fig. 2 in Fig. 3 will follow the reference numerals of Fig. 2. The dielectric substrate 1 of the circuit substrate 3 has a plurality of 12 1305481 A 1844-NEW-FINAL-TW-20061103, and the upper surface 112 of the laminated structure has a recess 116, and the wafer 200 is an active surface 210 thereof. The groove U16 is disposed in the groove U6. The circuit substrate 300 further includes a first surface wiring layer 31, which is disposed on the dielectric layer 110 exposed by the recess U6. The first surface layer 310 includes a plurality of second pads 312, wherein each of the second pads 312 corresponds to one of the bumps 250 and is electrically connected thereto. In addition, each of the first conductive vias 140 is electrically connected to one of the signal input/output terminals 132 and is electrically connected to one of the second pads 312. The second conductive via 15 is electrically connected to the two or more signal input/output terminals 132, and is electrically connected to one of the second pads 312, and the second conductive via 15 is located below the recess 116. . In the circuit substrate 4 having the embedded wafer of the embodiment, the second V through hole 150 and the second ball bottom metal layer 240 are electrically connected to the two or more signal input/output terminals 132 and two or more. The first pad 220. Therefore, when these signal input/output terminals 132 are applied with the same voltage, the portion of the wafer 200 between the first pads 22A of the learning can maintain the same voltage as those of the first pads 220. In this way, the circuit substrate 400 having the embedded wafer can be buried in a relatively short distance without shortening the distance between the first pad 22, the first conductive via 40, and the second conductive via 15 The superior performance of the crystal moon package structure. Moreover, since the first connection 220, the first conductive via 140 and the second conductive via 150 are not required to be shortened, the first pad 22, the first conductive via 140 and the second conductive via are caused. Since the fabrication of the holes 15 is easy, the circuit substrate 400 having the embedded wafer can be manufactured while maintaining a high yield. In addition, when the 131305481 ASEK1 844-NEW-FINAL-TW-20061103 second conductive via 150 is electrically connected to the power source, since the portion of the wafer 2 located between the first pads 220 can maintain these The first pads 220 have the same voltage, so that the power source can be sufficiently supplied to the wafer 200 through the second conductive vias 15A. In this embodiment, the circuit substrate 4 having the embedded wafer may further include a primer layer 410 disposed between the circuit substrate 3 and the active surface 210 of the wafer 2. The primary use of the primer layer 410 is to buffer the thermal stress generated between the wafer 2 and the circuit substrate 300 and to increase the structural strength. FIG. 5 is a top plan view of the circuit substrate illustrated in FIG. 3. FIG. Referring to FIG. 5, the surface shape of the second pad 312 can be adjusted to various shapes according to actual needs. In the present embodiment, the surface shape of the second pad 312 corresponds to the surface shape of the second ball bottom metal layer 24A which is not depicted in FIG. In summary, in the circuit substrate with a buried chip of the present invention, the second conductive via and the second ball metal layer can be electrically connected to two or more signal input/output terminals and two or more A pad. Therefore, when the k-number input/wheel-out terminals are applied with the same voltage, the portion of the wafer between the first pads can maintain the same voltage as the first pads. In this way, the circuit substrate having the embedded chip can have superior electrical power compared to the conventional buried chip package structure without shortening the distance between the first pad, the first conductive via, and the second conductive via. Sexual effectiveness. Moreover, since the present invention does not need to shorten the distance between the first pad, the first conductive via and the second conductive via, the first pad, the first conductive via and the second conductive via are easy to fabricate, so The wiring substrate in which the wafer is buried can be manufactured while maintaining high yield. Further, when the second conductive via is electrically connected to the rush ::: the portion between the first pads can be sufficiently supplied to the wafer. Although the present invention has been disclosed in the preferred embodiments as defined above, the above (4) 'any (four) technology Wei domain t financial knowledge is out of the spirit and scope of the present invention, t can be used as a protection scope of the invention 22 [Simple description of the diagram] For the fish diagram =if the electrical connection between the two pads and the 7-piece on the wafer of the buried chip package structure.塾^ lBtHt provides the potential curve between the two pads when the operating voltage is applied to the two pads shown in Figure 1. A schematic cross-sectional view of a circuit substrate according to an embodiment of the invention. A schematic view of the wafer shown in the active 3 of the circuit substrate having the buried wafer of the cross-sectional embodiment facing the main surface when the bump is not formed. Figure 5 is a top view of the circuit board shown in Figure 3 [main component symbol description] Η) ' 20 : pad 30 : component 100 , 300 : circuit substrate 110 · dielectric layer 15 1305481 ASEKl 844-NE W -FINAL-TW-20061103 112, 112': upper surface 114: lower surface 116: groove 120: inner patterned wiring layer 130: second surface wiring layer 132: signal input/output terminal 140: first conductive via 150 : second conductive via 160 : solder mask layer 170 : solder ball 200 : wafer 210 : active surface 220 : first pad 230 : first ball bottom metal layer 240 : second ball bottom metal layer 250 : bump 310 : First surface layer 312: second pad 400: circuit substrate 410 having embedded wafers: primer layer 16