TWI304631B - - Google Patents

Description

1304631

Description of the Invention: The present invention forms a main composite layer of the present invention, thereby preventing the formation and avoiding the subsequent current half-short line spacing madness or defect. The installation of the integrated body (SDAM) or the dynamic fuse is electrically redundant. The memory single-break and high-input in the circuit is related to the fact that a coating with a coating layer is first used as a fuse window on the fuse as a fuse window, and when the repair is required, the conductor device is increased to increase the accumulation degree. There is an increasing trend path (IC) such as memory random access memory to repair the welds connected to the manufacturing test. At present, the burning current is dominant. The method of forming the filament of the fuse, the oxidation is formed to retain the moderately surnamed and the exposed filament window may enter the maximum volume, thus, in the process of producing the yield (DRAM) in the yield device The method of replacing the memory wire, the method of breaking the dissolved wire, in particular, is applied to the semiconductor layer-stop layer-oxygen. When the thickness of the fuse can not be manufactured by the body circuit, it is also static and static, and the body unit is plucked and then the method is approximated. In the process of oxidizing or damage-breaking, the intermediate memory is followed by redundant memory for accessing the machine, and the laser can be used to guide the device. The layer of the layer, the filament, the opportunity. 'It must be born, because the memory circuit is early, the burnt line or the beam is burned. Please refer to the first la-- diagram, the h-丨j diagram shows the conventional formation of a fuse with a cover layer. method. Referring to Figure la, first, a semiconductor substrate 1 is provided, and any desired components can be formed on the semiconductor substrate 101. A dielectric layer 1〇2 and a patterned mask layer 1〇3 are sequentially formed on the semiconductor substrate 1〇1, and the patterned mask layer 103 has openings i〇4a and i〇4b, and openings l〇4a and l 〇4b exposes a part of the surface of the dielectric layer 102, and the position of the opening a4a is a subsequent metal formation.

1304631 -SS_9H23562 V. INSTRUCTIONS (2) The position of the interconnect, the position of the opening l〇4b is the position where the fuse is formed later. The semiconductor substrate 110 is, for example, a germanium wafer; the dielectric layer i 2 is, for example, a hafnium oxide layer. Referring to FIG. 1b, the dielectric layer 102' is etched by patterning the mask layer 1 〇3 to form openings 105a and 105b on the dielectric layer 102, and the openings i〇5a and 1 0 5 b are out. Part of the surface of the semiconductor substrate 1 〇1. After the etching is completed, the patterned mask layer 103 is removed, and a barrier layer 106 is formed conformally on the exposed surfaces of the openings l〇5a, 105b and the dielectric layer 1〇2. The barrier layer j 0 6 is, for example, a Ta (Ta ) and a tantalum nitride (TaN ) layer, and has a low sheet resistance, a good adhesion to a dielectric layer and a copper film, and good chemistry. The mechanical polishing compatibility and the like prevent the metal filling the openings 105a and 1b5b from diffusing into the dielectric layer 102 and the semiconductor substrate 1〇, please refer to the figure lc, and then to the barrier layer 106. A metal layer 107 is formed thereon, and the metal layer 107 fills the openings 105a and 105b. Among them, the metal layer 107 is, for example, a copper metal layer. Then, the metal layer 1 〇 7 is subjected to a planarization step until the surface of the dielectric layer 102 is exposed. In this way, only the metal interconnects i〇7a and l7b which fill the opening a5a and the opening 105b are left, and the metal interconnects i〇7a and 1077b respectively serve as metal interconnects and For the fuse, the thickness is about 6 9 ka; then a barrier layer 1 〇 8 is formed on the metal interconnect 10a, the fuse 107b and the dielectric layer 〇2, as shown in Fig. 1d. . The barrier layer 1 〇 8 is, for example, a tantalum nitride (SiN) layer having a thickness of about 750 A. The barrier layer 108 can prevent the metal interconnects from being connected to the thermal interconnects 1 0 7 a and the fuses 1 〇 7 b to other structures formed subsequently. .

0503 -7666TWF2;1i η1i η;20080402.ρ tc Page 7 1304631 f _ Case No. 91123562 Che Yueyue _ Amendment 5, Invention Description (3) Please refer to the figure le, and then on the barrier layer 1〇8 Forming a dielectric layer 109 and a patterned mask layer 11〇, the patterned mask layer has an opening 110a. The opening 110a exposes a portion of the dielectric layer 109 above the metal interconnect 1a-7a. surface. The dielectric layer 丨〇 9 is, for example, an oxide layer as a coating layer over the fuse 1 0 7 b. Referring to FIG. 1f, the dielectric layer 109' is patterned by masking the mask layer 1 to form an opening i〇9a in the dielectric layer 1〇9, and the position of the opening i〇9a is followed. The position of the 烊塾 ' 'opening 1 〇 9 a will expose the surface of the metal interconnect 1 〇 7 a, and then remove the patterned mask layer 1 1 。. Please refer to FIG. 1g'. Next, an adhesion layer 丨丨i, an alloy metal layer ii 2 and an anti-reflection layer 113 are formed in conformity on the exposed surface of the opening 109a and the dielectric layer 1〇9, and anti-reflection is formed. A patterned mask layer 114 is formed on the layer jig, and the patterned mask layer 114 covers the anti-reflection layer 113 at a position above the opening 1 〇 9a. The width of the patterned mask layer ι 14 is larger than the width of the opening 1 〇 9 & The barrier layer 1 11 is, for example, a nitride nitride (TaN) layer having a thickness of about 6 〇〇 a. The barrier layer 111 prevents the alloy metal layer 112 from diffusing into the dielectric layer 1 〇 9; the alloy metal layer 11 2 is, for example, copper. The aluminum (a 1 Cu ) layer has a thickness of about 1 2 K & the anti-reflective layer 113 is, for example, a layer of yttrium oxynitride (Si〇N) having a thickness of about goo a, which does not allow the alloy metal layer 112 to be transferred during pattern transfer. Cause reflections and avoid pattern distortion. Referring to FIG. 1h, the anti-reflective layer 113, the alloy metal layer 112 and the barrier layer 111 of the exposed surface are sequentially etched by using the patterned mask layer 114 as a mask to form a metal pad H2a, metal at the opening 109a. The pad 112a protrudes from the surface of the dielectric layer 109, and has an anti-reflection layer 113a above it.

0503-7666TWF2;1i η 1i η;20080402.ρ t c Page 8 1304631 91123562

Case ring V. Invention description (4) Barrier layer 11 1 a; Then, the patterned mask layer 丨丨 4 is removed. Since the anti-reflection layer 13a formed on the metal pad 112a has an insulating effect, when the metal pad 2a and the external pin are subsequently connected by a metal wire, there may be a possibility that the metal pad 无法2a cannot be turned on, so the metal pad 丨The anti-reflective layer 11 3 a formed on the crucible 2a must be removed to facilitate subsequent conduction. In the case of the gem test, a patterned mask layer 116 is formed on the interlaminar layer 1〇9 and the anti-reflection layer U3a. The patterned mask layer 116 has openings 117 & 117b. The opening U7a exposes a portion of the surface of the anti-reflective layer 11 3a above the metal pad 1123, and the opening 1 丨 7b exposes the position above the fuse 丨〇 7b. Part of the surface of the electrical layer 109. Next, the anti-reflective layer 113a and the dielectric layer 119 are etched by using the patterned mask layer 116 as a mask to form an opening a5a at the anti-reflective layer 113a and a dielectric layer formed over the fuse 117b. The wire window 11 5 b is melted and the patterned mask layer 116 is removed, as shown in Fig. 1 j.曰 Since the metal pad 11 2a must expose the surface to provide a connection to the outside, the anti-reflective layer 11 3a exposed by the opening 11 5a over the metal pad is etched and removed. At the same time, since the etching rate of yttrium oxynitride constituting the anti-reflection layer 丨丨3a is smaller than the etching speed of the dielectric layer i〇g composed of the yttrium oxide layer, the anti-reflection layer 113& exposed at the opening 115a is completed. After removal, the depth of the wire-making window 11 5 b will be deeper, so that only the dielectric layer 1〇9b with a small thickness remains at the position above the wire 10 7b. Since the thickness of the dielectric layer 1 〇 9 b at the upper position of the k wire 1 0 7 b is relatively thin, it is relatively easy to be lost in the subsequent process and lost its function; on the contrary, if it is formed above the dissolved wire 1 0 7 b The fuse window is shallower to avoid

0503 -7666TWF2;1i η1i η;20080402.ρ tc Page 9 1304631 Case No. 91123562 曰Revision 5, invention description (5) If the electric layer is accidentally worn, because the dissolved wire window above the dissolved wire 1 0 7 b 〇7 b The depth of the etched layer is not easy to control. The dielectric layer above the fuse 1 0 7 b may be made too thick. In the subsequent repairs, the fuse 1 〇 7 b may not be hit. wear. U.S. Patent No. 6,180,503, the disclosure of which is incorporated herein by reference in its entirety, the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of The method of covering the thickness of the layer above. In view of the above, an object of the present invention is to provide a method of forming a cover layer on a fuse, which has the function of isolating air and protecting the wafer, and can effectively ensure the efficiency of the fuse. In accordance with the above objects, the present invention provides a method of forming a fuse having a cap layer, comprising the steps of: providing a semiconductor substrate having a metal interconnect and a fuse structure formed thereon, and forming a barrier layer on the semiconductor substrate The layer and a second interlayer of the barrier layer are formed by a first dielectric layer and a stop coating layer; on the first surface; in the layer and the opening surface of FIG. 3, the first patterned metal forms a The first opening and opening metal welding mask, the second three opening mask layer forming a metal pad and the covering layer, the pattern opening exposes the gold to expose the molten wire as the mask surface. a cover layer, and a first open exposed pad, the metal layer sequentially forms a mask layer with an anti-reflection on the upper side of the pad. The anti-reflection is in the metal. The metal interconnect pad protrudes from a protective layer. a surface of the second opening and a portion of the first anti-reflective layer and a surface of the layer above the protective layer are covered by an anti-reflective surface; and

Page 10 1304631 Emperor 91123562 V. Description of invention (6) According to the above method of dissolving filaments

The invention further provides a step of providing a layer of dielectric layer shape, comprising a second opening, a first surface; after the first opening layer, filling a metal to the metal interconnect to the second barrier layer and the second dielectric layer Forming a third opening and a dielectric layer; in the third mask layer, first patterning the mask layer with a first patterned alloy metal pad, a protective layer, a dielectric opening and a first layer, Covering the fuse, forming a mask layer on the opening on the third surface, and removing the fourth surface of the anti-reflection with a semiconductor substrate - forming a half of the exposed portion of the first and second openings The surface of the opening of the second opening is formed on the surface of the metal and the dielectric layer, respectively, and a first dielectric coating layer having an anti-reflection layer above the anti-silver layer above the gold metal pad is sequentially engraved on the anti-reflection layer. And removing the second image of the present invention, protecting the layer of the wafer, and opening the compliant layer to cover the mask layer, except for exposing the metal solder layer and an opening and reflecting layer portion and the protection case The cover is formed by forming a _ interconnect and forming a second layer, and forming a third barrier layer and a gold metal layer on the surface of the metal interconnect which is stopped above the metal interconnect. a first width etched surface of the first pad and the third opening alloy metal layer three barrier layer; two dielectric layer upper mask layer, mouth, fourth open surface, fifth open two patterned mask Exposing a 'semiconductor opening of the metal-clad cover layer and a first barrier-dissolving filament on the integrated substrate, and a barrier layer; a layer and a first cover layer; a patterned width of the third alloy gold; to form a removal Forming a second pattern opening in sequence to expose the joint opening, exposing the fuse layer to a surface of the second pattern of the cover pad and a fifth open portion; the first layer, up to the curtain layer. A filament is formed which has an isolated space formed above.

0503-7666TWF2;1i η1i η;20080402.ρ tc Page 11 1304631 . — Case No. 91123562 Rev. ___ V. Invention Description (7) " -- According to the above purpose, the present invention provides a cover layer The fuse comprises: a semiconductor substrate, a fuse is formed on the semiconductor substrate; a composite dielectric layer is formed on the surface of the semiconductor substrate and the fuse, the composite dielectric layer is formed with a groove, and the groove is located above the fuse. And a dielectric layer of a predetermined thickness is separated from the fuse at the bottom of the groove to serve as a cover layer; and a protective layer is formed on the surface of the composite dielectric layer. Embodiment: Referring to Figure 2a, first, a semiconductor substrate 2 is provided, and any desired components can be formed on the semiconductor substrate 201. A dielectric layer 20 2 and a patterned mask layer 203 are sequentially formed on the semiconductor substrate 2 〇 1 , and the patterned mask layer 203 has openings 2 〇 4 a and 20 4 b , and the openings 20 4 a and 284 b are exposed. A portion of the surface of the dielectric layer 202, and the position of the opening 2〇4a is a position where the metal interconnection is subsequently formed, and the position of the opening 2〇4b is a position at which a fuse is subsequently formed. Wherein the semiconductor substrate 2 〇 1 is, for example, a germanium wafer; and the dielectric layer 2 〇 2 is, for example, a oxidized stone layer. Referring to FIG. 2b, the mask layer 203 is patterned to etch the dielectric layer 202' to form openings 2 0 5a and 20 5b on the dielectric layer 2〇2, and the openings 2 0 5a and 205b are exposed. The surface of the semiconductor substrate 2〇. After the etching is completed, the patterned mask layer 203 is removed, and a barrier layer 2 〇 6 is formed on the exposed surfaces of the openings 2〇5a, 205b and the dielectric layer 202. Among them, the barrier layer 2 〇6 is, for example, a group (Ta) and a nitride button (TaN) layer, and has a property of preventing diffusion of copper, having low sheet resistance, good adhesion to a dielectric layer and a copper film, and good adhesion. Chemical mechanical polishing compatibility and the like prevent the metal which is subsequently filled into the openings 205a and 20b from diffusing to the dielectric layer 2〇2 and the semiconductor substrate 2〇1

1304631 --- Case No. 91123562_ Year Month 修正 Amendment ___ V. Invention Description (8). Referring to Figure 2c, next, a metal layer 207 is formed on the barrier layer 206, and the metal layer 207 fills the openings 205a and 205b. Among them, the metal layer 207 is, for example, a copper metal layer. Then, the metal layer 20 7 is subjected to a planarization step until the surface of the dielectric layer 220 is exposed. In this way, only the metal layers 207a and 20 7b filling the openings 2 〇 5 a and the openings 205 b are left, and the metal layers 207 a and 207 b are used as metal interconnects and fuses, respectively, and have a thickness of about 1 〇〇〇. A to 100 k A, preferably 69 k A; next, a barrier layer 208 is formed over the metal interconnection 20 7a, the fuse 207b, and the dielectric layer 20 2 as shown in Fig. 2d. The barrier layer 208 is, for example, a tantalum nitride (S i N ) layer having a thickness of about 50 A to 5 5 A, preferably 750 A, and the barrier layer 2 08 can avoid metal interconnects 2〇7a, melting. The filaments 20 7b diffuse into other formations that are subsequently formed. Please refer to FIG. 2 e. Next, in a key step of the present invention, a dielectric layer 2〇9a, a stop layer 209b, a dielectric layer 209c and a patterned mask are sequentially formed on the barrier layer 208. The layer 210, the patterned mask layer 210 has an opening 21〇a in the predetermined area of the pad, and the opening 210a exposes a part of the surface of the dielectric layer 209c above the metal layer 2〇7a. Wherein, the dielectric layer 2〇93 is, for example, an oxide layer having a thickness of about 1 〇〇A to 丨〇〇k A; the stop layer 2〇9b is, for example, a tantalum nitride layer having a thickness of about 50 A to 50 kA; and the dielectric layer 2 The 〇9c is, for example, an oxide layer having a thickness of about 100 A to about 1 Å; the dielectric layer 2 〇 9a, the stop layer 209b, and the dielectric layer 209c together form a composite dielectric layer 209 over the solvox 207b. 2f picture, with the patterned mask layer 21 () as the mask, sequential etching

0503-7666TWF2;1i η1i η;20080402.ρ tc page 13 dielectric dielectric f209a, stop layer 20 9b and dielectric layer 2〇9c for dielectric layer 2 0 9a, stop layer 2〇9b and dielectric layer The cover layer composed of 2〇9c forms an opening 2 0 9a for subsequent fabrication of the pad, and the opening 2〇9a exposes the surface of the metal interconnect 20 7a; then, the patterned mask layer 21 is removed. Referring to FIG. 2g, next, an adhesion layer 2 n, an alloy metal layer 2 2 and an anti-reflection layer 213 are sequentially formed on the exposed surface of the opening 2 〇 9 (1 and the dielectric layer 2 〇 9c). And forming a patterned mask layer 214 ′ on the anti-reflective layer 213. The patterned mask layer 214 covers the anti-reflection layer 213 at a position above the opening 2〇9d, and the width of the patterned mask layer 214 is larger than the opening. Width of 209d. The early resist layer 21 1 is, for example, a nitride button (τ a N) layer having a thickness of about 50 A to 50 kA, preferably 600 A. The barrier layer 211 prevents the alloy metal layer 212 from diffusing to the dielectric layer 212. Among the electric layers 209a, 209c and the stop layer 209b; the alloy metal layer 212 is, for example, an aluminum bronze (AlCu) layer having a thickness of about οοοοΑ to i〇〇k A, preferably 12Ka; and the antireflection layer 21 3 is, for example, nitrogen. The yttrium oxide (SiON) layer, having a thickness of about 100A to 10kA, preferably 300A, does not cause the alloy metal layer 212 to reflect when pattern transfer is performed, thereby avoiding pattern distortion. Please refer to FIG. 2h to pattern the mask The curtain layer 2 1 4 sequentially etches the anti-reflection layer 213, the alloy metal layer 212 and the barrier layer 211 of the exposed surface. A metal pad 212a is formed at the opening 209d, and the metal pad 21 2a protrudes from the anti-reflection layer 213a above the surface of the dielectric layer 209c; then, the patterned mask layer 2 1 4 is removed. Please refer to the 2nd figure. Forming a protective layer 2 15 on the anti-reflective layer 2 1 3 a and the dielectric layer 2 0 9c, and forming a patterned mask on the protective layer 2 15

0503 -7666TWF2;1i η1i η;20080402.ρ t c Page 14 1304631

1^6. The patterned mask layer 216 has openings 217a and 217b, and the opening 217 is a part of the surface of the protective layer 215 at a position above the metal pad 2 12a, a : I 21 : Γ will expose the position of the fuse 2 Layer 215: Partially layered, formed by plasma chemical vapor deposition. Then, the patterned mask layer 216 is used as a mask etching protection layer 215, the f protective layer 215 forms an opening 215a and a fuse window 21, and the patterned mask layer 216 is removed, as shown in FIG. Shown. Since the metal pad 212& must expose the surface to provide a connection to the outside, the anti-reflection layer 21 of the opening 2 covered over the metal pad is etched and exposed after the protective layer 2i5 is exposed. Removed and engraved. The structure of the composite dielectric layer 2 〇 9 provided by the present invention is a combined layer θ structure formed by the dielectric layer 20 9a, the stop layer 2〇9b, and the dielectric layer 20 9c. Therefore, when the fuse window 21 5b After the dielectric layer 20 9 c is removed, the tantalum nitride layer is etched at a lower rate than the oxide layer because of the presence of the stop layer 2 〇 9b formed of a tantalum nitride layer, so the fuse window 2 丨 5b It is not too deep because the relationship of the anti-reflection layer 213a is to be removed at the opening 215a, and the electric layer 2 0 9 e at the position above the fuse 2〇7b is not too thin' and can be adjusted according to the actual needs of the repaired wire. To adjust the dielectric layer 20 9e. Therefore, the melted wire having a coating layer according to the present invention comprises a semiconductor substrate 201, a fuse structure 207b is formed in the semiconductor substrate 2〇1, and a dielectric layer 2〇9a and a stop layer 209b are included. And a composite dielectric layer of the dielectric layer 209c is formed on the surface of the semiconductor substrate 2〇1 and the fuse 2〇7b, and the composite dielectric layer is formed with a groove as the fuse window 215b, the groove

0503-7666TWF2;1i η1i η;20080402.ρ tc Page 15 1304631 Amendment No. 91123FiR?. V. Invention description (11) Above the fuse 2 0 7b, and the bottom of the groove is separated from the fuse 2〇7b by both The 1 degree " electrical layer is used as the cover layer 2 0 9 e • Finally, it also includes a protective layer 2 5, which forms a surface of the recomposited dielectric layer, and the protective layer protects the metal pad from external force. Squeeze and deform. Therefore, in the method for forming a fuse-covered cover layer provided by the present invention, the deep 2 sub-dielectric layer 2 of the fuse window 2丨5b can be controlled by controlling the depth of the gate layer 2 〇 9b. 0 9a thickness to control the oxide layer above the fuse 2 0 7b: because the thickness of the protective layer above the fuse 'is too thin to be pierced, nor because the thickness of the protective layer is too thick, Λ If w is to be repaired, it cannot be penetrated. Moreover, the present invention provides that "all steps can be completed in the same processing chamber, and it is not necessary to have a low mask, which can save time and cost, thereby achieving the purpose of low cost. The invention has been disclosed in the preferred embodiments as above, but it is: invention: any person skilled in the art, without departing from the invention:: within: can be used for modification and retouching, and therefore the invention is guaranteed; The scope defined in the scope of application for patents shall prevail.

The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims. The details are as follows: The first β-1j system shows a conventional method of forming a melted wire having a coating layer. Figures 2a-2j show a method of forming a fuse having a cover layer of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS: 101, 201~ semiconductor substrate; 102, 109, 202, 209a, 209c~ dielectric layer; 103, 110, 114, 116~ patterned mask layer; 10 4a, 104b, 105a, 105b, 109 a~open; 110a, 115a, 117a, 117b~open; 115b, 215b~fuse window; *1 0 6,1 ◦ 8,11 1 ,111 a,2 0 6 , 2 0 8 , 2 11 , 2 11 a ~ barrier layer; 107, 20 7 ~ metal layer; 107a, 207a ~ metal interconnect; 107b, 2 07b ~ fuse; 112, 21 2 ~ alloy metal layer; 112a, 212a ~ metal pad; 113a, 213, 213a~ anti-reflection layer; 2 1 5~ protective layer; 203, 210, 214, 216~ patterned mask layer;

0503 - 7666TWF2; 1 i η 1 i η; 20080402. ρ tc page 17 1304631 _ case number 91123562_year and month correction pattern simple description 20 4a, 204b > 2 0 5a, 205b, 209d ~ opening; 210a, 215a, 217a, 217b ~ opening; 209 ~ composite dielectric layer; 2 0 9b ~ stop layer; 209e ~ cover layer.

0503 -7666TWF2;1i η11η;20080402.ρ t c Page 18

Claims (1)

1304631 ____ Case No. 91123562_Yearly b_Amendment___ VI. Patent Application No. 1, a method of forming a fuse having a cover layer, comprising the following steps: providing a metal interconnect and a filament structure a semiconductor substrate; a cover layer composed of a first dielectric layer, a stop layer and a second dielectric layer is formed on the semiconductor substrate, and the cover layer above the metal interconnect line forms a first opening The first opening exposes a surface of the metal interconnect, and the cover layer is patterned to open the third protective layer, and the surface of the fuse window 2 is: the first surface; the metal The opening of the mask layer, the opening is exposed to the first time until the exposure is as described in the application method, the opening forms a metal pad, and the metal pad protrudes from the bonding pad and the covering layer to form a protective layer in sequence. The first 'the first patterned mask layer has a second opening and a second opening exposing a portion of the surface above the metal pad to a portion of the surface above the solution; and the patterned mask layer is a cover Curtain along the second opening Etching the surface of the metal pad while etching, and forming a cladding layer having a coating layer along the third open protective layer, the second dielectric layer and the stop layer according to the first aspect of the patent scope The step of forming the metal interconnect and the fuse structure provides a semiconductor substrate having a fourth opening and a fifth opening π formed on the layer of the semiconductor substrate, the opening and the opening Exposing a portion of the surface of the semiconductor substrate; and forming a first compliance on the fourth opening and the fifth opening surface Amendment 1304631 VI. Application scope ^ . /v ^ « π broken metal interconnect and the barrier layer are filled with metal layer to form the wire respectively. A method of forming a fuse of a germanium layer, wherein a method of forming a "Hai "" layer on the semiconductor substrate comprises the steps of: interconnecting the metal, the fuse, and a surface of the dielectric layer Forming a second barrier layer thereon; forming a cap layer composed of the first dielectric layer, the stop layer and the second dielectric layer on the second barrier layer. 4. The method of forming a fuse having a cover layer according to claim 3, wherein the method of forming the metal pad in the first opening comprises the steps of: the first opening and the second Compliance on the surface of the electrical layer forms a third barrier layer and an alloy metal layer; a second patterned mask layer is formed on the alloy metal layer above the first opening, and the second patterned mask layer The width is greater than the width of the first opening; the second patterned mask layer is sequentially etched by the mask: forming the metal pad, and removing the third barrier of the exposed surface: genus = removing the second pattern Cover layer. 5 · For example, the method of applying for the patent scope, the + wire, wherein the metal interconnecting wire: the steel is opened to have a melting layer of the covering layer. 6. The second covering layer described in the first claim of the patent scope is dissolved. Page 0503 -7666TWF2; 1i η1i η; 20080402.ρ tc 1304631 Six-way correction of the emperor 91123fifi?_ Patent application range of 7 sides of the wire = the material of the dissolved wire is steel. The method of silk; forming a melt having a cover layer as described in the item Kjff1, such as by biting _ Μ first; the thickness of the tantalum layer is 1000 to 10 Ok Α. ^ · The invention mentioned in the first paragraph of the patent scope is #1古, #JS > I- silk 9 square = where the first dielectric layer is oxygen: the formation of the two filaments has the The cover layer is fused to the first; the thickness of the electrical layer is from 1000 to 100 kA. Method of silking 熔 The melting of the coating layer is described in the first aspect of the patent, and the second dielectric layer is a layer of oxidized stone. The method of forming a melting, rolling, or crucible having a coating layer as described in Item 1 of the Japanese Patent No. 1, wherein the stopping layer is a nitride layer.铋 铋 、 、 、 、 申 申 申 申 申 申 申 申 申 申 申 申 申 申 申 申 申 申 申 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 13 . The method of forming a fusion layer having a coating layer according to claim 1, wherein the metal pad is an aluminized copper layer. 14 · forming the covering as described in claim 1 A method of forming a fuse of a layer, wherein the protective layer is a coating layer of an oxide layer and a nitride layer. 15) A method of forming a wire having a coating layer as described in claim 14 of the patent application, wherein the oxide layer And a coating layer of the nitride layer is formed by a plasma chemical vapor deposition method. [6] The method for forming a solution having a coating layer according to the first aspect of the invention, wherein the patterned mask layer is further Including an anti-reflection layer. The method of forming a solution having a coating layer according to the second aspect of the invention, wherein the dielectric layer is an oxide layer or a low dielectric constant material layer 0503 -7666TWF2;1i η1i η;20080402.ρ tc Page 21 1304631 ' _ Case No. 91123562_ Year Month _ Amendment _ VI. Patent Application Range 1 8. Forming a cover layer as described in item 2 of the patent application scope A method of a fuse, wherein the first barrier layer is one of a button or a tantalum nitride layer. A method of forming a fuse having a cover layer as described in claim 2, wherein the metal layer is a copper metal layer. A method of forming a fuse having a cover layer as described in claim 3, wherein the second barrier layer is a tantalum nitride layer. 2 1 . The method of forming a fuse having a cover layer according to claim 4, wherein the third barrier layer is a ruthenium layer or a nitride button layer - 〇2 2. The fuse of the layer comprises: a semiconductor substrate having a fuse and a metal interconnect formed thereon; a composite dielectric layer formed on the surface of the semiconductor substrate, the fuse, and the metal interconnect The composite dielectric layer is a combination layer of a first dielectric layer-nitride layer-second dielectric layer, and the composite dielectric layer is formed with a recess, and the recess is located above the fuse. The groove passes through the second dielectric layer and the nitride layer, and the first dielectric layer of the predetermined thickness of the bottom of the groove and the fuse is used as a cover layer; and a protective layer is formed thereon. On the surface of the composite dielectric layer. 23. The fuse having a cover layer according to claim 22, wherein the first dielectric layer has a thickness of 1000 to 100 kA. 24. The fuse having a cover layer according to claim 22, wherein the first dielectric layer is a ruthenium oxide layer. 0503 -7666TWF2;1i η1i η;20080402.ρ tc Page 22 1304631 _ Case No. 91123562_Yearly 曰 Revision _ VI. Patent application scope 2 5. The coating with the cover layer as described in item 2 of the patent application scope a wire, wherein the second dielectric layer has a thickness of 1000 to 1 〇〇 kA. The fuse having a cover layer as described in claim 2, wherein the second dielectric layer is a ruthenium oxide layer. 27. The fuse having a cover layer as described in claim 2, wherein the nitride layer has a thickness of 50 to 50 k A. 28. The fuse having a cover layer of claim 22, wherein the predetermined thickness is less than the thickness of the first dielectric layer. The fuse having a coating layer as described in claim 2, wherein the protective layer is a composite layer composed of an oxide layer and a nitride layer. 0503 - 76667W2; 1 i η 1 i η; 20080402. p t c Page 23 1304631 0503-7666TWF2;1i η1i η;20080402.ptc Page 3 I 1304631 Case No. 91123562 Year of the Amendment IV. Abstract of Chinese Invention (Name of Invention: Fuse with Overlay and Its Forming Method) 203, 210, 214, 216~ patterned mask layer; 204a, 204b, 205a, 205b, 209d~ opening; 21 0a, 215a, 217a, 21 7b ~ opening; 2 0 9 ~ composite dielectric layer; 209b~ stop layer; 209e~ cover layer . English abstract (name of invention:) ΓϊΓι m 1 0503-7666TWF2;1i η11η;20080402.ρ t c Page 4