1303440 # 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體記憶體裝置，以及更特別 地是有關於一種設計成控制一位元線之驅動的半導體記憶 體裝置。 【先前技術】 當已逐漸縮小半導體記憶體裝置之線寬及單元尺寸 時，許多硏發者已著重於可在低電源電壓下操作之記憶體 B 裝置的發展。因此，需要一種可提供低操作電壓狀況所需 之功能的佈局技術。 目前，將一內部電壓產生器安裝在一半導體記憶體裝 置中以提供該半導體記憶體裝置之操作所需的電壓，其中 該內部電壓產生器在被供應一外部電源電壓後產生一內部 電壓。在使用位元線放大器之那些記憶體裝置（例如：動態 隨機存取記憶體（DRAMs))中，一核心電壓係一對應於高邏 輯位準之資料信號的電壓。 » 一旦啓動由一列位址所選擇之一組字元線，將對應於 連接至該等選擇字元線之複數個記憶體單元的個別儲存資 料之電壓供應至位元線，以及該等位元線放大器感測被供 應至該等位元線之電壓及放大該等感測電壓。因此，許多 位元線放大器同時操作以放大被供應至該等位元線之電 壓。然而，大量電流從用以驅動該等位元線感測放大器之 核心電壓端消耗，以及一核心電壓位準下降。當該核心電 壓位準持續下降，常常有一短期間很難使用該核心電壓來 1303440 放大被供應至該等位元線之電壓。換句話說，該等位元線 之感測率變小了。 因此，在操作該等位元線感測放大器之初始階段（亦 即，在該等記憶體單元及該等位元線共用電荷之後）期間， 該等位元線感測放大器使用一比該核心電壓高之電壓（通 常是一外部電源電壓VDD)來感測及放大被供應至該等位 元線之電壓。此方法通常被稱爲”過驅動模式π。 第1圖描述一用於一位元線感測放大器區塊BLSΑ之 典型控制電路的簡化圖式。 該位元線感測放大器區塊BLSA包括一上拉電源線 RTO及一下拉電源線SB。提供第一至第三驅動器電晶體 Ml、M2及M3以驅動該上拉電源線RTO及該下拉電源線 SB。該第二驅動器電晶體M2用以使用一核心電壓VCORE 來驅動該上拉電源線RTO以回應一上拉電源線驅動控制信 號SAP。該第三驅動器電晶體M3用以使用一接地電壓VSS 來驅動該下拉電源線S B以回應一下拉電源線驅動控制信 號SAN。要回應一過驅動信號OVDP，該第一驅動器電晶體 Ml經由該第二驅動器電晶體M2供應一外部電源電壓VDD 至該上拉電源線RTO。 一過驅動信號產生區塊產生該過驅動信號OVDP以回 應一啓動指令ACT。該第一及第二驅動器電晶體Ml及M2 可以使用P-型通道金屬氧化半導體（PMOS)電晶體來取代。 供應該啓動指令ACT以啓動字元線，以及傳送在單元 中所儲存之資料至個別位元線對。在某一期間後，將該上 1303440 拉電源線驅動控制信號SAP及該下拉電源線驅動控制信號 SAN啓動成爲一高邏輯位準。在此時，該過驅動信號 OVDP(在該上拉電源線驅動控制信號SAP及該下拉電源線 驅動控制信號SAN之啓動前已啓動成爲一高邏輯位準以回 應該啓動指令ACT)指示該上拉電源線RTO之過驅動有一 預定期間。更特別地，當將該上拉電源線驅動控制信號 SAP、該下拉電源線驅動控制信號 SAN及該過驅動信號 OVDP啓動成爲高邏輯位準時，導通該第一至第三驅動器電 晶體Ml、M2及M3以使用該外部電源電壓VDD驅動該下 拉電源線RTO及使用該接地電壓VSS驅動該上拉電源線 SB。 在某一時間消逝後，啓動該過驅動信號OVDP成爲一 低邏輯位準，以及因此，關閉該第一驅動器電晶體Μ 1及 只使用該核心電壓VC ORE驅動該上拉電源線RT0。 第2A至2C圖描述依據一位元線感測放大器區塊之操 作狀況的一核心電壓 VC0RE端之電壓位準在時間上變化 的曲線圖。 特別地，第2A圖描述在該位元線感測放大器區塊沒有 實施一位元線過驅動操作之操作期間在該核心電壓端中之 電壓位準變化的曲線圖。在供應一啓動指令ACT0之後， 該核心電壓端之電壓位準陡峭地下降。做爲參考之用，如 果一被供應至DRAM之外部電源電壓VDD具有1.7V至1.9V 間之特定範圍，則一半導體記憶體裝置不僅應該在1.7V至 1.9V之外部電源電壓VDD的範圍內標準操作，而且亦可在 1303440 % 小於1.7V或大於1.9V(然而只高達至某一位準）之外部電源 電壓VDD的範圍操作。 第2B圖描述在該位元線感測放大器區塊在低外部電 源電壓VDD之狀況下實施該位元線過驅動操作之操作期間 在該核心電壓端中之電壓位準變化的曲線圖。由於該過驅 動操作，該核心電壓端可維持一穩定電壓位準。 第2C圖描述在該位元線感測放大器區塊在高外部電 源電壓VDD之狀況下實施該位元線過驅動操作之操作期間 > 在該核心電壓端中之電壓位準變化的曲線圖。因爲該核心 電壓VCORE與該外部電源電壓VDD間之電壓差較大，所 以該過驅動操作之實施以回應該啓動指令ACT0及ACT 1促 使該核心電壓端之電壓位準陡峭地增加。並且，當連續地 輸入啓動指令時，該核心電壓VC ORE之電壓位準因在該核 心電壓端中所保持之電荷而進一步增加以回應該先前啓動 指令。 在此一情況中，使用一高電壓 VPP驅動該選擇字元 B 線，該高電壓VPP係一比該外部電源電壓VDD高之內部電 壓，以及該位元線具有一過驅動電壓，該過驅動電壓之位 準比該核心電壓VC ORE之標準位準高。結果，在一具有連 接至一字元線之閘極及連接至一字元線之源極的單元電晶 體中，經常減少在該單元電晶體之閘極與源極間的電壓 Vgs。在該單元電晶體之閘極-源極電壓Vgs的減少可能損 害一讀取或寫入操作之可靠性，以及因此’ 一半導體記憶 體裝置可能錯誤地操作。 1303440 / 【發明內容】 因此，本發明之一目的在於提供一種半導體記憶體裝 置及其驅動方法，該半導體記憶體裝置可減少一核心電壓 端之電壓位準因在高外部電源電壓之狀況下一位元線感測 放大器區塊之操作期間所實施的一過驅動操作所造成之過 度增加。 依據本發明之一觀點，提供一種半導體記憶體裝置， 包括：一位元線感測放大區塊，用以感測及放大在位元線 • 上之資料；一第一驅動區塊，用以使用一被供應至一標準 驅動電壓端之電壓以驅動該位元線感測放大區塊之一上拉 電線；一第二驅動區塊，用以使用一過驅動電壓以驅動該 標準驅動電壓端；一過驅動信號產生區塊，用以產生一過 驅動信號以回應一啓動指令，該過驅動信號界定一過驅動 間隔；一外部電源電壓位準偵測區塊，用以偵測一外部電 源電壓之電壓位準；以及一選擇輸出區塊，用以選擇性地 輸出該過驅動信號以回應該外部電源電壓位準偵測區塊之 ® 輸出信號，其中該選擇輸出區塊之輸出信號控制該第二驅 動區塊。 依據本發明之另一觀點，提供一種半導體記憶體裝置 之驅動方法，包括：使用一被施加至一標準驅動電壓端之 s壓以驅動一位元線感測放大區塊之一上拉電源線；產生 一過驅動信號以回應一啓動指令，該過驅動信號界定一過 驅動間隔；偵測一外部電源電壓之電壓位準以選擇性地輸 出該過驅動信號；選擇性地輸出該過驅動信號以回應該偵 •1303440 測結果，其中如果該過驅動電壓比一預定電壓低，則使該 過驅動信號致能，以及如果該過驅動電壓比一預定電壓 高’則使該過驅動信號失能；以及使用該過驅動電壓來驅 動該標準驅動電壓端以回應該過驅動信號。 從下面配合所附圖式之示範性實施例的描述將更佳了 解本發明之上述及其它目的以及特徵。 【實施方式】 將配合所附圖式來詳細描述依據本發明之示範性實施 ® 例的一根據過驅動方案之半導體記憶體裝置及其驅動方 法。 第3圖係依據本發明之一實施例的一根據一過驅動方 案操作之半導體記憶體裝置的簡化方塊圖。 依據本實施例之半導體記憶體裝置使用一肓目驅動型 過驅動方案。在該盲目驅動型過驅動方案中，一標準驅動 器（未顯示）用以使用一被施加至一核心電壓端之電壓來驅 動一位元線感測放大器區塊之一上拉電源線RTO，以及一 ¥ 過驅動器用以使用一外部電源電壓VDD來驅動該核心電壓 端。該肓目驅動型過驅動方案之電路及其一般操作係被描 述於第1圖中，將不描述有關於該盲目驅動型過驅動器之 控制的那些部分。 依據本實施例之半導體記憶體裝置包括一過驅動信號 產生區塊300、一外部電源電壓（VDD)位準偵測區塊400、 一選擇輸出區塊500及一過驅動區塊600。該過驅動信號產 生區塊300產生一過驅動信號OVDP以回應一啓動指令BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device designed to control the driving of a bit line. [Prior Art] When the line width and cell size of a semiconductor memory device have been gradually reduced, many controversies have focused on the development of a memory B device that can operate at a low power supply voltage. Therefore, there is a need for a layout technique that provides the functionality required for low operating voltage conditions. Currently, an internal voltage generator is mounted in a semiconductor memory device to provide the voltage required for operation of the semiconductor memory device, wherein the internal voltage generator generates an internal voltage after being supplied with an external supply voltage. In those memory devices (e.g., dynamic random access memory (DRAMs)) that use bit line amplifiers, a core voltage is a voltage corresponding to a data signal of a high logic level. » once a group of word lines selected by a column of addresses is initiated, voltages corresponding to individual stored data of a plurality of memory cells connected to the selected word lines are supplied to the bit lines, and the bits The line amplifier senses the voltage supplied to the bit lines and amplifies the sense voltages. Therefore, many bit line amplifiers operate simultaneously to amplify the voltage supplied to the bit lines. However, a large amount of current is consumed from the core voltage terminal for driving the bit line sense amplifier, and a core voltage level is lowered. When the core voltage level continues to drop, it is often difficult to use the core voltage for a short period of time to 1303440 amplify the voltage supplied to the bit line. In other words, the sensing rate of the bit line becomes smaller. Thus, during operation of the first stage of the bit line sense amplifier (ie, after the memory cells and the bit lines share charge), the bit line sense amplifier uses a ratio of the core A voltage high voltage (usually an external supply voltage VDD) senses and amplifies the voltage supplied to the bit lines. This method is commonly referred to as the "overdrive mode π. Figure 1 depicts a simplified diagram of a typical control circuit for a bit line sense amplifier block BLS. The bit line sense amplifier block BLSA includes a Pull-up power supply line RTO and pull-up power supply line SB. First to third driver transistors M1, M2 and M3 are provided to drive the pull-up power supply line RTO and the pull-down power supply line SB. The second driver transistor M2 is used for Using a core voltage VCORE to drive the pull-up power line RTO in response to a pull-up power line drive control signal SAP. The third driver transistor M3 is used to drive the pull-down power line SB using a ground voltage VSS to respond to pull The power line drives the control signal SAN. In response to the overdrive signal OVDP, the first driver transistor M1 supplies an external power supply voltage VDD to the pull-up power supply line RTO via the second driver transistor M2. The block generates the overdrive signal OVDP in response to a start command ACT. The first and second driver transistors M1 and M2 may be replaced with a P-type channel metal oxide semiconductor (PMOS) transistor. Supplying the start command ACT to start the word line, and transferring the data stored in the unit to the individual bit line pair. After a certain period, the upper 1303440 pull power line drive control signal SAP and the pull down power line drive The control signal SAN is activated to a high logic level. At this time, the overdrive signal OVDP (starts to be a high logic bit before the pull-up power line drive control signal SAP and the pull-down power line drive control signal SAN are activated) The overdrive command ACT) indicates that the overdrive of the pull-up power line RTO has a predetermined period. More specifically, when the pull-up power line drive control signal SAP, the pull-down power line drive control signal SAN, and the overdrive When the signal OVDP is turned on to a high logic level, the first to third driver transistors M1, M2, and M3 are turned on to drive the pull-down power line RTO using the external power supply voltage VDD and the pull-up power line SB is driven using the ground voltage VSS. After a certain time has elapsed, the overdrive signal OVDP is activated to a low logic level, and thus, the first driver transistor Μ 1 is turned off and only The core voltage VC ORE drives the pull-up power line RT0. Figures 2A through 2C depict graphs of the voltage level of a core voltage VC0RE terminal varying in time according to the operating conditions of a one-bit sense amplifier block. In particular, Figure 2A depicts a graph of voltage level changes in the core voltage terminal during operation of the bit line sense amplifier block without performing a one-line overdrive operation. After that, the voltage level of the core voltage terminal drops steeply. For reference, if a external power supply voltage VDD supplied to the DRAM has a specific range between 1.7V and 1.9V, a semiconductor memory device should not only It operates in the range of 1.7V to 1.9V external supply voltage VDD, and can also operate in the range of 1303440% external power supply voltage VDD less than 1.7V or greater than 1.9V (however, up to a certain level). Figure 2B depicts a plot of voltage level changes in the core voltage terminal during operation of the bit line senser block under low external power supply voltage VDD during operation of the bit line. Due to the overdrive operation, the core voltage terminal maintains a stable voltage level. Figure 2C depicts a graph of voltage level changes in the core voltage terminal during operation of the bit line sense amplifier block performing the bit line overdrive operation under high external supply voltage VDD. . Since the voltage difference between the core voltage VCORE and the external power supply voltage VDD is large, the implementation of the overdrive operation causes the voltage levels of the core voltage terminal to be steeply increased in response to the start commands ACT0 and ACT1. Also, when the start command is continuously input, the voltage level of the core voltage VC ORE is further increased by the charge held in the core voltage terminal to respond to the previous start command. In this case, the select word B line is driven by a high voltage VPP, which is an internal voltage higher than the external power supply voltage VDD, and the bit line has an overdrive voltage, the overdrive The level of the voltage is higher than the standard level of the core voltage VC ORE. As a result, in a cell electro-optic body having a gate connected to a word line and a source connected to a word line, the voltage Vgs between the gate and the source of the cell transistor is often reduced. The reduction in the gate-to-source voltage Vgs at the cell transistor may compromise the reliability of a read or write operation, and thus a semiconductor memory device may operate erroneously. 1303440 / SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor memory device and a method of driving the same that can reduce the voltage level of a core voltage terminal due to a high external power supply voltage. An excessive increase in the overdrive operation performed during operation of the bit line sense amplifier block. According to one aspect of the present invention, a semiconductor memory device is provided, comprising: a one-line sensing amplification block for sensing and amplifying data on a bit line; a first driving block for Using a voltage supplied to a standard driving voltage terminal to drive one of the bit line sensing amplification blocks; a second driving block for driving the standard driving voltage terminal using an overdrive voltage An overdrive signal generating block for generating an overdrive signal in response to a start command, the overdrive signal defining an overdrive interval; and an external supply voltage level detection block for detecting an external power supply a voltage level of the voltage; and a selection output block for selectively outputting the overdrive signal to echo the output signal of the external power supply voltage level detection block, wherein the output signal of the selected output block is controlled The second drive block. According to another aspect of the present invention, a method of driving a semiconductor memory device is provided, comprising: driving a power supply line of one of a bit line sensing amplification block by using a voltage applied to a standard driving voltage terminal Generating an overdrive signal in response to a start command, the overdrive signal defining an overdrive interval; detecting a voltage level of an external supply voltage to selectively output the overdrive signal; selectively outputting the overdrive signal The result of the detection of 1303440, wherein if the overdrive voltage is lower than a predetermined voltage, the overdrive signal is enabled, and if the overdrive voltage is higher than a predetermined voltage, the overdrive signal is disabled And using the overdrive voltage to drive the standard drive voltage terminal to respond to the overdrive signal. The above and other objects and features of the present invention will become better understood from the following description of exemplary embodiments. [Embodiment] A semiconductor memory device according to an overdrive scheme and a driving method thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. Figure 3 is a simplified block diagram of a semiconductor memory device operating in accordance with an overdrive scheme in accordance with one embodiment of the present invention. The semiconductor memory device according to this embodiment uses an eye drive type overdrive scheme. In the blind drive type overdrive scheme, a standard driver (not shown) is used to drive a pull-up power line RTO of one of the bit line sense amplifier blocks using a voltage applied to a core voltage terminal, and An overdrive is used to drive the core voltage terminal using an external supply voltage VDD. The circuit of the eye-driven overdrive scheme and its general operation are described in Fig. 1, and those portions relating to the control of the blind drive type overdrive will not be described. The semiconductor memory device according to this embodiment includes an overdrive signal generating block 300, an external power supply voltage (VDD) level detecting block 400, a select output block 500, and an overdrive block 600. The overdrive signal generating block 300 generates an overdrive signal OVDP in response to a start command
-10- 1303440 ACT，該過驅動信號〇VDP界定一過驅動間隔。該VDD位 準偵測區塊400偵測該外部電源電壓VDD之電壓位準。該 選擇輸出區塊500使用該過驅動信號0VDP選擇性地輸出 一輸出信號0VDP_NEW以回應來自該VDD位準偵測區塊之 一偵測信號DET_VDD。藉由該選擇輸出區塊500之輸出信 號〇VDP_NEW控制該過驅動區塊600。 第4圖描述第3圖所述之VDD位準偵測區塊400及選 擇輸出區塊500的示範性電路圖。 t 該VDD位準偵測區塊400包括一位準隨從單元410及 一比較單元 420。該位準隨從單元 410輸出一信號 VDD一REF，該信號VDD一REF線性地相對於該外部電源電壓 VDD變化。該比較單元420比較該位準隨從單元410所輸 出之信號VDD_REF與一參考信號VREF。 該位準隨從單元4 1 0包括串接於該外部電源電壓端與 一接地電壓端間之第一及第二電阻器R1及R2。該位準隨 從單元410輸出該信號VDD —REF，該信號VDD_REF具有一 B 依據該第一電阻器R1對該第二電阻器R2之電阻比或反之 亦然所分割之電壓以做爲該對應電壓VDD_REF。例如：如 果該第一電阻器R1及該第二電阻器R2實質上具有相同電 阻，則該信號VDD_REF具有大約爲該外部電源電壓VDD 之1/2的電壓位準。 該比較單元420包括一偏壓N-型通道金屬氧化半導體 (NM0S)電晶體N3、第一及第二P·型通道m〇S(PM〇S)電晶 體P1及P2以及第一及第二輸入NM0S電晶體N1及N2。-10- 1303440 ACT, the overdrive signal 〇VDP defines an overdrive interval. The VDD level detection block 400 detects the voltage level of the external power supply voltage VDD. The selection output block 500 selectively outputs an output signal 0VDP_NEW using the overdrive signal 0VDP in response to a detection signal DET_VDD from the VDD level detection block. The overdrive block 600 is controlled by the output signal 〇VDP_NEW of the select output block 500. Figure 4 depicts an exemplary circuit diagram of VDD level detection block 400 and select output block 500 as described in Figure 3. The VDD level detection block 400 includes a bit compliant unit 410 and a comparison unit 420. The level follower unit 410 outputs a signal VDD_REF which varies linearly with respect to the external supply voltage VDD. The comparison unit 420 compares the signal VDD_REF output by the level following unit 410 with a reference signal VREF. The level following unit 4 1 0 includes first and second resistors R1 and R2 connected in series between the external power supply voltage terminal and a ground voltage terminal. The level following unit 410 outputs the signal VDD_REF, and the signal VDD_REF has a B divided according to the resistance ratio of the first resistor R1 to the second resistor R2 or vice versa as the corresponding voltage. VDD_REF. For example, if the first resistor R1 and the second resistor R2 have substantially the same resistance, the signal VDD_REF has a voltage level of approximately 1/2 of the external power supply voltage VDD. The comparing unit 420 includes a bias N-type channel metal oxide semiconductor (NMOS) transistor N3, first and second P-type channel m〇S (PM〇S) transistors P1 and P2, and first and second Input NM0S transistors N1 and N2.
-11- 1303440 該偏壓NMOS電晶體N3具有一接收一致能信號ENABLE之 閘極及耦接至該接地電壓端。該第一及第二PM0S電晶體 P1及P2耦接至該外部電源電壓端及因該第一及第二PM0S 電晶體P1及P2之閛極親接在一起而形成一電流鏡電路。 該第一輸入NM0S電晶體N1耦接於該第一 PM0S電晶體 P1與該偏壓NM0S電晶體N3之間，以及該第二輸入NM〇S 電晶體N2耦接於該第二PM0S電晶體P2與該偏壓NM0S 電晶體N3之間。該第一及第二PM0S電晶體P1及P2分別 B 接收該信號VDD_REF及該參考信號VREF。供應該致能信 號ENABLE以致能該比較單元420。該參考信號VREF具有 一固定電壓（例如：約該外部電源電壓VDD之1/2)而無關於 該外部電源電壓VDD之電壓位準的變化。可以由內部或外 部產生該參考電壓VREF。 該選擇輸出區塊500包括第一及第二反向器INV1及 INV2、一 NAND閘NAND1及一第三反向器INV3。該第一 及第二反向器IN VI及INV2串聯耦接及配置成用以緩衝該 ® 比較單元420所輸出之偵測信號DET_VDD。該NAND閘 NAND1接收該過驅動信號0VDP及該第二反向器INV2之輸 出信號B。該第三反向器INV3反向該NAND閘NAND1之 輸出信號及然後輸出該反向輸出信號做爲該選擇輸出區塊 5 00之輸出信號〇VDP_NEW。換句話說，該選擇輸出區塊 5 00實施該偵測信號DET_VDD及該過驅動信號〇VDP之邏 輯値的AND運算。 第5A及5B圖描述第4圖所述之信號的時序圖。 1303440 第5A圖描述當該外部電源電壓VDD爲低位準時之信 號的波形。該外部電源電壓VDD之電壓位準決定該信號 VDD_REF之電壓位準，以及因此，該外部電源電壓位準小 於該參考電壓位準。如果該信號VDD_REF之電壓位準小於 該信號VREF之電壓位準，則該比較單元420所輸出之偵 測信號DET_VDD處於高邏輯狀態。結果，該選擇輸出區塊 5 00之輸出信號〇VDP_NEW處於高邏輯狀態。因此，該外 部電源電壓VDD處於低位準，所以即使實施該位元線過驅 > 動操作，可穩定地維持該核心電壓VC ORE。 第5B描述當該外部電源電壓VDD處於高位準時之信 號的波形。該信號VDD_REF之電壓位準大於該參考信號 VREF之電壓位準。如果該信號VDD_REF之電壓位準大於 該參考信號VREF之電壓位準，則該比較單元420所輸出 之偵測信號DET_VDD處於低邏輯位準。結果，該選擇輸出 區塊500之輸出信號OVDP^NEW處於低邏輯狀態。亦即， 該輸出信號OVDP^NEW變成未啓動。該未啓動之結果爲： B 不實施該位元線過驅動操作；而實施一標準驅動操作。於 是，可減少該核心電壓VC ORE之電壓位準的過度增加，其 中該過度增加通常是因在該高外部電源電壓VDD之狀況下 實施過驅動操作所造成的。因此，可改善半導體記憶體裝 置之操作特性及可靠性。 當啓動該等輸入信號及輸出信號成爲高邏輯位準時， 上面實施例所述之邏輯型態及裝置佈局爲示範性實施。因 此，當改變該等信號之邏輯狀態時，亦改變該等所述實施。 -13- 1303440 因而’可允許許多其它實施方式。 在該位準隨從單元中所配置之電阻器可使用主動裝置 (例如：PMPS或NMOS電晶體）來取代。雖然實施依據該等 示範性實施例之選擇輸出單元以邏輯組合該偵測信號及該 過驅動信號’但是可實施例如使用一鎖存裝置及一傳輸閘 來允許該過驅動信號之選擇輸出的邏輯電路，以在該偵測 信號之控制下輸出該過驅動信號。 第6圖描述依據本發明之另一實施例的一 vdd位準偵 B 測區塊400B及一選擇輸出區塊500B之另一示範性電路圖。 該VDD位準偵測區塊400B包括一位準隨從單元401B 及一電壓位準偵測單元420B。該位準隨從單元401B係要 輸出一對應電壓VDD_REF，該對應電壓VDD_REF線性地 相對於一外部電源電壓VDD變化。該電壓位準偵測單元 420B係要偵測是否該過驅動電壓具有一大於一預定電壓位 準之電壓位準，以回應該位準隨從單元401B之對應電壓 VDD_REF。 ® 該位準隨從單元 40 1 B包括串接於該外部電源電壓 VDD端與一接地電壓VSS端間之第一及第二電阻器R3及 R4。該位準隨從單元401B經由該第一及第二電阻器R3及 R4間之共同節點輸出一電壓，其中該電壓係依據該第一電 阻器R3對該第二電阻器R4之電阻比或反之亦然分割所獲 得。此輸出電壓爲該對應電壓VDD_REF。例如：如果該第 一及第二電阻器R3及R4實質上具有相同電阻値，則該對 應電壓VDD_REF具有大約爲該外部電源電壓VDD之1/2-11- 1303440 The bias NMOS transistor N3 has a gate receiving the coincidence signal ENABLE and is coupled to the ground voltage terminal. The first and second PMOS transistors P1 and P2 are coupled to the external power supply voltage terminal and are connected to each other by the drains of the first and second PMOS transistors P1 and P2 to form a current mirror circuit. The first input NMOS transistor N1 is coupled between the first PMOS transistor P1 and the bias NMOS transistor N3, and the second input NM 〇S transistor N2 is coupled to the second PMOS transistor P2. Between the bias NM0S transistor N3. The first and second PMOS transistors P1 and P2 respectively receive the signal VDD_REF and the reference signal VREF. The enable signal ENABLE is supplied to enable the comparison unit 420. The reference signal VREF has a fixed voltage (e.g., about 1/2 of the external power supply voltage VDD) regardless of a change in the voltage level of the external power supply voltage VDD. This reference voltage VREF can be generated internally or externally. The selection output block 500 includes first and second inverters INV1 and INV2, a NAND gate NAND1, and a third inverter INV3. The first and second inverters IN VI and INV2 are coupled in series and configured to buffer the detection signal DET_VDD output by the comparison unit 420. The NAND gate NAND1 receives the overdrive signal 0VDP and the output signal B of the second inverter INV2. The third inverter INV3 reverses the output signal of the NAND gate NAND1 and then outputs the inverted output signal as the output signal 〇VDP_NEW of the selection output block 500. In other words, the selection output block 500 performs an AND operation of the detection signal DET_VDD and the logic 値 of the overdrive signal 〇VDP. Figures 5A and 5B depict timing diagrams of the signals described in Figure 4. 1303440 Figure 5A depicts the waveform of the signal when the external supply voltage VDD is low. The voltage level of the external supply voltage VDD determines the voltage level of the signal VDD_REF and, therefore, the external supply voltage level is less than the reference voltage level. If the voltage level of the signal VDD_REF is less than the voltage level of the signal VREF, the detection signal DET_VDD output by the comparison unit 420 is in a high logic state. As a result, the output signal 〇VDP_NEW of the selection output block 500 is in a high logic state. Therefore, the external power supply voltage VDD is at a low level, so even if the bit line overdrive > operation is performed, the core voltage VC ORE can be stably maintained. Section 5B describes the waveform of the signal when the external power supply voltage VDD is at a high level. The voltage level of the signal VDD_REF is greater than the voltage level of the reference signal VREF. If the voltage level of the signal VDD_REF is greater than the voltage level of the reference signal VREF, the detection signal DET_VDD output by the comparison unit 420 is at a low logic level. As a result, the output signal OVDP^NEW of the selection output block 500 is in a low logic state. That is, the output signal OVDP^NEW becomes unactivated. The result of this unstart is: B The bit line overdrive operation is not implemented; a standard drive operation is implemented. Thus, an excessive increase in the voltage level of the core voltage VC ORE can be reduced, which is usually caused by an overdrive operation under the condition of the high external power supply voltage VDD. Therefore, the operational characteristics and reliability of the semiconductor memory device can be improved. When the input signals and the output signals are activated to a high logic level, the logic patterns and device layouts described in the above embodiments are exemplary implementations. Therefore, the implementations are also changed when the logic states of the signals are changed. -13- 1303440 Thus many other embodiments are permitted. The resistors configured in the level follower unit can be replaced with active devices (e.g., PMPS or NMOS transistors). Although the selection output unit in accordance with the exemplary embodiments is implemented to logically combine the detection signal and the overdrive signal 'but logic such as using a latch device and a transfer gate to allow selection of the output of the overdrive signal can be implemented. a circuit for outputting the overdrive signal under the control of the detection signal. Figure 6 depicts another exemplary circuit diagram of a vdd level detection block 400B and a select output block 500B in accordance with another embodiment of the present invention. The VDD level detection block 400B includes a bit compliant unit 401B and a voltage level detecting unit 420B. The level follower unit 401B outputs a corresponding voltage VDD_REF which varies linearly with respect to an external power supply voltage VDD. The voltage level detecting unit 420B is configured to detect whether the overdrive voltage has a voltage level greater than a predetermined voltage level to correspond to the corresponding voltage VDD_REF of the level follower unit 401B. The level follower unit 40 1 B includes first and second resistors R3 and R4 connected in series between the external power supply voltage VDD terminal and a ground voltage VSS terminal. The level follower unit 401B outputs a voltage via a common node between the first and second resistors R3 and R4, wherein the voltage is based on the resistance ratio of the first resistor R3 to the second resistor R4 or vice versa. However, the segmentation is obtained. This output voltage is the corresponding voltage VDD_REF. For example, if the first and second resistors R3 and R4 have substantially the same resistance 値, the corresponding voltage VDD_REF has approximately 1/2 of the external power supply voltage VDD.
-14- •1303440 ' 的電壓位準。 該電壓位準偵測單元420B包括一 NMOS電晶體N4及 一 PMOS電晶體P3。該NMOS電晶體N4具有一被施加有該 對應電壓 VDD-REF之閘極及耦接至該接地電壓端。該 PMOS電晶體P3具有一被供應有該接地電壓之閘極及耦接 至該外部電源電壓VDD端。 該選擇輸出區塊500B包括一 NAND閘NAND2及一反 向器INV4。該NAND閘NAND2接收該電壓位準偵測單元 B 420B之輸出信號DET_VDD及一過驅動信號OVDP。該反向 器INV4反向該NAND閘NAND2之輸出信號及輸出該反向 信號成爲該選擇輸出區塊5 00B之輸出信號〇VDP_NEW。 第7A及7B圖描述第6圖所述之信號的時序圖。 第7A圖係當由於該外部電源電壓VDD之電壓位準非 常不同於一核心電壓之電壓位準而需要朝該電源電壓之過 驅動時的信號之波形。該過驅動信號OVDP具有該電源電 壓之電壓位準。如所述，該過驅動信號OVDP之電壓位準 ® 約爲1.6 V，以及此數値非常不同於該核心電壓之一般已知 電壓位準（亦即，約1.5V)。-14- • 1303440 ' voltage level. The voltage level detecting unit 420B includes an NMOS transistor N4 and a PMOS transistor P3. The NMOS transistor N4 has a gate to which the corresponding voltage VDD-REF is applied and is coupled to the ground voltage terminal. The PMOS transistor P3 has a gate to which the ground voltage is supplied and is coupled to the external power supply voltage VDD terminal. The select output block 500B includes a NAND gate NAND2 and a reverse INV4. The NAND gate NAND2 receives the output signal DET_VDD of the voltage level detecting unit B 420B and an overdrive signal OVDP. The inverter INV4 reverses the output signal of the NAND gate NAND2 and outputs the inverted signal to the output signal 〇VDP_NEW of the selection output block 500B. Figures 7A and 7B depict timing diagrams of the signals described in Figure 6. Fig. 7A is a waveform of a signal when it is necessary to drive over the power supply voltage because the voltage level of the external power supply voltage VDD is very different from the voltage level of a core voltage. The overdrive signal OVDP has a voltage level of the power supply voltage. As stated, the voltage level of the overdrive signal OVDP is about 1.6 V, and this number is very different from the generally known voltage level of the core voltage (i.e., about 1.5 V).
經由該位準隨從單元 401B 輸出該對應電壓 VDD_REF，以及然後將它輸出至該電位位準偵測單元 420B。因爲該電壓位準偵測單元420B之NMOS電晶體N4 因該NMOS電晶體N4之臨界電壓位準而無法導通，所以該 電壓位準偵測單元420B之輸出信號DET_VDD具有高邏輯 位準。結果，該選擇輸出區塊5 00B輸出該過驅動信號OVDP -15- .1303440 成爲該輸出信號OVDP_NEW。因此，實施一標準位元線過 驅動操作。因爲該外部電源電壓VDD係低位準，所以即使 實施該位元線過驅動操作，可穩定地維持該核心電壓之電 壓位準。 第7B圖係當因該電源電壓及該核心電壓彼此具有大 程度之不同電壓位準而不需朝該電源電壓之過驅動時的信 號之波形。該過驅動信號OVDP具有該外部電源電壓VDD 之電壓位準。例如：在此實施例中，該過驅動信號OVDP B 之電壓位準約爲2.2V，以及此電壓位準不同於該核心電壓 之一般已知電壓（亦即，約1.5V)。 該位準隨從單元401B輸出該對應電壓VDD_REF，隨 後將它輸入至該電壓位準偵測單元420B。因爲該對應電壓 VDD — REF具有一大於該NMOS電晶體N4之臨界電壓位準 的電壓位準，所以該NMOS電晶體N4導通。因此，該電壓 位準偵測單元420B之輸出信號DET_VDD具有一低邏輯位 準。結果，該選擇輸出區塊5 00B阻隔該過驅動信號OVDP， ® 藉以使該輸出信號〇VDP_NEW失能成爲一低邏輯位準。在 此情況中，跳過該位元線過驅動操作，以及取而代之，實 施一標準驅動操作。因此，該外部電源電壓VDD在該高電 壓位準下觸發該過驅動。結果，該核心電壓之電壓位準沒 有大程度的增加。 在上面示範性實施例中，該核心電壓VC ORE及該過驅 動電壓分別用以做爲一標準驅動電壓及一過驅動電壓。其 它型態之電壓亦可用於該標準驅動電壓及該過驅動電壓。The corresponding voltage VDD_REF is outputted via the level following unit 401B, and then output to the potential level detecting unit 420B. Because the NMOS transistor N4 of the voltage level detecting unit 420B cannot be turned on due to the threshold voltage level of the NMOS transistor N4, the output signal DET_VDD of the voltage level detecting unit 420B has a high logic level. As a result, the selection output block 5 00B outputs the overdrive signal OVDP -15 - .1303440 to become the output signal OVDP_NEW. Therefore, a standard bit line overdrive operation is implemented. Since the external power supply voltage VDD is at a low level, even if the bit line overdrive operation is performed, the voltage level of the core voltage can be stably maintained. Fig. 7B is a waveform of a signal when the power supply voltage and the core voltage have different voltage levels to each other without being driven over the power supply voltage. The overdrive signal OVDP has a voltage level of the external supply voltage VDD. For example, in this embodiment, the voltage level of the overdrive signal OVDP B is about 2.2V, and this voltage level is different from the generally known voltage of the core voltage (i.e., about 1.5V). The level follower unit 401B outputs the corresponding voltage VDD_REF, and then inputs it to the voltage level detecting unit 420B. Since the corresponding voltage VDD - REF has a voltage level greater than the threshold voltage level of the NMOS transistor N4, the NMOS transistor N4 is turned on. Therefore, the output signal DET_VDD of the voltage level detecting unit 420B has a low logic level. As a result, the select output block 500B blocks the overdrive signal OVDP, so that the output signal 〇VDP_NEW is disabled to a low logic level. In this case, the bit line overdrive operation is skipped and, instead, a standard drive operation is performed. Therefore, the external power supply voltage VDD triggers the overdrive at the high voltage level. As a result, the voltage level of the core voltage does not increase to a large extent. In the above exemplary embodiment, the core voltage VC ORE and the overdrive voltage are used as a standard driving voltage and an over driving voltage, respectively. Other types of voltages can also be used for the standard drive voltage and the overdrive voltage.
-16- (:'S 1303440 本申請案包含關於分別在2005年9月28日、2005年 9月29日、2005年12月28日及2005年12月28日向韓國 專利局所提出之韓國專利申請案第KR 2005 -0090837號、 第 2005-00909 1 1 號、第 2005-0 1 32504 號及第 2005 -0 1 325 86 號的標的’在此以提及方式倂入上述專利申請案之整個內 容。 雖然已以某些較佳實施例來描述本發明，但是熟習該 項技藝者將明顯易知在不脫離下面請求項所界定之本發明 ® 的精神及範圍內可以實施各種變化及修改。 【圖式簡單說明】 第1圖係一典型位元線感測放大器控制電路之簡化圖 式。 第2A至2C圖係依據一位元線感測放大器區塊之操作 狀況的一核心電壓端之電壓位準在時間上變化的曲線圖； 第3圖係依據本發明之一實施例的一根據一過驅動方 案操作之半導體記憶體裝置的簡化方塊圖； ® 第4圖係依據本發明之一實施例的一外部電源電壓位 準偵測區塊及一選擇輸出區塊之電路圖； 第5A及5B圖係第4圖所述之電路的時序圖； 第6圖係依據本發明之另一實施例的一外部電源電壓 位準偵測區塊及一選擇輸出區塊之簡化電路圖；以及 第7A及7B圖係第6圖所示之電路的時序圖。 【主要元件符號說明】 300 過驅動信號產生區塊 1303440 400 外部電源電壓（VDD)位準偵測區塊 400B VDD位準偵測區塊 401B 位準隨從單元 410 位準隨從單元 420 比較單元 420B 電壓位準偵測單元 500 選擇輸出區塊 500B 選擇輸出區塊 600 過驅動區塊 ACT 啓動指令 B 輸出信號 BLSA 位元線感測放大器區塊 DET_VDD 偵測信號 ENABLE 致能信號 INV1 第一反向器 INV2 第二反向器 INV3 第三反向器 INV4 第四反向器 Ml 驅動器電晶體 M2 驅動器電晶體 M3 驅動器電晶體 N1 第一輸入NMOS電晶體 N2 第二輸入NMOS電晶體 N3 偏壓N-型通道金屬氧化半導體（NMOS)電晶 -1303440 體 N4 NMOS電晶體 NANDI NAND 閘 NANDI NAND 閘 OVDP 過驅動信號 〇VDP_NEW 輸出信號 PI 第一 P-型通道MOS(PMOS)電晶體 P2 第二P-型通道MOS(PMOS)電晶體 P3 PM0S電晶體 R1 第一電阻器 R2 第二電阻器 R3 第一電阻器 R4 第二電阻器 RT〇 上拉電源線 SAN 下拉電源線驅動控制信號 SAP 上拉電源線驅動控制信號 SB 下拉電源線 VCORE 核心電壓 VDD 外部電源電壓 VDD_REF 信號 VREF 參考信號 接地電壓 vss-16- (:'S 1303440 This application contains Korean patents filed with the Korean Patent Office on September 28, 2005, September 29, 2005, December 28, 2005 and December 28, 2005, respectively. The subject matter of the above-mentioned patent application is hereby incorporated by reference in its entirety to the entire disclosure of the entire disclosures of The present invention has been described in terms of its preferred embodiments, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a simplified diagram of a typical bit line sense amplifier control circuit. Figures 2A to 2C are based on a core voltage terminal of the operating condition of a bit line sense amplifier block. A graph of voltage levels varying in time; FIG. 3 is a simplified block diagram of a semiconductor memory device operating in accordance with an overdrive scheme in accordance with an embodiment of the present invention; FIG. 4 is a diagram in accordance with the present invention An external power supply voltage of an embodiment a circuit diagram of a level detection block and a selection output block; 5A and 5B are timing diagrams of the circuit described in FIG. 4; and FIG. 6 is an external power supply voltage level according to another embodiment of the present invention. A simplified circuit diagram of the quasi-detection block and a selected output block; and a timing diagram of the circuit shown in Figure 7A and 7B. Figure 6. Description of the main component symbols 300 Overdrive signal generation block 1303440 400 External power supply Voltage (VDD) level detection block 400B VDD level detection block 401B level follower unit 410 level follower unit 420 comparison unit 420B voltage level detection unit 500 select output block 500B select output block 600 Drive block ACT start command B output signal BLSA bit line sense amplifier block DET_VDD detection signal ENABLE enable signal INV1 first inverter INV2 second inverter INV3 third inverter INV4 fourth inverter Ml driver transistor M2 driver transistor M3 driver transistor N1 first input NMOS transistor N2 second input NMOS transistor N3 bias N-channel metal oxide semiconductor (NMOS ) 晶晶-1303440 Body N4 NMOS transistor NANDI NAND gate NANDI NAND gate OVDP overdrive signal 〇VDP_NEW output signal PI first P-channel MOS (PMOS) transistor P2 second P-channel MOS (PMOS) transistor P3 PM0S transistor R1 first resistor R2 second resistor R3 first resistor R4 second resistor RT〇 pull-up power line SAN pull-down power line drive control signal SAP pull-up power line drive control signal SB pull-down power line VCORE Core Voltage VDD External Supply Voltage VDD_REF Signal VREF Reference Signal Ground Voltage vss