TWI302741B - Nand type non-volatile memory and manufacturing method and operstion method thereof - Google Patents

Description

1302741 19618twf.doc/g IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor element, and more particularly to a non-swing (NAND) type non-swing memory and its manufacturing Method and method of operation. [Prior Art] * Non-volatile memory components have become an individual because they have the ability to perform multiple data deposits, continuation, erasure, etc., and the stored data does not disappear after power-off. A memory component widely used in computers and electronic devices. Typical non-volatile memory components are typically designed to have a Stacked-Gate structure, including doped polycrystalline spine The floating gate and the control gate (c〇ntr〇1 shirt). The floating gate is located between the control pole and the base, and the floating (4) is not connected with any circuit, and the control _ The Wwd Une is connected, and the TunneHng 〇xide and the Age Dielectric Layer are located between the substrate and the floating interpole and the floating gate. Between the pole and the control gate. Another flash memory array that is commonly used in the industry includes an anti- or inter-NOR array structure and an anti-free (na rib) array structure. The non-volatile memory structure of the NAND type array is to make each record From the beginning, the non-volatile memory with better integration and area ratio than the (N) (N) column has been widely used in many electronic products. 1302741 19618twf.doc/g Figure 1 is shown as A cross-sectional view of a conventional non-volatile memory structure is shown in Fig. 1. As shown in Fig. 1, a plurality of memory cells M1 to M8 and two selection transistors ST1 and ST2 are disposed on a substrate 100. Memory cells M1~ M8 is disposed between the two selection transistors STb, ST2, in the substrate 100 between the memory cells M1 to M8i, in the substrate 100 between the memory cell M1 and the selection transistor ST1, and between the memory cell M8 and the selection transistor ST2. A doped region 102 is formed in the substrate 1 . The memory cells M1 to VI8 and the selective transistors ST1 and ST2 are connected in series via the doping region 102 to form a memory cell row. The source region 104 and the drain region 1〇6. The source line SL is electrically connected to the source region 1〇4. The bit line BL is electrically connected to the drain region 106 through the plug 1〇8. In the NAND type non-volatile memory, since the memory cells M1 to M8 are connected together by the doping region 102. In the case of continuous shrinking, the memory cell width is getting smaller and smaller, and there are problems such as short channel effect and Drain hduad Barrier Lowering (DIBL) effect between 1捧2 in the adjacent holding area. In addition, for the NAND type non-volatile memory described above, when the selected memory cell is privately selected, other unselected memory cells in the same memory cell are transmitted. Gate. Therefore, when programming, you need to select the memory cell to be completely paralyzed. To make the surface of the memory cell: the bias voltage in the * fully on state will limit the starting voltage range of the memory cell. For example, when the memory cell is a single-order memory cell, the reference reading power 1302741 19618twf .doc/g to discriminate between two different starting voltages (Vthl voltage Vref vthi < vrefi < Vth2. Vthl is less than 〇Vat; Vrefl is around 〇Vt' Itth2 is greater than 0 volts. When unselected memory cells are fully open When the bias voltage is 5 volts, then vth2 can only be set to 〇1 and 5 volts, and the range of Vth2 is small. ## When the memory cell is a multi-order memory cell, the voltage is read by the reference Vi. *efl, Vl*ef2, Vref3, come _ four different starting voltages (VtM, Vth2, νω, _4), νώι<νππ<νώ2<νΓεί2<νώ3<νΓεβ<·4. Similarly, when non-selected memory cells When the bias voltage is 5 volts in the fully open state, it is less than 〇VV; Vrefl is about 〇VV; and the boots 3, Vref3, Vth4 need to be set at οV and 5 volts, especially, v(4) is uV, and vth3 is: ==2.4 volts, Vth4 is 2.8~3 Wei

The range of It, I: is better than *. So, in the conventional job type D non-swing

St. Qing: In order to make the stylized memory cell accurate, it will take a long time. Moreover, in the case of a read operation, other non-selected records in the same-memory cell column cause read disturb to the selected memory cell. ~ [Description of the Invention] The object of the present invention is to provide a nand memory; the money-making method, another purpose of the present invention is to provide a kind of nand memory and its manufacturing method and operation method, which can be easily Together with === 1302741 19618twf.doc/g, you can increase the process margin. It is still another object of the present invention to provide a NAND type non-volatile memory, a method of fabricating the same, and a method of operating the same, which can widen the set start voltage range of the memory cell and shorten the stylized time of the memory cell. The present invention provides an anti-gate type non-volatile memory, and the inverse type non-volatile memory includes a plurality of memory cell rows. Each memory cell row includes a source region and a drain region, a plurality of memory cells, a plurality of transmission gates, a first remote selection transistor, and a second selection transistor. The source region and the bungee region are arranged; the plurality of suffix units in the base are disposed between the source region and the non-polar region, and upper, ', each memory unit includes a memory cell and a transistor, and the memory cell and Electro-crystal, 5 connected together. Multiple _ transmission gates are set in adjacent two! On the substrate between the cells, the memory cells are connected in series, and the second π-plane transistor and the second selection transistor are respectively connected to the outermost two solid memories, and are respectively connected to the source region and the secret region. adjacent. Recalling layer The anti-gate type non-volatile memory described in the preferred embodiment of the present invention fills the gap between adjacent memory cells. The anti-gate type non-volatile memory described in the preferred embodiment of the present invention includes at least a dielectric layer and a control gate from the dielectric ft layer. The material of the layer includes oxidized hair. Bay is reduced by more (four). The above-mentioned wear-through dielectric is preferably a reverse-type non-volatile type 1302741 196l8 twf.doc/g body as described in the preferred embodiment of the present invention, and further includes a plurality of element isolation structures. A plurality of element isolation gentleman structures are arranged in parallel in the substrate, and each memory cell row is disposed between adjacent two element structures. The surface of the element isolation structure is lower than the interface between the charge storage layer and the substrate to form a depressed portion, and the control gate fills the recess. An anti-gate type non-volatile memory body according to a preferred embodiment of the present invention further includes a gate dielectric layer. The gate dielectric layer is disposed between the control gate and the substrate, and each of the electro-crystalline systems is controlled by a gate, a gate dielectric layer, and the substrate is reversed and gated according to a preferred embodiment of the present invention. The memory unit of the above-mentioned memory unit is arranged in two dimensions to form a memory cell array. The gate-type forward memory further includes a plurality of word lines, a plurality of bit lines, a plurality of source lines, a plurality of selected gate lines, and a plurality of transmission gate lines. Most of the word lines are arranged in parallel in the column direction, and are connected to the (4) gate of the memory cell of the same column and the gate of f (4). Most of the bit lines are arranged in parallel in the row direction, and the branching line is connected to the bungee area of the row of memory cells. A plurality of source lines are arranged in parallel in the column direction, and are respectively connected to the source regions of the memory cell rows of the same column. The plurality of selected gate lines are arranged in parallel in the column direction, and the gates of the first selected transistor and the gate of the second selected transistor are connected to the memory cell row of the same column. A plurality of transmission gate lines are arranged in parallel in the column direction to divide the transmission gates of the memory cell rows of the same column. The anti-gate type non-volatile memory described in the preferred embodiment of the present invention includes a plurality of element isolation structures. The component isolation structures are disposed in the 氐Dushe and are arranged in parallel in the 仃 direction, and the memory cell rows are disposed between the adjacent structures. The surface of the element isolation structure is lower than the interface between the person bases f of the charge storage layer to form a depressed portion, and the control gate fills the depressed portion. According to the preferred embodiment of the present invention, the anti-valve type non-volatile record! 3〇2741 19618twf.doc/g think - enter 0 pay old "_... hundred ▽ > U / r " The electricity is placed between the control gates and the substrate, and each transistor is composed of a control gate, a gate dielectric layer and a substrate. In the above-mentioned anti-gate type non-volatile memory, since the surface of the element isolation structure is lower than the interface between the charge storage layer and the substrate, a trap portion is formed, and electricity connected in parallel with the memory cell is disposed in the recess portion. Crystal. The setting of this transistor will help the operation of the memory unit, shorten the stylized operation time and avoid reading interference. ", and, in the above-mentioned anti-gate type non-volatile memory, since the transmission gate is provided between the records, and the doping region is not required, the short channel effect and the bungee are avoided. The energy can be reduced by the effect, etc. = leakage current. In addition, the volume between the transfer units disposed between the memory units can shield the charge storage layer of the adjacent two memory cells from interfering with the memory cells. This is not the same as the transmission gate set between ^ and the gate type non-volatile memory. In the non-volatile _: J line erase operation of the present invention, electrons can be removed from the charge storage layer through the inter-gate:: subtractor. Because of this, the life of the 4 layers of the erase method, and the second = can therefore improve the wear and tear dielectric t - the invention and the non-swipe, including the following steps. First, the 7-layer fabric has a first-channel Μ Μ k k-substrate'. The substrate has been sequentially guided (4), the electric layer, the di-conductor layer and the second dielectric layer. A plurality of strip-shaped conductor layers arranged in parallel in the first and second parallel patterns are patterned, and the two strip-shaped conductor layers extend in the first direction. In these first-strip guides: 1302741 19618twf.doc/g extends to a number of ditches. Then, a plurality of isolation structures are formed in the trenches in the substrate, and the surface is low: the interface between the first strip conductor layer and the substrate is opened. After exposing a portion of the surface dielectric layer of the substrate, a filled recess is formed on the substrate to form a second conductor layer, a second dielectric layer, and a strip-shaped conductor layer, wherein the second conductor layer is patterned. Directions "Many second strip conductor layers of Newpin. Thereafter, a plurality of third strip conductor layers are formed on the side soils between the stacked gate structures and the outermost two stacked gate structures. The inverse and closed type non-volatile memory described in the t-dimensional example forms a plurality of floating = after the strip-shaped conductor layer. The material of the floating gate includes doped polysilicon. The anti- and non-volatile non-volatile materials described in the preferred embodiment include the oxidized stone. i The material of the second body layer comprises doped polycrystalline (tetra) multi-sanded metal 1 of the above second dielectric layer including oxygen cut/nitrite stone, the anti-gate type non-volatile as described in the embodiment The character LI U = method, the step of forming an isolation structure in the trench in the substrate, forming an insulating layer on the insulating layer and then removing a portion of the insulating layer so that the surface of the edge layer is lower than the surface of the substrate. Oxidation process. On the first brother, the formation method of the electric layer includes heat 12 1302741 19618twf.doc/g memory: the anti-free and non-volatile layer described in the example forms an inter-insulation between the non-volatile layers and The third strip conductor recalls the opposite and the gate type non-volatile record constitutes an anti-and closed-type non-volatile record as described in the three-dielectric layer of the transistor and the second strip-shaped conductor layer. The strip conductor is located on the side of the third structure between the adjacent two stacked idler structures, and the second stack gate junction X# t L conductor layer is formed as the selected lake H strip conductor layer The material shell includes doped polysilicon. The anti-free and non-volatile recording method described in the preferred embodiment of the invention further comprises forming a source region and a drain region in the substrate. In the method for manufacturing a non-volatile memory, the recessed portion is formed because the element adjacent surface is lower than the surface of the substrate, and the electric layer formed by the recessed electric layer and a portion of the second strip-shaped conductor layer The crystal body is connected in parallel with the memory cell. The formation of this transistor is the operation of the Wei body, which can shorten the stylized operation and avoid reading interference. Moreover, in the above-described method for manufacturing a non-volatile memory, since a third strip conductor layer (transmission idler) is formed between the stacked idler structures, the short channel effect and the infinitely induced energy band can be avoided. Reduce the memory leakage current and so on. In addition, a third strip conductor layer is formed between the stacked gate structures (transmission 13 1302741 19618twf.doc/g = ^^_ layer (transmission_ can shield adjacent sub-gates of ==, and can reduce memory cells) Between the memory cells and the 'field in the above-mentioned reverse-type non-volatile memory, between the stacking gate structure is open #彡-^ pole. In the recovery == dielectric layer injection The third strip of conductor layer is placed in the J because of 'this erasing method can reduce the electron crossing the number of wear and tear', so the life of the dielectric layer can be increased and increased. The above-mentioned anti-gate type non-volatile memory The manufacturing method can be integrated with the general process, and can increase the process margin. This (4) proposes that the operation of the non-volatile memory is applicable to a memory array including a plurality of memory cell rows. Each memory is disposed on the substrate as long as it has a plurality of memory cells disposed between the source region and the non-polar region, and each of the memory cells includes a memory cell and a transistor connected in parallel; and a plurality of transmission gates , set on the substrate between the memory cells, so that The 丨 单元 cells are connected in series; the first selection transistor f is the second selection transistor ′ respectively connected to the outermost two memory cells, and the first: the selection transistor is adjacent to the drain region, and the second selection transistor Contrary to the source region, the plurality of digital elements are arranged in parallel in the column direction, and are respectively connected to the control gates of the memory cells of the same column and the gates of the transistors; the plurality of source lines are respectively connected to the source regions of the same column; The plurality of bit lines are arranged in parallel in the row direction and are respectively connected to the drain regions of the same row; the plurality of first selected gate lines are arranged in parallel in the column direction, respectively connecting the first row of the memory cells of the same column 14 1302741 The gate of the electrification crystal; the plurality of first selection gate lines are arranged in parallel in the column direction, respectively connected to the gates of the second selection transistor of the memory cell row of the same column; the plurality of transmission gate lines are in the column direction Parallel arrangement, respectively connecting the transmission gates of the memory cells of the same column. The operation method of the non-volatile grammatical body of the gate type includes: programming and operating the memory cells of the selected memory unit Applying a first voltage to a bit line coupled to the selected memory cell, applying a second voltage to the unselected bit line, applying a third voltage to the first selected gate line _, coupled to the selected memory cell A fourth voltage is applied to the word line, a fifth voltage is applied to the unselected word line, and a sixth voltage is applied to all of the pass gate lines to utilize the channel Fowier-Nordheim (FN) tooth to effect the private operation. The voltage of the fourth voltage and the first electrical thickness can induce a FN tunneling effect, the third voltage is greater than or equal to the starting voltage of the first selected transistor, and the second voltage can suppress the non-selected memory. The first-select transistor of the cell row is turned on, the fifth voltage is greater than or equal to the start voltage of the transistor, and the sixth voltage is such that the channel under the transfer gate is turned on.

In accordance with a preferred embodiment of the present invention, the operation method of the non-volatile memory of the gate type is selected, and the memory of the remote memory unit is selected and selected by the selected memory unit. Cell read operation

The tenth electric 1302741 19618twf.doc/g is applied to the word line coupled to the fe unit, and the second voltage is applied to the non-transmission line, and the twelfth voltage is applied to all the transmission lines to read a selected memory cell, wherein the eighth voltage is greater than or equal to a starting voltage of the first selected transistor, the ninth voltage is greater than ^. equal to the starting voltage of the second selected transistor, and the eleventh voltage is greater than or equal to the second transistor The starting voltage, and the twelfth voltage can make the channel below the transmission gate/channel. In accordance with a preferred embodiment of the present invention, the anti-gate type non-volatile - • memory method of operation, the seventh voltage is about 1.5 volts; the eighth voltage is about 5 volts; the ninth voltage is 5 volts. Left and right; the tenth voltage is about volts; the eleventh voltage is about 5 volts; the twelfth voltage is 5 volts ^ right. According to a preferred embodiment of the preferred embodiment of the present invention, a method for fabricating a non-volatile gate type is applied to a memory cell of a memory cell, and a thirteenth is applied to all of the transmission gate lines. The voltage causes the substrate to float to erase the memory cells by the FN tunneling effect, wherein the voltage difference between the thirteenth voltage and the base can induce an F_N tunneling effect. According to a preferred embodiment of the present invention, the thirteenth voltage is about 15 volts in accordance with the operation method of the gate type non-volatile memory. In the above-described method for manufacturing a gate-type non-volatile memory, since each memory cell is composed of one transistor arranged in parallel and one memory cell, even if the voltage applied to the word line is not selected, • Open the channel of the memory cell, but as long as this voltage can open the channel of the transistor, the current can pass and reach the selected memory unit. Therefore, during the stylization operation, since the current can be turned on by the transistor, the setting of the memory cell start 16 1302741 19618 twf.doc/g is not biased by the non-selected memory cell in the fully-on state. The limitation of the memory cell is that the starting voltage range of the memory cell is wide, so that the number of steps and steps of the stylization can be reduced, and the time for the stylized operation can be shortened. Moreover, when 17 is purchased, it is not interfered by the memory cells sharing the same line. The transmission gate is arranged between the memory cells to avoid the memory leakage current caused by the short channel effect and the band-reduction effect caused by the drain. In addition, in the above-described method for manufacturing a gate-type non-volatile memory, channel FN tunneling is used to cause electrons to be injected into the charge storage layer through the tunnel through the tunnel dielectric layer to perform memory cell. Stylized operation; and FN tunneling effect is used to inject electrons from the charge storage layer through the inter-gate dielectric layer into the transfer gate for memory cell erase operation. Since this mode of operation reduces the number of times electrons pass through the tunneling dielectric layer, the lifetime of the tunneling dielectric layer can be increased and the reliability of the component can be increased. The above and other objects, features and advantages of the present invention will become more <RTIgt; '' σ [Embodiment] FIG. 2 is a circuit diagram showing a NAND (anti-gate) type non-volatile memory array of the present invention. In the present embodiment, a description will be given of an example of the behavior of a NAND memory cell in which eight memory cells are one line and three lines in total. Referring to FIG. 2, the NAND (non-gate) type non-volatile memory array includes a plurality of selection transistors ST11 to ST31 and ST12 to ST32, a plurality of 17 1302741 19618 twf.doc/g memory cells Q11 to Q38, and a plurality of words. The source lines WL1 WL WL8, the selection gate lines SG1 and SG2, the bit lines BL1 BLBL3 and the pass gate lines PL1 ～ PL7 〇 • the memory cells Q11 ～ Q18 are connected in series to the selection transistor stii and selected. Selecting between the transistors ST12 and forming the memory cells in the row direction MR memory cells Q21~Q28 are connected in series between the selective transistor anode and the selection transistor ST22, and form a memory cell in the row direction; MR2. The memory cells Q31~Q38 are connected in series between the selection transistor ST31 and the selection transistor ST32, and form a memory cell in the direction of the line. MR3 〇 Lu yiyi units Q11~Q38 are respectively composed of memory cells Mn~M38 and transistor T11 The structure of ~T38, the memory cells M11~M38 are connected in parallel with the transistors τη~T38. For example, the memory cell Qn is composed of the cell M and the transistor T11, and the memory cell M11 and the transistor τιι are connected in parallel; the memory cell Q12 is composed of the memory cell group 2 and the electric day and day body T12. And the memory cell M12 is connected in parallel with the transistor T12; and so on, the memory cell Q38 is composed of the memory cell 38 and the transistor Τ38, and the memory cell is connected to the transistor Τ3. The plurality of digital element lines WL1 WL WL8 are arranged in parallel in the column direction, and are connected to the gate of the control column of the same column and the gate of the transistor. For example, the control gates of the memory cells M11~Μ31 and the gates of the transistors T11~T31 are coupled to the corresponding word line WL1; the gates of the memory cells M12~M32 and the transistor T12~ The gate of T32 is coupled to the corresponding word line 18 1302741 19618twf.doc/g WL2 ·. 'And so on, the gate of the control cell crystal T18~T38 of the memory cell ~ M38 is coupled to the gate Corresponding character line wy selects the transistor ST11~ST31^, and the crystal is as follows: :;^ BL1~. Select the gate technique of the transistors ST12 to ST32 = the closed line SG2. The source line SL of the transistors ST12 to ST32 is selected. In the same line: the poles are arranged between the adjacent two memory cells, that is, the two-two-question poles are formed between the memory cells 7° Q11 and Q18, and the cells Q21 to Q28 are respectively formed with each other. The dry two-pole 'memory single 7G Q31 to Q38 are respectively formed with gates = the majority of the transmission gate lines PL1 to PL7 are arranged in parallel in the column direction, and the transmission gates of the two columns are arranged. That is, between the memory units Q11 to Q31 and the memory (10) to Q32, the transmission between the closed memory units (10) to Q32 and the memory sheets Q13 to Q33 is reduced to the corresponding transmission. Miscellaneous line PL2; according to this record:: QH~Q transmission unit Q18~Q38 between the transmission idle pole:: corresponding transmission gate line PL7. In the above embodiment, the eight memory cells are connected in series to illustrate. Of course, in the present invention, the serially connected memory sheets can be connected in an appropriate number according to actual needs. For example, the same line can be connected in series with 32 to 64 memory units. / 卞 70 Figure 3A shows the intention of stylizing memory cells. Figure 3B illustrates the memory cell for a read operation - not intended. @ 3C is a schematic diagram of an example of the erasure of all memory cells 19 1302741 19618twf.doc/g. Next, the NAND (reverse and gate) type non-volatile memory W歹(4)_ mode of the present invention will be described, which includes stylization, erasing, and data reading. In the case of the method of operation of the non-volatile memory of the present invention, only a preferred embodiment is provided below as an illustration. However, the method for knowing non-volatile and antimony of the present invention is not limited to these methods. In the following description, the memory unit Q22 of Fig. 2 will be described as an example. Γ It Photo 2 and FIG. 3A, when the memory cell Q22 in the selected memory cell row MR2 is programmed, the voltage Vpl is applied to the selected bit line BL2. A voltage Vp2 is applied to the unselected bit lines BL1, BL3. A voltage Vp3 is applied to the selection gate line SG1. A voltage Vp4 is applied to the selection gate line SG2. The voltage Vp5 is applied to the word line yL2 subtracted from the selected memory list $(10). The unselected word line wli, ~ 士 铋 voltage Vp6. A voltage Vp7' is applied to all of the transmission gate lines pu to pL7 to program the memory cell M22 of the selected memory cell Q22 by the channel F-N tunneling effect. ★,, because the voltage difference between voltage Vp5 and voltage Vpl needs to be sufficient to induce F_N tunneling effect, so the voltage difference between Vp5 and voltage Vpl needs to be about 12~20 volts. In the present example, the voltage Vp5 is, for example, about 2 volts, and the voltage Vpl is, for example, about volts. Since the selection transistor ST21 needs to be in an on state, the voltage Vp3 is equal to or equal to the starting voltage of the selection transistor 21. In the present example, the voltage Vp3 is, for example, about 5 volts. Since the selection transistor ST22 needs to be turned off, the voltage Vp4 needs to be smaller than the 20 1302741 19618 twf.doc/g starting voltage of the selection transistor ST22. In the present example, the voltage Vp4 is, for example, about 〇Vot. Moreover, in order to avoid stylized interference of other unselected memory cells Q12 to Q32 sharing the word line WL2, voltage VP2 may be applied to other non-selected positioning cells. The voltage Vp2 needs to suppress the non-selected memory cell rows MR1, MR3 select transistors STn, ST31 are turned on, so the voltage • VP2 needs to be greater than or equal to the start voltage of the selected transistor ST1 and ST31. In this example, the voltage VP2 is, for example, about 5 volts. Of course, the voltage difference between the # voltage Vp5 and the voltage VP2 is not sufficient to induce the F-N tunneling effect, and the voltage Vp2 is, for example, about 1 volt. Because the product is to make the channel of other non-selected memory cells Q2 Q23~Q28 (including memory cell 2] [, Μ23~Μ28 or transistor Τ21, Τ23~Τ28) in the cell line MR2 is turned on ( The unselected memory cells Q21, Q23~Q28 are all used as pass gates. Therefore, the voltages Vp6 to J need to be greater than or equal to the starting voltages of the transistors T11 to T38, and even greater than or equal to the starting voltages of the memory cells M21, M23 to M28. In this example, • the voltage VP6 is, for example, about 10 volts. Voltage Vp7 turns on the channel below the transmission gate. In the present example, the voltage Vp7 is, for example, about 5 volts. Under the above bias condition, a large electric field can be established between the floating gate of the selected memory cell M22 and the substrate, and the channel FN tunneling can be used to inject electrons from the channel into the charge storage layer. in.

Y When the above stylized operation is performed, the memory cells Q12 and Q32 sharing the same word line WL2 are not programmed. This is because the voltage of 5 volts is applied to the unselected locating elements BL1 and BL3, so the transistor ST11, 21 1302741 19618 twf.doc/g ST3^I tunneling phenomenon is selected, and of course, the memory cells Q12 and Q32 are not programmed. Moreover, since a voltage of 10 volts is applied to the unselected word lines WL1, WL3 to (4) 'this voltage is only used to open the channel of the memory cell, and is not sufficient to cause the channel FN phenomenon, the unselected word line, WL3 WL WL8 Connected memory cells qU~(9), ie % 4

~Q38 will not be stylized. Q

In addition, since the memory cells Qn to Q38 of the present invention are respectively composed of a plurality of transistors T11 to T38 arranged in parallel and one memory cell Mu~M38, the starting voltages of the transistors T11 to T38 are lower than the memory cells. The starting voltage of Mil~Μ38, so even if the voltage applied on the unselected word lines WL1, WL3~WL8 cannot open the channel of the memory cell, as long as this voltage can open the channel of the transistor, the current can pass and reach Select the memory unit. Therefore, during the stylization operation, since the current can be turned on by the transistors T11 to T38, the setting of the memory cell starting voltage range is not limited by the bias voltage for the unselected memory cells to be fully turned on, so that the memory Since the cell Mil~M38 has a wide starting voltage range, it can reduce the number of steps and steps of stylization confirmation, and can shorten the time of stylized operation. For example, when the memory cell is a single-order memory cell, two different threshold voltages (Vth1, Vth2), Vthl &lt; Vrefl &lt; Vth2, are discriminated by the reference reading voltage Vref. Vthl is less than 0 volts; Vrefl is about volts; Vth2 is greater than about volts. When 22 1302741 19618twf.doc/g is not fully selected, the bias voltage of the non-selected memory cell is 5 volts, and V 2 can also be set to be greater than 5 volts, making Vth2 wide. When the memory cell is a multi-order memory cell, the four readings are made by reading the electric V-, and the first two are: V〇ltage) (Vthl, Vth2, Vth3, VtM), Vthl&lt;Vrefl&lt;Vth2&lt;Vref2&lt;;Vth3&lt;Vref3&lt;Vth4. Similarly, when the unselected memory cell is in the fully open state, the bias voltage is 5 volts, 7 is less than the 〇f, which is about 〇VV; the 〇^2 volt is Vref2 is 2.2 volts, Vth3 is 2.4 to 4 volts, and Vref3 is 4 4 volts, Vth4 is 4.6 ~ 6.4 volts; and the range of vth2, Vth3, m is larger. In the above description, although the single memory of the memory device array is programmed in a unit of memory, the NAND (anti-gate) type non-volatile character _ is programmed by each character. The line, the selection of the polar line, and the control of the bit TL line are programmed in units of bytes, sections, or blocks. ^ Simultaneously, as shown in Figure 2 and Figure 3B, when the selected memory cell row is MR2. The unit Q22 performs a read operation, and the selected bit line is red and privately pressed Vrl. Voltage is applied to unselected bits, lines BU, and BL3. A voltage Vr3 is applied to the gate and the line SG1. Select gate line SG2: force [Vr4. It is known to power up M Vr5 on the character line of the selected memory list a (10). The unselected word lines WL1, WL3 WL WL8 ^ apply voltage Vr6 ° to apply power [Vl7 ' to all of the transfer gate lines PL1 to PL7 to obtain the memory cell M22 of the selected memory cell Q22. 23 1302741 19618twf.d〇c/g The voltage Vrl is the read bias applied to the selected bit line BL2. In the present example, the voltage Vrl is, for example, about L5 volts. The voltage Vr2 is, for example, about 〇Vot. Since the selection transistor ST21 and the selection transistor ST22 need to be in an on state, the voltages Vr3 and Vr4 need to be greater than or equal to the starting voltages of the selection transistor ST21 and the selection transistor ST22. In the present example, the voltage Vr3 and the voltage vr4 are, for example, about 5 volts. Because the channels of other unselected memory cells Q2 Q23~Q28 (including memory cells M21, M23~M28 or transistors T21, T23~T28) in the memory cell row MR2 need to be turned on (non-selected memory cells) Q21, Q23~Q28 are all used as gates. Therefore, the voltage vr6 needs to be greater than or equal to the starting voltage of the transistors T11 to D38. In the present example, the voltage Vr6 is, for example, about 5 volts. Voltage Vr7 turns the channel below the transmission gate on. In the present example, the voltage Vr7 is, for example, about 5 volts. In the above bias condition, the digital information stored in the memory cell can be judged by detecting the channel current of the memory cell. Moreover, since the memory cells Q11 to Q38 of the present invention are respectively composed of one transistor T11 to T38 arranged in parallel and one memory cell Mil to M38, the starting voltages of the transistors T11 to T38 are lower than the memory cell Mil~ The starting voltage of M38, therefore, even if the voltage applied to the unselected word lines WL1, WL3 WL WL8 cannot open the channel of the memory cell, as long as this voltage can open the channel of the transistor, the current can be passed. Therefore, when the selected memory cell Q22 is read, it is not interfered by the memory cells Q21, Q23 to Q28 sharing the same bit line BL2. 24 1302741 19618twf.doc/g In addition, between the memory cells of the present invention, the conventional doped regions are replaced by transmission gates, thereby avoiding short channel effects and buckoo-induced energy band reduction (Drain Induced Barrier Lowering) , DIBL) effect, etc. caused by memory leakage current. Moreover, in the above description, although the reading operation is performed in units of a single memory element in the memory element array, the reading operation of the NAND (inverse gate) type flash memory cell array of the present invention can also be performed by each character. The control of the line, the selection gate line, and the bit line, and reading the bit group, the section positive, or the block is the poor material of the early position. Next, the eraser of the NAND (anti-gate) type non-volatile memory array of the present invention will be described. The erasing method of the present invention is an example of erasing the entire nand (non-gate) type non-volatile memory array. Referring to FIG. 2 and FIG. 3C simultaneously, when the memory cell array is erased, a bias voltage source source, a word line WL1 WL WL8, and a bit line yang ~bu are applied to all of the transmission gate lines PL1 to PL7. And select closed;,,, SG1 ~ SG2 and the base is floating. Therefore, it is sufficient to establish between the transmission gate and the substrate - a large (four) ::: can be used to separate the N Tu charge by the FN tunneling effect: and (anti-gate) type non-volatile Memory: Divide by transmission _ (four) 彳, ring ==== 25 1302741 19618twf.doc/g. For example, if the corpse is chosen to be applied to the transmission gate line PL1, a bias voltage Vel, Bay z, is applied. The data in _Mll~M3 memory cells M12~M32 will be erased. That is, the data in the two columns of memory cells sharing the gate line of one pass will be erased. In addition. The present invention uses the channel F_N tunneling effect (FN Tunneling) to perform the Ναν〇 (reverse and ask) type non-volatile memory. In the layer, the stylized operation of the cell is carried out; and the F_N tunneling effect is used to inject electrons from the charge storage layer through the transmission layer to perform the cell erase operation. Since the operation of the present invention = 4 reduces the number of times the electrons cross the tunneling dielectric layer, the life of the electrical layer can be increased and the reliability of the component can be increased. Further, since the channel f_n wear-through effect with high electron injection efficiency is utilized in the %-formation operation, the memory cell current can be lowered and the operation speed can be improved. In addition, since the stylization and erasing actions utilize the F-N f tunneling effect, the current consumption is small, which can effectively reduce the power loss of the entire memory component. 4A is a top plan view of a reverse gate non-volatile steep memory in accordance with a preferred embodiment of the present invention. Fig. 4B is a cross-sectional view showing the structure taken along line A_A of Fig. 4A. 4C is a cross-sectional view showing the structure taken along line B_B of FIG. 4A. Referring to FIG. 4A to FIG. 4C, the anti-gate type non-volatile memory of the present invention includes a plurality of memory cell rows]y[R1~MR氕Mem()ry R〇w), and a plurality of word lines. WL1 to WL8, a plurality of bit lines BL1 to BL4, a plurality of source lines SL1, a plurality of transmission gate lines pL1 to pL7, and a plurality of strip selection gate lines SG and SG2. 26 1302741 19618twf.doc/g A plurality of memory cell rows MR1 to MR4 are arranged, for example, in row/column array A. In the present embodiment, only the memory cell array composed of four memory cell rows MR1 to MR4 is shown. However, the anti-gate type non-volatile body of the present invention is composed of, for example, a plurality of arrays A, and adjacent arrays A are arranged, for example, in a mirror-direction manner in the row direction (X direction). The adjacent two arrays A share the source line SL and the bit lines BL1 BLBL4. A plurality of memory cell rows MR 1 to MR 4 are, for example, disposed on the substrate 200. The substrate 200 is, for example, an N-type germanium substrate or a p-type germanium substrate. In the substrate 200, for example, a deep N-type well region 2〇la and a P-type well region 201b located on the deep N-type well region 201a are disposed. In the substrate 2, for example, a plurality of element isolation structures 202 are provided to define an active area. These element isolation structures 202 are, for example, located in p-type well regions 2〇ib, and the surface of these element isolation structures 202 is lower than the surface of the substrate 200, and recesses 204 are formed in the substrate 2''. The element isolation structures 202 are arranged in parallel in the row direction (X direction). Next, the structure of the memory cell row will be described. Since the structure of each memory cell row is the same, only the memory cell row MR2 will be described as an example in the following description. The memory cell row MR2 includes a source region 206, a drain region 208, a plurality of memory cells Q, a transfer gate 210, a selection gate 212a, and a selection gate 212b. The source region 206 and the drain region 208 are, for example, disposed in the substrate 200, and the source region 206 and the drain region 208 are, for example, at a distance. A plurality of memory cells Q are, for example, disposed on the substrate 200 between the source region 206 and the drain region 2〇8. There are gaps 214 between the adjacent two memory cells q. 27 1302741 19618twf.doc/g Next, the structure of the memory unit Q will be described. Each memory unit Q includes a memory cell and a transistor. The memory cell M and the transistor τ are arranged in parallel. The memory cell layer 216, the charge storage layer 218, the inter-gate dielectric layer 220, and the control gate 222 are sequentially formed by the substrate 200. The control closing electrode 222 is, for example, disposed on the base thinner and fills the recessed portion 204. The material of the control interpole 222 is, for example, a conductive material such as doped polycrystalline stone, metal or metal halide. The electrical storage layer is, for example, disposed of a material that controls the closed-pole from the substrate 200 to include a conductive material (such as a polysilicon or the like) or a charge trapping material (such as tantalum nitride). The dielectric layer 216 is disposed, for example, between the substrate 2 and the charge storage layer (10). The material thereof is, for example, oxidized oxide. The intervening dielectric layer is, for example, disposed on the control idler 222 and the charge storage layer 218 = (4), such as oxygen cut 'nitrogen cut' nitrogen or = material such as milk cutting, oxygen cutting / nitrogen cutting / oxidized stone Wait. On the second generation, the top cover layer member 224 can also be selectively provided with an insulating material, such as oxidized oxide, nitrogen, and nitrogen [1] in addition to the dielectric layer 216, the charge storage layer 218, and the gate. The side of the stacking pole structure formed by the layer 220 and the control gate 222 may be provided with an insulating spacer 226. The insulating spacer 226 is made of an insulating material such as tantalum oxide, tantalum nitride or the like.匕贝匕 The transistor Τ includes a gate dielectric layer 22 8 and a gate. The transistor is part of the control gate 222. The free dielectric layer is placed in the recess 21301301 19618twf.doc/g exposed surface 2G() surface and located between. The transistor τ is, for example, extended from the conductor layer of the (4)/镰222 and the substrate 200 to the thickness of the electric storage layer as the control gate 222 曰, the armor king 甩 storage layer (soil gate) 202 The recessed portion 204 is formed by the parasitic electric power (four) of the axis of the substrate 200 under the electrical storage m, , and the port ^ 200 ^ - V storage layer (the ocean gate). Since 222 acts as the idle pole of the transistor T, it is possible to arrange her in parallel. Japanese and Japanese

A plurality of transmission gates 210 are respectively disposed on the bottom 2GQ between the memory cells ,, and fill the gap 214 between the adjacent two memory cells Q. The memory cells Q are connected in series by transmitting the gates 21A. Between the transfer gate 21G and the substrate 2GG, for example, a material in which the gate dielectric layer 230/gate dielectric layer 230 is provided is, for example, hafnium oxide. The transfer gate 21〇 also fills the recess 204 of the element isolation structure, so that when the current is passed through the transistor τ (parasitic transistor), the transmission gate 21 turns on the channel next to it. The selection gate 212a and the selection gate 212b respectively set the sidewalls of the two outer sides of the memory cell q, which are adjacent to the source region, and are respectively adjacent to the source region. For example, select gate 212a is adjacent to source region 204 and select gate 212b is adjacent to drain region 206. The plurality of word line lines WL1 to WL8 are arranged in parallel in the column direction (Y direction), and are connected to the control gates 222 of the memory cells of the same column, respectively. The plurality of bit lines BL1 to BL4 are arranged in parallel in the row direction (X direction), and are respectively connected to the drain regions 208 of the memory cell rows of the same row. The bit lines BL1 to BL4 are connected, for example, by the interposer 232 and electrically connected to the 209 and the pole region 208. A plurality of source lines SL1 are arranged in parallel in the column direction (Y direction), and are connected to the source regions 206 of the memory cell rows of the same column, respectively. In the non-volatile memory of the present invention, since the surface of the element isolation structure 202 is lower than the interface between the charge storage layer 218 and the substrate 200, the recess 204 is formed, and the recess 204 is disposed in parallel with the memory cell μ. The transistor is crucible. The setting of this transistor will help the operation of the memory unit, shorten the stylized operation time and avoid reading interference. Moreover, in the non-volatile memory of the present invention, since the conventional doped region is replaced by the transfer gate 210 between the memory cells, the short channel effect and the buck-induced energy band reduction can be avoided (Drain Induced. Lowering 'DIBL) effect, etc. caused by memory leakage current. In addition, a transmission gate 21Q is disposed between the cells, and the material of the transmission gate 210 is a conductor, and the charge storage layer of the adjacent two memory cells can be shielded to reduce the coupling between the memory cells and the memory cells. interference. In addition, when operating the non-volatile memory of the present invention, the electron tunneling (FN Tunding) is used to pass electrons through the tunnel through the tunneling = electrical layer into the charge storage layer to perform the program of the memory cell. The operation of the present invention is reduced by using FN tunneling to cause electrons to be injected from the charge storage layer through the dielectric layer of the gate to perform the erasing operation of the memory cell. The electrons can pass through the tunneling dielectric layer, so that the lifetime of the tunneling dielectric layer can be increased and the components can be added to illustrate the method of manufacturing the non-volatile memory of the present invention. 30 1302741 19618twf.doc/g FIGS. 5A to 5H and 6A to 6H are cross-sectional views showing a manufacturing process of a non-volatile memory according to a preferred embodiment of the present invention. 5A to 5H are cross-sectional views corresponding to the line a-a in Fig. 4A, and Fig. 6A to Fig. 6H are diagrams corresponding to those in Fig. 4A; B-B. Referring to Figure 5A and Figure 6A, the substrate 3 is first provided. This substrate 3 is, for example, a crucible substrate. Next, a dielectric layer 3〇2 is formed on the substrate 3〇〇.

The material of the dielectric layer 302 is, for example, oxidized stone. The method of forming the dielectric layer 3〇2 is, for example, a thermal oxidation method. Then, a conductor layer 3〇4 is formed on the substrate 300. The conductor layer 3〇4, the material shell is, for example, a #heteropolycrystalline hair, and the conductor layer is formed by a method such as 疋 using a chemical IU-deposition method to form a layer of undoped township (four) layer (the ionic implantation step is not performed) It is formed by chemical vapor deposition by means of on-site I.

A dielectric layer 3〇6 is formed on the bottom of the gate, and the gate is, for example, an oxygen cut/a nitrogen cut/a nitrogen cut, and the gate is formed by a thermal oxidation method, for example, a layer bottom. Oxidation &quot; pick-up, then using a chemical vapor deposition method to form a layer of nitride and then forming a top oxygen layer on the nitrogen layer. Of course, the material of ^ : can also be oxidized (4) 嶋 fossil eve or its = Please refer to Figure 5B and Figure 6B to form a brow mask layer 3 〇 8 on the substrate 3 。. The patterned mask layer has an opening sl〇 dielectric layer 3〇6. The patterned mask layer is, for example, a hard mask layer. 31 1302741 19618twf.doc/g The material is, for example, tantalum nitride. The hard mask layer forming method is formed, for example, by forming a layer of material on the substrate and performing a lithography and etching process: of course, the material of the patterned mask layer 308 may also be a photoresist material, which forms the f method, for example. After forming a photoresist layer on the substrate, the photoresist layer is exposed and developed. θ Next, using the patterned mask layer 3〇8 as a mask, a part of the inter-gate dielectric layer 306, the conductor layer 3〇4, the dielectric layer 3〇2 and the substrate 3〇〇 are removed, and the substrate is 幵〆 A few ditches 312. The method of removing a portion of the inter-gate dielectric layer 306, the conductor layer 304, the dielectric layer 3〇2, and the substrate 3 (10) includes a dry-type lithography, such as reactive ion etching. The trenches 312 are arranged in parallel in the direction of the 对应 corresponding to Fig. 4A. In this step, after the conductor layer 304 is patterned, a conductor layer 3〇4a of a strip-like layout (corresponding to the X direction of FIG. 4A) is formed. A lining 314 is formed on the substrate 300 as shown in FIG. 5C and FIG. 6C. The material of =314 is, for example, oxidized stone. Lining, 314 formation method Thermal oxidation method. The material ΪΪμ forms a layer 316 of insulating material on the substrate. The material of the insulating layer 316 is, for example, oxidized stone. Formation of the rider layer 3!6 2 = Rugao chemical vapor deposition. Next, a portion of the insulating material layer I is removed until the mask gauge surface is exposed. Removing part of the insulating material layer ίνΐ is, for example, a chemical mechanical grinding method or a back-and-forth method. In this step, the mask layer gauge is, for example, a grinding (or money engraving) termination layer. Referring to FIG. 5D and FIG. 6D, a portion of the insulating material layer 316 and the pad 14 are removed to form an insulating material layer 316a and a pad 311⁄2. Insulation; 316a and the underlayer 314a #"...the surface of the material layer is lower than the 32 1302741 19618twf.doc/g interface between the conductor layer 304 and the substrate 300 to form the depressed portion 318, the insulating material layer 316a and the underlayer M4a That is, as the element isolation structure, the method of removing part of the insulating material layer 316 and the underlayer 3i4 is, for example, a dry rice carving method. Then, the patterned mask layer 3〇8 is removed, the pattern is removed, and the mask layer 3 is removed. The method is, for example, a wet side method. Next, a dielectric layer 32 is formed on the substrate 300, and a dielectric layer 322 is formed on the sidewalls of the conductor layer 3〇4 &amp; the material of the dielectric layer 32〇 and the dielectric layer milk is, for example, oxidized. The method of forming the dielectric layer 320 and the dielectric layer 322 is, for example, a thermal oxidation method. In this step, a dielectric layer (not shown) is also formed on the surface of the dielectric layer 306. 5E and FIG. 6E, another layer 324 is formed on the substrate 300. The conductor layer 324 fills the recess 318. The conductor layer is similar to the example j polycrystalline Wei metal' layer-doped polycrystalline dream layer and layer metal a layer composed of a stellite layer in which a doped polycrystalline layer is filled with a recess and formed on a doped polycrystalline layer Shaped like a conductor layer

Li, a vapor deposition method sequentially forms a doped polycrystalline layer and a metallized layer. Of course, the conductor thickness is 3&gt; 44· # other metal materials. The material of θ may also be a doped polycrystalline stone or a layer of capping layer 326 formed on the substrate 3〇〇. The top seedling sound %$ is composed of, for example, a top cover layer 326 dome hoist, a wide 曰 〃, and an inner layer 326b. The cap layer 326a is cut. The material of the top cover layer 326b is, for example, nitrite. The forming method of the U-coating layer is, for example, a chemical vapor deposition to "pattern the cap layer 326, the conductor layer 324, so that the conductor layer is similar", and the plurality of strip-shaped conductor layers are arranged in a row (corresponding to FIG. , in the square 33 1302741 19618twf.doc / g parallel to the word lines WL1 ~ WL8). The method of patterning the cap layer 326 and the conductor layer 324 is, for example, a lithography technique. Referring to FIGS. 5F and 6F, insulating spacers 328 are formed on the sidewalls of the cap layer 326 and the conductor layer 324. The material of the insulating spacer 328 is, for example, a dream. The insulating spacers 3 28 are formed, for example, by forming an insulating material layer by chemical vapor deposition and then performing an anisotropic etching process.

A portion of the conductor layer 304a is then removed by the cap layer 326 having the insulating spacers 328 and the conductor layer 324 as a mask to expose the dielectric layer 3〇2. After removing a portion of the conductor layer 304a, a plurality of conductive blocks 304b are formed which are isolated from each other. The conductive block 304b is a floating gate as a memory cell. The dielectric layer 3〇6 is a inter-gate dielectric layer as a memory cell. Conductor layer 324 is the control gate that begins as a stamp. The dielectric layer 302 is a tunneling dielectric layer conductor layer 324, a dielectric layer 306, a conductive block 304b, and a dielectric layer 3〇2 into a stacked gate structure (memory cell). Further, a portion of the conductor layer 324 filled in the recessed portion 318 and the dielectric layer 320 constitute a transistor. The conductor cells are placed in parallel with the transistor by the conductor layer 324. &quot; Then, a dielectric layer 33 is formed on the substrate 300, and a dielectric layer 332 is formed on the sidewall of the conductor layer 3. The dielectric layer is now in contact with the dielectric layer 332. The method for forming the dielectric layer 330 and the dielectric layer 332 is as follows. Referring to FIG. 5G and FIG. 6G, another layer (not shown) is formed on the substrate, and the conductor layer fills the gap between the stacked gate structures. After the absence, the anisotropic side process is performed to return to the partial layer, so that the phase is formed between the structures and the outermost two stacks are formed. The sidewall forms a conductor layer 334b. The conductor layer is, for example, a recess 318 of the object isolation structure. The dielectric layer 330 and the dielectric layer 3〇2 at the conductor layer 334a 盥 ^ = 2 are, for example, gates for transmitting the armature; The dielectric layer 330 and the dielectric layer 302 between the conductor layer 334b and the substrate 300 are, for example, gate dielectric layers that serve as gate electrodes. Guide

The dielectric layer 332 between the layout layer 334a and the conductive block 304b and between the conductor layer 334b and the conductive bumps 3〇4b also functions as a gate dielectric layer. Next, a source region 336a and a: and a polar region 336b are formed in the substrate 300. The method of forming the source region 336a and the drain region 336b is, for example, an ion implantation method. Thereafter, a cover layer 338 is formed on the substrate 300. The material of the cover layer 338 is, for example, tantalum nitride. The formation method of the cover layer 338 is, for example, a chemical vapor deposition method. Referring to FIG. 5H and FIG. 6H, an interlayer insulating layer 340 is formed on the substrate 300. The material of the interlayer insulating layer 340 is, for example, phosphorosilicate glass, boron strontium glass, or the like. The method of forming the interlayer insulating layer 340 is, for example, a chemical vapor deposition method. Next, a conductor layer 342 electrically connected to the source region 336a is formed in the interlayer insulating layer 340. The conductor layer 342 serves as a source line. The conductor layer 342 is formed by, for example, patterning the interlayer insulating layer 340 to form an opening exposing the source region 336a, and then filling the opening with a conductor material. Then, an interlayer insulating layer 344 is formed on the substrate 300. The material of the interlayer insulating layer 344 is, for example, phosphor glass or borophosphon glass. The method of forming the interlayer insulating layer 344 is, for example, a chemical vapor deposition method. 35 1302741 19618twf.doc/g Next, a conductor layer 346 (conductor plug) electrically connected to the drain region 336b is formed in the interlayer insulating layer 344 and the interlayer insulating layer 34A. The conductor layer 3 is formed by, for example, patterning the interlayer insulating layer 344 and the interlayer insulating layer 340 to form an opening exposing the drain region 336b, and then forming the opening material into the opening. Then, a conductor layer 348 is formed on the substrate 3A. This conductor layer 348 is used as a bit line (corresponding to BU to BL4 in Fig. 4A). The shape of the conductor layer 3 is formed, for example, by forming a layer of a conductor material on the substrate 3, and then forming a lithography and etching process. The subsequent process of completing the non-volatile memory is well known to those skilled in the art and will not be described here. In the method of fabricating the non-volatile memory of the present invention, since the surface of the element isolation structure is lower than the interface between the conductor layer 3〇4 and the substrate 3(8), the depressed portion 318 is formed, and the recessed portion 318 is formed with the memory cell. Electrical μ body connected in parallel. The formation of this transistor will aid in the operation of the memory, shortening the stylized operation time and avoiding read disturb. Moreover, the transfer gate also fills the recess 31 of the element isolation structure so that when a current is passed through the transistor (parasitic transistor), the transfer gate opens the channel next to it. Further, in the method of manufacturing a non-volatile memory of the present invention, since the conductor layer 334a (transmission gate) is formed between the memory cells, the short channel effect and the energy band induced by the drain can be avoided (Drain Induced) Barrier • LowerinS, DIBL) effects such as memory leakage current. In addition, a conductor layer 334a (transmission gate) is formed between the memory cells, and the conductor layer 334a (transmission gate) can shield the conductor layers 36 1302741 19618twf.doc/g 304b (the ocean gate) of the adjacent two memory cells. , while reducing the interference between memory cells and memory cells. ~ and = memory cells in the erasing operation can be used by F, tunneling = electricity from: floating from the float to the conductor layer _ = number = type of elimination can reduce the electron crossing through the dielectric. This can improve the lifetime of the dielectric layer and increase the manufacturing process of the two-dimensional memory of the device, which can be easily combined and can increase the process margin. Although the present invention has been disclosed in the above preferred embodiments, the iron defines the present invention, and anyone skilled in the art can make some changes and refinements when not taking off the county, so the scope of the present invention is considered to be专 专 专 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Schematic diagram of the process of the cell. 7 Fig. 3 is a schematic diagram showing an example of reading and dropping the source side memory cells. The WT TF - Figure 3C is a schematic representation of the erasing of the 汲 记忆 memory cell. 。 仃 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 。 。 。 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 Fig. 4B is a cross-sectional view showing the structure taken along line A-A' in Fig. 4A. Fig. 4C is a cross-sectional view showing the structure taken along line B-B' in Fig. 4A. 5A through 5H are cross-sectional views showing a manufacturing process of a non-volatile memory in accordance with a preferred embodiment of the present invention. 6A through 6H are cross-sectional views showing a manufacturing process of a non-volatile memory in accordance with a preferred embodiment of the present invention. [Main component symbol description] 100, 200, 300: Substrate 102: Doped regions 104, 206, 336a: Source regions 106, 208, 336b · No-pole region 108 · Plug 201a: Deep N-well region 201b : P-type well region 202: element isolation structure 204: recessed portion 204 210: transmission gate 212a, 212b: selection gate 214: gap 216: tunneling dielectric layer 218: charge storage layer 220: gate dielectric layer 222 : Control gate 38 1302741 19618twf.doc/g 224 : Cover layer 226, 328: Insulation spacers 228, 230: Gate dielectric layer 230: Plugs • 302, 320, 322, 330, 332: Dielectric layer • 304, 304a, 324, 334a, 334b, 342, 346, 348: conductor layer 304b: conductor block® 3G6: dielectric layer 308 · patterned mask layer 310: opening 312: trench 314, 314a: lining 316 316a: insulating material layer 326, 326a, 326b: top cover layer 338: cover layer • 340, 344: interlayer insulating layer BL, BL1 to BL4: bit line

Ml~M8, Mil~M38: Memory cells MR1~MR4: Memory cell row. PL1~PL7: Transmission gate line Q, Q11~Q38: Memory unit SGI, SG2: Select gate line SL: Source line 39 1302741 19618twf .doc/g ST1, ST2, ST11 to ST31, ST12 to ST32: Select transistor T, Til~T38: transistor WL1 to WL8: word line

40

Claims (1)

1302741 19618twf.doc/g X. Patent application scope: It includes a plurality of memory sheets. 1. A non-volatile memory cell line, each of which includes: _ a source region and a drain region. Set in a substrate, the element is set between the source 'and the bungee area, [the cell (10) is pre-existing - the memory cell and the - transistor, the phase has been "1 soldier" the transistor is connected in parallel Between the two (the fourth) is disposed in the adjacent two of the memory units, the two memory cells are connected in series; and the two sides of the two = single and the second selected transistor, respectively The outer neighbors have been connected to the front and the non-volatile gaps described in item 1 of the source region and the non-polar region respectively. The wheel gates fill the adjacent two. The layer between the memory cells, the memory cell from the substrate includes at least a dielectric layer, an inter-dielectric layer, and a closed-cell dielectric layer. The anti- and inter-type non-volatile memory described in the third item of the scope. The material of the inter-dielectric layer includes oxidized stone eve/nitrite eve/oxidation. The material of the reverse and _ volatile, and the storage layer of the body 3 are doped polycrystalline germanium. • The anti- and non-volatile notes described in item 3 of the patent application scope is claimed. 41 1302741 19618twf.doc/g The material of the tunneling dielectric layer includes yttrium oxide. 7. The anti-gate type non-volatile memory as described in claim 3 further includes a plurality of element isolation structures, which are disposed in parallel on the substrate. The memory cell rows are disposed between two adjacent element structures. The body 'in which the surface of the transfer isolation structure is formed below the charge storage contact-substrate interface--depression portion, the control gate fills the two depressions 9. The anti-sliding non-recallant body as described in claim 8 further includes a gate dielectric layer disposed between the control gate and the base red. The paste electrode, the dielectric layer and the base are formed. Soil &amp; 10. The non-volatile, non-volatile memory of the gate type described in claim 3, wherein the memory cells are arranged in a two-dimensional configuration, the cell array, and the gate-type non-volatile memory Body more includes sex into a memory Two plurality of word lines are arranged in parallel in the column direction, and are connected to the control gates of the same memory cells and the gates of the transistors; a plurality of bit lines are arranged in parallel in the row direction, respectively a drain region of the memory cell row; a plurality of source lines connected to the same column, arranged in parallel in the column direction, the source region of the memory cell row; a plurality of strips select gate lines in the fiscal direction Parallel (four), the gate of the first selection transistor of the memory cell of the first selection transistor is divided into two columns, and the plurality of transmission gate lines are arranged in parallel in the column direction, respectively connecting the gate 42 1302741 19618 twf.doc/g A list of the transmission gates of the memory cell row. 2. 丨1· The non-volatile self-extending limb of the anti-valve type as described in claim 10 further includes a plurality of element isolation structures disposed in the substrate and arranged in parallel in the row direction, each of the memory cells The rows are placed between adjacent two component structures.立立12. The anti-valve non-volatile = memory element according to claim 11 wherein the surface of the element isolation structure is lower than the interface between the bases of the charge storage layer to form a depressed portion. The control gate fills the second "Liu 13. The anti-gate type non-volatile memory element as described in claim 12 of the patent application scope" further includes a gate dielectric layer disposed on the control gate and the substrate Each of the pens is composed of a portion of the control gate and the gate dielectric layer. 曰1曰4. A method for manufacturing a gate-type non-volatile memory, comprising: μ providing a substrate, A first dielectric layer and a second dielectric layer are sequentially formed on the substrate; the first conductive layer is patterned to form a plurality of first conductive conductor layers arranged in parallel. a first strip-shaped conductor layer extending in a - direction - a plurality of trenches extending in the first direction in the substrate between the strip-shaped conductor layers; the trenches in the substrate a plurality of isolation structures, the surfaces of the two off structures being lower than the first strips Forming a depressed portion between the body layer and the bottom of the county to expose a portion of the substrate; forming a third dielectric layer on the surface of the exposed portion; forming a second conductive layer on the far substrate, wherein the first layer The second conductor layer is filled with 43 1302741 19618 twf.doc/g to fill the recess; the second conductor layer, the second dielectric layer, and the second strip are patterned: Γ ϊ 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 其中 其中 其中The strip-shaped conductor layer is formed into: a plurality of third strip-shaped conductor layers formed between the plurality of pole-junction structures extending in parallel and parallel, and the outermost sides of the two stacks. (4) Non-volatile ❹ ❹ 该 该 条 条 条 条 条 条 条 条 条 条 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = Shape and anti-non-volatile, 4 methods, the material of the first-dielectric layer of the towel X "ϊ =: genus:: = memory / /: 敎 敎 _ non-volatile / oxygen ^ money The method wherein the second dielectric layer comprises oxygen cut/nitridite eve 44 1302741 19618 twf.doc/g An insulating layer is formed on the substrate; and a surface. Removing a portion of the insulating layer such that the surface of the insulating layer is lower than the substrate. The method for manufacturing the memory according to the application of the above-mentioned item 14 is a thermal oxidation process of 豆-八+ &amp; F ^ . The method for forming a second dielectric layer includes the method of converting the non-volatile a-body of the gate type described in the above item 14, and further comprising the stacked gate structure and the second strip conductor An insulating spacer is formed between the layers. 23. The method for manufacturing a reverse gate memory according to claim 14, wherein the third dielectric layer and the second strip conductor form a transistor. 24. The manufacturer of the anti-gate type non-volatile memory according to claim 14 of the patent application scope, wherein the towel is formed on the third strip-shaped conductor layer between the stacked idler structures As the "transmission gate", the third strip-shaped conductor layers formed on the outermost side walls of the two stacked gate structures serve as a selection gate. 25. The method of manufacturing a reverse-type non-volatile memory according to claim 14, wherein the doped polycrystalline silicon is also doped. 26. The method of manufacturing a reverse-type non-volatile memory according to claim 14 of the invention, further comprising forming a source region and a non-polar region in the base towel. 27. A method for operating a gate-type non-volatile memory, for 45 1302741 19618 twf.doc/g, including a memory array of a plurality of memory cell rows, each of which is placed on a substrate The upper part has a plurality of memory cells disposed between a source region and a second region, and each of the memory cells includes a parallel connection of two cells, a cell and an electricity source; and a plurality of transmission gates Provided on the recording floor between the records, and the memory cells are connected in series, the selection transistor and the second selection transistor are respectively connected to the outermost unit, and the first Selecting a transistor and the drain region selecting transistor adjacent to the source region, and multi-numbering and respectively connecting the gates of the memory cells of the same-column; the plurality of source lines respectively Connections are the same as 1 2:, area: most of the bit lines are arranged in parallel in the row direction, and 'square 2: 5 ha of some bungee areas; most of the first selection gate lines, in the column selection gate f - the first plurality of second selection gate lines of the memory cell row, in the column direction Do not connect the second selected power_transmission gate line of the memory cell row in the same column, and arrange the two lines in the column direction in parallel: the transmission of the cell line, the method = the selected memory cell &quot;When the memory cell is programmed, the bit coupled to the cell is applied to the bit line of the unselected bit line, and the second voltage is applied to the second bit: The memory cell is selected to be added to the (4) plane, and the word (10) is not selected. The house 'applies a sixth power to all the poles of the transfer wheel' to utilize the channel = 46 1302741 19618twf.doc/g The tunneling effect stylizes the selected memory cell, wherein a voltage difference between the fourth voltage and the first voltage may induce an FN tunneling effect, the third voltage being greater than or equal to a starting voltage of the first selected transistor, The second voltage can inhibit the first selection transistor of the non-selected memory cell row from being turned on, the fifth voltage being greater than or equal to the start voltage of the transistor, and the sixth voltage causing the channel under the transmission gate to be turned on. 28. The method of operating a reverse-type non-volatile memory according to claim 27, wherein the first voltage is about volts; the second voltage is about 5 volts; and the third voltage is 5. The fourth voltage is about 20 volts; the fifth voltage is about 10 volts; the sixth voltage is about 5 volts. 29. The method for operating a reverse-type non-volatile memory according to claim 27, further comprising: when a memory cell of a selected memory cell is read, the memory cell is selected Applying a seventh voltage to the bit line, applying an eighth voltage to the first select gate line, applying a ninth voltage to the second select gate line, and coupling the selected memory cell Applying a tenth voltage to the word line, applying an eleventh voltage to the unselected word lines, applying a twelfth voltage to all of the transmission gate lines to read the selected memory cell, wherein the The eighth voltage is greater than or equal to a starting voltage of the first selection transistor, the ninth voltage being greater than or equal to a starting voltage of the second selection transistor, the eleventh voltage being greater than or equal to a starting voltage of the transistor And the twelfth voltage turns on the channel below the transmission gate. 30. The method of operating a non-volatile 47 1302741 19618 twf.doc/g memory according to claim 29, wherein the seventh voltage is about 1.5 volts; the eighth voltage is about 5 volts. The ninth voltage is about 5 volts; the tenth voltage is about 0 volts; the eleventh voltage is about 5 volts; and the twelfth voltage is about 5 volts. 31. The method for operating a reverse-type non-volatile memory as described in claim 27, further comprising: applying a first to all transmission gate lines when erasing the memory cells of the memory unit The thirteen voltage causes the substrate to float to erase the memory cells by the FN tunneling effect, wherein the voltage difference between the thirteenth voltage and the substrate can induce a FN tunneling effect. 32. The method of operating a reverse-type non-volatile memory according to claim 31, wherein the thirteenth voltage is about 15 volts. 48