1302312 * % 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種NAND型快閃記憶體元件（NAND flash memory device)之讀取方法（read method)及其記憶胞陣列 (memory cell array)，尤指一種應用於每一記憶胞（memory cell)儲存二位元資料（two-bit data)之多層次胞 (multi-level-cell)NAND型快閃記憶體元件之讀取方法及其 記憶胞陣列。 > 【先前技術】 - 在一傳統NAND型快閃記憶體中，每一記憶胞可儲存兩 、 種資料狀態，亦即可儲存「開」狀態Γ〇Ν” state)或「關」 狀態（"OFF” state)。資訊的每一位元（bit)係由個別的記憶胞 之「開」、「關」狀態所定義。在傳統NAND型快閃記憶體中， 為了能儲存N個位元資料（N為大於或等於2之整數），必須使 用N個個別的記憶胞。因此，若是使用傳統NAND型快閃記 憶體，當所要儲存的資料位元個數增加時，記憶胞的個數 B 也必須跟著增加。儲存在單一位元（one-bit)記憶胞之資訊係 決定於一記憶胞之寫入狀態（programmed status)，而該資料 係利用寫入（program)動作儲存至該記憶胞。存有記憶胞狀 態之資訊係由一位於該記憶胞中之電晶體之門檻電壓 (threshold voltage)所決定。門檻電壓係施予在該電晶體之 閘極及源極間，可將該電晶體導通（turn on)之最小電壓。 圖1顯示根據所寫入的資料，一記憶胞之四種門檻電壓分 佈圖。如圖1所示，所寫入的資料可以以下四種電壓分佈之 E39981 108.^67 108367.doc 1302312 一來表示：（1)小於-2.0V(伏特）之門檻電壓分佈，係代表（11) 之二位元資料；（2)介於0.7V及1.1V之門楹電壓分佈，係代 表（10)之二位元資料；（3)介於2.0V及2.4V之門檻電壓分 佈，係代表（01)之二位元資料及（4)介於3.6V及4.0V之門檻 電壓分佈，係代表（00)之二位元資料。資料可基於上述四種 不同門檻電壓分佈而儲存於一記憶胞中。 關於應用於一單一層次記憶胞（single level memory cell) NAND型快閃記憶體元件之讀取方法，美國專利US 6,671，204中（以下稱’204)已提出一種讀取方法。圖2(&)顯示 *204之一頁緩衝區（page buffer)，其係描述於讀取操作（read operation)時之資料流向。圖2(b)係圖2(a)相關訊號之時序 圖。詳細之讀取操作敍述如下，其中資料係假設自一記憶 胞（圖未示）中被讀取且該被讀取記憶胞之閘控制訊號（gate control signal)係用以施加一適當之電壓於其相關聯之字元 線（word line)上。讀取動作係直接經由一主暫存器150，而 不經由一附屬暫存器170。為執行一穩定的讀寫操作，二位 元線BLE及BL0首先藉由電晶體N1及N2放電（discharge)至 接地電位，其係將訊號VBLe及VBLo切換至高位準並將訊 號VIRPWR切至低位準（或接地電位）（參圖2(b)之階段1)。同 時，訊號PBRST自高位準切換至低位準以導通（turn on)電晶 體N5，使得該主暫存器150(或一反相器153之輸入）被設定 至一預設狀態（例如高位準）。接著進入階段2，一第一控制 訊號PLOAD切換至低位準以導通電晶體N9且電晶體N3之 控制訊號BLSHFe被保持在一特定電壓（例如2.1V)，該特定 E39981 108307 108367.doc 1302312 電壓係電晶體N3之門檻電壓與該位元線BLE之預充電壓 (precharged voltage)之和。在位元線BLE以一適當電壓預充 電（precharge)之後，控制訊號BLSHFe切換至接地電位之低 位準（參圖2(b)之階段3)。於階段3，一位元線之一預充電壓 係隨著一選定記憶胞（selected memory cell)之狀態而改 變。例如若該選定記憶胞係一關閉胞（off cell)(意即所施加 的字元線電壓低於該選定記憶洫之門檻電壓），則該位元線 (例如位元線BLE)之該預充電壓將被保持。若該選定記憶胞 係一導通胞（on cell)(意即所施加的字元線電壓高於該選定 記憶胞之門檻電壓），則該位元線（例如位元線BLE)之該預 充電壓將被放電。若控制訊號BLSHFe電壓變成一介於該預 充電壓及先前該控制訊號BLSHFe電壓之中間電壓，則當該 選定記憶胞係一關閉胞時，一節點SO之電壓將藉由關閉電 晶體N3而保持在電壓源位準（source voltage ; Vce);否則該 節點SO之電壓將透過位元線BLE放電。於階段3中之某一時 間點（此時控制訊號BLSHFe之電壓降至接地電位），該第一 控制訊號PL0AD切換至高位準。之後，進入階段4。訊號 PBLCHM升至高位準以導通電晶體N7且電晶體N6之狀態 (導通或關閉）則視該節點SO之狀態（高或低位準）而定。藉 此，該節點SO之狀態將被儲存在該主暫存器150之中。接 著，儲存在該主暫存器150中之資料再經由電晶體N8(藉由 訊號PBD1控制）及一 Y閘電路（Y-gating circuit)130傳送至一 資料線（data line)131。 關於應用於一多層次胞NAND型快閃記憶體之讀取方 108367.doc - 8 - E39981 1302312 法，美國專利US 5,754,475中（以下稱’475)揭示一多層次胞 讀取方法。圖3係’475中一與一區塊（block)中之記憶胞相關 聯之讀取電路簡化圖。在陣列（array) 112中之記憶胞MC11 至MCnm係排列成一矩陣狀（matrix)。其中記憶胞MCI 1、 MC12 · · ·及MClm係設置在同一列（row)且其選擇端 (selection terminal)均連接於相同的字元線WLi ;在陣列112 中，其餘各列均如此設置排列。此外，記憶胞MCI 1、 MC21 · · ·及MCnl ;記憶胞MC12、MC22· · ·及MCn2; · · · 及記憶胞MClm、MC2m . · •及MCnm等，均設置於個別 同一欄（the same respective columns)且其資料端（data terminal)均分別連接於相同之位元線BLi、BL2、···及 BLn。每頁（page)設有三條參考位元線122a至122c係使用在 四層次胞（four-level cell)。每一條參考位元線122與每一條 字元線WL之交叉處均設有一參考記憶胞（reference cell)RC。當頁寫入（page program)指令執行時，該頁之參考 記憶胞RC之門檻電壓將被調整至一目標值且該參考記憶 胞RC係與常態記憶胞（normal cell)MC同時進行寫入。參考 記憶胞RC具有如圖1所示之三種門檻電壓RT0、RT1及 RT2。為了能區分一記憶胞之四種狀態（即（11)、（10)、（〇1) 及（00))，’475所提出的讀取方法之讀取動作必須重覆三次 (three phases)，其中每次的讀取動作即執行如圖2(b)六個階 段之動作。於第一次（phase one)的讀取動作中，儲存在處 於（11)、（10)、（01)及（00)狀態之記憶胞中之二位元資料之 最高位元（most significant bit ; MSB)被讀取。於第二次 E39981 108367 108367.doc 1302312 (phase two)的讀取動作中，儲存在處於（11)及（1〇)狀態之記 憶胞中之二位元資料之最低位元（least significant bh ; LSB) 被讀取。於第三次（phase three)的讀取動作中，儲存在處於 (01)及（00)狀態之記憶胞中之二位元資料之最低位元被讀 取。圖4(a)表示’475中讀取方法之三次讀取動作順序 (sequence)圖。 美國專利US 5,768,188中（以下稱’188)揭示一多層次胞讀 取方法。該讀取方法不需使用參考記憶胞而是利用三次分 別施加不同固定字元線電壓之讀取動作，以區分處於四種 不同狀態之記憶胞。其讀取動作順序如下。儲存在處於（10) 及（〇1)狀態之記憶胞中之二位元資料之最低位元於第一次 讀取動作（phase one)中被讀取，此時施加在選定字元線 (selected word line)上之電壓係2伏特。接著，儲存在處於 (11)、（10)、（01)及（〇〇)狀態之記憶胞中之二位元資料之最 高位元於第二次讀取動作（phase two)中讀取，此時施加在 選定字元線上之電壓係1伏特。最後，於第三次讀取動作 (phase three)中，儲存在處於（11)及（10)狀態之記憶胞中之 二位元資料之最低位元被讀取，此時施加在選定字元線上 之電壓係0伏特。圖4(b)表示’188中讀取方法之三次讀取動 作順序圖。 美國專利公開號US 2005/0018488中（以下稱·488)揭示一 多層次胞讀取方法。該讀取方法係利用三次分別施加不同 固定字元線電壓之讀取動作，以區分處於四種不同狀態之 記憶胞而不需使用參考記憶胞。該讀取方法之讀取動作順 108367.doc -10- Ε39981 108367 1302312 序不同於’475及’ 188之讀取動作順序。其讀取動作順序如 下。儲存在處於（01)及（00)狀態之記憶胞中之二位元資料之 最低位元、儲存在處於（11)及（10)狀態之記憶胞中之二位元 賃料之最低位元及儲存在處於（11)、（10)、（01)及（〇〇)狀態 之記憶胞中之二位元資料之最高位元係依序分別於第一、 第二及第三讀取動作中被讀取且施加於其相應之字元線電 壓分別為1、2及3伏特。圖4(c)表示，488中讀取方法之三次 讀取動作順序圖。 美國專利US 5,986,929中（以下稱，929)揭示一多層次胞讀 取方法。該讀取方法亦利用三次分別施加不同固定字元線 電壓之讀取動作，以區分處於四種不同狀態之記憶胞而不 需使用參考記憶胞。該讀取方法之讀取動作順序不同於 ’475、4 88及’488之讀取動作順序。其讀取動作順序如下。 儲存在處於（11)及（1 〇)狀態之記憶胞中之二位元資料之最 低位元、儲存在處於（11)、（10)、（01)及（00)狀態之記憶胞 中之二位元資料之最高位元及儲存在處於（〇1)及（〇〇)狀態 之記憶胞中之二位元資料之最低位元係依序分別於第一、 第二及第三讀取動作中被讀取且施加於其相應之字元線電 壓分別為0、1·2及2.4伏特。圖4(d)表示，929中讀取方法之三 次讀取動作順序圖。 【發明内容】 本發明之主要目的係提供一種多層次胞 (multi-levei-ceii)NAND型快閃記憶體元件之讀取方法，係 利用與複數個參考記憶胞（reference cell)相關聯之複數條 E39981 108307 108367.doc •11· 1302312 參考位元線（reference bit line)，於單一階段（single phase) 中讀取複數個常態記憶胞以減少讀取時間。 本發明之另一目的係提供一相關於該讀取方法之記憶胞 陣列（memoiry cell array)，係利用一電壓產生器及複數個參 考記憶胞，於單一階段中讀取複數個常態記憶胞，進而減 少常態位元線之預充電（precharging)及放電（discharging)之 數量，藉此減少讀取時間。 為達到上述之目的，本發明揭示一種NAND型快閃記憶 體元件之讀取方法，係應用在一包含複數個常態記憶胞之 多層次胞NAND型快閃記憶體元件。該讀取方法包含以下步 驟：（a)於一預定期間提升一選定字元線電壓；及（b)於該預 定期間讀取處於一零狀態、一第一狀態、一第二狀態及一 第三狀態之該複數個常態記憶胞。其中該零狀態、該第一 狀態、該第二狀態及該第三狀態分別代表一儲存於每該複 數個常態記憶胞之二位元資料。 本發明另揭示一種記憶胞陣列，其係運用於一 NAND型 快閃記憶體元件。該記憶胞陣列包含（1)複數個平行設置之 常態記憶胞區塊，每該常態記憶胞區塊包含複數個常態記 憶胞，每該常態記憶胞係處於一零狀態、一第一狀態、一 第二狀態或一第三狀態；（2)複數個參考記憶胞區塊，係設 置於該複數個常態記憶胞區塊之間；（3)複數條常態位元 線係與母該複數個常態記憶胞區塊及複數個常態頁緩衝 區耦合；（4)複數條參考位元線，係與每該複數個參考記憶 胞區塊及複數個參考頁緩衝區耦合；及（5)一電壓產生器， 108367.doc E39981 108367 •12- 1302312 1 % 係產生一作用於在一預定期間之一選定字元線上之提升字 元線電壓。其中與該選定字元線相關聯之處於該零狀態、 該第一狀態、該第二狀態及該第三狀態之該複數個常態記 憶胞係於該預定期間讀取。 【實施方式】 以下將先敍述本發明之記憶胞陣列，以助於了解本發明 之NAND型快閃記憶體元件之讀取方法。 圖5係本發明一實施例之記憶胞陣列10。於本實施例中， 該記憶胞陣列10包含：1024個平行設置之常態記憶胞區塊 (ΒΚ[0]至ΒΚ[1023])、二設置於該1024個常態記憶胞區塊 (ΒΚ[0]至ΒΚ[1023])之間之參考記憶胞區塊（RBK[0]及 RBK[1])(即 RBK[0]設置在 BK[255]及 BK[256]之間而 RBK[1] 設置在BK[767]及BK[768]之間）、8196條與每該常態記憶胞 區塊及複數個常態頁緩衝區（圖未示）相互耦合之常態位元 線（BL[0]至BL[8195])、三條與二該常態記憶胞區塊及三參 考頁緩衝區（圖未示）相互耦合之參考位元線（RBL[1]至 RBL[3])及一電壓產生器（圖未示）。每一常態記憶胞區塊BK 包含複數個常態記憶胞（圖未示）且每一常態記憶胞係處於 一零狀態、一第一狀態、一第二狀態或一第三狀態。於本 實施例中，（11)、（10)、（01)及（00)狀態（參圖1)係分別定義 成該零狀態、該第一狀態、該第二狀態及該第三狀態。參 考記憶胞區塊RBK之設置位置係以降低沿著常態位元線BL 方向之電阻電容負載延遲（normal bit line resistance-capacitance loading delay)為原貝丨J 〇 例如本實施例 108367.doc -13 - Ε39981 108367 1302312 中，二參考記憶胞區塊RBK[0]及RBK[1]分別設置於ΒΚ[255] 及ΒΚ[256]之間及ΒΚ[767]及ΒΚ[768]之間，使得當任何一位 於記憶胞陣列10之上半侧之常態記憶胞區塊（即上半側 ΒΚ[0]至ΒΚ[5 11 ]中之任一 ΒΚ)被選定進行讀取動作時，位於 上半側之參考記憶胞區塊RBK[0]將被啟動（active);類似 地，當任何一位於記憶胞陣列10之下半側之常態記憶胞區 塊（即下半侧BK[512]至BK[1023]中之任一 BK)被選定進行 讀取動作時，位於下半側之參考記憶胞區塊RBK[1]將被啟 動。此外，每一參考記憶胞區塊RBK之尺寸大小係與每一 常態記憶胞區塊BK之尺寸大小相同且每一參考記憶胞區 塊RBK中之參考字元線RBL之數目與每一常態記憶胞區塊 BK中之常態字元線之數目BL相同。該電壓產生器係產生一 在一預定期間（a predetermined period)作用於一選定字元線 (selected word line)上之提升字元線電壓（ramp-up word line voltage)。而與該選定字元線相關聯之處於該零狀態、該第 一狀態、該第二狀態及該第三狀態之該複數個常態記憶胞 係於該預定期間被讀取。該三條參考位元線RBL[1]至 RBL[3]係與三個參考頁緩衝區（圖未示）相互耦合。於另一 實施例中，參考位元線可設置成六條；每二條參考位元線 與一參考頁緩衝區相互搞合且該二條參考位元線之一係作 為一遮蔽參考位元線。另，該三條參考位元線RBL[1]至 RBL[3]可視為一參考群（reference group)。在運用上，每一 頁（page)可依字元線之電阻值、電阻電容乘積（product of resistance and capacitance)及字元線電壓之提升率（ramp_up 108367.doc -14- E39981 108367 1302312 rate of the word line voltage)等因素而使用一或多個參考 群。 圖6係圖5中之參考記憶胞區塊RBK之一實施例。該參考 記憶胞區塊RBK包含三條參考位元線RBL[1]至RBL[3]、三 條遮蔽參考位元線SRBL1至SRBL3、三個參考頁緩衝區 RPB1至RPB3、複數個常態頁緩衝區PB、複數條參考字元 線RWLo'RWLi· · •及RWLn、一 參考串選擇線（reference string select line)RSSL及一參考地選擇線(reference ground select line)RGSL。每一常態頁緩衝區PB係經由一相應之常 態位元線BL與複數個串接之常態記憶胞NC相互耦合。該三 個參考頁緩衝區RPB1至RPB3均經由相應之參考位元線 RBL及相應之遮蔽參考位元線SRBL與複數個串接之參考 記憶胞RC相互耦合。每一參考字元線RWL、該參考串選擇 線RSSL及該參考地選擇線RGSL均電連接於同一列（same row)上之複數個參考記憶胞RC之控制閘極（control gate)， 然而卻與同一列上之一常態記憶胞NC之控制閘極相互電 絕緣。與該三條參考位元線RBL[1]至RBL[3]相關聯且位於 同一參考字元線（例如RWL〇，稱為一指定參考字元線）上之 三參考記憶胞RC係經由一預調程序（a trimming procedure) 分別被預調（pre-trimmed)至三個目標門檻電壓分佈，如圖1 之（A)、（B)及（C)狀態所示；而位於其他參考字元線（例如 RWL〗、RWL2 · · •及RWLn等）之其他參考記憶胞RC則寫 入（programmed)至（00)狀態，其門檻電壓係高於3.6V。位於 參考記憶胞區塊RBK中之常態記憶胞NC並沒有跟常態位 108367.doc -15- E39981 108367 1302312 * % 元線BL連接而參考位元線RBL則沒有跟常態記憶胞區塊 BK連接（參圖5)。於讀取操作（read operation)時，該指定參 考字元線與選定字元線（selected normal word line)具有相 同之電壓位準。於另一實施例中，每個常態頁緩衝區PB與 二條常態位元線相互耦合且該二條常態位元線之一係作為 一遮蔽位元線。另，參考記憶胞RC分成三組，每一組參考 記憶胞RC係與其相關聯之參考頁緩衝區RPB相互耦合；每 一組參考記憶胞RC均具有一預調門檻電壓分佈 (pre-trimmed threshold voltage distribution 5 即上述之目標 門檻電壓分佈），該預調門檻電壓分佈係區分該零狀態、該 第一狀態、該第二狀態及該第三狀態之門檻電壓分佈。例 如，若（11)、（10)、（01)及（00)狀態係分別對應於圖1所示之 門檻電壓分佈，則該三組參考記憶胞RC之該預調門檻電壓 分佈係對應於圖1中之（A)、（B)及（C)狀態。該（A)、（B)及（C) 三狀態則可用以區分（11)、（10)、（01)及（〇〇)狀態。特別值 得注意的是，於本發明中，每條參考位元線RBL、每條遮 蔽位元線SRBL及其相關聯之複數個參考記憶胞RC之佈局 (physical lay out)係與該常態位元線BL及其相關聯之該常 態記憶胞NC之佈局相同。圖7係該電壓產生器20電路之一 實施例。其包含一電壓單元24、一均壓器23、複數個電壓 選擇器22〇至22n&—總體字元線解碼器21。該電壓單元24 包含一藉由一第一節點242接地之電容器C、一電流源241 及一連接該電流源241之電壓源Vdd。該電流源241係經由一 第二節點243對該電容器C充電並於該第二節點生成該第一 108367.doc -16- E39981 108367 1302312 * % 電壓V。。該均壓器23係提供該提升字元線電壓VGWL，該 提升字元線電壓VGWL則係經該第一電壓Ve之等化 (equalized)而生成。位於該第二節點243之該第一電壓Vc被 線性增加並和該提升字元線電壓VGWL—起傳送至一比較 器231中。之後，該比較器231之輸出訊號GP0被送入一包含 二電晶體G1及G2之反相器，用以等化（equalize)該提升字元 線電壓VGWL及該第一電壓Ve。電壓選擇器22〇至22n則根據 字元線選擇訊號GPl〇至GPln將該提升字元線電壓VGWL送 至該選定字元線及該指定參考字元線；並傳送一逾越字元 線電壓（pass word line voltage)Vpp至複數條逾越字元線 (pass word line or unselected word line)及複數條非指定參 考字元線（unassigned word line)。其中該逾越字元線電壓 Vpp係大於4.0V以確保於本實施例中之所有常態記憶胞NC 於讀取操作時均可導通。該總體字元線解碼器21，係接收 一總體字元線位址（global word line address)並用以輸出該 字元線選擇訊號GPl〇至GPln。 同時參考圖7及圖8，該總體字元線解碼器21接收該總體 字元線位址之後，則根據該字元線選擇訊號GPl〇至GPln(例 如訊號GPl〇為高位準而訊號0?11至0卩111為低位準）決定那 一條字元線作為該選定字元線（例如WL〇)以接受該提升字 元線電壓VGWL ;而其他字元線（例如WLiSWLn)則作為逾 越字元線以接受該逾越字元線電壓Vpp。電壓選擇器22〇至 22n之輸出訊號GWL〇至GWLn於一區塊訊號BKS處於高位準 時（參圖8)被送至相應之字元線WL〇至WLn。藉此，該提升 108367.doc -17- E39981 108367 1302312 字元線電壓VGWL被傳送至該較字元線（例如机。）。意 即選疋字線電壓於該讀取操作中被提升。其中圖8 係表示連接該電壓產生器2〇及該常態記憶胞随之訊號 傳送圖。 圖9係應用於本發明之記憶胞陣 一實施例。該常態頁緩衝區3〇包含 一第一暫存器36、一第二暫存器351302312 * % Nine, the invention relates to: [Technical Field] The present invention relates to a NAND flash memory device read method and a memory cell array thereof a method for reading a multi-level-cell NAND type flash memory component for applying two-bit data to each memory cell and Memory cell array. > [Prior Art] - In a conventional NAND type flash memory, each memory cell can store two kinds of data states, and can also store an "on" state "state" or "off" state ( "OFF" state). Each bit of information is defined by the "on" and "off" states of individual memory cells. In conventional NAND type flash memory, in order to store N bit data (N is an integer greater than or equal to 2), N individual memory cells must be used. Therefore, if a conventional NAND type flash memory is used, when the number of data bits to be stored increases, the number B of memory cells must also increase. The information stored in a single-bit memory cell is determined by a programmed state of the memory cell, and the data is stored to the memory cell using a program action. The information stored in the memory state is determined by the threshold voltage of a transistor located in the memory cell. The threshold voltage is applied to a minimum voltage that can be turned on between the gate and the source of the transistor. Figure 1 shows a graph of the four threshold voltage distributions of a memory cell based on the data written. As shown in Figure 1, the data written can be expressed in the following four voltage distributions: E39981 108.^67 108367.doc 1302312: (1) Threshold voltage distribution less than -2.0V (volts), representative (11) (2) threshold voltage distribution between 0.7V and 1.1V, representing the binary data of (10); (3) threshold voltage distribution between 2.0V and 2.4V, The two-dimensional data representing (01) and (4) the threshold voltage distribution between 3.6V and 4.0V represent the two-dimensional data of (00). The data can be stored in a memory cell based on the four different threshold voltage distributions described above. Regarding a method of reading a NAND type flash memory device applied to a single level memory cell, a reading method has been proposed in U.S. Patent No. 6,671,204 (hereinafter referred to as '204). Figure 2 (&) shows *204 a page buffer, which is the flow of data described in a read operation. Figure 2(b) is a timing diagram of the associated signal of Figure 2(a). The detailed read operation is described below, wherein the data is assumed to be read from a memory cell (not shown) and the gate control signal of the read memory cell is used to apply an appropriate voltage to Its associated word line. The read operation is directly via a master register 150 and not via an associated register 170. In order to perform a stable read and write operation, the two bit lines BLE and BL0 are first discharged to the ground potential by the transistors N1 and N2, which switches the signals VBLe and VBLo to a high level and the signal VIRPWR to a low level. Quasi (or ground potential) (refer to phase 1 of Figure 2(b)). At the same time, the signal PBRST is switched from the high level to the low level to turn on the transistor N5, so that the main register 150 (or the input of an inverter 153) is set to a preset state (for example, a high level). . Then enter phase 2, a first control signal PLOAD is switched to the low level to conduct the transistor N9 and the control signal BLSHFe of the transistor N3 is maintained at a specific voltage (for example, 2.1V), the specific E39981 108307 108367.doc 1302312 voltage system The threshold voltage of the transistor N3 is the sum of the precharged voltage of the bit line BLE. After the bit line BLE is precharged with an appropriate voltage, the control signal BLSHFe is switched to the low level of the ground potential (refer to phase 3 of Figure 2(b)). In phase 3, one of the one-line precharge voltages changes with the state of a selected memory cell. For example, if the selected memory cell is an off cell (ie, the applied word line voltage is lower than the threshold voltage of the selected memory port), then the bit line (eg, bit line BLE) is pre-empted. The charging voltage will be maintained. If the selected memory cell is on cell (ie, the applied word line voltage is higher than the threshold voltage of the selected cell), the pre-charge of the bit line (eg, bit line BLE) The voltage will be discharged. If the control signal BLSHFe voltage becomes an intermediate voltage between the precharge voltage and the previous control signal BLSHFe voltage, when the selected memory cell is turned off, the voltage of a node SO will be maintained by turning off the transistor N3. Source voltage (Vce); otherwise the voltage of the node SO will be discharged through the bit line BLE. At a certain time point in phase 3 (when the voltage of the control signal BLSHFe falls to the ground potential), the first control signal PL0AD is switched to a high level. After that, enter phase 4. The signal PBLCHM rises to a high level to conduct the transistor N7 and the state of the transistor N6 (on or off) depends on the state of the node SO (high or low level). By this, the state of the node SO will be stored in the main register 150. Then, the data stored in the main register 150 is transferred to a data line 131 via the transistor N8 (controlled by the signal PBD1) and a Y-gating circuit 130. A multi-level cell reading method is disclosed in U.S. Patent No. 5,754,475 (hereinafter referred to as '475), which is incorporated herein by reference. Figure 3 is a simplified diagram of a read circuit associated with a memory cell in a block in '475. The memory cells MC11 to MCnm in the array 112 are arranged in a matrix. The memory cells MCI 1, MC12 · · · and MClm are arranged in the same column (row) and their selection terminals are connected to the same word line WLi; in the array 112, the remaining columns are arranged in this way. . In addition, memory cells MCI 1, MC21 · · · and MCnl; memory cells MC12, MC22 · · · · and MCn2; · · · and memory cells MClm, MC2m · · and MCnm, etc., are set in the same column (the same The respective columns and their data terminals are respectively connected to the same bit lines BLi, BL2, . . . and BLn. Each of the three reference bit lines 122a to 122c is used in a four-level cell. A reference cell RC is provided at the intersection of each of the reference bit lines 122 and each of the word lines WL. When the page program instruction is executed, the threshold voltage of the reference memory cell RC of the page is adjusted to a target value and the reference memory cell RC is simultaneously written with the normal cell MC. The reference memory cell RC has three threshold voltages RT0, RT1 and RT2 as shown in FIG. In order to distinguish the four states of a memory cell (ie, (11), (10), (〇1), and (00)), the read operation of the read method proposed by '475 must be repeated three times. , in which each read operation performs the six-stage action as shown in FIG. 2(b). In the first phase of the read operation, the most significant bit of the binary data stored in the memory cells in the (11), (10), (01), and (00) states. ; MSB) is read. In the second reading operation of E39981 108367 108367.doc 1302312 (phase two), the least significant bit of the binary data stored in the memory cells in the (11) and (1〇) states (least significant bh; LSB) is read. In the phase three read operation, the lowest bit of the binary data stored in the memory cells in the (01) and (00) states is read. Fig. 4(a) shows a sequence of three read operation sequences of the reading method in '475. U.S. Patent No. 5,768,188 (hereinafter referred to as '188) discloses a multi-level cell reading method. The reading method does not require the use of a reference memory cell but uses a read operation of applying different fixed word line voltages three times to distinguish memory cells in four different states. The order of reading operations is as follows. The lowest bit of the binary data stored in the memory cells in the (10) and (〇1) states is read in the first phase (phase one), and is applied to the selected word line ( The voltage on the selected word line) is 2 volts. Then, the highest bit of the binary data stored in the memory cells in the (11), (10), (01), and (〇〇) states is read in the second phase (phase two). The voltage applied to the selected word line at this time is 1 volt. Finally, in the third read phase, the lowest bit of the binary data stored in the memory cells in the (11) and (10) states is read, and the selected character is applied at this time. The voltage on the line is 0 volts. Fig. 4(b) shows a sequence of three read operations of the reading method in '188. A multi-layer cell reading method is disclosed in U.S. Patent Publication No. US 2005/0018488 (hereafter, 488). The reading method utilizes a read operation of applying different fixed word line voltages three times to distinguish memory cells in four different states without using a reference memory cell. The reading operation of the reading method is different from the reading operation sequence of '475 and '188. The order of its reading actions is as follows. The lowest bit of the binary data stored in the memory cells of the (01) and (00) states, and the lowest bit of the binary material stored in the memory cells of the (11) and (10) states and The highest bit of the binary data stored in the memory cells in the (11), (10), (01), and (〇〇) states is sequentially in the first, second, and third reading actions, respectively. The voltages that are read and applied to their respective word lines are 1, 2, and 3 volts, respectively. Fig. 4(c) shows a sequence of three read operations of the reading method in 488. A multi-level cell reading method is disclosed in U.S. Patent No. 5,986,929 (hereinafter referred to as 929). The reading method also utilizes a read operation of applying different fixed word line voltages three times to distinguish memory cells in four different states without using a reference memory cell. The reading operation sequence of the reading method is different from the reading operation sequence of '475, 4 88 and '488. The order of reading operations is as follows. The lowest bit of the binary data stored in the memory cells in the (11) and (1 〇) states is stored in the memory cells in the (11), (10), (01), and (00) states. The highest bit of the binary data and the lowest bit of the binary data stored in the memory cells in the (〇1) and (〇〇) states are sequentially read in the first, second and third respectively. The voltages that are read during the operation and applied to their respective word lines are 0, 1.2, and 2.4 volts, respectively. Fig. 4(d) shows a sequence of three read operations of the reading method in 929. SUMMARY OF THE INVENTION The main object of the present invention is to provide a multi-levei-ceii NAND type flash memory device reading method, which utilizes a plurality of reference cells associated with a reference cell. Article E39981 108307 108367.doc •11· 1302312 The reference bit line reads a plurality of normal memory cells in a single phase to reduce the reading time. Another object of the present invention is to provide a memoiry cell array related to the reading method, which uses a voltage generator and a plurality of reference memory cells to read a plurality of normal memory cells in a single phase. Further, the number of precharging and discharging of the normal bit line is reduced, thereby reducing the reading time. In order to achieve the above object, the present invention discloses a method for reading a NAND type flash memory device, which is applied to a multi-layer cell NAND type flash memory device including a plurality of normal memory cells. The reading method includes the steps of: (a) boosting a selected word line voltage for a predetermined period of time; and (b) reading in a zero state, a first state, a second state, and a The plurality of normal memory cells of the three states. The zero state, the first state, the second state, and the third state respectively represent a binary data stored in each of the plurality of normal memory cells. The present invention further discloses a memory cell array for use in a NAND type flash memory device. The memory cell array comprises (1) a plurality of normally arranged normal memory cell blocks, each of the normal memory cell blocks comprising a plurality of normal state memory cells, each of the normal state memory cell systems being in a zero state, a first state, and a a second state or a third state; (2) a plurality of reference memory cell blocks are disposed between the plurality of normal memory cell blocks; (3) a plurality of normal bit line systems and a mother of the plurality of normal states a memory cell block and a plurality of normal page buffer couplings; (4) a plurality of reference bit lines coupled to each of the plurality of reference memory cells and a plurality of reference page buffers; and (5) a voltage generation , 108367.doc E39981 108367 • 12- 1302312 1 % produces a boost word line voltage that acts on a selected word line for a predetermined period of time. The plurality of normal memory cells in the zero state, the first state, the second state, and the third state associated with the selected word line are read during the predetermined period. [Embodiment] Hereinafter, a memory cell array of the present invention will be described first to facilitate understanding of a method of reading a NAND type flash memory device of the present invention. Figure 5 is a memory cell array 10 in accordance with one embodiment of the present invention. In this embodiment, the memory cell array 10 includes: 1024 parallel normal channel cells (ΒΚ[0] to ΒΚ[1023]), and two 1024 normal memory cells (ΒΚ[0] Reference memory cell block (RBK[0] and RBK[1]) between ΒΚ[1023]) (ie RBK[0] is set between BK[255] and BK[256] and RBK[1] Set between BK[767] and BK[768], 8196 and each normal memory cell block and a plurality of normal page buffers (not shown) are coupled to the normal bit line (BL[0] to BL[8195]), three and two reference bit lines (RBL[1] to RBL[3]) and a voltage generator (the RBL[1] to RBL[3]) and the three reference page buffers (not shown) are coupled to each other ( The figure is not shown). Each normal memory cell block BK includes a plurality of normal memory cells (not shown) and each normal memory cell system is in a zero state, a first state, a second state, or a third state. In the present embodiment, the (11), (10), (01), and (00) states (see Fig. 1) are defined as the zero state, the first state, the second state, and the third state, respectively. The position of the reference memory cell RBK is set to reduce the normal bit line resistance-capacitance loading delay along the direction of the normal bit line BL to the original 丨J 〇, for example, this embodiment 108367.doc -13 - Ε39981 108367 1302312, the two reference memory blocks RBK[0] and RBK[1] are respectively set between ΒΚ[255] and ΒΚ[256] and ΒΚ[767] and ΒΚ[768], respectively. Any normal memory cell located on the upper half of the memory cell array 10 (i.e., any one of the upper half ΒΚ[0] to ΒΚ[5 11 ]) is selected for reading, and is located on the upper half The reference memory cell block RBK[0] will be active; similarly, when any of the normal memory cell blocks located on the lower half of the memory cell array 10 (ie, the lower half BK[512] to BK[ When any of 10B] is selected for the read operation, the reference memory cell block RBK[1] located on the lower half side will be activated. In addition, the size of each reference memory cell block RBK is the same as the size of each normal memory cell block BK and the number of reference word lines RBL in each reference memory cell block RBK and each normal memory. The number of normal word lines BL in the cell block BK is the same. The voltage generator generates a ramp-up word line voltage that acts on a selected word line for a predetermined period. And the plurality of normal memory cells in the zero state, the first state, the second state, and the third state associated with the selected word line are read during the predetermined period. The three reference bit lines RBL[1] through RBL[3] are coupled to three reference page buffers (not shown). In another embodiment, the reference bit line can be set to six; each of the two reference bit lines and a reference page buffer are combined with each other and one of the two reference bit lines is used as a masked reference bit line. In addition, the three reference bit lines RBL[1] to RBL[3] can be regarded as a reference group. In operation, each page can be based on the resistance value of the word line, the product of resistance and capacitance, and the rate of increase of the word line voltage (ramp_up 108367.doc -14- E39981 108367 1302312 rate of One or more reference groups are used for factors such as the word line voltage). 6 is an embodiment of a reference memory cell block RBK in FIG. The reference memory cell block RBK includes three reference bit lines RBL[1] to RBL[3], three masked reference bit lines SRBL1 to SRBL3, three reference page buffers RPB1 to RPB3, and a plurality of normal page buffers PB. And a plurality of reference character lines RWLo'RWLi·· and RWLn, a reference string select line (RSSL) and a reference ground select line (RGSL). Each normal page buffer PB is coupled to a plurality of serially connected normal cells NC via a corresponding normal bit line BL. The three reference page buffers RPB1 to RPB3 are coupled to a plurality of serially connected reference memory cells RC via respective reference bit lines RBL and corresponding masked reference bit lines SRBL. Each of the reference word line RWL, the reference string select line RSSL, and the reference ground select line RGSL are electrically connected to a control gate of a plurality of reference memory cells RC on the same row, but It is electrically insulated from the control gate of one of the normal memory cells NC in the same column. Three reference memory cell RCs associated with the three reference bit lines RBL[1] through RBL[3] and located on the same reference word line (eg, RWL〇, referred to as a designated reference word line) The trimming procedure is pre-trimmed to the three target threshold voltage distributions, as shown in (A), (B), and (C) of Figure 1, and at other reference word lines. Other reference memory cells, RC, such as RWL, RWL2, and RWLn, are programmed to the (00) state, with threshold voltages above 3.6V. The normal memory cell NC located in the reference memory cell block RBK is not connected to the normal bit 108367.doc -15-E39981 108367 1302312 * % cell line BL and the reference bit line RBL is not connected to the normal memory cell block BK ( See Figure 5). The designated reference word line has the same voltage level as the selected normal word line during a read operation. In another embodiment, each of the normal page buffers PB and the two normal bit lines are coupled to each other and one of the two normal bit lines is used as a mask bit line. In addition, the reference memory cell RC is divided into three groups, each group of reference memory cell RC lines and their associated reference page buffer RPB are coupled to each other; each group of reference memory cells RC has a pre-trimmed threshold voltage distribution (pre-trimmed threshold) The voltage distribution 5 is the target threshold voltage distribution described above, and the preset threshold voltage distribution distinguishes the threshold voltage distribution of the zero state, the first state, the second state, and the third state. For example, if the (11), (10), (01), and (00) states respectively correspond to the threshold voltage distribution shown in FIG. 1, the pre-adjusted threshold voltage distribution of the three sets of reference memory cells RC corresponds to The state of (A), (B) and (C) in Fig. 1. The three states (A), (B), and (C) can be used to distinguish between (11), (10), (01), and (〇〇) states. It is particularly worth noting that, in the present invention, each reference bit line RBL, each of the mask bit lines SRBL, and a plurality of associated reference memory cells RC (physical lay out) and the normal bit The layout of line BL and its associated normal memory cell NC is the same. Figure 7 is an embodiment of the voltage generator 20 circuit. It comprises a voltage unit 24, a voltage equalizer 23, a plurality of voltage selectors 22A to 22n&-the overall word line decoder 21. The voltage unit 24 includes a capacitor C grounded by a first node 242, a current source 241, and a voltage source Vdd connected to the current source 241. The current source 241 charges the capacitor C via a second node 243 and generates the first 108367.doc -16-E39981 108367 1302312 * % voltage V at the second node. . The voltage equalizer 23 provides the boost word line voltage VGWL, and the boost word line voltage VGWL is generated by equalization of the first voltage Ve. The first voltage Vc at the second node 243 is linearly increased and transmitted to a comparator 231 along with the boost word line voltage VGWL. Thereafter, the output signal GP0 of the comparator 231 is sent to an inverter including two transistors G1 and G2 for equalizing the boost word line voltage VGWL and the first voltage Ve. The voltage selectors 22A to 22n send the boost word line voltage VGWL to the selected word line and the designated reference word line according to the word line selection signals GP1〇 to GPln; and transmit a pass word line voltage ( Pass word line voltage) Vpp to pass word line or unselected word line and a plurality of undesigned word lines. The over-character line voltage Vpp is greater than 4.0V to ensure that all of the normal memory cells NC in the embodiment can be turned on during the read operation. The overall word line decoder 21 receives a global word line address and outputs the word line select signals GP1 to GPln. Referring to FIG. 7 and FIG. 8 , after receiving the overall character line address, the overall word line decoder 21 selects the signal GP1〇 to GPln according to the word line (for example, the signal GP1〇 is a high level and the signal 0 is? 11 to 0卩111 are low level) determining which word line is the selected word line (eg, WL〇) to accept the boost word line voltage VGWL; and other word lines (eg, WLiSWLn) as the pass character Line to accept the pass word line voltage Vpp. The output signals GWL〇 to GWLn of the voltage selectors 22A to 22n are supplied to the corresponding word lines WL〇 to WLn when a block signal BKS is at a high level (refer to Fig. 8). Thereby, the boost 108367.doc -17-E39981 108367 1302312 word line voltage VGWL is transmitted to the comparison word line (eg, machine.). This means that the selected word line voltage is boosted during the read operation. FIG. 8 is a diagram showing the connection of the voltage generator 2 and the normal memory cell followed by a signal transmission diagram. Figure 9 is an embodiment of a memory cell array applied to the present invention. The normal page buffer 3〇 includes a first register 36 and a second register 35.
列之常態頁緩衝區30之 一位元線選擇電路37、 、一第一控制電路33、 一第二控制電路34、一第一輸出電路31及一第二輸出電路 32 j位元線選擇電路37係決定一遮蔽位元線（於本實施例 係位兀線BLO)。該第一暫存器36及該第二暫存器35係用以 栓鎖（latch)—儲存於其相關聯之常態記憶胞中之二位元資 料。該第一控制電路33及該第二控制電路34根據一第一讀 取訊號R10、一第二讀取訊號们及一第三讀取訊號r〇i(參 圖11)將該二位元資料之最高位元及最低位元分別輸出至 該第一輸出電路31及該第二輸出電路32。One bit line selection circuit 37 of the normal page buffer 30, a first control circuit 33, a second control circuit 34, a first output circuit 31 and a second output circuit 32 j bit line selection circuit The 37 series determines a mask bit line (in the present embodiment, the tie line BLO). The first register 36 and the second register 35 are used to latch-binary data stored in its associated normal memory cell. The first control circuit 33 and the second control circuit 34 convert the two-bit data according to a first read signal R10, a second read signal, and a third read signal r〇i (refer to FIG. 11). The highest bit and the lowest bit are output to the first output circuit 31 and the second output circuit 32, respectively.
圖1 〇係應用於本發明之記憶胞陣列之參考頁緩衝區4〇之 一實施例。該參考頁緩衝區4〇包含一參考位元線選擇電路 43、一經由電晶體T5與該電壓源Vce耦合之調整電路 (trimming circuit)42 及一讀取預備電路（read ready cnxuit)41。該調整電路42係決定該預調門檻電壓分佈。該 躓取預備電路41係提供一第一控制訊號pL〇AD至複數個常 悲頁緩衝區30(參圖9)。於圖5所示之記憶胞陣列1〇之實施例 中，三條參考位元線RBL[1]至RBL[3]係分別與一參考頁緩 衝區40(參圖1〇)相互耦合，然而僅有與參考位元線 108367.doc 1302312 相互耦合之參考頁緩衝區40所產生之該第一控制訊號 PLOAD會傳送至與參考位元線RBL[1]相關聯之常態位元 線BL相互麵合之常態頁缓衝區3 0。與個別參考位元線 (RBL[1]、Brl[2]及RBL[3])相互耦合之參考頁緩衝區4〇中 之一反相器414之輸出訊號係藉由一外部電路（圖未示）分別 用以驅動（drive)該第一讀取訊號R10、該第二讀取訊號R2 及該第三讀取訊號R01。 圖11係圖9及圖10相關之訊號時序圖。本發明之多層次胞 NAND型快閃記憶體元件之讀取方法將根據圖u詳細說明 如下。該多層次胞NAND型快閃記憶體元件包含複數個常態 記憶胞。復參圖6，假設與參考頁緩衝區RPB1、rpb2及RPB3 相關聯之複數個參考記憶胞RC係分別被預調（pre七immed) 至如圖1所示之（A)、（B)及（C)狀態。在讀取操作之前，訊號 RESET(參圖9)切換至南位準以重置（reset)所有的常態記憶 胞NC且此時常態頁缓衝區30之栓鎖狀態為（1丨）；即 (Q2，Q1)=(0,0)。於階段1，假設位元線BLE被選定作為讀取 使用。首先，所有的常態位元線及參考位元線藉由觸發訊 號VBLE、VBLO及RVBL至高位準而放電至接地位準；同 時，訊號BLSHFE及RBLSHF切換至高位準，分別將節點SO 及RS0放電至接地位準。於階段2，訊號VBL0保持在高位 準（即Vcc)，將未選定位元線（unselected bit line)BL0接地以 作為一遮蔽位元線；同時，電晶體T2保持在導通狀態使得 該遮蔽參考位元線SRBL接地。然而；訊號VBLE及RVBL切 換至低位準且訊號PL0AD及RPL0AD被觸發至低位準，以 108367.doc -19- Ε39981 108367 1302312BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an embodiment of a reference page buffer 4 applied to a memory cell array of the present invention. The reference page buffer 4A includes a reference bit line selection circuit 43, a trimming circuit 42 coupled to the voltage source Vce via the transistor T5, and a read ready circuit (read ready). The adjustment circuit 42 determines the pre-tune threshold voltage distribution. The capture preparation circuit 41 provides a first control signal pL〇AD to a plurality of constant page buffers 30 (see Fig. 9). In the embodiment of the memory cell array shown in FIG. 5, the three reference bit lines RBL[1] to RBL[3] are respectively coupled to a reference page buffer 40 (refer to FIG. 1), but only The first control signal PLOAD generated by the reference page buffer 40 coupled to the reference bit line 108367.doc 1302312 is transferred to the normal bit line BL associated with the reference bit line RBL[1]. The normal page buffer is 3 0. The output signal of one of the reference page buffers 4 相互 coupled to the individual reference bit lines (RBL[1], Brl[2], and RBL[3]) is by an external circuit (not shown) The first read signal R10, the second read signal R2, and the third read signal R01 are respectively driven. FIG. 11 is a timing diagram of signals related to FIG. 9 and FIG. The method of reading the multi-layer cell NAND type flash memory device of the present invention will be described in detail with reference to Fig. 9 as follows. The multi-layer cell NAND type flash memory device includes a plurality of normal memory cells. Referring to Figure 6, it is assumed that the plurality of reference memory cell RC systems associated with the reference page buffers RPB1, rpb2, and RPB3 are pre-adjusted (pre seven immed) to (A), (B) as shown in FIG. (C) status. Before the read operation, the signal RESET (refer to FIG. 9) is switched to the south level to reset all the normal memory cells NC and the latch state of the normal page buffer 30 is (1丨); (Q2, Q1) = (0, 0). In Phase 1, it is assumed that the bit line BLE is selected for reading. First, all normal bit lines and reference bit lines are discharged to the ground level by triggering signals VBLE, VBLO, and RVBL to a high level; at the same time, signals BLSHFE and RBLSHF are switched to a high level, respectively discharging nodes SO and RS0. To the ground level. In phase 2, the signal VBL0 remains at a high level (ie, Vcc), and the unselected bit line BL0 is grounded as a mask bit line; at the same time, the transistor T2 remains in an on state such that the masked reference bit The source line SRBL is grounded. However, the signals VBLE and RVBL are switched to the low level and the signals PL0AD and RPL0AD are triggered to the low level to 108367.doc -19- Ε39981 108367 1302312
藉由該電壓源vcc對節點SO及RSO充電。訊號BLSHFE及 RBLSHF係被驅動至大約2.0V且訊號BbSHFO保持在低位 準，用以將位元線BLE及RBL分別預充電至一特定電壓位 準，其中該特定電壓位準係分別等於2.0V減掉電晶體M3及 Τ3之門檻電壓。一般情況下，位元線BLE及RBL上之電壓 位準大約為1.0V。於階段3，訊號RPLOAD被拉至高位準而 訊號BLSHFE切換至低位準以供位元線BLE上之常態記憶 胞進行訊號發展（signal development)。此時，訊號RBLSHF 之位準保持在2.0V且該選定字元線電壓（即圖11中之訊號 WL或上述之提升字元線電壓）緩慢上升。該選定字元線電 壓之提升速率（ramp-up rate)必須被適當地控制以提供足夠 的時序餘裕（timing margin)來彳貞側相鄰之兩狀態。例如，該 選定字元線電壓之提升速率為lV/2000ns(即每2000奈秒提 升一伏特）且圖1中（A)及（10)狀態間之電壓餘裕（voltage margin)為0.5V，因此所形成之時序餘裕（1000ns)已足夠偵 測處於（11)及（10)狀態的常態記憶胞。當該選定字元線電壓 介於0.2V至0.7V之間，則參考位元線RBL[1]將被放電，然 而參考位元線RBL[2]及RBL[3]則否。此時，與處於（11)狀 態之常態記憶胞相關聯之常態位元線也會被放電，但與處 於（10)、（01)或（00)狀態之常態記憶胞相關聯之常態位元線 則不被放電。在階段3結束時，參考位元線RBL[1]之位準被 放電至0.3V，該第一控制訊號Pl〇AD之位準將根據圖10中 該讀取預備電路41之邏輯而拉至高位準（代表訊號發展已 經完成）。注意，當參考位元線RBL[1]之位準被放電至0.3V 108367.doc -20- E39981 108367 1302312 時，與處於（11)狀態之常態記憶胞相關聯之常態位元線則會 被放電至0.3V以下，其係因為處於（11)狀態之常態記憶胞之 門檻電壓小於與該參考位元線RBL[1]相關聯之參考記憶胞 之門檻電壓。此時，訊號BLSFHE之位準被拉至1.3V。接著 進入階段4，該第一讀取訊號R10、該第二讀取訊號尺2及該 第三讀取訊號R〇 1藉由該外部電路被依序觸發。此外，於該 第一讀取訊號R10被觸發前可選擇性地設置一時間延遲 (time delay)Td。該第二讀取訊號R2及該第三讀取訊號 R01 (和該第一讀取訊號R10相同）係分別藉由該參考位元線 RBL[2]及RBL[3]上之一預定電壓位準（於本實施例中係 0.3V)所觸發。 圖12係圖11階段4期間之四個子階段狀態轉換圖，其係與 不同狀態之常態記憶胞相關聯之第一暫存器3 6及第二暫存 器35之狀態轉換圖。以下以訊號Q1&q2分別代表第一暫存 器36及第二暫存器35之狀態。於子階段4-〇中，暫存器Q2 及Q1均係處於低位準。於子階段4-1中，該選定字元線電壓 介於0.2V至0.7V之間，以導通處於（11)狀態之常態記憶胞且 此時該第一讀取訊號R1 〇以一脈衝高位準（pUlse high)之型 式被送出以栓鎖Q1之狀態。若欲被讀取之常態記憶胞處於 (11)狀態’則Q1之狀悲保持在低位準；然而，對於欲被讀 取之常態記憶胞處於（10)、（01)或（00)狀態，則其相應之Q1 之狀態將由低位準切換至高位準（參圖12之子階段4-1)。當 該選定字元線電壓介於1.5V至2.0V之間時，將導通處於（10) 狀態之常態記憶胞且參考位元線RBL[2]將被放電。當參考 108367.doc -21- E39981 108367 1302312 位元線RBL[2]放電至0.3V時，該第二讀取訊號尺2被送出以 栓鎖Q2之狀態’意即栓鎖該二位元資料之最高位元。若欲 被讀取之常態s己憶胞處於（01)或（〇〇)狀態，則其相應之Q2 狀態將切換至高位準；之後其相應之Qi狀能將重置至低位 準。若此時Q2狀態為低位準，則其相應之Q1狀態將保持在 原有狀態。藉此’處於（11)或（10)狀態之常態記憶胞可被偵 測出（參圖12之子階段4-2)。當該選定字元線電壓介於3.1V 至3.6V之間時，將導通處於（〇 1)狀態之常態記憶胞且參考位 元線RBL[3]將被放電。當參考位元線rbl[3]放電至0.3V 時，該第三讀取訊號R01被送出以栓鎖Qi之狀態。若此時 Q2為高位準，則處於（〇1)或（〇〇)狀態之常態記憶胞可以被偵 測出。意即，處於（00)狀態之常態記憶胞在該選定字元線電 壓（3· IV至3.6V)下無法被導通且節點SO處於高位準以導通 電晶體M10。當該第三讀取訊號R01被觸發時，Q1狀態將切 換至低位準（注意此時Q2狀態為高位準）。然而，對於處於 (〇 1)狀態之常態記憶胞，因其相應之節點SO被放電而無法 導通電晶體M10，則其相應之Q1狀態維持不變（參圖12之子 階段4-3)。此時，若Q2狀態為低位準，其相應之Q1狀態將 保持不變，因此，處於（11)或（10)狀態之常態記憶胞將保持 不變。從圖12中可知，處於零狀態（即（11)狀態）之常態記憶 胞、處於第一狀態（即（10)狀態）之常態記憶胞及處於第二狀 態（即（〇1)狀態）之常態記憶胞係分別於該第一讀取訊號 R10、該第二讀取訊號R2及該第三讀取訊號R01觸發後被讀 取。此外，處於第三狀態（即（00)狀態）之常態記憶胞係在該 108367.doc -22- E39981 108367 1302312 第三讀取訊號R01觸發後被讀取。復參圖11，於階段5中， 訊號 VBLE、VBLO、RVBL、BLSHFE、BLSHFO及RBLSHF 被觸發至高位準以分別導通電晶體Ml、M2、Tl、M3、M4 及T3以對位元線BLE及BLO及參考位元線RBL進行放電。此 時，該選定字元線電壓也被關閉。於階段6，所有的訊號被 關閉。 關於用以形成該預調門檻電壓分佈之該預調程序，其係 類似於常態記憶胞之寫入操作（program operation)及寫入 驗證操作（program verify operation)。該預調程序包含步 驟：（a)提供處於抹除狀態（erased state)之該複數個參考記 憶胞；（b)調整（trimming)與一參考位元線相關聯之該複數個 參考記憶胞；（c)確認（verify)與該參考位元線相關聯之該複 數個參考記憶胞；以及（d)重覆步驟（b)及（c)直到與該參考位 元線相關聯之該複數個參考記憶胞調整完畢。復參圖10， 於步驟（b)中，訊號RRST被觸發至脈衝高位準（pulse high) 將一節點RQ設定至低位準；之後，訊號RPGM及RBLSHF 被觸發至高位準將節點RQ之位準傳送至參考位元線RBL。 若節點RQ為高位準，則與參考位元線RBL相關聯之參考記 憶胞之調整（trimming，於此相當於寫入）動作將被禁止；若 節點RQ為低位準，則上述之調整動作將被允許。於步驟 (c)，訊號TPV於寫入驗證操作時，保持在高位準，用以栓 鎖參考記憶胞之狀態。若該參考記憶胞被寫入至具有一大 於該選定參考字元線電壓（selected reference word line voltage)之門檻電壓，則參考位元線RBL將無法放電且節點 E39981 108367 108367.doc 胃 23. 1302312 RQ之狀態將由低位準切換至高位準；如此，便可防止對該 參考記憶胞作進一步的寫入動作。對於與三條參考位元線 RBL[1]至RBL[3]相關聯之參考記憶胞，於寫入驗證操作 時，係分別施加電壓位準RT0、RT1及RT2(參圖丨）於其相應 之選定參考字元線（selected reference word line)。一旦該來 考記憶胞之寫入驗證通過，其相應之節點RQ將被設定為高 位準’藉此防止進一步的調整（或寫入）動作。該電壓位準 RT0、RT1及RT2係循序施加於該選定參考字元線。此外， 在該預調程序中，每次的寫入時間（program time of one sh〇t) 均被適當控制以限制該預調門檻電壓分佈之電壓分佈寬 度。 本發明之技術内容及技術特點已揭示如上，然而熟悉本 項技術之人士仍可能基於本發明之教示及揭示而作種種不 背離本發明精神之替換及修飾。因此，本發明之保護範圍 應不限於實施例所揭示者，而應包括各種不背離本發明之 替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡單說明】 圖1係一記憶胞之四種門檻電壓分佈圖； 圖2(a)係習知技藝中之頁緩衝區； 圖2(b)係圖2(a)相關訊號之時序圖； 圖3係習知技藝中之與一區塊中之記憶胞相關聯之讀取 電路簡化圖； 圖4(a)至4(d)分別係習知技藝中讀取方法之三次讀取動 作順序圖； E39981 108367 108367.doc -24- 1302312 圖5係本發明一實施例之記憶胞陣列； 圖6係圖5中之參考記憶胞區塊之一實施例； 圖7係本發明之電壓產生器電路之一實施例； 圖8係本發明之電壓產生器及常態記憶胞區之訊號傳送 圖； 圖9係使用於本發明之記憶胞陣列之常態頁緩衝區之一 實施例； 圖10係使用於本發明之記憶胞陣列之參考頁缓衝區之一 實施例； 圖11係圖9及圖1〇相關之訊號時序圖；以及 圖12係圖11階段4期間之四個子階段狀態轉換圖。 【主要元件符號說明】 10 記憶胞陣列 20 電壓產生器 22(r ^22η電壓選擇器 21 總體子元線解碼器 23 均壓器 24 電壓單元 30 常態頁緩衝區 31 第一輪出電路 32 第二輸出電路 33 第一控制電路 34 第二控制電路 35 苐一暫存器 36 第一暫存器 37 位元線選擇電路 40 參考頁緩衝區 41 讀取預備電路 42 調整電路 43 參考位元線選擇電3 112 陣列 122a '〜122c參考位元線 108367.doc E39981 108367 -25- 1302312 * %The node SO and the RSO are charged by the voltage source vcc. The signals BLSHFE and RBLSHF are driven to approximately 2.0V and the signal BbSHFO is kept at a low level for precharging the bit lines BLE and RBL to a specific voltage level, respectively, wherein the specific voltage level is equal to 2.0V, respectively. The threshold voltage of the falling transistors M3 and Τ3. In general, the voltage level on the bit lines BLE and RBL is approximately 1.0V. In phase 3, the signal RPLOAD is pulled to a high level and the signal BLSHFE is switched to a low level for normal signal generation on the bit line BLE for signal development. At this time, the level of the signal RBLSHF is maintained at 2.0 V and the selected word line voltage (i.e., the signal WL in FIG. 11 or the above-mentioned boost word line voltage) rises slowly. The ramp-up rate of the selected word line voltage must be properly controlled to provide sufficient timing margin to align the two adjacent states. For example, the selected word line voltage has a rate of increase of 1V/2000ns (ie, one volt per 2000 nanoseconds) and the voltage margin between the (A) and (10) states in FIG. 1 is 0.5V, thus The resulting timing margin (1000 ns) is sufficient to detect normal memory cells in the (11) and (10) states. When the selected word line voltage is between 0.2V and 0.7V, the reference bit line RBL[1] will be discharged, but the reference bit lines RBL[2] and RBL[3] will be no. At this time, the normal bit line associated with the normal memory cell in the (11) state is also discharged, but the normal bit associated with the normal memory cell in the (10), (01) or (00) state. The line is not discharged. At the end of phase 3, the level of the reference bit line RBL[1] is discharged to 0.3V, and the level of the first control signal P1〇AD will be pulled to the high level according to the logic of the read preparation circuit 41 in FIG. Standard (on behalf of the signal development has been completed). Note that when the level of the reference bit line RBL[1] is discharged to 0.3V 108367.doc -20- E39981 108367 1302312, the normal bit line associated with the normal memory cell in the (11) state will be The discharge is below 0.3V because the threshold voltage of the normal memory cell in the (11) state is less than the threshold voltage of the reference memory cell associated with the reference bit line RBL[1]. At this point, the level of the signal BLSFHE is pulled to 1.3V. Then, in the fourth stage, the first read signal R10, the second read signal level 2 and the third read signal R〇1 are sequentially triggered by the external circuit. In addition, a time delay Td can be selectively set before the first read signal R10 is triggered. The second read signal R2 and the third read signal R01 (same as the first read signal R10) are respectively predetermined by a predetermined voltage bit on the reference bit lines RBL[2] and RBL[3]. Triggered by (0.3V in this embodiment). Figure 12 is a diagram showing four sub-phase state transitions during phase 4 of Figure 11 as a state transition diagram for the first register 36 and the second register 35 associated with normal state cells of different states. Hereinafter, the states of the first temporary register 36 and the second temporary register 35 are represented by signals Q1 & q2, respectively. In the sub-stage 4-〇, the registers Q2 and Q1 are both at a low level. In sub-phase 4-1, the selected word line voltage is between 0.2V and 0.7V to turn on the normal memory cell in the (11) state and the first read signal R1 〇 is at a pulse high level. The type of pUlse high is sent out to lock the state of Q1. If the normal memory cell to be read is in the (11) state, then the sorrow of Q1 remains at a low level; however, for the normal state memory cell to be read is in the (10), (01) or (00) state, Then the state of its corresponding Q1 will be switched from the low level to the high level (see sub-stage 4-1 of Figure 12). When the selected word line voltage is between 1.5V and 2.0V, the normal memory cell in the (10) state will be turned on and the reference bit line RBL[2] will be discharged. When the reference 108367.doc -21- E39981 108367 1302312 bit line RBL[2] is discharged to 0.3V, the second read signal ruler 2 is sent out to latch the state of Q2 'meaning that the two-bit data is latched The highest bit. If the normal state to be read is in the (01) or (〇〇) state, its corresponding Q2 state will switch to the high level; then its corresponding Qi shape will be reset to the low level. If the Q2 state is low, the corresponding Q1 state will remain in the original state. The normal memory cell in the state of (11) or (10) can be detected (see sub-phase 4-2 of Fig. 12). When the selected word line voltage is between 3.1V and 3.6V, the normal memory cell in the (〇 1) state will be turned on and the reference bit line RBL[3] will be discharged. When the reference bit line rbl[3] is discharged to 0.3V, the third read signal R01 is sent out to latch the state of Qi. If Q2 is at a high level at this time, the normal memory cell in the (〇1) or (〇〇) state can be detected. That is, the normal memory cell in the (00) state cannot be turned on at the selected word line voltage (3·IV to 3.6V) and the node SO is at a high level to turn on the transistor M10. When the third read signal R01 is triggered, the Q1 state will switch to the low level (note that the Q2 state is high). However, for a normal memory cell in the (〇 1) state, since its corresponding node SO is discharged and cannot conduct the crystal M10, its corresponding Q1 state remains unchanged (see sub-phase 4-3 of Fig. 12). At this time, if the Q2 state is low, its corresponding Q1 state will remain unchanged, and therefore, the normal memory cell in the (11) or (10) state will remain unchanged. As can be seen from FIG. 12, the normal memory cell in the zero state (ie, the (11) state), the normal memory cell in the first state (ie, the (10) state), and the second state (ie, the (〇1) state) The normal memory cell is read after the first read signal R10, the second read signal R2, and the third read signal R01 are triggered. Further, the normal memory cell in the third state (i.e., the (00) state) is read after the trigger of the third read signal R01 of the 108367.doc -22-E39981 108367 1302312. Referring to FIG. 11, in phase 5, signals VBLE, VBLO, RVBL, BLSHFE, BLSHFO, and RBLSHF are triggered to a high level to respectively conduct the transistors M1, M2, T1, M3, M4, and T3 to the bit line BLE and The BLO and the reference bit line RBL are discharged. At this time, the selected word line voltage is also turned off. In phase 6, all signals are turned off. The presetting procedure for forming the pre-tune threshold voltage distribution is similar to a normal operation of a normal memory cell and a program verify operation. The preconditioning procedure includes the steps of: (a) providing the plurality of reference memory cells in an erased state; and (b) trimming the plurality of reference memory cells associated with a reference bit line; (c) verifying the plurality of reference memory cells associated with the reference bit line; and (d) repeating steps (b) and (c) until the plurality of reference bit lines are associated The reference memory cell is adjusted. Referring to FIG. 10, in step (b), the signal RRST is triggered to the pulse high level to set a node RQ to a low level; after that, the signals RPGM and RBLSHF are triggered to the level of the high level node RQ. To the reference bit line RBL. If the node RQ is at a high level, the adjustment of the reference memory cell associated with the reference bit line RBL (trimming, this is equivalent to writing) will be prohibited; if the node RQ is low, the above adjustment action will be allowed. In step (c), the signal TPV remains at a high level during the write verification operation to latch the state of the reference memory cell. If the reference memory cell is written to have a threshold voltage greater than the selected reference word line voltage, the reference bit line RBL will not be discharged and the node E39981 108367 108367.doc stomach 23.1302312 The state of the RQ will be switched from the low level to the high level; thus, further writing to the reference memory cell can be prevented. For the reference memory cells associated with the three reference bit lines RBL[1] through RBL[3], voltage write levels RT0, RT1, and RT2 are applied to the corresponding write operations during the verify operation. The selected reference word line is selected. Once the write verification of the memory cell is passed, its corresponding node RQ will be set to a high level' thereby preventing further adjustment (or write) actions. The voltage levels RT0, RT1, and RT2 are sequentially applied to the selected reference word line. Further, in the presetting procedure, each program time of one sh〇t is appropriately controlled to limit the voltage distribution width of the pre-tune threshold voltage distribution. The technical contents and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims. [Simple diagram of the diagram] Figure 1 is a four-threshold voltage distribution diagram of a memory cell; Figure 2 (a) is a page buffer in the prior art; Figure 2 (b) is a timing diagram of the correlation signal of Figure 2 (a) Figure 3 is a simplified diagram of a read circuit associated with a memory cell in a block in the prior art; Figures 4(a) through 4(d) are three readings of a read method in the prior art, respectively. FIG. 5 is a memory cell array according to an embodiment of the present invention; FIG. 6 is an embodiment of a reference memory cell block in FIG. 5; FIG. 7 is a voltage of the present invention. One embodiment of the generator circuit; FIG. 8 is a signal transmission diagram of the voltage generator and the normal memory cell region of the present invention; FIG. 9 is an embodiment of a normal page buffer used in the memory cell array of the present invention; One embodiment of a reference page buffer used in the memory cell array of the present invention; FIG. 11 is a timing diagram of the signals associated with FIG. 9 and FIG. 1; and FIG. 12 is a four-phase state transition during phase 4 of FIG. Figure. [Main component symbol description] 10 Memory cell array 20 Voltage generator 22 (r ^ 22η voltage selector 21 Overall sub-line decoder 23 Voltage equalizer 24 Voltage unit 30 Normal page buffer 31 First round-out circuit 32 Second Output circuit 33 first control circuit 34 second control circuit 35 first register 36 first register 37 bit line selection circuit 40 reference page buffer 41 read preparation circuit 42 adjustment circuit 43 reference bit line selection 3 112 Array 122a '~122c Reference Bit Line 108367.doc E39981 108367 -25- 1302312 * %
130 Y閘電路 131 資料線 150 主暫存器 170 附屬暫存器 231 比較器 241 電流源 242 第一節點 243 第二節點 351、 352 、 361' 362、 ，411 、412 反相器 413、 414 、 415 、 421、 422 反相 器 416、 417 、 418 NAND邏輯閘 BK、 ΒΚ[0]〜BK[1023] 常態記憶 胞區塊 BKS 區塊訊號 BL、 BL[0]〜BL[8195] 常態 ,位元線 BLE 、BLO 位元線 G1〜G4 電晶體 GS 地選擇訊號 GSL 地選擇線 Ml〜M18 電晶體 MC 記憶胞 N1〜 N8 電晶體 NC 常態記憶胞 PB 常態頁緩衝區 RBK[0]〜RBK[1] 參考記憶胞區塊 RBL[1]〜RBL[3] 參考位元線 RC 參考記憶胞 RGSL 參考地選擇線 RPB1〜RPB3 參考頁缓衝區RSO、SO 節點 RSSL 參考串選擇線 RWL〇〜RWLn 參考字元線 SRBL1〜SRBL3 遮蔽位元線SS 串選擇訊號 108367.doc -26- 1302312 f Ιί130 Y gate circuit 131 data line 150 main register 170 auxiliary register 231 comparator 241 current source 242 first node 243 second node 351, 352, 361' 362, 411, 412 inverter 413, 414, 415, 421, 422 inverter 416, 417, 418 NAND logic gate BK, ΒΚ[0]~BK[1023] Normal memory cell block BKS block signal BL, BL[0]~BL[8195] Normal, bit Element line BLE, BLO bit line G1~G4 transistor GS ground selection signal GSL ground selection line M1~M18 transistor MC memory cell N1~ N8 transistor NC normal memory cell PB normal page buffer RBK[0]~RBK[ 1] Reference memory block RBL[1]~RBL[3] Reference bit line RC Reference memory cell RGSL Reference ground selection line RPB1~RPB3 Reference page buffer RSO, SO node RSSL Reference string selection line RWL〇~RWLn Reference character line SRBL1 to SRBL3 Shield bit line SS string selection signal 108367.doc -26- 1302312 f Ιί
SSL 串選擇線 T1〜T13 電晶體SSL string selection line T1~T13 transistor
Vcc、Vdd、vss 電壓源 vpp 逾越字元線電壓 WL〇〜WLn 字元線 108367.doc -27-Vcc, Vdd, vss voltage source vpp Overpass word line voltage WL〇~WLn word line 108367.doc -27-