伽m twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種薄膜電晶體(tWn mm transist〇r， 及其製造方法，且特別是有關於一種可提高驅動電流 之薄膜電晶體及其製造方法。 * 【先前技術】 屏下近ΐΐΐΐΪ位時代的來臨，平面顯示器市場蓬勃發 ^ ^mZ ;、的平面液示器的需求急劇的成長， 二資訊產品、筆記型_、數位相機等 雨後春®般的出現帶給人們更便利的生活。 矚目。。夕4穎的製作技術與薄膜電晶體的相關研究備受 ，為了α應大尺寸畴析度的液晶電視的要求，目前 產非膜電晶體㈣TFT)較符合大面積化生 薄膜+ 了麵大面積高解析度的要求，非晶石夕 ί Jr要求曰益增進，除了本身的導線與 析产生^RC延遲的影響外，為因應大面積化高解 動率，來達到較高的驅動電載= 體應用在大/小面積; 驅動電路及元件改善補償元件啟始 也叫娜所及編的問題。 本發明的目的就是在提供一種薄膜電晶體，可應用於 1302032 16989twf.doc/006 薄膜電晶體之通道層製作_電晶體，所以 能帶的差異，形成“的超^格 率達到高 曰聛可、壁担九〜上 肉儿本發明之薄膜電 im 薄膜電晶體結構與财之I-d-in ===atiMI4__w咖在 諸為ΐίΪΓ之上述和其他目的、特徵和優點能更明顯 錄下文特舉紐實施例，並配合所_式，作詳細說 明如下。 【實施方式】 圖1是依照本發明-較佳實施例之一種薄膜電晶體的 剖面示意圖。 睛參照圖1，本實施例之薄膜電晶體包括基板1〇〇、第 一閘極102、閘極介電層1〇4、多通道層㈨汕“匕仙以 layer)l〇6、歐姆接觸層108以及源極金屬層11〇&與汲極金 屬層ii〇b所構成。其中，第一閘極102是位於基板1〇〇 上，且通常於基板100與第一閘極1〇2之間會有一層緩衝 層101。閘極介電層104則是覆蓋於第一閘極1〇2上，其 中閘極介電層104的材質例如是氧化矽或氮化矽，且其厚 度例如約在300nm〜400麵之間。而多通道層106位於第 一閘極102上方的閘極介電層1〇4上，其是由兩兩相疊的 非晶矽(a-Si)薄膜116a以及非晶矽鍺(a_siGe)薄膜110b所 構成’如圖2所示。圖2是圖1的第π部分之放大示意圖， 1302032 16989twf.doc/006 雖然在圖2中顯示先形成一層非晶矽薄膜丨丨如再形成一層 非晶梦鍺薄膜116b(亦即a-Si/a-SiGe)的形式，但是也可^ 用先形成-層非晶石夕錯薄膜再形成一層非晶石夕薄膜(亦= a-SiGe/a-Si)的形式，以便用於電子型(n々pe)或是電洞型 (P-type)薄膜電晶體。由於前述非晶矽及非晶矽鍺間能帶的 差異會形成超晶格(SuPperlattice)之結構，因此可因量子效 應而造成較高載子(η型或p型)移動率，達到高 元件特性。此外，多通道層刚的厚度例如動是屯二 50nm〜20〇nm之間，而每一非晶矽薄膜丨丨如的厚度約在％ 埃〜50埃之間、每一非晶石夕錯薄膜⑽的厚度約在2 〜50埃之間。 請再參照圖1’其中的歐姆接觸層1〇8與多通道声應 接觸且位於第-閘極搬兩側的閘極介電層刚上 ^接觸層應的材⑽如是摻雜非晶㈣摻雜非^ 鍺丄且歐姆接觸層的厚度約在3Gnm〜5Gnm之間。 金屬層110a與汲極金屬層11%是分別位於第一閘極 ==接;=上。此外，本實施例的薄膜電晶體 包括-層位於多通道層刚上的保護層ιΐ4以及位 於弟- 102上方的保護層114上的另―個第 的㈣❹是氧切(恥X)或氮化石夕 ，’而保隻層114的厚度例如約在鳥以〜綠 L = 來，將可以有效增力W件之載子移動率，達到 f丄6動電紅元件躲。不僅如此，若第二 112 ^ 透光的金屬時’將能更有效的_正關散射狀射所產 16989twf.doc/006 生之凡件光漏電的現象。因此，本實施例所提之薄膜電晶 體I明顯提升元件之驅動電流L，而在元件光漏電^上 也得了附加的抑制效果。 ^圖3A至圖3D是依照本發明另一較佳實施例夂一種薄 膜電晶體的製造流程剖面圖。 請參照圖3A，先提供一基板3〇〇,且基板3〇〇上通常 已具有一層緩衝層301。之後，於基板3⑻上形成一第一 閘極302，且其步驟譬如是先以濺鍍或蒸鍍的方式沉積一 閘，金屬，再以微影方式蝕刻定義出這個閘極302。接著， =第-祕3〇2上例如以電漿化學氣相沉積製程形成閘極 鲕爹版圖，利用如化學氣相沉積製程或電漿 ^方式於閘極介電層遍上形成-多層結構層306，其中 =結構層306是由兩兩相疊的多層非晶砍薄膜31如以及 t二ί日日秒錯薄膜316t>所構成。之後，於多層結構層3〇6 ^成Γ保護層綱，而形成保護層之步驟例如電裝 化孥氣相沉積製程。 水 ’請參照圖3C，定義保護層308(請見圖3B)與多 二=306(請見圖3B)，以於第一閘極3〇2上方 成—多通道層3G6a，而在多通道層⑽ —歐姆接觸層310，霜苔/ / 上升乂成 且形成歐二;=二層3°8,極介電層3〇4’ 程沉積摻雜非晶彻雜二化:氣相沉積製 开日日7鍺。釦之，於歐姆接觸層 310上利用濺鍍或蒸鍍形成一金屬層312。 接著，請參照圖犯，定義金屬層312，以於第-閉極 =2兩側的歐姆接觸層31〇上形成源極金屬層3i2a與汲極 孟j層^12b。接著，去除暴露出的歐姆接觸層。此外， 在這個實施例中，可以在上述定義金屬層312的同時於第 間極302上方的歐姆接觸層310上形成-第二間極 312c。 綜上所述，本發明之特點在於·· ,1.本發明利用互相交疊之非晶石夕薄膜與非晶石夕錯薄膜 a ia SiGe或a-SiGe/a-Si)所形成的多層超晶格結構，因 增加元件之載子移動率，達到高驅動電流工加 2.此外，本發明之薄膜電晶體在元件光漏電Ioff上也得 =加的抑制效果’因此對於應用在大面積高解析度的液 =二面顯示器將有許多的優點。而與平面顯示器之遮光結 樹亦即閘極面積大於主祕面積，又稱151齡叫及通道 保護層（Channel_Passivati〇n)的結構製程相容 量產的考量。 ㈣於 士 a t本發明逛可搭配雙閘極(D〇Uble_gate)的方式。由於同 有兩條通道產生，目此將更加容㈣細 子移動率及薄膜電晶體的驅動電流。 θ 牛之載 4.本發明之薄膜電晶體可形成電子型Mype)或是電 洞型(p-type)薄膜電晶體，因而可用於大面積化發 極體之驅動電路及元件。 *尤一 11 之一種薄膜電晶體的Gam twf.doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor (tWn mm transist〇r, and a method of fabricating the same, and particularly to an improved driving current) Thin film transistor and its manufacturing method. * [Prior Art] The advent of the era of near-screen era, the flat-panel display market is booming ^ ^mZ; the demand for flat liquid display is growing rapidly, two information products, notebook type _, digital camera, etc. After the rain, the appearance of the spring has brought people a more convenient life. Eyes.. Xi 4 Ying's production technology and thin film transistor related research, in order to α should be large size domain resolution LCD TV Requirement, the current production of non-film transistor (four) TFT) is more in line with the requirements of large-area biofilms + large-area high-resolution surface, and the increase in the demand for amorphous steel, in addition to its own wire and precipitation, RC delay In addition to the impact, in order to respond to large area high deactivation rate, to achieve higher drive electric load = body application in large / small area; drive circuit and component improvement compensation components also started to be called Na and edited question. The object of the present invention is to provide a thin film transistor which can be applied to the channel layer of the 1302032 16989 twf.doc/006 thin film transistor to form a transistor, so that the difference in the band can be formed to achieve a "super high rate". The wall film of the invention is the same as the above-mentioned and other purposes, features and advantages of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a thin film transistor according to a preferred embodiment of the present invention. FIG. 1 is a perspective view of a thin film transistor of the present embodiment. The substrate 1A, the first gate 102, the gate dielectric layer 1〇4, the multi-channel layer (9), the “layer”, the ohmic contact layer 108, and the source metal layer 11〇& The base metal layer is composed of ii〇b. The first gate 102 is located on the substrate 1A, and a buffer layer 101 is generally disposed between the substrate 100 and the first gate 1〇2. The gate dielectric layer 104 is overlying the first gate 1〇2, wherein the gate dielectric layer 104 is made of, for example, tantalum oxide or tantalum nitride, and has a thickness of, for example, between about 300 nm and 400 mm. The multi-channel layer 106 is located on the gate dielectric layer 1〇4 above the first gate 102, which is an amorphous germanium (a-Si) film 116a and an amorphous germanium (a_siGe) film which are stacked one on another. The composition of 110b is shown in Figure 2. 2 is an enlarged schematic view of the πth portion of FIG. 1, 1302032 16989 twf.doc/006. Although FIG. 2 shows that an amorphous germanium film is formed first, for example, an amorphous nightmare film 116b is formed (ie, a-Si). /a-SiGe), but it can also be formed into a layer of amorphous austenitic film (also = a-SiGe/a-Si) by using a first-layer amorphous thin film to be used for electronic type. (n々pe) or a P-type thin film transistor. Since the difference between the amorphous germanium and the amorphous inter-turn energy band forms a structure of a superlattice (SuPperlattice), a higher carrier (n-type or p-type) mobility can be caused by a quantum effect, and a high component is achieved. characteristic. In addition, the thickness of the multi-channel layer is, for example, between 5050 nm and 20 〇nm, and each amorphous thin film has a thickness of about ≥50 angstroms, and each amorphous ray is wrong. The film (10) has a thickness of between about 2 and 50 angstroms. Referring again to FIG. 1 'the ohmic contact layer 1 〇 8 and the multi-channel acoustic contact should be in contact with the gate dielectric layer on both sides of the first gate transfer, the material (10) of the contact layer should be doped amorphous (four) The doping is ^ and the thickness of the ohmic contact layer is between about 3Gnm and 5Gnm. The metal layer 110a and the drain metal layer 11% are respectively located at the first gate == junction; In addition, the thin film transistor of the present embodiment includes a protective layer ι 4 in which the layer is located on the multi-channel layer and another (four) ytterbium on the protective layer 114 above the 228-102 is oxygen cut (sharp X) or nitride. On the eve, 'while the thickness of the layer 114 is only about ~L green L =, it will be able to effectively increase the carrier mobility of the W piece, and reach the f丄6 moving red component to hide. Not only that, if the second 112 ^ light-transmissive metal will be more effective _ positive-off scattering shot produced 16989twf.doc/006 phenomenon of light leakage. Therefore, the thin film transistor I of the present embodiment significantly increases the driving current L of the element, and an additional suppressing effect is obtained on the element light leakage. 3A to 3D are cross-sectional views showing a manufacturing process of a thin film transistor in accordance with another preferred embodiment of the present invention. Referring to Figure 3A, a substrate 3 is provided first, and the substrate 3 has a buffer layer 301 thereon. Thereafter, a first gate 302 is formed on the substrate 3 (8), and the steps are as follows: first depositing a gate by sputtering or evaporation, metal, and lithographically etching to define the gate 302. Then, on the first-secret 3〇2, a gate electrode layout is formed, for example, by a plasma chemical vapor deposition process, and is formed on the gate dielectric layer by a chemical vapor deposition process or a plasma method. Layer 306, wherein = structural layer 306 is comprised of a plurality of layers of a plurality of layers of amorphous chopped film 31, such as t and a second film 316t. Thereafter, the multi-layer structure layer 3 is formed into a protective layer, and the step of forming a protective layer is, for example, an electrical vapor deposition process. Water 'Please refer to Figure 3C, defining a protective layer 308 (see Figure 3B) and more than two = 306 (see Figure 3B) to form a multi-channel layer 3G6a over the first gate 3〇2, while in multiple channels Layer (10) - ohmic contact layer 310, frost moss / / rising and forming ohmic; = two layers of 3 ° 8, very dielectric layer 3 〇 4 ' process deposition doping amorphous heterodimerization: vapor deposition 7 days on the opening day. Alternatively, a metal layer 312 is formed on the ohmic contact layer 310 by sputtering or evaporation. Next, referring to the figure, the metal layer 312 is defined to form the source metal layer 3i2a and the drain electrode layer j12b on the ohmic contact layer 31〇 on both sides of the first-closed pole=2. Next, the exposed ohmic contact layer is removed. Further, in this embodiment, the second interpole 312c may be formed on the ohmic contact layer 310 above the interpole 302 while defining the metal layer 312 as described above. In summary, the present invention is characterized in that: 1. The present invention utilizes a plurality of layers formed by mutually overlapping amorphous austenite films and amorphous austenite films a ia SiGe or a-SiGe/a-Si). The superlattice structure increases the carrier mobility of the element and achieves a high driving current. 2. In addition, the thin film transistor of the present invention also has an additive suppression effect on the element light leakage Ioff', so that it is applied to a large area. High resolution liquid = two-sided display will have many advantages. The shading tree with the flat panel display, that is, the gate area is larger than the main secret area, is also called the 151-year-old channel protection layer (Channel_Passivati〇n) structural process compatible mass production considerations. (4) Yu Shi a t This invention can be used with a double gate (D〇Uble_gate). Since the same two channels are generated, it is more convenient to (4) the fine mobility and the driving current of the thin film transistor. θ cattle carrier 4. The thin film transistor of the present invention can form an electronic type Mype or a p-type thin film transistor, and thus can be used for driving circuits and components of a large-area emitter. *A special film of a thin film transistor
1302032 • 1 〇989twf.doc/006 雖然本發明已以較佳實施例揭露如上，然其並非用r 限定本發明，任何熟習此技藝者，在不脫離本發明之^ 和範圍内，當可作些許之更動與潤飾，因此本發明 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是依照本發明一較佳實施例 剖面示意圖。 圖2是圖1的第π部分之放大示意圖。 ★圖3A至圖3〇τξ：依照本發明另一較佳實施例之—種 膜電晶體的製造流程剖面圖。 、 【主要元件符號說明】 100、300 :基板 101、 301 :缓衝層 102、 302 :第一閘極 104、304 :閘極介電層 106、306a :多通道層 108、310 :歐姆接觸層 110a、312a ·源極金屬屬 11 Ob、312b ·>及極金屬層 112、312c :第二閘極 114、308、308a :保護層 116a、316a .非晶碎薄膜 116b、316b ·非晶發錯薄膜 306 :多層結構層 ' 312 :金屬層1302032 • 1 〇 989 twf.doc / 006 Although the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and any person skilled in the art can make it without departing from the scope of the invention. There are a few changes and modifications, and therefore the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view showing a preferred embodiment of the present invention. Fig. 2 is an enlarged schematic view showing a πth portion of Fig. 1. Figure 3A to Figure 3 is a cross-sectional view showing the manufacturing process of a seed crystal according to another preferred embodiment of the present invention. [Main component symbol description] 100, 300: substrate 101, 301: buffer layer 102, 302: first gate 104, 304: gate dielectric layer 106, 306a: multi-channel layer 108, 310: ohmic contact layer 110a, 312a · source metal genus 11 Ob, 312b · > and polar metal layer 112, 312c: second gate 114, 308, 308a: protective layer 116a, 316a. amorphous flake film 116b, 316b Wrong film 306: multilayer structure layer '312: metal layer
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