TWI298196B - Chip build-up structure for positioning bond pads and method for fabrication the same - Google Patents

Description

1298196

TECHNICAL FIELD OF THE INVENTION A wafer build-up structure with pad positioning and a method of manufacturing the same, a bump is formed on a wafer build-up layer to accurately position a wafer build-up structure on a wafer and a method of fabricating the same. , Yu Yu location [previous technology] With the continuous expansion of the transmission capacity of the poor transmission, and the development trend of portable electronic products, the high input and (I / 0), the same political heat, and the size reduction of the general integrated circuit The demand for the more demanded: ::5's sorrow and sorrow toward the high-end wafer size package (CSP), the evolution of the day (fllp chlp), and at the same time, in the InformaUon Appliance In addition, portable digital assistants such as Personal Digital Assistant (PD and 昝-type computers) have also significantly increased the market demand for wafer metrics. 忒Technology US Patent No. 6, 271, 46 9 A wafer structure and a method for manufacturing the same, as shown in Figures 7-8 to 7D, firstly, a groove 401 is formed on the edge carrier 40, and the groove is as shown in the seventh figure. 1 is provided with a semiconductor wafer 50, and the semiconductor wafer 5 has a plurality of pads 501 thereon; then, as shown in FIG. 7B, a dielectric layer 60 is overlaid on the wafer 5 to cover the The surface of the wafer 50; A via hole (Vi a) 601 is drilled on the dielectric layer 60 corresponding to the pad 5 0 1 of the wafer 5, so that the pad 501 is exposed outside the dielectric layer 60. In FIG. 7D, a conductive trace 70 is disposed on the dielectric layer 60 and the exposed pad 501 to utilize the conductive trace layer 70.

1298196, the invention describes a private connection of a plurality of pads 5 该 on the wafer 5, and then repeats the steps as needed to form a multi-layer wafer build-up structure to complete the wafer size of such electronic components. Packaging process. $ and 'the dielectric layer 60 is used to expose the plurality of pads 5 〇 through holes 601 are drilled by laser drilling (LaSer Drilling) method, so the positioning point of the drilling is accurate or not It is important that, since the wafer 5 is formed after the dielectric layer 60, the position coordinates of the pad 5〇1 cannot be accurately positioned by the clamp pattern on the wafer (F iducia 1 M ask ), resulting in the Knowing the alignment method often has the problem that the alignment of the via hole 6 〇丨 and the pad 5 不 is inaccurate, forming an error in the laser drilling hole, and also making it difficult for a part of the pad 5 to sufficiently expose the dielectric layer. In addition to 60, it leads to a large bottleneck in electrical connection and component yield, and also a significant increase in process cost. Therefore, 'how to design a wafer-added structure with pad positioning and its manufacturing method' to accurately align the pads and through-holes in the process, thereby reducing the process cost and improving the quality yield of the parts, indeed related fields The subject that is urgently needed. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a wafer build-up structure capable of accurately aligning vias and pads with pad positioning and a method of fabricating the same. Another object of the present invention is to provide a wafer build-up structure with pad positioning that does not require a preset reference point on the carrier and a method of making the same. Still another object of the present invention is to provide a wafer build-up structure having pad positioning which can reduce process cost and a method of fabricating the same.

17297石夕品.ptd Page 7 1298196 V. Invention Description (3) Another object of the present invention is the quality of the component and the solder pad of the component. Therefore, there is a four-slot method for the wafer layering method of the foregoing and the pad. a carrier; at least one dielectric layer is formed on the active surface of the active surface of the wafer to cover the exposed portion of the at least two portions of the crystal to expose the exposed portion of the block, and the opening is formed The method of the present invention may further include: preparing a carrier for attaching at least one wafer to the surface and having a plurality of solder bumps; and forming the bump portion on the wafer The second part of the bump is exposed, and the position of the pad forms a hole. The method of the foregoing method comprises: forming a plurality of pads on the surface with the groove attached to the carrier; and forming the substrate by providing a wafer build-up structure capable of improving the positioning of the electrical connector and the method of manufacturing the same. For other purposes, the steps of the present invention for positioning can include: forming at least one wafer on a surface and having a plurality of fresh enamels on the surface of the groove of the carrier; the bumps on the wafer (Bump) Laying a sheet and a bump on the carrier; grinding the dielectric layer to make the dielectric layer outside; and using at least two dielectric layers corresponding to the plurality of pads The solder pad is exposed outside the dielectric layer. A wafer pad forming method for positioning a pad, the step block having a groove formed on one surface thereof; the groove of the carrier, and the action of the wafer is formed on the active surface of the wafer to be placed on the carrier a dielectric layer for covering the outer portion of the dielectric layer; and the plurality of solder pads corresponding to the plurality of solder pads on the dielectric layer to expose the dielectric layer a wafer build-up structure for positioning a pad, a recessed carrier; at least one wafer, and the active surface of the wafer has at least two bumps on the active surface of the wafer

1298196 V. DESCRIPTION OF THE INVENTION (4) (B u m p ); and laying on the carrier to cover the wafer and exposing the at least two bump portions to the outside of the dielectric layer. The aforementioned bumps may be formed on the active surface of the wafer and are a gold bump formed by wire bonding technology, or a tin made by flip chip or ball bonding technology. (S ο 1 der B um ρ ); at the same time, the position at which the bump is formed is recorded, or the two-dimensional coordinates of the bump outside the dielectric layer are exposed to the outside of the carrier, the groove and the wafer. Therefore, by using a specific bit gauge formed on the wafer, the partially exposed bump coordinates can be used as a reference point, and the coordinates of the plurality of pads can be accurately aligned, thereby reducing the process. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 This creation can also be carried out or applied by its own examples. The various viewpoints and applications in this manual are subject to change without departing from the spirit of this creation. 1A to 1F are the crystal flow chart of the pad positioning of the present invention. First, as shown in FIG. A, the upper surface of the carrier 10 is: As shown in FIG. 1B and FIG. 1C, a wafer 20 is recessed in the carrier, and a square edge of the wafer 2 and a concave dielectric layer are formed, and the Stud P is electrically convex. The block "pre-plans the inch, and the obtained bumps are set to obtain the drilling step implementation. It is easy to understand that his different sections can also be based on various modified sheet-making methods (Carrier 1 0 1 ; The groove 101 is connected to the groove 101 adjacent to 1298196. 5. The invention (5) is connected; wherein the surface of the wafer 20 has a plurality of pads for electrically connecting the wafer 20 (B〇). Nd Pad) 2〇1& preformed two bumps 2 0 2, the two bumps 2 0 2 may be a conductive bump, and its formation position is as shown in the upper view of FIG. 2, Two symmetric edges on the active surface of the wafer 20 that do not have the pads 2 〇 1; then, a dielectric layer is placed on the carrier 10 as in FIG. 1D (Diele Ctric Layer 30, to cover the wafer 2 and the conductive bumps 2 0 2 by the dielectric layer 3, and then perform a polishing operation on the upper surface of the dielectric layer 3 as shown in FIG. Grinding to the two conductive bumps 2 〇 2 can expose the dielectric layer 30. At this time, the position of the conductive bump 2 〇 2 is known in advance, or the carrier 10 is further matched. The groove 1 〇丨 is different from the size of the wafer 2, and the two-dimensional χ-γ coordinates of the two conductive bumps 2〇2 on the dielectric layer 30 can be known, and can be as shown in FIG. 1F. The X-Y coordinate of the two exposed conductive bumps 2 〇 2 is used as a reference point, and a plurality of two-dimensional coordinates of the plurality of solder bumps 20 1 formed on the active surface of the wafer 20 are calculated, thereby being When a layer is to be subsequently connected to electrically connect the plurality of pads 2, a two-dimensional coordinate of the pad 2 0 1 is used to implement a precisely positioned laser drilling step for the dielectric layer 30 is drilled to set a plurality of corresponding laser through holes (Laser Vi a) 3 01 to expose the plurality of pads 2 0 1 , and to perform subsequent electrical connection of the wafer layer The method of the present invention can also be applied to the second embodiment shown in Figures 3A to 3F, which differs from the first embodiment described above in that the embodiment is shown in Figure 3D. In the electrical layer 3 〇 step, the dielectric layer 30 is slightly lowered.

17297矽品.ptd Page 10 1298196 V. Invention Description (6) Laying the thickness of the two conductive bumps 2〇2 to expose the dielectric layer 30 directly after the dielectric layer is exposed The grinding step of the foregoing embodiment is omitted, and as shown in FIG. 3E, the two-dimensional XY coordinates of the two exposed conductive bumps 2 0 2 are used as reference points, and are calculated on the active surface of the wafer 20 in advance. The two-dimensional coordinates of the plurality of pads 2〇1 can be implemented by using the two-dimensional coordinates of the pad 201 when the wafer is to be subsequently laminated to electrically connect the plurality of pads 201. a precisely positioned laser drilling step for drilling a plurality of corresponding laser through holes 301 on the dielectric layer 3 to expose the plurality of pads 2 〇丨; and in this embodiment The two conductive bumps 2 0 2 are still exposed outside the dielectric layer 30 after the laser drilling step, so it is still necessary to be as shown in FIG. 3F before performing the subsequent layering step. Grinding method grinds out the exposed ends of the two conductive bumps 2 0 2 to achieve surface flatness at the subsequent layering; However, the polishing process is not limited to the foregoing operation sequence, and may be performed by the user, and before the laser drilling step (ie, after the 3D image, before the 3E image), the two conductive materials are first ground. The exposed end of the bump 2 〇 2 is subjected to laser drilling on the flat surface. The conductive bump 2 0 2 is a design of a dummy bump, which is intended to be used for reference positioning, and the conductive bump 2 〇 2 can be formed by any known method, for example. Solder bumps formed by FI ip-Chip or ball-fed technology in semiconductor packages can also be reduced in cost and formed using lower cost wire bonding technology. The gold bumps (AlJ Stud Bump) and the like can achieve the effects of the present invention.

17297矽品.ptd Page 11 1298196 V. Invention Description (7) " ' ----- Therefore, by the method of the foregoing two embodiments, the position of the exposed conductive bump 02 can be accurately positioned. The position of the plurality of pads 2〇1 does not cause a poor error when the pad is exposed except for the through hole. As in the case of the subsequent electrical connection quality, there is no::= on the carrier 10. Preset positioning points are used to fully reduce the process cost by 141⁄4 liters. Therefore, the wafer build-up structure of the positionable pad obtained by the method of the present invention, as shown in FIG. 4, includes: a carrier 10 having a groove J 〇i on the surface; The wafer 2 in the recess 1 〇 1 of the carrier 1 has a plurality of pads 2 〇 1 on the active surface of the solar wafer 20, and the opposite edges of the active surface of the wafer 20 Then, two conductive bumps 20 2 are respectively formed in advance; and a dielectric layer 30 is disposed on the carrier 1 包覆 to cover the wafer 2 、, so that the two conductive bumps 2 q 2 respectively Exposed to the dielectric layer 3, and can be exposed by the two parts of the exposed conductive bumps 2 〇 2 according to the needs of the subsequent process; the laser drilling is performed on the dielectric layer 3 俾, so that the plurality of Fresh 塾 2 〇 1 accurately reveals the dielectric layer 3 〇 outside. . Figure 5 is a top view of another embodiment of the wafer build-up structure of the present invention, which is respectively formed at the four corner positions of the active surface of the wafer 20, and the conductive bumps 2 0 2 ' So that the four conductive bumps 2 〇 2 are partially exposed to the j dielectric layer 30, and the four sets of two-dimensional χ-γ reference coordinates are provided, so that the more accurate Cang test points can be calculated as the position of the fresh 塾 2 0 1 position. Use, to further improve the accuracy of the subsequent laser drilling step. The conductive bumps 20 2 designed by the present invention are not limited to being formed at the corners of the crystals, and the number of formations thereof is not limited, and the user is viewed from the end.

1298196 V. According to the requirements of the invention (8), in principle, the more conductive bumps 2 0 2 are formed, the more precise the formation position is, the more the position of the pad 2 0 1 is estimated. Precisely, a more precise drilling alignment can be performed. For example, a further embodiment of the wafer build-up structure of the present invention shown in FIG. 6 shows other design methods, which are applied to the wafer 20 surface. The upper conductive pads 2 0 1 respectively form two conductive bumps 2 0 2, which can provide the reference coordinates of the non-angular position, which also achieves the ideal invention effect. In summary, it can be seen that the wafer stacking structure with the pad positioning disclosed in the present invention and the manufacturing method thereof have the functions of accurately aligning the through holes and the solder pads, thereby reducing the process cost and simultaneously increasing the power. Sexual connection quality and component yield. The above examples are merely illustrative of the principles and functions of the present invention and are not intended to limit the present invention. Any person skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this creation should be as listed in the scope of the patent application described later.

17297矽品.ptd Page 13 1298196 Brief Description of the Drawings [Simple Description of the Drawings] Figures 1A to 1F are flowcharts of a preferred embodiment of the wafer layering of the present invention; Figure 2 is the first Figure 3 is a top view of the wafer build-up structure; Figure 3A to 3F is a flow chart of the second embodiment of the wafer buildup of the present invention; Figure 4 is a side view of the wafer build-up structure of the present invention; Figure 6 is a top view of another embodiment of the wafer build-up structure of the present invention; Figure 6 is a top view of still another embodiment of the wafer build-up structure of the present invention; and Figures 7A through 7D are conventional wafer build-up layers Process flow chart. 10 carrier 101 groove 20 wafer 201 fresh 塾 202 bump 30 dielectric layer 301 laser through hole 40 insulating carrier 401 groove 50 wafer 501 pad 60 dielectric layer 601 through hole 70 conductive trace layer

17297 products.ptd第14页

Claims (1)

1298196 Case No. 92132112 Amendment No. Patent Application No. L. A wafer build-up method for positioning a pad, the steps comprising: preparing a carrier having a groove formed on one surface thereof; placing at least one wafer In the recess of the carrier, the active surface of the wafer has a plurality of pads and at least two bumps formed in advance; a dielectric layer is disposed on the carrier to cover the a wafer and a bump, the dielectric layer being polished to expose the at least two bump portions to the outside of the dielectric layer; and the exposed portion of the at least two bumps corresponding to the complex layer on the dielectric layer The pads are formed to form holes so that the plurality of pads are exposed outside the dielectric layer. 2. The wafer build-up method of a positionable pad according to claim 1, wherein the bump is formed on a corner of the active surface of the wafer. 3. The method for wafer layering of a positionable pad according to claim 1, wherein the bump is a conductive bump. 4. The method for wafer layering of a positionable pad according to claim 3, wherein the conductive bump is a gold bump made by wire bonding technology (Au Stud Bump) 〇 5. Patent application No. 3 of the method for wafer layering of a locating pad, wherein 'the conductive bump is a solder bump made by flip chip technology 〇6 · as claimed in the first item The wafer layering method for positioning the pad, wherein the hole is drilled by laser drilling. 17297 sand product. ptc page 15 1298196 _ case number 92132112 VIII. Patent scope revision 7. A method for wafer layering of a locating pad, the steps of which include: preparing a carrier having a surface formed thereon a groove; the at least one wafer is placed in the groove of the carrier, wherein the active surface of the wafer has a plurality of pads and at least two bumps formed in advance; the device is laid on the carrier a dielectric layer to coat the wafer and expose the bump portion to the outside of the dielectric layer; and to the exposed portion of the at least two bumps corresponding to the plurality of solders on the dielectric layer A hole is formed in the position of the pad to expose the plurality of pads to the outside of the dielectric layer. 8. The wafer build-up method of a positionable pad according to claim 7, wherein the bump is formed on a corner of the active surface of the wafer. 9. The wafer build-up method of a positionable pad according to claim 7, wherein the bump is a conductive bump. 1 0. The wafer layering method for positioning a soldering pad according to claim 9 wherein the conductive bump is a gold bump (Au Stud Bump) made by wire bonding technology. The method for wafer layering of a locating pad according to claim 9 is characterized in that the conductive bump is a solder bump formed by a flip chip technique (1). A method for wafer stacking of a locating pad of 7 items, wherein the hole is drilled by means of laser drilling. 1 3 . The wafer layering method of the locating pad according to claim 7 , wherein the exposed portion of the bump outside the dielectric layer is formed in the hole 17297Sand.ptc Page 16 1298190 Case No. 92132112 January 曰 Amendment _ 6. Grinding leveling before the steps of applying for patent scope. 1 . The wafer layering method of the locating pad according to claim 7 , wherein the exposed portion of the bump outside the dielectric layer is polished and smoothed after the step of forming the hole. 1 . The wafer build-up structure of the locating pad comprises: a carrier having a groove on a surface thereof; at least one wafer is attached to the groove of the carrier, and the wafer The surface of the action has a plurality of pads; at least two bumps are formed on the active surface of the wafer; and a dielectric layer is applied on the carrier to cover the wafer, and The at least two bump portions are exposed outside the dielectric layer; wherein the bumps are disposed at a predetermined distance from the solder pads for positioning the pads. 16. The wafer build-up structure of a positionable pad according to claim 15 wherein the bump is formed on a corner of the active surface of the wafer. 1 7. The wafer build-up structure of a positionable pad according to claim 15 wherein the bump is a conductive bump. 18. The wafer build-up structure of the positionable solder pad of claim 17 of the patent application 'where' is a gold bump (Au Stud Bump) made of a glow wire technique. 1 9 . The wafer build-up structure of the positionable solder pad according to claim 17 , wherein the conductive bump is a solder made by flip chip technology 17297矽品.ptc Page 17 1298196 Case No. 92132112 <?3Γ年°|月曰 Amendment VI. Patent Application Scope Block (Solder Bump) Page 18 17297 Product.ptc