TWI297979B - Brushless motor drive device - Google Patents

Description

1297979 IX. Description of the Invention: The present invention relates to a motor driving device, and more particularly to a motor driving device for driving a brushless motor. [Prior Art] Fig. 1 (a) shows a circuit block diagram of a conventional brushless motor driving device. Lu' Referring to Figure 1 (a), the motor is a three-phase DC brushless motor with three-phase coils u, V, and W. The Hall sensing circuit 11 is disposed around the motor , to detect the rotor position of the motor ,, thereby generating three position detecting signals HU, HV, and HW. In response to the position detection signals hu, HV, and HW,

The Ik signal synthesizing circuit 12 generates three driving sine wave signals su, SV, and SW. Subsequently, the sine wave signals SU, S V and the S W input pulse width modulation (PWM) comparison circuit 13 are used to individually compare the high frequency triangular wave signal τ generated by the oscillation circuit 14 with Φ. Based on the comparison between the drive sine wave signals SU, SV, and s W and the high frequency triangular wave signal T, the p WM comparison circuit 13 generates three pulse signals pu, PV and p W ' to be supplied to three pre-drive circuits ( Pre_driver) N 1, N2, and N3. In response to the pulse signal PU, the pre-driver circuit N1 generates the switching signals UH and UL. In response to the pulse signal p v , the pre-driver circuit N2 generates switching signals VH and VL. In response to the pulse signal p w , the pre-drive circuit N3 generates switching signals WH and WL. The two-phase switching circuit 15 has switches si and S2, switches S3 and S4, 6 1297979, and switches S5 and S6, which are controlled by switching signals UH and UL, VH and VL, and WH and WL, respectively. When the switch S1 forms a short circuit, the motor drive current Im can flow from the drive voltage source Vdd to the coil u, and when the switch S2 forms a short circuit, the motor drive current Im can flow from the coil u to the ground potential. When _S3% is short-circuited, the motor drive current 1〇1 can flow from the drive voltage source Vdd to the coil v, and when the switch S4 forms a short circuit, the motor drive current Im can flow from the coil v to the ground potential. When the switch S5 forms the short circuit %' motor drive current Im, it can flow from the drive voltage source vdd into the coil W, and when the switch S6 forms a short circuit, the motor drive current Im can flow from the coil w to the ground potential. In order to detect the motor drive current Im, the series resistance Rs is set between the common connection point of the switches S2, S4, and S6 and the ground potential. The potential difference caused by the motor drive current flowing through the series resistor Rs is supplied to the inverting input terminal of the error amplifying circuit EA as a negative feedback. The error amplifying circuit ea compares the potential difference representing the motor drive current Im with the current command signal to generate a motor error nickname Ierr. The signal synthesizing circuit i2 adjusts the amplitudes of the driving sine wave signals SU, SV, and SW2 in accordance with the current error signal 1err. Fig. 1(b) shows a waveform timing diagram of the operation of the brushless motor driving device which is not known. Since the motor of the two-phase coil U, ν, and w of each phase of the motor is selected in a similar waveform, H 4 # 丁,, for the sake of simplicity, Figure 1 (b) ) Only the waveform timing chart of the line ττ # π ^丄, and the circle u associated with the motor Μ is displayed. Referring to Fig. 1(b)', the sine wave (four) su and the high-frequency triangular wave signal τ are passed through the comparison circuit 13 to generate a pulse to the 4^ punching PU. Specifically, the high level of the pulse signal pu 1297979 corresponds to the case where the driving sine wave signal su is greater than the high frequency triangular wave signal τ, and the low order criterion of the pulse signal PU corresponds to the case where the driving sine wave signal SU is smaller than the high frequency triangular wave signal τ. . In response to the pulse signal pu, the pre-driver circuit N1 generates switching signals 1; 11 and ul for controlling the switches S1 and S2, respectively. In order to make the motor drive current Im equal to the current command signal, the error amplifying circuit EA takes the current error signal to the signal: into the circuit 12 for adjusting the amplitude of the drive sine wave signal su. For example, when the motor drive current Im is smaller than the current command signal Ic 〇 m, the current error 1 difference L 唬 Ierr controls the signal synthesizing circuit 12 so that the amplitude of the drive sine wave signal becomes large to drive the sine wave signal su. As is clear from Fig. 1(b), the amplitude-driven sine wave signal su causes the pWM comparison circuit Η to generate a relatively large pulse signal PU. In response to the relatively large pulse, pu', the three-phase switching circuit 15 causes the motor drive current to increase to approach the current command signal Ic 〇 m. However, in the case where the motor drive current Im and the current command signal ^ are too far apart, for example, the motor drive current Im is almost zero when the motor M_ is started, and the signal synthesizing circuit 12 responds to a large current error: the signal 1err even It is possible to generate a drive f-number whose amplitude exceeds the high-frequency triangular wave signal T: ". As a result, the comparison circuit 13 generates a low frequency: pulse signal pu,. This kind of low-frequency pulse signal & motor torque is connected to the female, too large, and the motor is not running smoothly. · Again, the low-frequency pulse signal PU, with a high level or low level Off, (4) M mi is in the forgiveness, V-induced two-phase switching circuit 丨 5 long time 8 1297979 is maintained in the operating state in which the supply gas does not supply the motor drive current Im. Long time = supply motor drive current Im may burn motor M and three-phase switching power =, or trigger the protection mechanism to force the circuit to close due to excessive temperature. SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide (1) a motor drive device that limits the duty ratio of a pulse signal. " # Another object of the present invention is to provide a brushless motor driving device to prevent the generation of low frequency pulse signals. The second object of the present invention is to provide a brushless motor drive (4) 'state. State or low-level quasi-phase: According to Ben Maoming, a brushless motor drive device is provided, - a comparison circuit and a duty ratio limit circuit. The comparison is made with a comparison-drive signal and a - reference signal - (4) to spit the circuit Having: a first circuit, a _.. a working division and a Dijon 踗 乐 - circuit, a first logic circuit signal. The second circuit generates a second half cycle ^ + week work ratio limit circuit The operation of the pulse signal is greater than the k-limit signal. The first pass is limited to the limit of the signal, and the output signal is limited to the limit signal. According to another aspect of the present invention, the half-cycle work is provided with a comparison circuit and a work ratio: "a type of brushless motor drive is mounted as a ratio limiting circuit. The comparison circuit is from 1297979 " one less three-wheeled end Comparator implementation , for comparing the -& reference signal with a first half-circle limit level, and generating a motion signal, such that the first half of the pulse signal is limited in operation ratio: the pulse signal, the circuit is provided with: A circuit and a logic operation limit half-week work ratio limit signal. The logic electric house is a second work limit than the first half cycle of the second half week work. In another aspect, a set is provided, and a comparison circuit is provided with a working motor drive device to have a first one: a dry-in and a turn-off limit circuit. The comparison circuit is from a younger input to a comparator and at least one first __ 芏Compared with the implementation of the device. The first = Han into the input and output of the second than the u input is compared to the device m - drive dreaming

A reference signal, and a first handle, the H-brain limit level, and a clear signal, so that the first pulse signal 苐-pulse • mouth work b &lt; Le Yi Ping Zhou work system. The second three-input comparator uses a 2 sense sign and a second half cycle limit level, and the first pulse signal of the second pulse signal is considered to make the work ratio of m^1+week limited. . The working ratio limiting circuit is in the driving missing step. ^ L #ϋ is supplied to the switching circuit at half time of the brother, and the switching signal is in the second half of the driving signal. The second pulse signal should be applied to the switching power 4. The above and other objects and advantages of the present invention will become more apparent from the description and drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments in accordance with the present invention will be described in detail with reference to the drawings. Figure 2 shows a circuit block 10 1297979 of a brushless motor drive according to the invention. Referring to Fig. 2, the motor Μ is a two-phase DC brushless motor having three* phase coils U, V, and w. The Hall sensing circuit 11 includes a Hall sensor and a Hall amplifier. The Hall sensing circuit is disposed around the motor , to generate three position detecting signals HU, HV, and HW, which respectively represent the positional relationship between the rotor of the motor 与 and the three-phase coil υ, ν, and W. Each of the positional debt measurement signals HU, HV, and HW is a sine wave signal that is synchronized with the operation of the motor , and has a phase difference ι2 彼此. In response to the position detection signals HU, HV, and HW, the signal synthesizing circuit 12 generates three drive signals SU, SV, and sW. In one embodiment of the invention, the drive signals su, SV, and sW are implemented by phase offsets of the corresponding position detection signals HU, HV, and HW, so that the waveform is still maintained at the sine wave signal. In another embodiment of the present invention, the driving signals SU, SV, and SW are phase-shifted by 30 degrees from the corresponding positional debt signal HU, HV, and HW and superimposed with appropriate correction signals to compensate for conduction. The terminal voltage offset caused by the delay (Turn-〇n Delay) is implemented, so the waveform becomes a superposition of the sine wave signal and the correction number. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; In an embodiment of the invention, the high frequency reference signal T is implemented by a single two-angle signal, wherein the amplitude average of each period of the triangular wave signal substantially coincides with the drive signal su, SV, or SW. The average amplitude of the period. In another embodiment of the present invention, the high frequency reference signal T is implemented by superposing an upper triangular wave signal having the same frequency and a lower triangular wave signal 11 11297979, wherein the valley of the upper triangular wave signal substantially corresponds to the lower two The peak of the angular wave signal, and substantially coincides with the amplitude average of each period of the drive signal su, SV, or SW. The use of the superimposition of the upper triangular wave signal and the lower two-dimensional wave signal is disclosed in U.S. Patent No. 3,585,5, the disclosure of which is incorporated herein by reference. Based on the comparison between the driving sine wave signals SU, SV, and the SW and the high frequency triangular wave signal τ, the PWM comparison circuit 2 〇 and the duty ratio limiting circuit

Interacting to produce a work ratio finite pulse signal —_ _ PWd. (The detailed circuit operation waveforms of the various embodiments of the lighter circuit 20 and the duty ratio limiting circuit 21 according to the present invention will be described in detail below with reference to the drawings.) In response to the pulse signal pUd, the pre-drive circuit ni is switched to the UHd. With ULd. In response to the pulse signal p%, pre-drive, path N2 produces switching signals % and %. In response to the pulse signal (10)d, the pre-driver circuit N3i generates the switching signals WHd and U to drive the arm paths N1, N2, and N3 to not only enhance the driving capability of the pulse signal, but also includes a time delay circuit to cause the generated switching signal. ? Tiger UHd# ULd, VH^ VLd, and each of ^ and ι have a stacked waveform feature. The three-phase switching circuit 15 has switches S1 and S2, switches 83 and ^^, and switches, S5 and S6, which are controlled by switching signals UHd and ULd, V] 22 and ^ and WLd, respectively. Specifically, the switch S1: is combined with the driving electric 懕, the shield vh ^ , and the coil U, and the switch S2 is coupled to the ring U and the ground electric imitation gate., the .^ w number UHd is input to the end point U1, With . 幵# , the switching signal ULd is input to the endpoint U2 to control 12 1297979 off S2. Therefore, when the switch S1 forms a short circuit, the motor drive current Im can flow from the drive voltage source Vdd into the coil U, and the volume _ _ _ _ sentence switch S2 forms a short circuit

The switch S5 is controlled, and the switching signal WLd is input to the terminal W2 to control the switch S6. Therefore, when the switch S5 forms a short circuit, the motor drive current 匕: flows into the coil w from the drive voltage source Vdd, and when the switch % forms a short circuit, the motor drive current Im can flow from the coil w to the ground potential. ¥, the motor drive current Im can flow from the coil U to the ground potential. Switch S3 is coupled between drive voltage source Vdd and coil v, and switch S4 (4) is coupled between coil V and ground potential. The switching signal VHd is input to the terminal νι to control the switch S3, and the switching signal VLd is input to the terminal V2 to control the switch S4. Therefore, when the switch S3 forms a short circuit, the motor drive current h can flow from the drive voltage source Vdd to the coil v, and when the open Ms4 forms a short circuit, the motor drive current &amp; can flow from the coil v to the ground potential. The switch S5 is coupled between the driving voltage source Vdd and the coil, and the switch is coupled between the coil W and the ground potential. The switching signal WHd is input to the terminal W1, in an embodiment of the invention, each of the switches S1, S3, S5 is implemented by a PM〇S transistor and each of the switches S2, S4, S6 is derived Implemented by an NMOS transistor. In another embodiment of the invention, each of the switches S1 through S6 is implemented by a NM 〇s transistor.

In the embodiment of the present invention, each pair of switches S1 and S2, switch S3, and switches S5 and S6 are hardly extracted by each pair of switching signals UHd and ULd, VHd and VLd, and WHd and WLd (Hard Chopping) ) The way to perform the modulation operation. The hard-switching modulation operation refers to the lower-side switch (ie, open_S2, S4, and S6) when the upper switch (ie, switches S1, S3, and S5) is switched between pwM 13 1297979 on and FF. At the same time, the PWM switching of 0FF and (10) is reversed. In another embodiment of the present invention, 'each pair of switches s! and S2, switches' and S4, and switch ”' S6 are correspondingly switched by each pair of signal ports ~ and ULd, VHd and VL^, d', WLd is modulated by Soft Chopping. The 5-week operation of It is the upper switch Sb S3 during the positive half cycle of the drive letter &amp; s, sv, and SW. S5 performs PWM switching of 〇N and , and the lower switches S2, S4, and % are maintained at the time of ～ and during the negative half cycle of driving k, SU, SV, and SW, the upper switches S1 and S3, The S5 is maintained in the OFF state, and the lower switches S2, S4, and S6 perform the pWM switching of 〇N and 0FF. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; In order to detect the motor drive current lm, the series resistance rs is set between the common connection point of the lower switches S2, S4, and S6 and the ground potential. Please note that in another embodiment of the present invention, the series resistor Rs is also disposed between the common connection point of the upper switches S1, S3, and S5 and the driving voltage source vdd. The potential difference caused by the motor drive current Im flowing through the series resistor Rs is supplied to the inverting input terminal of the error amplifying circuit EA as a negative feedback. The error amplifying circuit EA generates a current error signal Ierr by comparing the potential difference representing the motor drive current im with the current command signal Icom'. The signal synthesizing circuit I] adjusts the amplitudes of the drive signals SU, SV, and SW in accordance with the current error signal Ierr. Although the current error signal Ieir is supplied to the signal synthesizing circuit 1297979 12 in FIG. 2 for feedback adjustment of the vine motion signals su, sv, and sW2, Ren Ben is not limited thereto. As described above, the PWM comparison circuit 2 determines the pulse widths of the pulse signals 1 &gt; 11, ??, and pw based on the relative relationship between the amplitudes of the drive signals SU, SV, and SW and the amplitude of the reference signal τ. Therefore, in another embodiment, the current error signal Ierr is supplied to the oscillation - to feedback the amplitude of the 5 week integer reference # τ, thereby achieving an adjustment

The effect of the relative relationship of amplitudes. In still another embodiment, the current error signal is supplied to the Hall sensor u for feedbacking the amplitudes of the position detection signals HU ΗV and HW such that the signal synthesis circuit 丨2 generates the drive signal SU. The amplitudes of SV and SW are indirectly adjusted, thereby achieving the effect of adjusting the relative relationship of amplitudes. A technique for the relative relationship of such amplitude adjustments is disclosed in U.S. Patent No. 6,71, 568, the disclosure of which is incorporated herein by reference. Fig. 3 (a) shows a detailed circuit diagram of the pwM comparison circuit 20-1 and the duty ratio limiting circuit 21-1 according to the first embodiment of the present invention. The figure shows a timing chart of the operation waveforms of the PWM comparison circuit 2 〇_丨盥 operation ratio control circuit 2H according to the first embodiment of the present invention. Since the phase of each of the three-phase coils U, V, and W of the motor % is operated in a similar waveform, for the sake of simplicity of explanation, the object 3(b) only shows the waveform timing when the coil associated with the motor M is made. Figure. The drive signals SU, SV, and the SW 钤 士 input pWM comparison circuit 2 (M, for individually and independently comparing the high frequency reference 栌, 乂 唬 k 唬 T. Specifically, the PWM comparison circuit 20-1 includes two钿m π — a ratio of the parent states CU, cv, and CW, where the inverting input is used to receive the team drive #SU, SV, and SW, 15 1297979 instead of the reverse wheel input. Receiving the high frequency reference signal τ. Based on the comparison between the driving signal SU and the high frequency reference signal τ, the comparator (3) generates a pulse U PU-b based on the ratio between the driving signal s ν and the high frequency reference signal 乂The benefit cV generates a pulse signal pi. Based on the comparison between the drive signal sw and the inter-frequency reference k number T, the comparator cw generates a pulse PW-1. The duty ratio limiting circuit 2 1 -1 limits the pulse signals Pu_丨, pv_ Comparing with the operation of PW-1, the comparator CL is used to compare the high frequency reference signal τ with a predetermined negative half cycle limit level VL to generate a negative half cycle duty ratio static number, L. negative half cycle limit bit The quasi-fire system is set to be substantially equal to the trough of high _ #唬T, and is preferably set to be slightly larger than the trough value. The CH system is used to compare the high frequency reference (4) τ with a predetermined positive half cycle limit level vH to generate a positive half cycle duty ratio limit signal Η Η. The positive half cycle limit level vH is set to be substantially equal to the high frequency reference signal τ The peak value of the wave is preferably set to be slightly smaller than the peak 佶. 卩 left secret &gt; r , and 哔 value tunneling, PWM comparison circuit 2 (M pulse signal PU_ ρν·b and pw-i Each of them is compared with the positive half-week work ratio limit signal PH by the employee's work week to limit the signal PL· to achieve the effect of the positive half cycle and the negative half cycle work ratio limit. For example, the pulse signal The cutting and negative half-cycle work ratio limit signal pL first = NAND logic gate NL1 performs Nand logic operation, = number is called. Subsequently, the signal PU1 is further subjected to * NAND logic gate ^ + week work ratio limit signal PH for another job Logical operation, thus, can produce the desired work than the finite pulse signal. Therefore, the positive half cycle works more effectively than the limit signal pH to limit the pulse letter 16 1297979 in the PU-ld corresponding to the positive half of the drive signal su Partial work ratio, and negative half-week work ratio limit letter The number PL effectively limits the duty ratio of the pulse signal PU-1 d corresponding to the negative half cycle portion of the drive signal su. Even at the motor drive power / ', L lm and the current command signal 1 〇〇 111 are too large In this case, the brushless motor driving device according to the present invention can effectively limit the duty ratio and frequency of the pulse L number PU ld Pv_id and pw_ld, thereby ensuring reliable operation of the motor. Fig. 4 (4) shows the PWM according to the second embodiment of the present invention. A detailed circuit diagram of the comparison circuit 20-2 and the duty ratio limiting circuit 21_2. Fig. 4 is a timing chart showing the operation waveforms of the PWM comparison circuit 2?_2 and the duty ratio limiting circuit 21_2 according to the second embodiment of the present invention. Since the three-phase coil of the motor μ and each phase of the W operate in a similar waveform, for the sake of simplicity of explanation, the head 4(b) only displays the waveform timing diagram of the coil u associated with the motor M during operation. . The PWM comparison circuit 2G_2 includes three three-input comparators clu, (10), and CLW. The three-input comparator comparator cj has two non-inverting inputs 'respectively for receiving the drive signal and the negative half cycle limit level I and one inverting input terminal' for receiving the high frequency reference signal T: the standard position The VL system is set to be substantially equal to the high frequency reference signal τ, which is set to be slightly larger than the valley value. Once the high frequency reference signal Τ is less than any of the drive signal SU and the negative half cycle limit level V1, the three-transistor two-terminal comparator CLU is triggered to output a high level signal. Therefore, the pulse signal pu_2 generated by the third ::: comparator CLU has been characterized by the weekly duty ratio limit. Similarly, the pulsed signal PV_2 of 17 1297979 generated by the three-input comparator (10) has the characteristics of negative half cycle work ratio ~ limit. 1. Input the pulse signal p generated by the comparator CLW: the characteristic of the weekly duty ratio limit. , eight have a negative working limit (4) Road 21_2, for the pulse signal and PW · 2 for the positive half cycle work ratio limit. The comparator CH is used to: 2:: wide and the predetermined positive half cycle limit level to generate: === number. H. The positive half cycle limit level % is set to the peak value of the real two &quot; and is preferably set to be slightly smaller than the wave peak. Subsequently, the PWM compares ^ pU_2, pVj . The pulse signal generated by KM 2〇·2 is compared with the signal ΡΗ to achieve the effect of the positive + weekly duty ratio limit with w , 乂 . :: and:, the pulse signal PU_2 and the positive half cycle work ratio limit signal pH = NAND logic gate Nm for nand logic operation, so that the desired work ratio finite pulse signal PU-2d can be produced. b positive half cycle work than the limit signal PH effectively limits the duty ratio of the pulse signal PU-2d corresponding to the positive half cycle portion of the drive signal, I negative + weekly guard ratio limit signal PL effectively limits the pulse signal p, : Pair: The working ratio of the negative half-cycle portion of the drive signal SU. Even in the case where the motor drive current &amp; and the current command signal 1_ are too far apart: the brushless motor drive device according to the present invention can effectively limit the duty ratio and frequency of the pulses AU 2d PV-2d and pw_2d, This ensures that the motor operates reliably. Fig. 5 (4) shows a detailed circuit diagram of the PWM comparison circuit 2〇-3 and the duty ratio limiting circuit 仏3 according to the third embodiment of the present invention.胄 ) 显示 显示 18 1297979 According to the present invention, the FWM comparison circuit 2 of the third embodiment operates on a waveform diagram of the operation waveform 21-3. Since the horse μ, the working ratio U, V, and the three-phase coiling of the π Μ Μ 说明 说明 说明 说明 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导 导The order of the wave during the work. U is operating in comparison circuit 2. _3 includes three three-input comparators (10), terminals, and eight-input comparators (10) with two inverting inputs =: another to receive the drive signal su and the positive half-cycle limit level VH, and a non-inverting The input terminal is used to receive high frequency participation, and 1 is, 隹, and / is T. The positive half cycle limit level VH is set to be equal to the high frequency reference signal value &apos; and is preferably set to be slightly smaller than the wave peak. - Day: / Into the second and positive half-week limit level VH, the three-input j-in = the pulse signal Pu_3 generated by the parent-child CHU already has the characteristic of the work-to-work ratio limit. Similarly, the second /, the generated mail IA - input pulse 鳊 comparator CHV pulse "No. pV-3 already has abundance. Three-wheeled human comparator CHW production work than the limit of the specific positive half-week work ratio limit The pulse signal PW·3 has been limited to the pulse signal PU+PV-3, a r W-3 input negative half cycle working high frequency reference signal τ and predetermined / week. The CL system is used to compare the half-week work ratio PP 4丨π A Bayan weekly limit level vL to produce a negative D-Q ratio ratio limit signal PL. The warehouse quality is equal to the high-frequency reference signal T wave ^ ^ level The 1 system is set to the real valley value. Subsequently, the PWM ratio: 2 is preferably set to a pulse signal 19 1297979 generated by the slightly larger egg path 20-3. Each of PU-3 and Pm PW-3 is respectively The negative half cycle operation is compared with the limit signal PL to achieve the effect of the negative half cycle duty ratio limit. For example, the pulse signal PU _ 3 and the negative half cycle duty ratio limit signal pl perform NAND logic operations via the NAND logic gate NL1, This produces the desired working ratio finite pulse signal pi%. Therefore, the positive half cycle duty ratio limit signal The pH effectively limits the duty ratio of the pulse signal PU-3d corresponding to the positive half cycle portion of the drive signal su, and the negative half cycle duty ratio limit signal PL effectively limits the negative of the pulse signal PU-3d corresponding to the drive signal su The working ratio of the half-cycle portion. Even in the case where the difference between the motor drive current Im and the current command signal Ic〇m is too large, the brushless motor driving device according to the present invention can effectively limit the pulse signals PU-3d, PV- 3d, working ratio and frequency with PW_3d, thus ensuring reliable operation of the motor. Fig. 6(a) shows a detailed circuit diagram of the pwM comparison circuit 214 and the duty ratio limiting circuit 21_4 according to the fourth embodiment of the present invention. 胄6(8) shows Lu The operation waveform timing chart of the PWM comparison circuit 2〇_4 and the duty ratio limiting circuit 21-4 according to the fourth embodiment of the present invention. Since the three-phase coils u, =V, and W of the motor m are similar to each other The waveform is operated, so it is shown in Fig. 6(b) only the waveform timing diagram of the coil U associated with the motor μ during operation. The WM ratio ruling circuit 2〇·4 includes three three-input terminals. Comparators cLu, CLV and CLW, and three three losers The input comparators CHu, chv, and the PWM comparator circuit 20_4 are substantially combined by the PWM comparison circuit 2〇_2 of FIG. 4(a) and the pWM comparison circuit 2〇_3 of FIG. 5(4). On the other hand, the pulse signals PU-4a, PV-4a, and PW-4a generated by the three three-input comparators CLU, CLV, and CLW, respectively, have a negative half-cycle duty ratio limitation. On the one hand, the pulse signals pu_4b, PV_4b, and Xiao Pw_4b generated by the three three-wheeled-end comparators CHU, CHV, and CHW, respectively, have the characteristics of a positive half-cycle duty ratio limitation. The duty ratio limiting circuit 21_4 is provided with three inverters π, ΐ2, and Η for generating inverted pulse signals pu_4a, pv_4a, and pw_4a. In addition, the working ratio limiting circuit 21_4 is further provided with three multiplexers (_ screaming M1, M2, and M3. The multiplexer M1 has two source inputs for respectively receiving the inverted pulse signal Pu_4a, and the pulse signal The multiplexer M1 has a selective input terminal 'for receiving the polarity selection signal. Specifically, the polarity selection signal psu is used to indicate the polarity of the driving signal SU, that is, the positive half cycle state or the negative half. Week state. When the drive flag su is in the positive half cycle state, the polarity selection signal psu controls the multiplexed cry (4) to output the inverted pulse money PU_4a as a work to achieve the desired duty ratio limit than the finite pulse signal. When the signal su is in the negative half cycle state, the polarity selection signal psu controls the multiplexed crying (4) output pulse signal PU_4b as the working ratio finite pulse signal ρυ, thereby achieving the desired working ratio limit. The same principle 'multiplexer M2 has Two source inputs for respectively receiving the inverted pulse signal PV_4a and the pulse balance signal pv_4b. The multiplexed crying] has a selection input terminal for receiving the polarity selection signal PSVf and In other words, the polarity selection signal E psv is used to indicate the polarity of the driving signal sv 21 1297979 i. that is, the positive half cycle state or the negative half cycle state. When the driving signal sv is in the positive half cycle state, the polarity selection signal The psv control multiplexer M2 outputs the inverted pulse signal PV_4a as the working ratio finite pulse signal ρν_~ to achieve the desired duty ratio. When the drive signal sv is in the negative half cycle, the polarity selection signal Psv The control multiplexer M2 outputs the pulse signal PV-4b as the working ratio finite pulse signal pv_4d, thereby achieving the desired working ratio limit. 'Similarly, Xigongyi M3 has two source inputs for respectively receiving the opposite The phase pulse signal PW-4a has a selection input terminal for receiving the polarity selection signal pSwf° and the polarity selection signal PSW is used to indicate the driving signal sw. The extreme f is also a positive or negative half-week state. When the drive signal is in the positive half cycle state, the polarity selection signal psw controls the multiplexer M3 to output the inverted phase pulse signal PW-4a as the duty ratio finite pulse signal pw乂 to achieve the desired duty ratio. When the drive (four) sw is in the negative half cycle state, the polarity selection signal PSW controls the multiplexer (10) to output the pulse signal PW shoulder as the work ratio finite pulse of the tiger team 4d, thereby achieving the desired work ratio limit. Although the present invention has been described by way of illustration of preferred embodiments, it is understood that the invention is not limited to the disclosed embodiments. Rather, the invention is intended to cover such modifications as the subject matter of those skilled in the art. Due to &amp;, the scope of the patent application scope should be based on the extensive &amp; release to accommodate all such modifications and similar configurations. 22 1297979 [Simple diagram of the diagram] Circuit block diagram of the brush motor drive unit. The waveform of the operation of the brush motor driving device Fig. Ha) shows the conventional no. Fig. 1(b) shows a conventional disorder diagram. 2 shows a circuit block of a brushless motor driving device according to the present invention. FIG. 3(a) shows a PWM comparison circuit according to a second embodiment of the present invention.

Detailed circuit diagram of the circuit with the limit of work. Fig. 3(b) is a timing chart showing the operation waveforms of the pwM comparison circuit and the duty ratio limiting circuit of the embodiment of the present invention. Fig. 4(a) is a detailed circuit diagram showing a PWM comparison circuit and a duty ratio limiting circuit in accordance with the present invention. Fig. 4 (b) is a timing chart showing the operation waveforms of the comparison circuit and the duty ratio limiting circuit in accordance with the second embodiment of the present invention. Fig. 5 (a) shows a detailed circuit diagram of a comparison circuit and a duty ratio limiting circuit in accordance with a third embodiment of the present invention. Fig. 5 (b) is a timing chart showing the operation waveforms of the comparison circuit and the duty ratio limiting circuit in accordance with the third embodiment of the present invention. Fig. 6 (a) is a detailed circuit diagram showing a % comparison circuit and a duty ratio limiting circuit in accordance with a fourth embodiment of the present invention. Fig. 6 (b) is a timing chart showing the operation waveforms of the pwM comparison circuit and the duty ratio limiting circuit in accordance with the fourth embodiment of the present invention. [Main component symbol description] 23 1297979 11 Hall sensing circuit 12 Signal synthesis circuit 13 PWM comparison circuit 14 Vibrating circuit 15 Three-phase switching circuit 20 PWM comparison circuit 21 Operation ratio limiting circuit

NL1 ~ NL3, NH1 ~ NH3 NAND logic gate CU, CV, CW, CH, CL Comparator CLU, CLV, CLW, CHU, CHV, CHW Three-input comparator D1 ~ D6 Diode EA error amplifier Μ Brushless motor Ν1~Ν3 pre-driver circuit

Rs series resistor S1 ~ S6 switch U, V, W three-phase coil

Ul, U2, VI, V2, Wl, W2 Switch Control Terminal II~13 Inverter

Ml~M3 multiplexer HU, HV, HW position detection signal PH positive half cycle work ratio limit signal PL negative half cycle work ratio limit signal PU, PV, PW, PU,, PU" pulse signal 24 1297979 PUd, PVd, PWd i is a finite pulse signal su, sv, sw, su', su" Synthetic signal T High frequency reference signal UH, UL, VH, VL, WH, WL switching signal UHd5 ULd9 VHd5 VLd? WHd? WLd Working ratio limited switching signal

Ierr current error signal

Icom current command signal

Im motor drive current

Vdd drive voltage source VH positive half cycle limit level VL negative half cycle limit level V〇 amplitude average

25

Claims (1)

1297979 Patent Application Range·· 1. A brushless motor driving device comprising: a comparison circuit for comparing a driving signal fish-generated pulse signal, wherein the driving signal is associated with a second turn and the reference is generated The frequency of the signal is greater than the drive&gt;·, the switching circuit of the brush motor is coupled to a frequency of σ; the W port A dynamic voltage source is controlled by the pulse signal to drive the brushless motor/ -, b..., between the brush motor, - an adjustment circuit for adjusting between the amplitude of a current error signal and the amplitude of the reference signal, the drive difference signal representing a current command signal and the ',, current error; And the difference between the motor drive current and the work ratio limiting circuit, having a first circuit for generating a first main brother + weekly work ratio limit signal second circuit for generating a 箆 - brother half-week work ratio Limiting the signal _ _ logic circuit for causing the working ratio of the pulse signal to be limited by the first half of the working ratio limiting signal, and generating a number; and ^ logic circuit 'for the first logic gate The working ratio of the output signal is limited by the limit signal of the second half of the working period of the younger brother. The number of the first circuit is a brushless motor driving device, wherein : The comparator is implemented, the comparator has a 26th, 1297979 type input, a field input terminal for receiving: a reference signal; and a second type of transmission level system (4) a reference signal: The first-half-week limit is as follows: Shen: Patent No. 1 of the brushless motor drive device, wherein: - class = r:: followed by a rr implementation, the comparator η two types are input with a half-cycle limit level, And a first 鸲1鸲, for receiving the reference signal, wherein the first-half-week limit level is less than the maximum value of the reference signal. (4) Limits 4. The brushless motor drive device of the first paragraph of the patent scope, wherein: 忒 The first logic circuit is implemented by a NAND logic gate. 5. The brushless motor driving device of claim 1, wherein: the second logic circuit is implemented by a financial gate. 6 · A brushless motor drive device, including: than the car and the circuit, implemented by at least one three-input comparator, with, than the rut · drive ^ 5 tiger, a reference signal, and _ first half Limiting the level, and generating a pulse signal, such that the working ratio of the first half of the pulse signal is limited, wherein the driving signal is associated with the operation of a brushless motor and the frequency of the reference signal is greater than the driving signal a switching circuit coupled between a driving voltage source and the brushless motor, controlled by the pulse signal to drive the brushless motor; 27 1297979 an adjusting circuit for adjusting the driving signal according to a current error signal a relationship between the amplitude and the amplitude of the reference signal, the current error signal representing a difference between a current command signal and a motor drive current; and a duty ratio limiting circuit having: a circuit for generating a second a half cycle duty ratio limiting signal, and a logic circuit for operating the second half of the pulse signal to be subjected to the second half cycle ratio That the regulating signals. 7. The brushless motor driving device of claim 6, wherein: the three-input comparator has two #1 type inputs ^ for respectively receiving the driving signal and the first half-circle limit level, And a second type of input for receiving the reference signal. 8. The brushless motor driving device of claim 7, wherein: the first type input is implemented by a non-inverting input, and the second type input is provided by an inverting input terminal. Implementation. 9. The brushless motor driving device of claim 7, wherein: the first type of input is implemented by an inverting input, and the second type of input is provided by a non-inverting input. Implementation. 1 〇 · The brushless motor drive device of claim 6 of the patent scope, wherein 28 1297979 ^ The first half cycle limit level is greater than the minimum value of the reference signal. U• The brushless motor driving device of claim 6 wherein the first half cycle limit level is less than the maximum value of the reference signal. · I1 2 · A brushless motor driving device according to claim 6 wherein a circuit type comparator is used to generate the second half cycle duty ratio limit signal, the comparator having a first type The input terminal is limited by the receive-second half cycle μ, and a second type of input terminal receives the reference signal 'where the second half cycle limits: the maximum value of the slave signal. In the brushless motor driving device of claim 6, the electric-comparator for generating the second half-cycle duty ratio limiting signal is implemented by the (four) comparator having a first type of wheel-in. end, Receiving the reference signal, and a second type of input terminal, using a two-half cycle limit level, wherein the first car; the minimum value of the signal. + Week limit level is greater than this, 14. As claimed in the sixth paragraph of the patent application, the logic circuit is implemented by a NAND logic gate. 29 1 5 · A brushless motor drive device, comprising: 2 The circuit is implemented by at least a third-to-three input comparator and an I297979 first two-input comparator, the first three-input comparator comparing a driving signal, a reference signal, and a first half The first limit pulse signal is generated to generate a first pulse signal, so that the first half of the first pulse signal and the working ratio of the R problem are limited. The second three-input comparator is used to compare the Μ drive signal, the reference signal, Restricting the level with a second half cycle to generate a second pulse signal such that the second half of the second pulse signal operates, &lt; tb is limited 'where the drive signal is associated with a brushless motor The frequency of the reference signal is greater than the frequency of the driving signal; a switching circuit is coupled between a driving voltage source and the brushless motor, and reads the first pulse signal and the second pulse The number is controlled to drive the brushless motor; ^ an adjustment circuit for adjusting the relative relationship between the amplitude of the driving mirror and the amplitude of the reference signal according to a current error signal, the current error is generated T7 y * S 5 The tiger system represents a difference between a current command signal and a motor drive current; and a duty ratio limiting circuit for supplying the first pulse signal to the switching circuit when the driving signal is at the first half, and The second pulse signal is supplied to the switching circuit when the driving signal is in the second half cycle. 1 6 . The brushless motor driving device of claim 5, wherein: the first half of the limit level is greater than the minimum value of the reference signal, and the first half cycle limit level is less than the reference The maximum value of the signal. 30 1297979 17. As claimed in the patent application, the first half-circle limit level is less than the maximum value of the 〃5彳, and the first-half-week limit level is greater than the minimum value of the reference signal. ζApplicant's patent range No. 15 brushless motor drive device, Lizhong, the brother one or three input comparator has two first two to receive the drive signal and the first _ ^ | input 钿, two types of input End, for receiving the reference = the standard position and - 19. In the full-time (four) 15 items of the brushless motor drive (four), wherein the first two-input comparator has one-to-one receiving the reference signal And two C-th inlets for the wheel-in terminal to receive the driving signal and the second half-circle limit level respectively. 31