TWI297933B - Chip package structure - Google Patents

Chip package structure Download PDF

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Publication number
TWI297933B
TWI297933B TW095118209A TW95118209A TWI297933B TW I297933 B TWI297933 B TW I297933B TW 095118209 A TW095118209 A TW 095118209A TW 95118209 A TW95118209 A TW 95118209A TW I297933 B TWI297933 B TW I297933B
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TW
Taiwan
Prior art keywords
wafer
package structure
wires
wire
chip package
Prior art date
Application number
TW095118209A
Other languages
Chinese (zh)
Other versions
TW200744165A (en
Inventor
Wang Tong-Hong
Original Assignee
Advanced Semiconductor Eng
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Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW095118209A priority Critical patent/TWI297933B/en
Publication of TW200744165A publication Critical patent/TW200744165A/en
Application granted granted Critical
Publication of TWI297933B publication Critical patent/TWI297933B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48996—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/48998—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

'I297?J^doc/e 九、發明說明： 【發明所屬之技街領域】 本發明是有關於一種a 高散熱效果的^ “ 且特別是有關於 【先鈾技術】 近，來’隨著積體電路㈤egrated㈤此们 之内。卩線路的積集度（ :'I297?J^doc/e IX. Invention description: [Technology street field to which the invention belongs] The present invention relates to a high heat dissipation effect and is particularly relevant to [pre-uranium technology] Integrated circuit (5) egrated (five) within this. 积 line accumulation (:

生的熱能也不斷增加辦請as片所產 運作，使ic晶月維牲〜使述之IC晶片能夠維持正常 高造成效能;=私作溫度下，㈣免溫度過 =構件，高效能的散熱需求而不斷推陳出= S = 合金’其可藉由導熱膠貼附在晶^ 、月、或導線架（leadframe)的晶片座（diepad)的背 2 ’以直接/間接狄晶#所產生的廢熱，轴避免廢熱 木中在晶片内。 立明芩考圖1，其繪示習知一種晶片封裝結構的剖面示 Ί、°,晶片102配置於導線架11〇的晶片座112上，而大 舜知平板狀的散熱片120在以封膠（encapSuiati〇n) 13〇包 覆之前，貼附在晶片座112的背面，以提高晶片封裝結構 101的散熱效果。值得注意的是，晶片102所產生的廢熱 也會經由傳遞訊號的導線104傳導至各個輸入/輸出引腳 4且在熱傳遞的過程中，仍會有一部份的廢熱殘留在導 04内而未被帶走，致使晶片封裝結構100的内部溫度 變向。同時，導線104與封膠130的熱膨脹係數不匹配也 1297撕一 成導線104斷裂或其他不良的影響。因此，習 ?散熱問題，而未考量導線_所 片⑽只提供晶片1〇2散的r響/且習知的散熱 熱的解決之道。放'、、、之用’但部未提供導線刚散 【發明内容】 決導線提供片封裝結構，用以解 果。 … 、、以提咼晶片封裝結構的散熱效 包括多婁種日日片封I結構，其包括：—導線架， 具有-打線接人Γ開的引腳以及—3日日片座，這些引腳分別 多數個銲墊配i:上座之周圍;-晶片，具 座上；多數條導域上’該晶片係配置於晶片 接合部；—縣塊，二連接這些料至這些引腳之打線 晶片座，該凸二/ : 一凹穴及一凸伸部，該凹穴係容置 -封膠，包覆圪：：延伸至晶片座與這些引腳之間；以及 及散熱塊 些弓丨腳之打線接合部、晶片、這些導線以 依照本發明—每 膠之外，並織e列所述，上述之這些引腳延伸出封 亚弓折成一支撐部。 依照本發明—每 、、 於該些_的距離：：：所述’上述之凸伸部的頂部相對 的打線接合部的^=/2於這些導線的最高點相對於引腳 本毛月貫施例所述，上述之晶片封裝結構更包 129793^,oc/e 括一絕緣層，配置於凸伸部的頂部。 依照本發明一實施例所述，上述之散熱塊的底面顯露 於封膠之底面。 依照本發明一貫施例所述，上述之導線可為金線、钢 線或銘線。 依照本發明一實施例所述，上述之凸伸部可為一環狀 塊’其J衣繞於凹穴之周圍。此外，凸伸部亦可包^多個凸 起’其對應配置於凹穴之兩侧區域或角落區域。 本發明因採用可同時吸收導線及晶片的廢熱的散熱 結構，因此可避免導線發熱所產生的不良後果，同時可解 决V線與封膠在局溫的環境下因熱應力而造成導線的斷裂 或接觸不良。 、' .為讓本發明之上述和其他目的、特徵和優點能更明顯 董，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 實施例之晶片封裝結構的剖面示意 力月 &gt; 考圖2，晶片封裝結構200包括一晶片2〇2、一導 ，木210、多條導線204、一散熱塊220以及一封膠23〇。 晶片202具有多個銲墊2〇2a，且晶片2〇2獨立地配置於用 二ί $合的導咖10上’以使晶片202上的銲墊202a L猎3自獨立的導線204來傳遞輸入/輸出訊號。導線架 〇曰用以承載晶片202的晶片座212，以及多個引腳 214自曰曰片座212的周圍向外延伸。常見的晶片座212為 7 1297^3 1 咖 wf.doc/e 平板狀，並有支撐桿（未繪示）配置於晶片座212的周圍， - 以f撐晶片202的重量。此外，晶片座212的支撐桿亦可 - 稍彳放向下焉折成形，以使晶片座212的高度略低於周圍的 引腳214的高度。當然，在另一實施例（未繪示）中，晶 片座212與周圍的引腳214亦可位於同一平面上，或以其 他的相對關係存在。 / 基本上，引腳214在彎折成形之前，晶片2〇2先以導 熱膠或銀膠203固定在晶片座212上，再以導線204由晶 片202的銲墊202a跨接到鄰近的引腳214上，而引腳214 的内側表面可先形成一打線接合部214a，以使導線2〇4的 一端與引腳214的打線接合部214a緊密接合。除此之外， 在包覆封膠230之前，晶片座212的底部先配置散熱塊 220 ’而散熱塊220除了可容納晶片座212之外，更可延伸 至晶片座212與引腳214之間形成的間隙。最後，封膠23〇 包覆引腳214之打線接合部214a、晶片202、導線204以 及散熱塊220之後’還可選擇性地將引腳214的外侧部份 _ 恭露出來或將引腳214顯露於封膠230之外的部分予以彎 折成一支撐部216 ’以使晶片封裝結構2〇〇能固定於一基 板（未繪示）或物件上。 值得注意的是’由於導線204 (例如是金線、銅線或 鋁線）與封膠230的熱膨脹係數相差甚大，且封膠230不 易散熱，因此導線204的溫度相對於周圍的環境溫度高出 許多，容易導致熱應力集中而斷裂。經應力分析實驗證明， 導線204的中央區段是溫度最高的部分，也是熱應力影響 8 doc/eThe heat energy of the company is also increasing, and the operation of the film is required to make the film of the ic crystal. The IC chip can maintain the normal high efficiency; = private temperature, (4) temperature-free = component, high-efficiency heat dissipation The demand continues to evolve = S = alloy 'which can be attached to the back 2' of the die pad of the crystal, moon, or leadframe by the thermal paste to the direct/indirect Dijing# The waste heat, the shaft avoids waste heat in the wood inside the wafer. 1 is a cross-sectional view showing a conventional chip package structure, wherein the wafer 102 is disposed on the wafer holder 112 of the lead frame 11 , and the flat fins 120 are sealed. Before being coated, the adhesive is attached to the back surface of the wafer holder 112 to improve the heat dissipation effect of the chip package structure 101. It should be noted that the waste heat generated by the wafer 102 is also conducted to the respective input/output pins 4 via the wires 104 for transmitting signals. During the heat transfer process, a part of the waste heat remains in the guide 04. It is taken away, causing the internal temperature of the chip package structure 100 to be reversed. At the same time, the coefficient of thermal expansion of the wire 104 and the sealant 130 does not match and the tear of the wire 104 is broken or other undesirable effects. Therefore, the heat dissipation problem is not considered, and the unrecognized wire_10 (10) only provides the r-sound of the wafer 1 and the conventional heat dissipation solution. The use of ',,,,, but the part of the wire is not provided. [Summary of the invention] The wire is provided with a sheet package structure for solving the problem. The heat dissipation effect of the chip package structure includes a plurality of day-and-day chip I structures, including: a lead frame, a pin with a wire connection, and a 3-day sun piece. Each of the legs has a plurality of pads with i: around the upper seat; - a wafer, with a seat; on the plurality of guides, the wafer is disposed at the wafer joint; and the second block connects the wires to the wires of the pins. Seat, the convex second /: a recess and a protrusion, the recess is accommodating-sealing, covering the 圪:: extending between the wafer holder and the pins; and the heat sink block The wire bonding portion, the wafer, and the wires are arranged in accordance with the present invention - in addition to the glue, and the pins are extended to form a support portion. According to the present invention - the distance between each of the _::: ^=/2 of the wire-bonding portion of the top of the above-mentioned convex portion is at the highest point of the wires with respect to the pin In the embodiment, the chip package structure further includes 129793, and the oc/e includes an insulating layer disposed on the top of the protruding portion. According to an embodiment of the invention, the bottom surface of the heat dissipation block is exposed on the bottom surface of the sealant. According to a consistent embodiment of the invention, the wire may be a gold wire, a steel wire or a wire. According to an embodiment of the invention, the protruding portion may be an annular block </ br> around which the J is wrapped around the recess. Further, the protruding portion may also include a plurality of protrusions </ s> corresponding to the two side regions or the corner regions of the recess. The invention adopts a heat dissipation structure capable of absorbing the waste heat of the wire and the wafer at the same time, thereby avoiding the adverse effects caused by the heat generation of the wire, and at the same time, solving the breakage of the wire due to thermal stress of the V wire and the sealant in a local temperature environment or Poor contact. The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] The cross-section of the wafer package structure of the embodiment is shown in FIG. 2. The chip package structure 200 includes a wafer 2, a guide, a wood 210, a plurality of wires 204, a heat sink 220, and a 23 胶 glue. The wafer 202 has a plurality of pads 2〇2a, and the wafers 2〇2 are independently disposed on the conductive wafers 10 to transfer the pads 202a on the wafer 202 from the individual wires 204. Input/output signals. The lead frame 〇曰 is used to carry the wafer holder 212 of the wafer 202, and a plurality of pins 214 extend outwardly from the periphery of the raft holder 212. The common wafer holder 212 is 7 1297^3 1 coffee wf.doc/e flat plate, and has a support rod (not shown) disposed around the wafer holder 212, and the weight of the wafer 202 is supported. In addition, the support bars of the wafer holder 212 can also be folded down slightly to form the wafer holder 212 to a height slightly lower than the height of the surrounding pins 214. Of course, in another embodiment (not shown), the wafer holder 212 and the surrounding pins 214 may also be on the same plane or in other relative relationships. / Basically, before the pin 214 is bent, the wafer 2〇2 is first fixed on the wafer holder 212 with a thermal paste or silver paste 203, and then the wire 204 is bridged from the pad 202a of the wafer 202 to the adjacent pin. 214, and the inner side surface of the pin 214 may first form a wire bonding portion 214a such that one end of the wire 2〇4 is tightly engaged with the wire bonding portion 214a of the pin 214. In addition, before the encapsulation 230 is coated, the bottom of the wafer holder 212 is first disposed with the heat dissipation block 220 ′, and the heat dissipation block 220 can extend between the wafer holder 212 and the pin 214 in addition to the wafer holder 212 . The gap formed. Finally, the encapsulant 23 〇 covers the wire bond portion 214a of the pin 214, the wafer 202, the wire 204, and the heat slug 220, and may also selectively expose the outer portion of the pin 214 or pin 214. The portion exposed outside the sealant 230 is bent into a support portion 216' so that the chip package structure 2 can be fixed to a substrate (not shown) or an object. It is worth noting that 'the temperature difference between the wire 204 (for example, gold wire, copper wire or aluminum wire) and the sealing tape 230 is very large, and the sealing tape 230 is not easy to dissipate heat, so the temperature of the wire 204 is higher than the surrounding ambient temperature. Many, easily lead to thermal stress concentration and break. The stress analysis experiment proves that the central section of the wire 204 is the highest temperature part and is also affected by thermal stress. 8 doc/e

I297%L 最大的地方。因此，導線204的中央區段即容易因導線204 與封膠230的熱膨脹係數不匹配而產生最大的熱應力。故 本發明設置散熱塊220的目的，除了可直接吸收由晶片2〇2 傳導至晶片座212的廢熱之外，更可吸收由晶片202傳導 至導線204的廢熱或導線204在傳輪資料的過程中發出的 熱能’以提南晶片封裝結構200的散熱效果。 如圖2所述，散熱塊220包括一凹穴222以及一凸伸I297%L the biggest place. Therefore, the central section of the wire 204 is liable to cause maximum thermal stress due to a mismatch in the coefficient of thermal expansion of the wire 204 and the sealant 230. Therefore, the purpose of the heat dissipating block 220 of the present invention is that, in addition to directly absorbing the waste heat conducted from the wafer 2〇2 to the wafer holder 212, the waste heat conducted from the wafer 202 to the wire 204 or the wire 204 in the transfer data can be absorbed. The thermal energy emitted in the 'heat dissipation effect of the southern wafer package structure 200. As shown in FIG. 2, the heat sink block 220 includes a recess 222 and a protrusion.

部224 ’而凹穴222至少可容置晶片座212，且凸伸部224 延伸至晶片座212與相鄰引腳214之間。在本實施例中， 政熱塊220以凹八222接觸晶片座212的底部，以吸收由 晶片202傳導至晶片座212的廢熱，且散熱塊22〇的凸伸 邛224相對罪近於導線204的周圍區域，以吸收導線2Q4 所輻射及/或傳導的廢熱。雖然在本實施例中，散熱塊22〇 的剖面形狀大致上為凹形，但其立體結構可實' 形來改變，其中凸伸部224可以是圍繞於凹穴 -環狀塊、或各自突起於凹穴222的兩側區域、角落區域 的多個凸起等’而凹穴222除了是平底四方結構之外，更 可以是圓盤結構、多邊形結構或者是框架結構所組合而成 的，至於材質的選訂可關或料高㈣材料，利用一 體成型或分段成_方式來製作散熱塊22g 或凸伸部224。 J凹人」2及/ 請參考圖3，其緣示散熱塊之凸伸部相對於導線的距 離的放大不意圖。在本實施例中， 、、、、 砰查旦土 &lt;认省A j甲政熱塊220的凸伸部224 了趾1罪近於導線204，尤盆η 土、&amp;认憎μ 兀其疋罪近於導線204的中央區 9 1297組 w£d〇c/e 段仁不會直接接觸導線204，以避免短路。另一種可行 的方式疋在凸伸部224的頂部224a形成一絕緣層226，因 而即使凸伸部224很靠近導線2G4，也會被絕緣層226隔 絕以避免短路。 在相對位置上，假設導線204的最高點相對於引腳214 的打線接合部214a的距離為η，❿散熱塊220的凸伸部 224至少會超過引腳214的打線接部21如所在的平面，但 不會超過導線2〇4的最高點。由於凸伸部224越靠近導線 204則效果越好，因此凸伸部224的頂部22如相對於導線 204的距離最好少於等於1/2H，以達到最佳的效果。此外-: 如圖2所示，散熱塊220的底部228可全面或部分地顯露 於封膠230之外，以使散熱塊220可透過外界的冷卻氣^ 或其他散熱裝置予以冷卻。 ' 綜上所述，本發明之晶片封裝結構包括可吸收晶片及 導線的廢熱的散熱塊，其可容置晶片座並延伸至晶片座與 相鄰引腳之間。當晶片及/或導線的溫度超過正常的工作溫 度時，可透過凸伸部及接觸晶片座的凹穴來吸收大量的^ 熱’以使溫度下降並達到冷卻的效果。因此，本發明之曰曰 片封裝結構不僅可使晶片的内部溫度降低，更可解味道二 溫度過高產生的不良影響。 、、〜 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保雙 範圍當視後附之申請專利範圍所界定者為準。 10 I297?J1 【圖式簡單說明】 圖1繪示習知一種晶片封裝結構的剖面示意圖。 圖2繪示本發明一實施例之晶片封裝結構的剖面示意 圖。 圖3繪示圖2之散熱塊之凸伸部相對於導線的距離的 放大示意圖。 【主要元件符號說明】 100 ·· 晶片封裝結構 102 ： 晶片 104 ·· 導線 110 ： 導線架 112 ： 晶片座 114 ： 引腳 120 ： 散熱片 130 ： 封膠 200 ： 晶片封裝結構 202 ： 晶片 202a :銲墊 203 ： 銀膠 204 ： 導線 210 ： 導線架 212 ： 晶片座 214 ： 引腳 214a ： .打線接合部 11 twf.doc/e 216 支撐部 220 散熱塊 222 凹六 224 凸伸部 224a :頂部 226 絕緣層 228 底部 230 封膠The portion 224' and the recess 222 can accommodate at least the wafer holder 212, and the projection 224 extends between the wafer holder 212 and the adjacent pin 214. In the present embodiment, the heat block 220 contacts the bottom of the wafer holder 212 with a recess 222 to absorb waste heat conducted from the wafer 202 to the wafer holder 212, and the protrusion 224 of the heat sink 22 is relatively close to the wire 204. The surrounding area absorbs the waste heat radiated and/or conducted by wire 2Q4. Although in the present embodiment, the heat dissipating block 22 is substantially concave in cross-sectional shape, its three-dimensional structure may be changed in shape, wherein the protruding portion 224 may be surrounded by a recess-annular block or a respective protrusion. In the two sides of the recess 222, a plurality of protrusions of the corner area, etc., and the recess 222 may be a combination of a disc structure, a polygonal structure or a frame structure, in addition to a flat-bottomed structure. The material can be selected or closed (4) material, and the heat sink block 22g or the protrusion portion 224 can be formed by integral molding or segmentation. J recessed person 2 and / Referring to Fig. 3, the reason for the enlargement of the distance of the projection of the heat dissipating block with respect to the wire is not intended. In the present embodiment, the sac of the sacred land of the AJ kezhen hot block 220 is sinned by the toe 1 and is close to the wire 204, the yam η soil, the & 憎 μ 兀The blame is close to the central zone 9 1297 of the wire 204. The w£d〇c/e segment does not directly contact the wire 204 to avoid a short circuit. Another possible way is to form an insulating layer 226 on the top 224a of the projection 224, so that even if the projection 224 is very close to the wire 2G4, it is separated by the insulating layer 226 to avoid a short circuit. In the relative position, assuming that the highest point of the wire 204 is η with respect to the wire bonding portion 214a of the pin 214, the protrusion 224 of the heat sink block 220 at least exceeds the plane of the wire bonding portion 21 of the pin 214. , but will not exceed the highest point of the wire 2〇4. The closer the projections 224 are to the wire 204, the better the effect, so that the top 22 of the projection 224, preferably at a distance of less than or equal to 1/2H, for the best effect. In addition - as shown in Fig. 2, the bottom portion 228 of the heat slug 220 can be fully or partially exposed outside the sealant 230 so that the heat sink block 220 can be cooled by external cooling air or other heat sinks. In summary, the chip package structure of the present invention includes a heat sink block that absorbs waste heat from the wafer and wires, which can accommodate the wafer holder and extend between the wafer holder and adjacent pins. When the temperature of the wafer and/or the wire exceeds the normal operating temperature, a large amount of heat can be absorbed through the projection and the pocket contacting the wafer holder to lower the temperature and achieve the cooling effect. Therefore, the chip package structure of the present invention not only lowers the internal temperature of the wafer, but also adversely affects the excessive temperature of the taste. The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is defined by the scope of the appended claims. 10 I297?J1 [Simple Description of the Drawings] FIG. 1 is a schematic cross-sectional view showing a conventional chip package structure. 2 is a cross-sectional view showing a wafer package structure in accordance with an embodiment of the present invention. 3 is an enlarged schematic view showing the distance between the protrusion of the heat sink block of FIG. 2 with respect to the wire. [Main component symbol description] 100 ·· Chip package structure 102: Wafer 104 ·· Conductor 110: Lead frame 112: Wafer holder 114: Pin 120: Heat sink 130: Sealant 200: Wafer package structure 202: Wafer 202a: Solder Pad 203: Silver glue 204: Wire 210: Lead frame 212: Wafer holder 214: Pin 214a: Wire bonding portion 11 twf.doc/e 216 Support portion 220 Heat sink block 222 Concave six 224 Projection portion 224a: Top 226 Insulation Layer 228 bottom 230 sealant

Claims (1)

’1297·— 十、申請專利範圍： , 1.一種晶片封裝結構，包括： 一導線架，包括多數個獨立分開的引腳以及一晶片 ~ 座，該些引腳分別具有一打線接合部，其鄰近於該晶片座 之周圍； • 一晶片，具多數個銲墊配置於其一打線區域上，該晶 . 片係配置於該晶片座上， 多數條導線，電性連接該些銲墊至該些引腳之打線接 ® 合部； 一散熱塊，具一凹穴及一凸伸部，該凹穴係容置該晶 片座，該凸伸部係延伸至該晶片座與該些引腳之間；以及 一封膠，包覆該些引腳之打線接合部、該晶片、該些 導線以及該散熱塊。 2. 如申請專利範圍第1項所述之晶片封裝結構，其中 該些引腳延伸出該封膠之外，並彎折成一支撐部。 3. 如申請專利範圍第1項所述之晶片封裝結構，其中 φ 該凸伸部的頂部相對於該些導線的距離小於等於該些導線 的最高點相對於該引腳的打線接合部的距離的1/2。 ' 4.如申請專利範圍第1項所述之晶片封裝結構，更包 括一絕緣層，配置於該凸伸部的頂部。 5. 如申請專利範圍第1項所述之晶片封裝結構，其中 該散熱塊的底面顯露於該封膠之底面。 6. 如申請專利範圍第1項所述之晶片封裝結構，其中 該些導線為金線、銅線或鋁線。 13 1297¾¾ 破 d〇c/e 对1:申請專利範圍第1項所述之晶片封裘結構，t中 5亥凸伸部為-環狀塊，其環繞於該凹穴之周圍中 8·如申請專利範圍第1項所述之晶片封裝結槿， 〜凸伸部包括多個凸起，其對應配置於該凹穴之二 或角落區域。 陶侧區域'1297·—10. Patent application scope: 1. A chip package structure comprising: a lead frame comprising a plurality of independently separated pins and a wafer-mount, each of the pins having a wire bonding portion, Adjacent to the periphery of the wafer holder; a wafer having a plurality of pads disposed on a single-line region thereof, the wafer is disposed on the wafer holder, and a plurality of wires are electrically connected to the pads a heat-dissipating block having a recess and a protrusion, the recess receiving the wafer holder, the protrusion extending to the wafer holder and the pins And a glue covering the wire bonding portions of the pins, the wafer, the wires, and the heat dissipation block. 2. The chip package structure of claim 1, wherein the pins extend beyond the sealant and are bent into a support portion. 3. The chip package structure of claim 1, wherein a distance between a top portion of the protrusion and the plurality of wires is less than or equal to a distance from a highest point of the wires to a wire bonding portion of the pin. 1/2. 4. The wafer package structure of claim 1, further comprising an insulating layer disposed on top of the protrusion. 5. The chip package structure of claim 1, wherein a bottom surface of the heat sink block is exposed on a bottom surface of the sealant. 6. The chip package structure of claim 1, wherein the wires are gold wires, copper wires or aluminum wires. 13 12973⁄43⁄4 Broken d〇c/e Pair 1: The wafer sealing structure described in claim 1, wherein the 5 hai convex portion is a ring-shaped block that surrounds the periphery of the cavity. The wafer package structure according to claim 1, wherein the protrusion comprises a plurality of protrusions corresponding to the two or corner regions of the recess. Pottery side area 1414
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