1297819 九、發明說明： 【發明所屬之技術領域】 —本發明係關於一種校正發光二極體訊號之方法及其襞置，尤指一 種藉由蚊參考日，脈寬度綠正發光二極舰狀綠及其裝置，使 訊號經長距離之傳輸後仍保持正確波形而不失真。 t 【先前技術】 一發光二極體（LED)因具有高效率、壽命長、易調控等優點，為 目可最受矚目的照明、指示或顯示光源之―。其中用於—般交通號諸 或廣告看板的發光二極體因訊號傳輸距離較長或面積較大，容易發生 訊號延遲、衰減或失真等問題。 第1圖為典型LED驅動裝置傳輸訊號之示意圖，其中驅動積體電 路裝置11、21、31藉由訊號線12、22、32串接，將控制訊號傳輸至 各驅動積體電路裝置所連接之發光二極體叢13、23、33，每—發光二 極體叢通常包括紅綠藍三色光。當串接之LED叢愈多時，控制訊號往 往會發生錯誤。1297819 IX. Description of the invention: [Technical field to which the invention pertains] - The present invention relates to a method and apparatus for correcting a light-emitting diode signal, and more particularly to a pulse-width green positive-lighting dipole ship by means of a mosquito reference day The green and its device keep the signal in the correct waveform without distortion after long distance transmission. t [Prior Art] A light-emitting diode (LED) is the most attractive lighting, indicating or display light source because of its high efficiency, long life and easy regulation. Among them, the light-emitting diodes used for general traffic numbers or advertising billboards are prone to signal delay, attenuation or distortion due to the long transmission distance or large area of the signal. 1 is a schematic diagram of a typical LED driving device transmission signal, wherein the driving integrated circuit devices 11, 21, 31 are connected in series by signal lines 12, 22, 32, and the control signals are transmitted to the respective driving integrated circuit devices. The light-emitting diode bundles 13, 23, 33, each of the light-emitting diode bundles usually comprise red, green and blue light. When there are more LED bundles connected in series, the control signal will often have an error.
•為解決上述問題，已知德州儀器、東芝、意法半導體（ST ^roelectronics)等國際大廠皆採用放大輸出訊號的方式，來解決訊 號衰減的問題，但無法解決訊號延遲及失真制題。在此情況下，傳 輸距離通纟僅大約3G公分，且兩個驅紐體電路晶片之間的距離有 限；因此仍必料加巾麵（零齡）。然而，此種方法不僅增加成 本，且浪費空間。 此外，驅動積體電路晶片與發光二極體通f共用_電壓源，但由 於線路上寄生電感等的影響，使驅動積體電路晶片的電壓無法穩定。 傳=解決此問題的方法主要為，於㈣積體電路晶片與電源接點之間 加,片納（Zener) 一極體。然而，因齊納二極體對於高頻雜訊反應 很，此法效果將使輸出峨受制於電_定度，尤其是高速傳送時 特別明顯，也因此直接景彡響傳輸訊號的正碟性。 有L於此’貝有必要針對上述習知技術的種種缺失加以改善。 1297819 【發明内容】 本發明之目的在於提供一種控制發光二極體訊號傳輸之方法及其 裝置，以避免發光二極體_接後發生傳輸訊號失真的問題。 本發明校正發光二極體訊號之方法係用於複數個串接之LED驅動 積體電路，由外部輸入之參考時脈訊號及]LED控制時序訊號，經由串 接之LED驅動積體電路傳送，用以驅動或控制與每一級驅動積體電路 連接之發光二極體；該方法之特徵在於··於至少一級驅動積體電路中， 使為參考時脈訊號之脈衝寬度為固定值後，再將led控制時序訊號與 參考時脈訊號同步化，以校正該LED控制時序訊號之波形。 上述之每一級驅動積體電路之LED控制時序訊號可用以驅動或控 制任何發光二極體之組合，例如，一紅綠藍發光二極體叢（RGB cluster)。 參考時脈訊5虎之脈衝寬度並無特別限制，通常被固定為2〇〜looo ns，較佳為20〜1〇〇 ns 〇 本發明參考時脈訊號與LED控制時序訊號可藉由任何適當方法使 之同步化；例如，使用交互關聯使同為上緣或同為下緣；二波形之上 緣或下緣較佳為相距約20〜3〇ns。 本發明並根據上述方法設計一驅動發光二極體之積體電路裝置，• In order to solve the above problems, it is known that international companies such as Texas Instruments, Toshiba, and ST ^roelectronics use amplified output signals to solve signal attenuation problems, but cannot solve signal delay and distortion problems. In this case, the transmission distance is only about 3G cm, and the distance between the two drive circuit chips is limited; therefore, the towel surface (zero age) must still be added. However, this approach not only increases costs but also wastes space. Further, the integrated integrated circuit wafer and the light-emitting diode pass f share a voltage source, but the voltage of the integrated integrated circuit wafer cannot be stabilized due to the influence of parasitic inductance or the like on the line. Pass = The main solution to this problem is to add a Zener to the (4) integrated circuit chip and the power contact. However, since the Zener diode reacts very well to high-frequency noise, the effect of this method will make the output 峨 subject to the electric _ determination, especially when it is transmitted at high speed, and therefore the direct view of the transmission signal. . It is necessary to improve the various defects of the above-mentioned conventional techniques. 1297819 SUMMARY OF THE INVENTION An object of the present invention is to provide a method and a device for controlling signal transmission of a light-emitting diode to avoid the problem of distortion of a transmission signal after the LED is connected. The method for correcting the LED signal is used for a plurality of serially connected LED driving integrated circuits, and the externally input reference clock signal and the LED control timing signal are transmitted through the serially connected LED driving integrated circuit. The method is characterized in that the light-emitting diode connected to each stage of the driving integrated circuit is driven or controlled; the method is characterized in that, in at least one stage of driving the integrated circuit, after the pulse width of the reference clock signal is a fixed value, The LED control timing signal is synchronized with the reference clock signal to correct the waveform of the LED control timing signal. Each of the above stages drives an LED control timing signal of the integrated circuit to drive or control any combination of light emitting diodes, for example, a red, green, and blue RGB cluster. The pulse width of the reference pulse is not particularly limited, and is usually fixed to 2 〇 tolooo ns, preferably 20 to 1 〇〇 ns. The reference clock signal and LED control timing signal of the present invention can be any appropriate. The method makes it synchronized; for example, using the interactive association to make the upper edge or the same lower edge; the upper or lower edge of the second waveform is preferably about 20 to 3 ns. According to the present invention, an integrated circuit device for driving a light-emitting diode is designed according to the above method.
主要包括一參考時脈訊號之輸入端及對應之輸出端，及至少一個LED 控制時序訊號之輸入端及對應之輸出端；LED控制時序訊號係用以驅 動或控制至少一個發光二極體；積體電路裝置之特徵在於：包括一訊 旒傳輸控制單元，用以固定該參考時脈訊號之脈衝寬度為定值，及使 該LED控制時序訊號與該參考時脈訊號同步化，以校正該led控制 時序訊號。 上述之訊號傳輸控制單元包括：一第一開關、一第二開關及一電 容。第二開關與第一開關串聯；電容的一端由第一開關與第二開關之 間接出，另一端則接地。據此，當輸入參考時脈訊號為『〇N』時，第 一開關『ON』及第二開關同為『〇FF』，此時電容開始充電，當電容 1297819 充電達飽和時開始放電，並觸發第一開關為『0FF』及第二開關為 『ON』，而使參考時脈訊號變為『OFF』。 上述之第一開關及第二開關較佳為M〇s電晶體開關。例如，第一 開關包括以源極及沒極串聯之第一 PM〇s電晶體及第二pm〇s電晶 體，第二開關包括以源極及汲極串聯之第一 NM〇s電晶體及第二 NMOS電晶體；第二PM0S電晶體之汲極則連接至第一 NM〇s電晶體 之源極。較佳地，第一 PMOS電晶體及第二NM0S電晶體之閘極分別 連接至一電流鏡源。 本發明之積體電路裝置尚可包括一穩壓單元，該穩壓單元包括一 PMOS電晶體、一工作放大器及一電阻。pM〇s電晶體之源極連接至 一電壓源，閘極連接至該工作放大器的輸出端，汲極則連接至一共同 接點。工作放大器之負極輸入端連接至一固定電位，正極輸入端連接 至該共同接點。電阻之一端連接至該共同接點，另一端接地。據此， 该共同接點可提供積體電路裝置一穩定之低電壓。 上述之積體電路裝置中，相鄰之訊號輸入或輸出端之間尚可包括 一隔離用之接地線，以避免相互干擾。 實際使用時，可將積體電路裝置與發光二極體共同容置於一透明 管或包覆於透明樹脂中，亦可視需要使用其他適當容器或材料。 本發明亦可延伸至包括上述積體電路裝置之配線模组，該配線模 組尚包括一訊號輸入/輸出端、一電阻及一電容；電阻之一端連接至該 配線模組之訊號輸入/輸出端，另一端連接至該積體電路裝置之訊號輸 入/輸出端；電容之一端連接至該配線模組之訊號輸入/輸出端，另一端 則接地。 【實施方式】 本發明方法主要係使用於如第1圖所示典型LED驅動裝置串接架 構。其中驅動積體電路晶片11、2卜31藉由訊號線12、22、32 _接Y 將控制訊號傳輸至各驅動積體電路晶片所連接之發光二極體叢13、 23、33，每一發光二極體叢通常包括紅綠藍三色光（RGBdu_)。 1297819 到寄 的LED接收到的喊失真，無法於正確時 L X致往後 為解決此-問題，本發明於每—驅動積體電度及顏色。 :爆時脈·—時脈 第2圖為本發明於每—個LED驅動積體電路裝置中使用的參考時 s) 1 正I將參考時脈的寬度蚊為初始設定的寬度。圖中開關 =S2為串耳外，電容c的一端由開關81及82之間接出，另一端則 田此;^正電路有—參考時脈訊號為『⑽』的電位觸發開關Μ， 控牵士J電，Vee電纽人時，觸發開關S1 ν〇Ν』及開關S2為『卿』， 匕T電『谷C開始充電。當電容c充電達飽和時開始放電，則觸發開關 S1為OFF』及開關S2為『〇N』，並使參考時脈訊號變為『〇ff』。 在此過程中，參考時脈訊號保持『ON』的時間，相當於電容c充電的 時間。因此，只要適當選擇電容C的充電容量，便可將參考時脈的寬 度固定。 第3圖為根據上述之參考時脈校正電路實際設計之電路。圖中。 PMOS電晶體τΐ、T2，NMOS電晶體T3、T4串聯。其中，電晶體T1 及電晶體T4的閘極分別連接一充電pM〇s電流鏡源（currents〇urce) 及放電NMOS電流鏡源U2 ’以提供定電流（constant current)充 放電機制以產生固定時間間格。電晶體丁2及電晶體乃則分別為第2a 圖中的開關S1及S2，電容C則由其間接出。藉由電容C的充放電， 可控制電晶體T2的汲極及電晶體T3的源極的電流，而電晶體T2及 T3的閑及提供參考時脈訊號之脈衝電壓，脈波寬度則由電容C的充放 電時間來決定。 /第4圖為參考時脈訊號校正前號的示意圖。圖（a)中，由外部控 制系統輸入驅動積體電路晶片11的參考時脈訊號ref具典型的波形； 1297819 週期中『ON』的時間佔5〇%，亦即工作週期（d尔㈣）為5〇%。 積體電路晶之校正電路（例如第2a圖）校正後，輸出 :考時脈訊號ref的母-週期中，『⑽』的時間為固定值（本實施 2為40 ns)。圖㈤顯示串接中的任一驅動積體電路晶片N以校正 電路校正後，輸出的參考時脈訊號ref的每一週期中，『⑽』的時間 再度被固定為40 ns。由此可知，就本發明之每—級驅動積體電路裝置 而言，參考時脈訊號的輸入及輸出脈衝寬度並不相關。 〜第5圖為藉由參考時脈訊號校正LED控制時序訊號的示意圖。藉 由父互關聯（eoirelation)參考時脈訊號與LED控制時序訊號，當參 考時脈訊號的寬度SI定後，便可據以校正LED控辦序喊的脈寬， 並使二者同步化。其中® (a)之轉積體電路晶片他細參考時脈 訊號refl的『上緣』校正lED控制時序訊號sU〜sn的『上緣』；圖 (b)之驅動積體電路晶片Nb則以參考時脈訊號代乜的『下緣』校正 LED控制時序訊號s21〜s23的『下緣』。藉由脈寬的校正及同步化， 可明顯減少輸入或輸出各驅動積體電路晶片的訊號誤傳情形。 須注意的是，如第5圖所示，在本發明的較佳實施例中，參考時 脈甙旎與LED控制時序訊號的邊緣並非完全對齊，其邊緣距離u或 t2約為20〜30 ns，其目的在於確認LED控制時序訊號處於最高或最低 電位，而非僅上、下緣的不確定區域。 此外，為提南驅動積體電路晶片電壓的穩定性，本發明之較佳實 施例於驅動積體電路晶片内部設計一穩壓整流器（L〇w Dr〇p 〇ut Regulator ’ LDO)。如第6圖所示，穩壓整流器包括一 pM〇s電晶體 T5，其源極連接至電壓源Vcc (12V)，閘極連接至一工作放大器 (Operational Amplifier ) 〇p的輸出端，汲極則串接一電阻r，電阻r 的另一端則接地。工作放大器〇p的負極輸入端連接至一固定電位Vref (約1.24V) ’正極輸入端則連結至電晶體T5的沒極與電阻r之間。 電壓源Vcc (12V)經過此LDO快速穩壓整流器後，可使驅動積體電 1297819 路晶片的輸出喊_於高位料轉在5 v，較不受外部電源vcc穩 定度的影響，而不致失真。 、，根據本發明之設計，由於每一驅動積體電路裝置在輸出訊號之 • 則，便將參考時脈訊號及LED控制時序訊號校正一次；因此，訊號的 正確性理論上將完全不受傳輸距離影響。 • 然而’驅動積體電路晶片的訊號接腳因相距甚近，而造成彼此干 擾。因此，於本發明之較佳實施例中，各相鄰的訊號接腳之間更插設 一隔離用的接地線。如第7圖所示，驅動積體電路晶片Nc典型地包括 串序訊號（serial data)輸入接腳SDi及輸出接腳SD〇、參考時脈訊號 # 輸入接腳CKi及輸出接腳CK〇、栓鎖（latch)訊號輸入接腳LEi及^ 出接腳LEo、致動（enable)訊號輪入接腳〇m及輸出接腳〇E〇。藉 由接地線G1〜G6適當地將各訊號接腳隔離，將可避免傳輸訊號彼此干 擾。 通常，本發明之每一驅動積體電路晶片於實際應用時，係插設於 一配線模組（module)上；再將模組以導線連接以進行訊號的傳輸。 然而，模組之間的導線亦常產生寄生電感，使傳輸中的脈衝波形不佳。 例如脈衝的上緣或下緣拖曳或震盪過大。為進一步使波形清晰而完 整，如第8圖所示，可於驅動積體電路晶片N1 &N2所在的模組 及M2上，分別設置一組電阻R1/電容C1及電阻R2/電容c2。電阻及 電谷的大小可依據導線L的距離及附加元件作調整。 為證明本發明校正電路之效果，將模組串接進行如下之實際量測 分析。 1·量測條件 第9圖為量測條件示意圖。如圖所示，串接25〇個含發光二極體 叢的模組Ml〜M250，相鄰的二個模組之間距為2公尺，全長約5〇〇公 尺。母一個發光二極體叢典型地包括四個紅色發光二極體、三個綠紅 色發光二極體、及三個藍色發光二極體。電壓源供給DC電壓， 10 1297819 且在第一個模組Ml的輸入端輸入5MHZ之參考時脈訊號。以示波器 量測第一個及第250個模組參考時脈訊號之輸出值。 2.量測結果 第10圖顯示量測數據結果，其中CH3及CH2為第一個模組的（5见) 及參考時脈訊號之輪出波型’· CH4及CH1為第250個模組的GND及 參考時脈訊號之輸出波型。由CH2與CH1之比較結果顯示，當輸入 5MHZ之參考時脈訊號時，傳送250個模組後的波型與原先傳送的波 型並無太大差別，因此仍可繼續傳送。此量測結果證明，本發明確實 有效增加發光二極體訊號之傳輸距離。 、 由於本發明方法及裝置可校正傳輸中的LED控制訊號，因此特別 適用於長距離的水管燈、線燈、大型看板、交通號制或告示等等。只 要將f接的LED及其驅動積體電路裝置以透明的樹脂、塑膠軟管或^ 克力f封裝，便可卩思思安裝在需要的場所或戶外。由於本發明之封聲 形式簡單，因此在維修更換時，只要將故障段剪除，接上可用的發光 二極體段，便可繼續使用。 【圖式簡單說明】 f 1圖為典型LED驅動裝置傳輸訊號之示意圖。 第2圖為本發明於每一個㈣驅動積體電路裝置中使用的參考時脈校 正電路， ^ 3圖為根據上述之參考時脈校正電路實際設計之電路。 ^ 4圖為參考時脈《校正前後的示意圖。 二圖為藉由參考時脈訊號校正led控制時序訊號的示意圖。 ，6圖為驅動積體電路晶片内部之穩壓電路。 :圖·、、、貞:各相鄰的訊號接腳之間更插設—隔離用的接地線。 圖顯示驅動積體電路晶片所在的配線模組。 f 9圖為量測條件示意圖。 第1〇圖顯示量測數據結果。 1297819 【主要元件符號說明】 驅動積體電路晶片 訊號線 發光二極體叢 電容 參考時脈訊號輸入/輸出接腳接腳 接地線 栓鎖訊號輸入、輸出接腳 導線 模組 致動LED輸出訊號輸入、輸出接腳 工作放大器 參考時脈訊號 電阻 開關 時序訊號輸入、輸出接腳 LED控制時序訊號 PMOS電晶體 PMOS電晶體 邊緣距離 電流鏡源 電源 固定電位 U、21、31、N、Na、Nb Nc、N1、N2 12、 22、32 13、 23、33 C、Cl、C2 CKi/CKo G1 〜G6The method mainly includes a reference clock signal input end and a corresponding output end, and at least one LED control timing signal input end and a corresponding output end; the LED control timing signal is used to drive or control at least one light emitting diode; The body circuit device is characterized in that: a signal transmission control unit is configured to fix a pulse width of the reference clock signal to a fixed value, and synchronize the LED control timing signal with the reference clock signal to correct the LED Control timing signals. The above signal transmission control unit comprises: a first switch, a second switch and a capacitor. The second switch is connected in series with the first switch; one end of the capacitor is indirectly led out by the first switch and the second switch, and the other end is grounded. Accordingly, when the input reference clock signal is “〇N”, the first switch “ON” and the second switch are both “〇FF”, at which time the capacitor starts to charge, and when the capacitor 1297819 is charged to saturation, the discharge starts, and The first switch is triggered to be "0FF" and the second switch is "ON", and the reference clock signal is changed to "OFF". The first switch and the second switch are preferably M〇s transistor switches. For example, the first switch includes a first PM〇s transistor and a second PM〇s transistor in a source and a gateless series, and the second switch includes a first NM〇s transistor in which the source and the drain are connected in series, and a second NMOS transistor; a drain of the second PMOS transistor is coupled to a source of the first NM 〇s transistor. Preferably, the gates of the first PMOS transistor and the second NMOS transistor are respectively connected to a current mirror source. The integrated circuit device of the present invention may further comprise a voltage stabilizing unit comprising a PMOS transistor, an operational amplifier and a resistor. The source of the pM〇s transistor is connected to a voltage source, the gate is connected to the output of the operational amplifier, and the drain is connected to a common contact. The negative input of the working amplifier is connected to a fixed potential, and the positive input is connected to the common contact. One end of the resistor is connected to the common contact and the other end is grounded. Accordingly, the common contact provides a stable low voltage of the integrated circuit device. In the above integrated circuit device, a grounding wire for isolation may be included between adjacent signal input or output terminals to avoid mutual interference. In actual use, the integrated circuit device and the light-emitting diode can be accommodated in a transparent tube or coated in a transparent resin, and other suitable containers or materials can be used as needed. The present invention can also be extended to a wiring module including the above-mentioned integrated circuit device. The wiring module further includes a signal input/output terminal, a resistor and a capacitor; and one end of the resistor is connected to the signal input/output of the wiring module. The other end is connected to the signal input/output terminal of the integrated circuit device; one end of the capacitor is connected to the signal input/output terminal of the wiring module, and the other end is grounded. [Embodiment] The method of the present invention is mainly applied to a tandem structure of a typical LED driving device as shown in Fig. 1. The driving integrated circuit chips 11, 2, 31 transmit the control signals to the light-emitting diode bundles 13, 23, 33 connected to the respective driving integrated circuit chips by the signal lines 12, 22, 32_Y. The light-emitting diode bundle usually includes red, green and blue three-color light (RGBdu_). 1297819 The shouting distortion received by the LED sent to the LED cannot be correct. L X is sent back. To solve this problem, the present invention drives the integrated electrical power and color. : Explosion Clock · Time Clock Figure 2 is the reference used in each of the LED driver integrated circuit devices. s) 1 Positive I will adjust the width of the reference clock to the initially set width. In the figure, the switch = S2 is the string ear, one end of the capacitor c is connected between the switches 81 and 82, and the other end is the field; the positive circuit has a reference trigger signal 『 "(10)" potential trigger switch Μ, control pull When the J electric, Vee electric button, the trigger switch S1 ν〇Ν』 and the switch S2 are "Qing", 匕T electric "Valley C starts charging. When the capacitor c starts to discharge when it is saturated, the trigger switch S1 is OFF and the switch S2 is "〇N", and the reference clock signal is changed to "〇ff". During this process, the time when the reference clock signal remains "ON" is equivalent to the time when the capacitor c is charged. Therefore, the width of the reference clock can be fixed by appropriately selecting the charging capacity of the capacitor C. Figure 3 is a circuit diagram based on the actual design of the reference clock correction circuit described above. In the picture. The PMOS transistors τ ΐ, T2, and the NMOS transistors T3 and T4 are connected in series. The gates of the transistor T1 and the transistor T4 are respectively connected to a charging pM〇s current mirror source (currents〇urce) and a discharge NMOS current mirror source U2′ to provide a constant current charge and discharge mechanism to generate a fixed time. Grid. The transistor D2 and the transistor are respectively switches S1 and S2 in Fig. 2a, and the capacitor C is indirectly derived therefrom. By charging and discharging the capacitor C, the drain of the transistor T2 and the source of the transistor T3 can be controlled, while the transistors T2 and T3 idle and provide the pulse voltage of the reference clock signal, and the pulse width is determined by the capacitor. The charge and discharge time of C is determined. / Figure 4 is a schematic diagram of the reference clock number correction reference number. In the figure (a), the reference clock signal ref of the integrated integrated circuit chip 11 is input by the external control system with a typical waveform; the time of "ON" in the cycle of 1297819 accounts for 5〇%, that is, the duty cycle (d (four)) It is 5〇%. After the correction circuit of the integrated circuit crystal (for example, Fig. 2a) is corrected, the time of the "(10)" is fixed in the mother-cycle of the test pulse signal ref (40 ns in the present embodiment 2). Fig. 5 shows the time of "(10)" is fixed to 40 ns in each cycle of the output reference clock signal ref after the correction circuit correction is performed by any of the drive integrated circuit chips N in the series connection. From this, it can be seen that with the per-stage driving integrated circuit device of the present invention, the input and output pulse widths of the reference clock signal are not correlated. ~ Figure 5 is a schematic diagram of the LED control timing signal by reference clock signal correction. By referring to the echo signal and the LED control timing signal by the parent eoirelation, when the width of the reference clock signal is set to SI, the pulse width of the LED control sequence can be corrected and the two can be synchronized. The product of the (a) revolving circuit is referenced to the "upper edge" of the clock signal refl, and the "upper edge" of the timing signal sU~sn is controlled; the driving integrated circuit chip Nb of the figure (b) is Refer to the "lower edge" of the clock signal to correct the "lower edge" of the LED control timing signal s21~s23. By correcting and synchronizing the pulse width, the signal mis-transmission of the input or output driver integrated circuit chip can be significantly reduced. It should be noted that, as shown in FIG. 5, in the preferred embodiment of the present invention, the reference clock and the edge of the LED control timing signal are not completely aligned, and the edge distance u or t2 is about 20 to 30 ns. The purpose is to confirm that the LED control timing signal is at the highest or lowest potential, not just the upper and lower edges of the uncertainty region. In addition, in order to stabilize the voltage of the integrated circuit of the driver circuit, a preferred embodiment of the present invention designs a voltage regulator rectifier (L〇w Dr〇p 〇ut Regulator 'LDO) inside the driver integrated circuit chip. As shown in Figure 6, the regulated rectifier includes a pM〇s transistor T5 whose source is connected to a voltage source Vcc (12V) and whose gate is connected to the output of an operational amplifier (Operational Amplifier) 〇p. Then, a resistor r is connected in series, and the other end of the resistor r is grounded. The negative input of the operational amplifier 〇p is connected to a fixed potential Vref (about 1.24V). The positive input is connected to the between the transistor T5 and the resistor r. After the voltage source Vcc (12V) passes through the LDO fast-regulated rectifier, the output of the 1297819-channel chip that drives the integrated body can be turned to 5 v, which is less affected by the stability of the external power supply vcc without distortion. . According to the design of the present invention, since each of the driving integrated circuit devices outputs the signal, the reference clock signal and the LED control timing signal are corrected once; therefore, the correctness of the signal is theoretically completely untransferred. Distance influence. • However, the signal pins that drive the integrated circuit chip are interfering with each other due to the close proximity. Therefore, in the preferred embodiment of the present invention, a grounding wire for isolation is further interposed between adjacent signal pins. As shown in FIG. 7, the drive integrated circuit chip Nc typically includes a serial data input pin SDi and an output pin SD, a reference clock signal # input pin CKi, and an output pin CK〇, The latch signal input pin LEi and the output pin LEo, the enable signal wheel input pin m and the output pin 〇E〇. By properly isolating the signal pins by the ground lines G1 to G6, the transmission signals can be prevented from interfering with each other. Generally, each of the driving integrated circuit chips of the present invention is inserted into a wiring module in practical application; and the modules are connected by wires for signal transmission. However, the wires between the modules also often produce parasitic inductance, which makes the pulse waveform in transmission poor. For example, the upper or lower edge of the pulse is dragged or oscillated too large. In order to further make the waveform clear and complete, as shown in Fig. 8, a set of resistor R1/capacitor C1 and resistor R2/capacitor c2 can be respectively disposed on the module and M2 where the integrated circuit chip N1 & N2 are driven. The size of the resistor and valley can be adjusted according to the distance of the wire L and the additional components. In order to prove the effect of the correction circuit of the present invention, the modules are connected in series for the following actual measurement analysis. 1. Measurement conditions Fig. 9 is a schematic diagram of measurement conditions. As shown in the figure, 25 modules M1 to M250 with LED stacks are connected in series, and the distance between adjacent modules is 2 meters and the length is about 5 feet. The mother-emitting diode bundle typically includes four red light-emitting diodes, three green-red light-emitting diodes, and three blue light-emitting diodes. The voltage source supplies a DC voltage, 10 1297819 and a reference clock signal of 5 MHz is input at the input of the first module M1. The oscilloscope measures the output values of the first and 250th module reference clock signals. 2. Measurement results Figure 10 shows the results of the measurement data, where CH3 and CH2 are the first module (5 see) and the reference clock signal is the round-out waveform '· CH4 and CH1 are the 250th module Output waveform of GND and reference clock signal. The comparison between CH2 and CH1 shows that when the reference clock signal of 5MHZ is input, the waveform after transmitting 250 modules is not much different from the original transmitted waveform, so the transmission can continue. This measurement result proves that the present invention effectively increases the transmission distance of the LED signal. Since the method and device of the present invention can correct the LED control signals in transmission, it is particularly suitable for long-distance water tube lights, line lights, large billboards, traffic numbers or notices, and the like. As long as the LEDs connected to the f and their drive integrated circuit devices are packaged in transparent resin, plastic hose or chrome f, they can be installed in the desired place or outdoors. Since the sound sealing form of the present invention is simple, when the repair and replacement is performed, the fault segment can be cut off and the available light-emitting diode segments can be connected to continue use. [Simple description of the diagram] The f 1 diagram is a schematic diagram of a typical LED driver transmission signal. Fig. 2 is a reference clock correction circuit used in each (four) drive integrated circuit device of the present invention, and Fig. 3 is a circuit actually designed according to the above reference clock correction circuit. ^ 4 is a reference clock "schematic diagram before and after correction. The second figure is a schematic diagram of correcting the LED control timing signal by referring to the clock signal. Figure 6 shows the voltage regulator circuit inside the integrated circuit chip. : Figure ·, ,, and 贞: Insert the grounding wires for isolation between adjacent signal pins. The figure shows the wiring module in which the integrated circuit chip is driven. Figure f 9 is a schematic diagram of the measurement conditions. Figure 1 shows the results of the measurement data. 1297819 [Key component symbol description] Driver integrated circuit chip signal line LED emitter capacitor reference clock signal input/output pin pin ground wire latch signal input and output pin wire module actuation LED output signal input Output pin working amplifier reference clock signal resistance switch timing signal input, output pin LED control timing signal PMOS transistor PMOS transistor edge distance current mirror source power supply fixed potential U, 21, 31, N, Na, Nb Nc, N1, N2 12, 22, 32 13, 23, 33 C, Cl, C2 CKi/CKo G1 ~ G6
Lei、Leo LLei, Leo L
Ml 〜M250 OEi、OEo OP ref' refl、ref2 R、R1、R2 SI、S2 SDi、SDo sll〜sl3、s21〜s23 ΤΙ、T2、T5 T3、T4 tl、t2 U1 及 U2Ml ~ M250 OEi, OEo OP ref' refl, ref2 R, R1, R2 SI, S2 SDi, SDo sll~sl3, s21~s23 ΤΙ, T2, T5 T3, T4 tl, t2 U1 and U2
VccVcc
Vref 12Vref 12