1297547 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種電晶體之製造方法，特別係指一種 薄膜電晶體之製造方法。 【先前技術】 隨著科技的發展，顯示器的體積日漸輕薄，傳統的陰 極射線管顯示器雖然有其優點，然而其體積大並且耗電， 因此，液晶顯示器、電漿顯示器及電致發光顯示器等平面 顯示器已漸漸成為主流，其中液晶顯示器由於具有低操作 電壓、無輻射線、重量輕及體積小等優點，更是蓬勃的發 展。 液晶顯示器的製造過程中，微影製程是高成本而且需 要高精密度控制的關鍵步驟，特別是在液晶顯示器的微影 製程中，陣列製程是最關鍵的步驟，因為眾多微小的薄膜 電晶體要同時形成在一塊基板上，因此，降低薄膜電晶體 的製程步驟可以有效的提升液晶顯示器的製造良率以及降 低其製造成本。 請參照第1A圖至第1G圖，第1A圖至第1G圖所示 係一習知製程中薄膜電晶體之結構剖面圖，其中，請參照 第1A圖，首先，提供一基板11，該基板11可採用一玻璃 基板11，之後，形成一第一金屬層12於該基板11之上， 並利用一第一光罩（圖中未示）定義出一閘極結構12a，且蝕 刻該第一金屬層12以形成該閘極結構12a。請參照第1B 圖，於該閘極結構12a與該基板11之上形成一第一絕缘層 1297547 13明參第1C圖，形成一半導體層15於兮〜 13之上，利用摻雜製程使該半導體層15之^弟絕緣層 Π 型摻雜半導體層15a，並姻—第二料（圖中^形r 一半導體結構15b，且蝕刻該半導體層15 丁）疋義出 導體層15a以形成該半導體結構15b。請炎；I""型摻雜半 成-第二金屬層16於該半導體結構15/及=^圖’形 13之上，並利用-第三光糊中未示)定義；二絕緣層 恤及-〉及極結構16b，且㈣該第二全 雜^構 ，，、⑹及該纖構i6b。心^ H亥弟二光罩作為遮罩，㈣該n型摻雜 ’ 再剝除光阻以形成-通道結構15c 、Ua， :第二_17於該源極賴16a、該：二= ⑽中未罐義出—接觸窗結構m，且_該第二絕緣声 亥接觸窗結構17a。請參照第犯圖，形成一透明 至屬層18於該汲極結構16b及該第二絕緣層17之上 五光罩（圖中未示）定義出一晝素電極結構心且 則f透明金屬層1W形成該晝素電極結構18a。 明麥恥第2圖’第2圖所示係第1A圖至第犯圖中習 其了膜電晶體之製造流程步驟圖，首先，提供一基板，該 之上具有-間極結構，且該開極結構與該基板之上具 弟-絕緣層（步驟S2G)，其中該間極結構係將一第一金 屬層經钱刻製程形忐& 雜半導體層於該第-絕^ ’形成一半導體層及一 η型推 昂 '，、巴、，豕層之上（步騾S21);之後，形成一 1297547 第一光阻層於該半導體層及該η型摻雜丰導體層之 «XL ( Λ/ 驟 S22)，之後’钱刻該半導體層及該^型摻雜半導㉟岸 少 成一半導體結構（步驟S23);之後，去除該第一光阻層 驟S24);之後，形成一第二金屬層於該半導體結構及唁第 一絕緣層之上（步驟S25);之後，形成一第二光阻層於 二金屬層之上（步驟S26);之後，#刻該第二金屬; -源極結構及-&極結構(步驟S27);之後，η型捧 雜半導體層，形成-通道結構(步驟S28);最後，ς = 二光阻層（步驟S29)。 ’、μ弟 減少習知薄膜電晶體之製造流程步驟，即可 ,陣=製程的製造良率以及降低其製造成本，此對二液^ _不為的生產製造，係一重要課題。 【發明内容】 本發明之目的係減少薄膜電晶體之1297547 IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a transistor, and more particularly to a method of manufacturing a film transistor. [Prior Art] With the development of technology, the size of the display is becoming thinner and lighter. Although the conventional cathode ray tube display has its advantages, it is bulky and consumes electricity. Therefore, the plane of the liquid crystal display, the plasma display, and the electroluminescence display Display has gradually become the mainstream, and liquid crystal displays are booming due to their low operating voltage, no radiation, light weight and small size. In the manufacturing process of liquid crystal displays, the lithography process is a costly step and requires high-precision control. Especially in the lithography process of liquid crystal displays, the array process is the most critical step, because many tiny thin film transistors are required. At the same time, it is formed on one substrate. Therefore, the process steps of reducing the thin film transistor can effectively improve the manufacturing yield of the liquid crystal display and reduce the manufacturing cost thereof. Please refer to FIG. 1A to FIG. 1G. FIG. 1A to FIG. 1G are structural cross-sectional views of a thin film transistor in a conventional process. Referring to FIG. 1A, first, a substrate 11 is provided. 11 can use a glass substrate 11, after which a first metal layer 12 is formed on the substrate 11, and a gate structure 12a is defined by a first mask (not shown), and the first The metal layer 12 forms the gate structure 12a. Referring to FIG. 1B, a first insulating layer 1297547 13 is formed on the gate structure 12a and the substrate 11. The semiconductor layer 15 is formed on the 兮-13, and the doping process is used to make the The semiconductor layer 15 is doped with a semiconductor layer 15a, and a second material (the semiconductor structure 15b is etched and the semiconductor layer 15 is etched) to form the conductor layer 15a to form the conductive layer 15a. Semiconductor structure 15b. Inflammation; I"" type doped semi-finished-second metal layer 16 is defined over the semiconductor structure 15/ and the pattern 13 and is defined by a third photo paste; Shirt and -> and pole structure 16b, and (d) the second full structure, (6) and the fiber i6b. Heart ^ H Haidi two mask as a mask, (d) the n-type doping 're-radiating the photoresist to form a channel structure 15c, Ua, : the second _17 at the source pole 16a, the: two = (10) The middle can not be out-contact window structure m, and the second insulating sound contact window structure 17a. Referring to the first map, a transparent layer 18 is formed on the drain structure 16b and the second insulating layer 17. A mask (not shown) defines a halogen electrode structure and the transparent metal is f. The layer 1W forms the halogen electrode structure 18a. Fig. 2 is a diagram showing the manufacturing process of the film transistor in the first drawing to the first drawing. First, a substrate is provided, which has an inter-electrode structure, and The open-pole structure and the substrate have a dielectric-insulating layer (step S2G), wherein the inter-pole structure forms a first metal layer through the etching process and the impurity semiconductor layer forms a first a semiconductor layer and an n-type push-on, a, and a germanium layer (step S21); thereafter, a 1297547 first photoresist layer is formed on the semiconductor layer and the n-type doped conductor layer «XL (Λ/Step S22), after which the semiconductor layer and the doped semiconductor semiconductor 35 are reduced to a semiconductor structure (step S23); thereafter, the first photoresist layer S24 is removed; thereafter, a a second metal layer over the semiconductor structure and the first insulating layer (step S25); thereafter, forming a second photoresist layer over the two metal layers (step S26); thereafter, #刻刻 the second metal; a source structure and a - & pole structure (step S27); thereafter, the n-type semiconductor layer is formed to form a channel structure (step S28); finally, ς = Photoresist layer (step S29). </ br> </ br> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> SUMMARY OF THE INVENTION The object of the present invention is to reduce the thickness of a thin film transistor.
提升陣列製程的f谇声至m U 本。 &良率，進而降低液晶顯示II之製造成 方法土：目的’本發明揭露-種薄膜電晶體之製造 Τ列步驟··提供—基板，該基板上呈有-門 氣结構，且該開 土敬上閘 形成-半導構與縣板之上具有—第—絕緣層； 忐外、月且日及—歐姆接觸層於該第一絕緣舞之上. 成-弟-光阻層於該 4狀上，形 該歐姆接觸声，祐〃培接奶層之上，钱刻該半導體層及 結構，並使‘半導：：姆接觸層形成-源極結構及-汲極 層於該第—光卩层足成一逋迢結構；形成一第二光阻 層及财導縣之上；㈣該半導體層， 7 1297547 使該半導體層形成一半導體結構；及去除該第一光阻層及 該第二光阻層等步驟。 本發明之薄膜電晶體之製造方法，於形成該源極結 構、該没極結構、該通道結構後，不去除該第一光阻層， 而直接於該第一光阻層上形成該第二光阻層，藉以形成該 半導體結構’並且’採用η型接雜之非晶碎、多晶梦層或 有機金屬化合物取代金屬作為該源極結構及該汲極結構之 材料，以減少薄膜電晶體的製程步驟，進而提升液晶顯示 器的製造良率並降低其製造成本。 為讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 【實施方式】 請參照第3Α圖至第3Η圖，第3Α圖至第3Η圖所示 係本發明製程中薄膜電晶體之結構剖面圖，其中，請參照 第3Α圖，首先，提供一基板30，該基板30可採用一玻璃 基板，之後，形成一金屬層31於該基板30之上，該第一 金屬層31可採用鋁(Α1)、銅（Cu)、鎢（W)、鉻（Cr)等金屬或 其合金，並以濺鍍製程形成於該基板30之上，之後，利用 一第一光罩（圖中未示）定義出一閘極結構31a，且蝕刻該金 屬層31以形成該閘極結構31a。請參照第3B圖，於該閘 極結構31a與該基板30之上形成一第一絕緣層32及一半 導體層33，該第一絕緣層32可採用氮化矽（SiNx)或氧化矽 (SiOx)，該半導體層33可採用非晶矽（a-Si)，之後，形 8 1297547 成一歐姆接觸層34於該半導體層33之上，該歐姆接觸層 34之形成可採用數種方式，例如，可利用摻雜製程使該半 導體層33之表層形成一 η型摻雜半導體層33，以增加其 導電性，此外，該歐姆接觸層34亦可採用一多晶矽層（Poly Silicon; P-Si)，該多晶矽層可利用準分子雷射退火(Excimer Laser Anneal; ELA)將該半導體層33表層之非晶矽轉換為 多晶矽，以增加其導電性，此外，該歐姆接觸層34亦可採 用一有機金屬化合物層，例如該半導體層3 3以一化學氣相 沉積製程形成後，於同一化學氣相沉積製程採用六羰基化 鶴氣體（t皿gsten hexacarbonyl，W(C〇)6)為材料形成於該 半導體層33之上，而後，形成一第一光阻層35於該半導 體層33之上，並利用一第二光罩（圖中未示）使該第一光阻 層35形成一第一光阻結構35a及一第二光阻結構35b。請 參照第3C圖，以乾式蝕刻技術蝕刻該第一光阻結構35a 及該第二光阻結構35b以外之該歐姆接觸層34，並蝕刻一 部分厚度之該半導體層33,如此可利用該歐姆接觸層34 形成一源極結構34a及一汲極結構34b，並於該半導體層 33形成一通道結構33a。請參照第3D圖，形成一第二光阻 層36於該第一光阻結構35a、該第二光阻結構35b及該半 導體層33之上，並利用一第三光罩（圖中未示）使該第二光 阻層36形成一第三光阻結構36a。請參照第3E圖，以乾 式蝕刻技術蝕刻該第一光阻結構35a、該第二光阻結構35b 及該第三光阻結構36a以外之該半導體層33，如此可使該 半導體層33形成一半導體結構33b。請參照第3F圖，去 9 1297547 除該第一光阻層35及該第二光阻層36，使該源極結構 34a、該汲極結構34b及該通道結構33a暴露於外界環境。 請參照第3G圖，形成一第二絕緣層37於該源極結構34a、 % 該汲極結構34b、該通道結構33a及該第一絕緣層32之上， . 該第二絕緣層37可採用氮化矽（SiNx)或氧化石夕（Si〇x)，之 後，利用一第四光罩（圖中未示）使該第二絕緣層37形成一 接觸窗結構37a，該接觸窗結構37a係位於該没極結構34b 春 上方。請參照第3H圖，形成一透明導電層於該没極結 構34b及該第二絕緣層37之上，該透明導電層38為銦錫 氧化物（Indium Tin Oxide; ITO)或銦鋅氧化物（indium zincRaise the f-click of the array process to m U. & yield, and further reduce the manufacturing method of liquid crystal display II. The purpose of the present invention is to provide a substrate having a gate-air structure on the substrate. The earth gate is formed - the semi-conducting structure has a -first insulating layer on the county plate; the outer, moon and day and - ohmic contact layers are above the first insulating dance. The Cheng-di-photoresist layer is In the shape of 4, the ohmic contact sound is formed, and the semiconductor layer and the structure are engraved on the milk layer, and the 'semiconductor:: the contact layer is formed - the source structure and the drain layer are in the first - the pupil layer is formed into a unitary structure; forming a second photoresist layer and over the financial prefecture; (4) the semiconductor layer, 7 1297547, the semiconductor layer is formed into a semiconductor structure; and removing the first photoresist layer and the The second photoresist layer and the like. In the method for fabricating a thin film transistor of the present invention, after forming the source structure, the gate structure, and the channel structure, the first photoresist layer is not removed, and the second photoresist layer is formed directly on the first photoresist layer. a photoresist layer for forming the semiconductor structure 'and' using an n-type amorphous amorphous, polycrystalline dream layer or an organometallic compound in place of the metal as the source structure and the material of the drain structure to reduce the thin film transistor The process steps further increase the manufacturing yield of the liquid crystal display and reduce its manufacturing cost. The above described objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims appended claims 3, FIG. 3 to FIG. 3 are cross-sectional views showing the structure of a thin film transistor in the process of the present invention. Referring to FIG. 3, first, a substrate 30 is provided. The substrate 30 may be a glass substrate. Forming a metal layer 31 on the substrate 30. The first metal layer 31 may be made of a metal such as aluminum (Α1), copper (Cu), tungsten (W), or chromium (Cr) or an alloy thereof, and is sputtered. A process is formed on the substrate 30. Thereafter, a gate structure 31a is defined by a first mask (not shown), and the metal layer 31 is etched to form the gate structure 31a. Referring to FIG. 3B, a first insulating layer 32 and a semiconductor layer 33 are formed on the gate structure 31a and the substrate 30. The first insulating layer 32 may be made of tantalum nitride (SiNx) or yttrium oxide (SiOx). The semiconductor layer 33 may be made of amorphous germanium (a-Si). Thereafter, the shape 8 1297547 is formed as an ohmic contact layer 34 over the semiconductor layer 33. The ohmic contact layer 34 may be formed in several ways, for example, The surface of the semiconductor layer 33 can be formed into an n-type doped semiconductor layer 33 by a doping process to increase its conductivity. In addition, the ohmic contact layer 34 can also be a polysilicon layer (P-Si). The polycrystalline germanium layer can convert the amorphous germanium in the surface layer of the semiconductor layer 33 into polycrystalline germanium by excimer laser annealing (ELA) to increase the conductivity thereof. In addition, the ohmic contact layer 34 can also adopt an organic metal. After the compound layer, for example, the semiconductor layer 33 is formed by a chemical vapor deposition process, a hexacarbonylated helium gas (t(s) hexacarbonyl, W(C〇)6) is formed in the same chemical vapor deposition process. Above the semiconductor layer 33, and Thereafter, a first photoresist layer 35 is formed on the semiconductor layer 33, and the first photoresist layer 35 is formed into a first photoresist structure 35a and a first portion by a second mask (not shown). Two photoresist structure 35b. Referring to FIG. 3C, the ohmic contact layer 34 except the first photoresist structure 35a and the second photoresist structure 35b are etched by a dry etching technique, and the semiconductor layer 33 is partially etched, so that the ohmic contact can be utilized. The layer 34 forms a source structure 34a and a drain structure 34b, and forms a channel structure 33a in the semiconductor layer 33. Referring to FIG. 3D, a second photoresist layer 36 is formed on the first photoresist structure 35a, the second photoresist structure 35b, and the semiconductor layer 33, and a third mask is used (not shown). The second photoresist layer 36 is formed into a third photoresist structure 36a. Referring to FIG. 3E, the first photoresist structure 35a, the second photoresist structure 35b, and the semiconductor layer 33 other than the third photoresist structure 36a are etched by a dry etching technique, so that the semiconductor layer 33 can be formed. Semiconductor structure 33b. Referring to FIG. 3F, in addition to the first photoresist layer 35 and the second photoresist layer 36, the source structure 34a, the drain structure 34b, and the channel structure 33a are exposed to the external environment. Referring to FIG. 3G, a second insulating layer 37 is formed on the source structure 34a, the drain structure 34b, the channel structure 33a, and the first insulating layer 32. The second insulating layer 37 can be used. Nitridium nitride (SiNx) or oxidized stone (Si〇x), after which the second insulating layer 37 is formed into a contact window structure 37a by a fourth mask (not shown), and the contact window structure 37a is Located above the spring of the immersed structure 34b. Referring to FIG. 3H, a transparent conductive layer is formed on the non-polar structure 34b and the second insulating layer 37. The transparent conductive layer 38 is indium tin oxide (ITO) or indium zinc oxide (indium tin oxide). Indium zinc
Oxide; IZO)，並以瘛鍍被程形成，之後，利用一第五光罩 - (圖中未示）定義出一晝素電極結構38a，且蝕刻該透明導電 層〇8以形成該晝素極、居構3 8a，該晝素電極結構3可 透過該接觸窗結構37a與該汲極結構34b電性連接。 請蒼照第4圖’弟4圖所示係本發明之薄膜電晶體結 φ 構圖，其係於一基板30上形成一閘極結構31a、一第一絕 緣層32、-半導體結構33b、一源極結構％及一没極处 構34b，其中，該基板30可採用一玻璃基板3〇，該閘極結 - 構31&之材料可採用鋁、铜、鎢、鉻等金屬或其合金，並 以濺鍍製程形成於該基板3G之上，該第—絕緣層I之材 • 料可制氮M(SiNX)錢切(驗），形成於該閘極結構 化與該基板3〇之上，該半導發結構ssb之材料可採用非 日日日石夕’形成於該第-絕緣層32之上，該源極結構％及該 汲極結構34b之材料可採用n型摻雜之非晶梦、多晶石夕層 10 1297547 或有機金屬化合物，形成於該半導體結構33b之上。 請參照第5圖，第5圖所示係第4圖中本發明之薄膜 電晶體之製造流程步驟圖，首先，提供一基板，該基板之 上具有一閘極結構，且該閘極結構與該基板之上具有一第 一絕緣層（步驟S51)，其中，該基板可採用一玻璃基板，該 閘極結構之材料可採用紹、銅、鎮、絡等金屬或其合金， 該第一絕緣層之材料可採用氮化矽（SiNx)或氧化矽 (Si〇x);之後，形成一半導體層及一歐姆接觸層於該第一 絕緣層之上（步驟S52)，其中，該半導體層之材料可採用非 晶矽，該歐姆接觸層之材料可採用η型摻雜半導體；之後， 形成一第一光阻層於該歐姆接觸層之上（步驟S53);之後， 蝕刻該半導體層及該歐姆接觸層，使該歐姆接觸層形成一 源極結構及一汲極結構，並使該半導體層形成一通道結構 (步驟S54)，此蝕刻步驟可採用乾式蝕刻技術；之後，形成 一第二光阻層於該第一光阻層及該半導體層之上（步驟 S55);之後，蝕刻該半導體層，使該半導體層形成一半導 體結構（步驟S56)，此蝕刻步驟亦可採用乾式蝕刻技術；最 後，去除該第一光阻層及該第二光阻層（步驟S57)。與第2 圖所示習知薄膜電晶體之製造流程步驟相較，本發明之薄 膜電晶體之製造流程步驟減少了去除該第一光阻層（步驟 S24)、形成一第二金屬層於該半導體結構及該第一絕緣層 之上（步驟S25)及蝕刻該第二金屬層，形成一源極結構及 一汲極結構（步驟S27)等三個製程步驟。 如上所述，相較於習知技術，本發明之薄膜電晶體之 1297547 製造方法，於形成該源極結構、該汲極結構、該通道結構 後，不去除該第一光阻層，而直接於該第一光阻層上形成 該第二光阻層，藉以形成該半導體結構，並且，採用η型 摻雜之非晶矽、多晶矽層或有機金屬化合物取代金屬作為 該源極結構及該；及極結構之材料’具有製造流程步驟較少 之優點，因此可有效的提升陣列製程的製造良率，並進而 降低液晶顯示器的製造成本。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範.圍所界定者為準。 【圖式簡單說明】 第1Α圖至第1G圖係一習知製程中薄膜電晶體之結構剖面 圖。 第2圖係第1Α圖至第1G圖中習知薄膜電晶體之製造流程 步驟圖。 第3Α圖至第3Η圖係本發明製程中薄膜電晶體之結構剖面 圖。 第4圖係本發明之薄膜電晶體結構圖。 第5圖係第4圖中本發明之薄膜電晶體之製造流程步驟圖。 【主要元件符號說明】 11 基板 12 1297547Oxide; IZO), and formed by a ruthenium plating process, after which a ruthenium electrode structure 38a is defined by a fifth photomask - (not shown), and the transparent conductive layer 〇 8 is etched to form the ruthenium The pole electrode structure 3 is electrically connected to the gate structure 34b through the contact window structure 37a. Please refer to the fourth embodiment of FIG. 4, which is a thin film transistor junction φ pattern of the present invention, which is formed on a substrate 30 to form a gate structure 31a, a first insulating layer 32, a semiconductor structure 33b, and a The source structure % and the electrodeless structure 34b, wherein the substrate 30 can be a glass substrate 3, and the material of the gate junction 31 & can be metal such as aluminum, copper, tungsten or chromium or an alloy thereof. And forming on the substrate 3G by a sputtering process, the material of the first insulating layer I can be nitrided M (SiNX), formed on the gate structure and the substrate 3〇 The material of the semi-conducting structure ssb may be formed on the first insulating layer 32 by using a non-daily day, and the material of the source structure and the material of the drain structure 34b may be doped with n-type doping. A crystal dream, a polycrystalline layer 10 1297547 or an organometallic compound is formed over the semiconductor structure 33b. Referring to FIG. 5, FIG. 5 is a process flow diagram of the thin film transistor of the present invention shown in FIG. 4. First, a substrate is provided. The substrate has a gate structure thereon, and the gate structure and the gate structure are The substrate has a first insulating layer (step S51), wherein the substrate can be a glass substrate, and the material of the gate structure can be a metal such as Shao, copper, town, or the like or an alloy thereof, the first insulation The material of the layer may be tantalum nitride (SiNx) or tantalum oxide (Si〇x); thereafter, a semiconductor layer and an ohmic contact layer are formed on the first insulating layer (step S52), wherein the semiconductor layer The material may be an amorphous germanium, and the material of the ohmic contact layer may be an n-type doped semiconductor; thereafter, a first photoresist layer is formed on the ohmic contact layer (step S53); thereafter, the semiconductor layer is etched and An ohmic contact layer, the ohmic contact layer is formed with a source structure and a drain structure, and the semiconductor layer is formed into a channel structure (step S54). The etching step may employ a dry etching technique; thereafter, forming a second light Resisting layer on the first light a layer and the semiconductor layer (step S55); thereafter, etching the semiconductor layer to form a semiconductor structure (step S56), the etching step may also adopt a dry etching technique; finally, removing the first photoresist The layer and the second photoresist layer (step S57). Compared with the manufacturing process steps of the conventional thin film transistor shown in FIG. 2, the manufacturing process step of the thin film transistor of the present invention reduces the removal of the first photoresist layer (step S24), forming a second metal layer thereon. Three process steps, such as a source structure and a drain structure (step S27), are formed on the semiconductor structure and the first insulating layer (step S25) and etching the second metal layer. As described above, the 1297547 manufacturing method of the thin film transistor of the present invention does not remove the first photoresist layer after forming the source structure, the drain structure, and the channel structure, as compared with the prior art. Forming the second photoresist layer on the first photoresist layer to form the semiconductor structure, and replacing the metal with the n-type doped amorphous germanium, polysilicon layer or organometallic compound as the source structure; The material of the pole structure has the advantages of fewer manufacturing process steps, so that the manufacturing yield of the array process can be effectively improved, and the manufacturing cost of the liquid crystal display can be reduced. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the patent application scope attached. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 1G are structural cross-sectional views of a thin film transistor in a conventional process. Fig. 2 is a flow chart showing the manufacturing process of a conventional thin film transistor in the first to the first Fig. 1G. 3D to 3D are cross-sectional views showing the structure of a thin film transistor in the process of the present invention. Fig. 4 is a structural view of a thin film transistor of the present invention. Fig. 5 is a flow chart showing the manufacturing process of the thin film transistor of the present invention in Fig. 4. [Main component symbol description] 11 substrate 12 1297547
12 第一金屬層 12a 閘極結構 13 第一絕緣層 15 半導體層 15a η型摻雜半導體 15b 半導體結構 15c 通道結構 16 第二金屬層 16a 源極結構 16b >及極結構 17 第二絕緣層 17a 接觸窗結構 18 透明金屬層 18a 晝素電極結構 30 基板 31 金屬層 31a 閘極結構 32 第一絕緣層 33 半導體層 33a 通道結構 33b 半導體結構 34 歐姆接觸層 34a 源極結構 34b ;及極結構 1297547 35 第一光阻層 35a 第一光阻結構 35b 第二光阻結構 36 第二光阻層 36a 第三光阻結構 37 第二絕緣層 37a 接觸窗結構 38 透明導電層 38a 晝素電極結構 步驟S20提供一基板，該基板之上具有一閘極結構，且該 閘極結構與該基板之上具有一第一絕緣層 步驟S21形成一半導體層及一 η型摻雜半導體層於該第一 絕緣層之上 步驟S22形成一第一光阻層於該半導體層及該η型摻雜半 導體層之上 步驟S23蝕刻該半導體層及該η型摻雜半導體層，形成一 半導體結構 步驟S24去除該第一光阻層 步驟S25形成一第二金屬層於該半導體結構及該第一絕緣 層之上 步驟S26形成一第二光阻層於該第二金屬層之上 步驟S27蝕刻該第二金屬層，形成一源極結構及一汲極結 構 步驟S28蝕刻該η型摻雜半導體層，形成一通道結構 14 1297547 步驟S29去除該第二光阻層 步驟S51提供一基板，該基板之上具有一閘極結構，且該 _ 閘極結構與該基板之上具有一第一絕緣層 ， 步驟S52形成一半導體層及一歐姆接觸層於該第一絕緣層 之上 步驟S53形成一第一光阻層於該歐姆接觸層之上 步驟S54蝕刻該半導體層及該歐姆接觸層，使該歐姆接觸 層形成一源極結構及一汲極結構，並使該半導體 層形成一通道結構 步驟S55形成一第二光阻層於該第一光阻層及該半導體層 之上 • 步驟S56蝕刻該半導體層，使該半導體層形成一半導體結 構 步驟S57去除該第一光阻層及該第二光阻層 1512 first metal layer 12a gate structure 13 first insulating layer 15 semiconductor layer 15a n-type doped semiconductor 15b semiconductor structure 15c channel structure 16 second metal layer 16a source structure 16b > and pole structure 17 second insulating layer 17a Contact window structure 18 transparent metal layer 18a germanium electrode structure 30 substrate 31 metal layer 31a gate structure 32 first insulating layer 33 semiconductor layer 33a channel structure 33b semiconductor structure 34 ohmic contact layer 34a source structure 34b; and pole structure 1297547 35 First photoresist layer 35a first photoresist structure 35b second photoresist structure 36 second photoresist layer 36a third photoresist structure 37 second insulating layer 37a contact window structure 38 transparent conductive layer 38a germanium electrode structure step S20 provides a substrate having a gate structure thereon, the gate structure having a first insulating layer on the substrate and a step S21 forming a semiconductor layer and an n-type doped semiconductor layer on the first insulating layer The upper step S22 forms a first photoresist layer over the semiconductor layer and the n-type doped semiconductor layer. The step S23 etches the semiconductor layer. The n-type doped semiconductor layer forms a semiconductor structure. Step S24 removes the first photoresist layer. Step S25 forms a second metal layer on the semiconductor structure and the first insulating layer. Step S26 forms a second photoresist layer. The second metal layer is etched on the second metal layer to form a source structure and a drain structure step S28 to etch the n-type doped semiconductor layer to form a channel structure 14 1297547. Step S29 removes the second layer The photoresist layer step S51 provides a substrate having a gate structure thereon, and the _ gate structure and the substrate have a first insulating layer thereon, and the step S52 forms a semiconductor layer and an ohmic contact layer. Step S53 is formed on the first insulating layer to form a first photoresist layer on the ohmic contact layer. The semiconductor layer and the ohmic contact layer are etched in step S54, so that the ohmic contact layer forms a source structure and a drain structure. And forming the semiconductor layer into a channel structure step S55 to form a second photoresist layer on the first photoresist layer and the semiconductor layer. Step S56: etching the semiconductor layer to form the semiconductor layer The semiconductor structure of a step S57 of the first photoresist layer, and removing the second photoresist layer 15