TWI297503B - Charge pump with ensured pumping capability - Google Patents

Description

1297503 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an electronic circuit structure, and more particularly to a charge pump applied to an integrated circuit. [Prior Art] A charge pump is an electronic circuit structure that uses a pUmping technique to generate a pump charge output voltage, wherein the range of the pump charge output voltage value is Exceeding the operating supply voltage of the charge pump. When the pump charge % output voltage is greater than the upper limit of the charge pump supply voltage range, the % street pump is generally regarded as a p〇shive charge pump. When the pump charging wheel output voltage is less than the lower limit of the supply voltage range of the charge pump, the charge pump is generally regarded as a negative charge pump. A charge pump mostly contains a group of pump stages in series. Each p is a step that provides an increasing or decreasing voltage in the pump's charging output voltage. The increase or decrease in the value is generally determined by the voltage gain at that stage. The first figure reveals a conventional n-th order positive charge charge pump) that supplies power from a ground reference (0V) to a high voltage labeled Vdd. In the first figure, the ~$ < load pump contains n PN diodes of the same essential structure Dhj) #缝电n, 侗6 6 2 2 2 2 〇3 corresponding pump capacitor Cl-Ci output PN diode D calls and an output, - Gong Gong ^ ^ One of your limbs Un + 】 Han Γ Η Η arranged as shown. Each pump charging phase contains a two-pole power, where the value of 1 varies from one to one. 2 numbers. Supply to the supply system as diode D, which is the input capacitor C for input UJ. To reduce the fluctuation of the output voltage, the two poles are difficult to provide. The pump is charged with a constant value greater than ^.

«voltage (clQck voltage) VeK is provided to an odd number; two 1^ and so on. The even-numbered millet capacitors of C2, C4, etc. receive the clock voltage of the anti-Lu Yu-VcK voltage. As shown in the second figure, the Bayer Bay/VCK system varies from 〇 to ^ at an appropriate frequency. In each stage of Di/Gi, the 'segment voltage gain is the same, and the C:vPn value can be equal' where the Vpn is the voltage value of each diode. Since each phase has the same phase voltage increase, the increase in output voltage Vpp is linear with the number of phases. ~ As shown in the figure, the diode charge pump is a high efficiency component. However, the one-pole turn-on voltage Vpn is basically incapable of unrestricted shrinkage. Therefore, when the supply voltage range is reduced as the feature size of the average integrated circuit is reduced, the diode charge pump cannot easily be scaled down. Furthermore, the diode charge pump with a pN dipole volume circuit structure also has the problems of solid manufacturing to overcome the dimensional shrinkage and manufacturing difficulties, and the Dicks〇n遂 rate 7 1297503 first proposes a η stage. The forward charge pump, which is described in IEEE J. Solid-State Circs, SC., vol. SC-11, pp. 374-378, March 1997, "Metal-nitride-oxide-salt complex using improved voltage-added technology" "〇n-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique" - as indicated in the third figure, in the Dickson electric Luhe pump, each two The diodes Di of the polar charge pump are all replaced by a diode-configured n-channel insulated gate FET Qi, wherein the field effect transistor The source and the gate electrode are connected together. The body region of the field effect transistor 'Qi-Qn+ ι' is all grounded. The voltage gain at the ith stage of the Dickson charge pump can be as high as the Vdd-Vn value, where yTi is the threshold voltage of the field effect transistor & If the voltage (or low voltage) of each source Qi source is increased, the field effect transistor Qi will further reduce the charge pump action, that is, the value of i increases. Since the body regions of the field effect transistors are grounded and at the same potential, the field effect transistors Ql-Qn are subjected to the bulk effect such that the threshold voltage vTi increases as the value of i increases. The phase voltage gain thus decreases as the value of i increases. For the first stage with the same number of stages and the same voltage conditions, the Dickson charge pump is less efficient than the diode charge pump. vShln et al., IEEE J. Sol id-State Circs, Vol. 35, pp. 1227-123(), August 2000, "New Charge Pump with No Body Effect Reduction and 1129503 Boundary Voltage" (A New Charge Pump) Without

Degradation in Threshold Voltage Due to Body

Effect)—Describes the efficiency loss due to the Dickson charge pump with n-stage forward charge pump as shown in Figure 4. Shin et al. replaced each field effect transistor in the Dickson charge pump with a

Three-FET charge-transfer cell 20i, which consists of p-channel charge transfer transistor QTi, p-channel source extreme field effect transistor QSi& p-channel 汲 extreme field effect The crystal QDi is constructed and arranged as shown in the figure, wherein the i value is an integer from 1 to n+1. Each cell 2〇i provides a cell output voltage signal Vm to the drain gate electrode and the drain of the cell charge transfer field effect transistor QTi. The pump charging wheel output voltage ^ is the output voltage VDn+i of the second 〇n+1 output unit cell. The body region of each single charge-transfer field-effect transistor QTi is connected to the drain of the QDI and QDi junctions, with the number VBi. The main body voltage signal is received if a unit cell 2i of the pump capacitor Ci is received. When the pulse voltage VCK becomes low, the cell potential is strong, and the electric field effect transistor QTi will start when the cell output voltage v: turn I is less than ‘. At that time, the voltage voltage boosted the charge transfer electric field effect transistor QTi. Emperor ^ 4, close :: considerable amount. Since the clock voltage ~: the clock power will be instantaneous = low, so in the next cell 2〇n+1, the crystal QTi+1 will start. The charge passes through the field effect transistor and can transfer the electric field effect package—Qmi to gradually reduce the voltage from 1297503 Vm to less than Vdd.

The difficulty of the operation of the two polarizations is to increase the connection between the first cell 2〇1 and the output cell 2〇n+1 and the sixth figure (3) and the sixth figure (b) below. The crystals QS1 - Qsn + 1 and QD1-QDn + 1 are generally operated in the following manner. When the charge transfer field effect transistor Qn of the preamble cell 20i is activated by the clock voltage VcK becoming high, the source terminal field effect transistor Qsr is activated and the 汲 extreme field effect transistor QDi is turned off. The body region of the charge transfer field effect transistor QTi is temporarily electrically connected to its source terminal by an electrical connection circuit through the source field effect transistor QSi. The opposite condition occurs when the clock voltage VCK goes low to turn off the electric transfer field effect transistor QTi. The 汲 extreme field effect transistor will be activated when the source extreme % effect transistor Qsi is off. Then, the body region of the charge transfer field effect transistor QTi is electrically connected to the button terminal through the electrical connection circuit through the 汲 extreme field effect transistor ', thereby preventing the body voltage vBi from being electrically floating. . , the desired 两 再次 两 再次 再次 = = = = — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 当 — 当 当 当The temporary electrical connection of the pole can cause the charge transfer field effect transistor to effectively achieve the same zero reverse bias (back-biaS: P2 VT"Shen's charge system widely avoids the bulk effect The voltage gain decreases in the near and subsequent stages, which increases with the increase of the value of i. Shin reveals a charge pump that is substantially repeated, ^ chart 'showing Shin's charge pump 1297503 is more efficient than Dickson's charge pump and The effect of the diode electric sealing effect is more closely achieved. The sixth figure (a) shows that the unit cell structure of Shin is applied to the first unit cell 2 (h's sectional view. The p-type semiconductor substrate 22 is provided, which has four The n-type well 24 of the P+ region, and the p+ region 26 is generally used as the field effect electrical aa body Qti immersion and the field effect transistor QD1 source. The ρ+ region 28 is the field effect transistor Qdi immersed through an n+ The contact region 3 is electrically connected to the n-type well 24. The P-type substrate 22, The n-type well 24 and the P+ region 26 respectively constitute a collector, a base, and an emitter of a parasitic prip bipolar transistor 32. Parasitic pnp bipolar transistor • Parasitic collector (reSistanCe) 34 and parasitic base resistance 36 〇 In order for the first cell 20 to operate normally, the pnp transistor 32 must not be In order to turn off the ρηρ transistor 32, the cell output voltage VD1 at the emitter terminal 26 must be less than a vBE value, which is typically 0·6-0·9 volts, greater than the body voltage vB1 of the base terminal 24. When the pulse voltage Vck becomes high, the voltage Vdi immediately rises above the Vdd value, causing the charge transfer field effect transistor QT1 and the source field effect transistor Qsi to be turned off. The buckfield field effect transistor QD1 tends to start (strongly And electrically connecting its source 26 to the n-type well 24, which is accomplished by an electrical path through the field effect transistor Qdi channel region, the field effect transistor qd1 drain 28 and the contact region 3〇. When the voltage VCK is at a high value, The bulk voltage vBl 11 1297503 thus tends to be substantially equal to the cell output voltage vD1, thus closing the transistor 32. However, for a full Vck high time course, the application to the field effect transistor Qdi value-added electrode 38 is fixed. The south supply voltage vDD may sometimes be insufficient to be smaller than the cell output voltage Vdi. In particular, during the time course, since the voltage Vm drops, the activation of the 场 extreme field effect transistor QD1 is sufficient to ensure that the body voltage is sufficiently close to the voltage. vD1 causes the pnp • field effect transistor 32 to be turned off during the entire Vck high time history. In connection with various factors, such as noise, manufacturing variables, etc., the bulk voltage ν Β 1 may occasionally float relatively low, causing the ρηρ field effect transistor 32 to turn on and conduct current to the substrate 22. This polarization action reduces the phase voltage gain of the first cell 21, and the voltage gain of the subsequent cell phase is also reduced, so that the overall operational performance of Shin's charge pump is substantially reduced.

Similar to others, but in addition, the phenomenon of polarization is also occurring in the output unit dragon 2〇n+1. Referring to the sixth figure (b), it is a cross-sectional view showing the unit cell structure of Shin applied to the unit cell 2〇n+ι. The p-type substrate 22 is provided with an n-type well 4 having four p+ regions, wherein the Ρ+ region 42 is used as a field effect transistor... source and field effect transistor ^ source P+ region 44 is field effect The transistor QDn+i is drained and connected to the n-well 40 through an n+ contact region 46. The p-type substrate 22, the n-type well and the Ρ+ region 42 respectively constitute a base and an emitter of a parasitic ρηρ bipolar transistor 48, and the parasitic Ρηρ bipolar transistor 48 has a parasitic collector resistance 50 and a parasitic base. Polar resistance 52. 12 1297503 Figure 6(b) shows an example in which n is an even number, so the pump capacitor receives the clock voltage. In order for the output cell 2G(4) to operate properly as needed, the transistor 48 must be turned off, and the cell input voltage ^ at the emitter terminal = 2 must be at least one I value, which is at the base terminal 4G. Body power M v_. At that time, the pulse voltage is changed to ^7^·, and the voltage k of the gate electrode QDn+i gate electrode is immediately increased above the pump charging output voltage Vpp, so that the field is not extremely extreme. When the pump charge output voltage Vpp and the cell input voltage ν»π are respectively applied to the charge transfer field effect transistor Cenzhou source terminal u and the gate electrode 56, the charge transfer field effect transistor will be simultaneously activated. The sample field 'as the source 42 is the source of the source extreme field effect transistor qs state, and the gate electrode 58 receives the voltage L, then the field effect transistor and the body Qsi also tend to turn on (strongly) and will The source terminal 42 is electrically coupled to the n-well 40, wherein the electrical connection is connected through a circuit protection circuit that passes through a field effect transistor such as a channel, a field effect transistor Qsi drain 44, and a contact region 46. At a high value, the 'body voltage' thus tends to be substantially equivalent to the cell input voltage VDn, causing the transistor 48 to turn off. , , , : and in the entire vCK high time range, applied to the field effect transistor gain. The stable pump charge output voltage Vpp of the gate may not be enough to be less than The cell loses money VDn', in particular, because the voltage VDn drops during the time course', the activation of the source-extreme field-effect transistor is sufficient to ensure that the body (four) U is close to the voltage ^, making the parasitic pnp field effect The crystal 42 is turned off in the high time course of the whole crucible. 13 1297503 The prime is related to noise, manufacturing variables, etc., the body electric =: ί, the two T floating is relatively low 'to make the Pnp field effect transistor 42 to the substrate 22, in the charge pump will lose a lot /, body power [incubation, then you have to look at the transistor 4 and more powerful.

Shin-charged chestnut is quite efficient. However, how to provide an operating phase, the private pump structure of the Shin, can avoid the occurrence of two polarization problems that hinder its operational performance, which is the goal of this case. According to the concept of the present invention, the η P segmentation circuit includes n main electric valleys and n+1 charge transfer cells, which are respectively labeled as the first to n+1th. Unit cells (for ease of distinction), and sources of first and second clock signals that are opposite to each other. The n main capacitance elements respectively correspond to the first to nth charge transfer unit cells, wherein the value of η is at least 3. In particular, each of the primary capacitive elements and their corresponding cells can form a gain phase of the charge pump. The charge transfer unit cell can be a similar polarity field-effect transistor. That is, all p-type channels are used for forward pump charging (p〇sitive pUmping) or all n-type channels for negative pumping (negative pumping). Each of the transistors has a gate electrode and has its second and second source/drain ("S/D") regions partially separated by a common portion of the body region. Each cell is typically constructed using three field effect transistors labeled 1297503 charge transfer field effect transistor, first end field effect transistor, and second end field effect transistor. ^ The pump charge input signal is supplied to the first S/D region of the charge transfer field crystal in the first cell. The unit cells are arranged in series, except for the first = 1 unit cell, the first S/D region of the charge transfer field effect transistor of each cell is the same as the cell charge transfer field effect transistor of the other cell The two S/D regions are coupled. A pump charge and output signal is obtained on the second S/D region of the nHth cell cell. % each of the main capacitive elements is coupled to its corresponding unit intra-cell charge, the second S/D region of the transfer field effect transistor, and (i) the first clock signal to the source, when the unit cell is an odd number Unit cell time; or (i丨) second time • between the source of the pulse signal, when the unit cell is the even number of unit cells. The first and second S/D regions of the first end field effect transistor of each cell are respectively coupled to the first s/D_ region and the body region of the intracellular charge transfer field effect transistor of the cell. And the first and second S/D regions of the intracellular second field effect transistor of each cell are respectively coupled to the second S/D region and the body region of the intracellular charge transfer field effect transistor of the cell. Unlike the Sh i η charge pump structure, the source terminal of each charge transfer cell in the sh i η charge pump is connected to the same cell direction of the gate electrode of the 汲 extreme field effect transistor. In the charge pump structure of the present invention, the gate electrodes of the first end and the second end field effect transistor are differently connected to the n-1 cell of the interval, and at least connected to the first or n+th unit. One of the cells. In particular, in the charge pump of the present invention, the first cell 15 1297503 and the gate electrode of the second field effect transistor are more typically coupled to the first charge cell field effect transistor of the first cell. a second S/D region and a second clock signal source; at this time, the electrode electrodes between the first and second field effect transistors in the cell of the μth unit are respectively coupled to a selected region of the charge pump And two of the n+1th cell: the first S/D region of the field effect transistor. And the other remaining inner cell-in-the-cell and the second-end field-effect transistor between the pole electrodes are preferably #1 respectively to the remaining unit cell charge transfer field effect transistor An S/D area. As described above, the result 'in the first cell, the second end of the field, the younger brother, the S/D area, through one of the main components, is engaged to the first-clock money (four). The first unit: the transistor is thus turned on, in order to change the first clock signal in response to the first clock signal, the first effective cell crystal of the first early cell, the eleven electrode (the fourth (sh) Shln-cell) The source of the second electrode is the source of the second clock, and the voltage difference between the gate electrode and the first-S/D region in the field effect body is large, regardless of what happens during the conduction. If the gate electrode is merged, the point is 'because the second clock signal is usually opposite to the first clock signal. The second stage of the charge pump is the second terminal field effect transistor. The voltage value is more different from the power of the first-clock signal' rather than the pump charging input voltage. The increase difference avoids that the second end field 16 1297503 in the first cell of the charge pump of the present invention is turned off when the first clock signal is at a value that turns on the field effect transistor, thereby avoiding unnecessary two polarization actions. In order to avoid the loss of voltage gain during the phase of the pump charging phase. The charge pump of the present invention generally includes a circuit for providing the gate electrode of the charge transfer field effect transistor, wherein (a) within each odd number of cells, having a control consistent with the first-clock signal The signal, and (8) in each even number of cells, has a signal associated with the second clock signal. According to how the main capacitive elements vary from the second to the first and second clock signals, these connecting portions can be transferred to the gate electrode of the field effect transistor by intracellular charge of each of the nth to nth units. It is connected to the second S/D region of the field effect transistor. The practical application can be achieved by coupling an external capacitive element to the charge transfer field effect gate electrode of the n+1th cell and (i) the first clock signal source when η is even; (ii) The source of the second clock signal, when n is an odd number, between. According to the concept of the present invention, the first end field effect transistor gate electrode of the n+1th cell can be connected in various ways. In one embodiment, the first end field effect transistor gate electrode of the first cell can be coupled to the second S/D region of the charge transfer field effect transistor of the n-1 cell, ie, f The n+1 cell is connected to the second S/D region of the charge transfer field effect of the two cells. In the electric pump including the above-described external capacitive element, the gate electrode of the n+1th unit intracellular charge transfer field effect transistor and the second S/D region are electrically coupled to each other. Thus, the gate electrode of the first end field effect transistor of the n+1th cell can be selectively connected to the n+1th intracellular charge electrode. According to the connection result described above, the first S/D region of the η+ι single-effect transistor passes through one of the main capacitive components to a specific first or Second, depending on whether the η money is even or odd and the 禚-terminal field effect transistor will start, it will change due to the second-Β early-intracellular first-cut value. The mouth-specific clock signal is converted to the gate electrode of the gate electrode of the field effect transistor when the gate electrode of the first-end field effect transistor is connected. Because the n+1J in the charge pump of this case is +, the gate electrode of the field effect transistor of the younger end (equivalent to the gate electrode of the first source of the early source field of the Shin) is coupled to the input, so that The difference between the gate electrode and the first (four) voltage in the field effect transistor is relatively high, no matter what happens during the conduction. == "The first-end field effect transistor of the +1 cell" The voltage of the 8f pulse signal (4) is more different, (4) (4) (10) Charging output special power 疋;: === Pressure difference avoids the n+1th unit intracellular field effect transistor of the charge pump in this case, the signal is on at the specific clock signal The value of the 2 private crystals is turned off' to avoid the loss of the overall electric dust mites of the charge pump. The charge pump in this case can operate in two-phase component mode, ie # is only controlled by the 18 1297503 two-clock signal. The pump charging efficiency can be converted by the signal (4). Μ = ;= is different from the -th clock signal and the second clock letter ::: pulse source. The four clock signals are essentially varied between a first voltage value. In essence, the third clock signal is located at the first voltage value during the period of the 甩#, as long as each time zone is four: the clock signal is located at the first power position. Similarly, the second signal is located in the first electric castle-electricity= during the pump charging operation. The second clock signal is located in the second main capacitive component except the n main capacitive components. The external capacitive element of the t-light is lightly combined with (1) the first-to-six-cell electric prayer transfer field effect transistor gate electrode and the source of the element number, when the unit cell is an even type of single type two days: four hours The source of the pulse signal 'when the unit cell is - odd number... between. Each n-stage pump charge thus contains two uppers::: each unit cell is also representatively provided - a capacitor with a suitable interface between the capacitive elements in the unit cell phase: the fourth The charge pump for the phase implementation may include - plus a specific ^(10) coupled to the selected first or second clock signal source. Ϊ 日 二 二 η If η is even, it is connected to the first-clock signal; if η is connected to the second clock signal. When the (4)th cell is intracellular. The gate electrode of the first 19 1297503 end field effect transistor is not connected according to any of the foregoing methods, the gate electrode of the first end field effect transistor of the n+1th cell Can be connected to the external capacitor. In this embodiment, the arrangement of the gate electrode and the second S/D region of the (n+1)th cell intracharged field effect transistor is generally not directly electrically connected to each other. The charge pump more representatively couples the S/D regions of at least one applied field effect transistor to the n+l unit intracellular charge transfer and the gate electrode of the first end field effect transistor. In the foregoing method, the gate electrode of the first terminal field effect transistor of the n+1 cell is coupled to the selected first or second clock signal source through the external capacitor, thereby making the fourth phase of the case The application of the electro-pumped pump achieves an operational advantage by connecting the gate electrode of the n+1th unit cell and the first end field effect transistor, which is different from the foregoing two modes. Thus, the gate electrode of the field effect transistor is coupled to the output terminal 5, and the voltage difference between the gate electrode and the first S / D region _ in the field effect transistor is large, whether during conduction. What happened. This increased voltage difference again avoids the loss of the overall voltage gain of the charge pump. Regardless of the number of clock signals introduced by the charge pump in this case, some of the cell cells located between the first and the n+1th cell are sometimes connected differently from the above-mentioned method. . When some charge transfer transistor is to be left, some of the cell cells located between the first and the n+1th cell, the side end field effect transistor may not even exist in some embodiments. 20 1297503 Jane's charge pump in this case eliminates the difficulty of polarization and prevents the operating characteristics of the Shin charge pump from being severely degraded. On the same day, the efficiency of the charge pump in this case is very similar to that of the diode charge pump. Because the charge pump system of this case uses the field effect transistor, it can be reduced to a small size, thereby eliminating the difficulty of reducing the size of the diode charge pump. . Therefore, this case does provide a more significant improvement than the prior art. The same or homogeneous items are as described in the drawings and the description of the embodiment of the present invention. The present invention is not limited to the above-described examples. Other features of the present invention are described below. The invention is defined by the scope of the appended claims. [Embodiment] The seventh (a) and seventh (b) (collectively referred to as the seventh) are circuit diagrams for reading the two-phase forward charge pump of the preferred embodiment of the present invention. The beginning and end of the two-phase forward charge spring are shown in Figure 7(a), while the intermediate charge pump portion is shown in Figure 7 (8). In the seventh figure, Christine == starts from the power supply, the power supply has a high supply: the ground voltage Vss, the low supply voltage Vss is typically = tea test value '剌 剌 to define VD' Vss power supply voltage grinding When Vss is the ground reference value, the high supply voltage ^ is 2·5~4·0 volts, usually 3·〇V. The charge pump in the seventh figure contains n+1 transfer unit cells 60丨, 6〇2 , ... 60n_丨, 6〇 and "] package of the same main pump capacitor components Cci, Cc2, ... Ccni and &, respectively, 1297503 corresponding charge transfer unit cell 6Gl_6 () n; - Capacitor element ^. An output capacitor element ^ and - the first clock voltage signal n the source of the second clock voltage signal (both not separately disclosed), wherein = the second clock voltage signal veKP and the first clock voltage The signal is "system-to-relationship. Each charge transfer unit cell 6〇i and its corresponding primary capacitive element Cn form a pump charge phase 62i of the charge pump, where the 丄 value is an integer value from the pass to n. The integer n value is the pump The charging phase 62 is a number of 62 s, and its value is greater than or equal to 3. Therefore, the charge pump in the seventh figure has at least four charge transfer unit cells 6〇ι_6〇η+ι. Each of the private valley components Cci-Ccn and CGn+l can be applied as a standard capacitor consisting of a dielectric layer sandwiched between two conductors: S and 'the use of integrated circuit form for charge pumping each capacitive element “ wide" and CGn + 丨 preferably with more than one ^ ^ ^ Enhancement-mode) ^ ^ ^ (depletion-mode) insulation gate field effect The insulated-gate FET is implemented, and the application of the source/no-pole region is short circuited by two m well capacitors as a semiconductor element having substantially equivalent capacitance field The configuration of the effect transistor, unless the body region of the well type capacitor and the two interconnected lateral separation regions are in a same conduction state rather than in an opposite conduction state, wherein the two sides are separated along the semiconductor region The upper surface is extended and corresponds to the source/no-polar region of the capacitively-connected field-effect transistor. The body region of the well-type capacitor is slightly more doped than the source corresponding to the capacitively-connected field-effect transistor. Two regions of the pole/drain region. 22 1297503 The mother turtle component Cci-Ccn and CGn+i can also be applied by more than one well type capacitor. The output capacitive component CPP can be parasitic at the Cpp position. The conductor load capacitance is simply constructed. If the value of the Cpp parasitic capacitance is too low, the Cp'p value can be increased by combining the Cpp parasitic capacitance with a non-parasitic capacitance. Also for the capacitive element and the capacitive element The non-parasitic capacitance part of Cpp can be applied with a #f capacitor, but when the charge is made by the integrated circuit form, it is better to use more than one capacitively connected field effect transistor or more than one well type capacitor. Implementation of the application. Capacitively connected field effect transistors and well type capacitors, in essence and privately-precision capacitors, have (4) the work of 35. Therefore, the capacitive elements ^^^+1 and Cpp are sometimes only regarded as "Capacitor cap: i t (four))". The same application of other such capacitive components is detailed in the statement on the 1 side "positive charge is transferred to or formed - capacitor, that is, the table is not positively charged to or form a - connected to the transmission The circuit line carrying the transferred charge. (10) Valley plate system is equal to high supply (four) fly ° pump charging wheel power failure number -i -... Cold brother one pump charging phase must be charged when the nth unit cell contains the "solid pump heart a final pump charge In the stage, the n+th unit cell is connected to the output unit cell of an output circuit conductor 66, and the == electric two conductor (9) provides a pump charging wheel out (four) signal which is greater than VDD. The output capacitor Cpp is connected to 23 1297503 is connected between the output circuit conductor 66 and a Vss source which can reduce the pump charging output voltage Vpp ripple. The charge transfer unit cell 60ι-6〇η+ι is enhanced by the p-channel insulating gate field effect. Formed by a transistor, each enhanced p-channel insulated gate field effect transistor has a first p-type source/> and a polar region, a second p-type source and a region, and a source of the source a gate electrode for current flow between the regions of the immersion region. The first and second source/no 10 pole regions (generally indicated by "S/D") of each field effect transistor are channels of an n-type body region Partially separated, and the n-type body region and the S/D region of each field effect transistor Forming a pn junction (pn juncti〇n), and the gate electrode of each field oxide body is separated from the channel region by a gate dielectric layer. The first S/ of each field effect transistor The D area is generally used mainly as its source function, and will be referred to as "source," in the following text. On the other hand, the second S/D region of each field-effect transistor is generally used as its bungee function, which is sometimes referred to as "dip pole," in the text. Figure 10 (a) and Figure 10 (b) reveals a representative cross-sectional view of the two field effect transistors, which will be discussed later. Each charge transfer unit cell 60i is composed of a charge transfer field effect transistor PTi, a first end field effect transistor. Psi is composed of a second end field effect transistor PDi, wherein the value of i changes from 1 to n+1. The charge transfer field effect transistors ΡΤ1 - Ρτη +1 are essentially identical; the first end field effect transistor Psn +1 is essentially the same in nature; the second end field effect transistor PD1-PDn+i is essentially identical in nature. The first cell of the early cell 60y charge transfer field effect transistor Ρτι first 24 1297503 S/D area ( The source is connected to an input conductor 64 to receive the pump charging input voltage Vd 〇 substantially equal to Vdd as the input of the cell 60! In addition to outputting the early cell 6〇n+1, The second S/D region (bungee) of the charge transfer field effect transistor PTi in each cell 6〇i is connected to the next The first S/D region (source) of the unit cell 6〇i+1 charge transfer field effect transistor Pmi. Each unit cell 6〇i from the cell cell charge transfer field effect transistor PTi second The S/D area provides a cell output voltage signal VDi. Therefore, in addition to the output cell 6〇n+1, the output voltage VDi of each cell 6〇i is the input signal of the next cell 6〇i+i In another state, each cell 60i receives a voltage VDi^ in the first S/D region of the intracellular charge transfer field effect transistor pTi+1 as a unit cell rounding signal. The second S/D region (drain) of the 〇η+ι internal charge transfer field effect transistor ρτ1+1 is connected to an output conductor = for providing an output voltage from the cell 6011+1... as a pump Charging wheel output voltage VPP 〇

The gate voltage nickname Vei is located on the intracellular charge of each cell to the pTi gate electrode of the second effect transistor. When the value of i is an odd number, the second: electricity? The signal VGi is synchronized with the clock voltage VcKP; and when the value of i is a synchronization number, the gate voltage signal Vci is related to the clock voltage VCKP. Refer to the seventh diagram (b), which reveals the field. The effect transistor value is ~1 for each of the charge transfer 塲 effect transistor η η linkage application. When i: 之, the main capacitor Cci is connected between the field effect transistor S/D region and the source of the clock voltage yap. When the i value 25 1297503 is an even number, the main capacitor Cci is connected between the second S/D region of the field effect transistor Ρπ and the source of the clock voltage γεκρ. The gate electrode of each transistor Ρη is connected to its own second s/d region. Therefore, in addition to the field effect transistor, each capacitor cci is connected between the field effect transistor PTi gate electrode and the second S/D positive domain junction point and the following signals. Its _, when the 丨 value is - odd, the source of the signal is the source of the clock voltage signal yCKP; or two, when the 丨 value is an • even number, the source of the signal is the clock voltage signal, ΚΡ. Similarly, in the two-phase electric pump of the seventh figure, except for the gate voltage Vci, therefore, the gate voltage Vci is equal to the cell output voltage V])i 〇 to the output charge transfer field effect transistor ρτη+1, plus Capacitor·_cGn+1 is connected to the gate electrode of the field effect transistor Ρτη+ι and (i) clock power, signal VCKP source, when n is even; or (ii) clock voltage signal VCKP, When η is an odd number. The seventh diagram (a) reveals an important 疋 of the embodiment in which the one is an even number. The gate electrode of the field effect transistor pTn+1 is electrically decoupled from the second S/D region (dec〇).叩led). Therefore, the gate voltage VGn+1 is a separate signal from the pump charge output voltage Vpp (or VDn+i). The first and second S/D regions of the first end field effect transistor Psi are connected to the first s/D region and the body region of the intracellular charge transfer field effect transistor Pn, respectively, in each cell 60i. . The first and second S/D regions of the second end field effect transistor pDi in each cell 60i are similarly connected to the second S/D region of the intracellular charge transfer field effect transistor η, respectively. Body area. Intracellular electricity in each unit 26

6 (h, each cell 6〇i+1 between the output cell 6〇n+1 and 6〇1 and 6〇n+1 is the first in each cell 60i except for the cell 60n+1 The gate electrode of the terminal field T transistor PSi is connected to the second S/D region of the intracellular charge of the unit to the unit cell pTi to receive the unit cell output, 塾Κ. Due to the charge transfer field effect transistor The second S/D region of Ρπ is connected to the first-S/D region (source) of the second end field effect transistor PDi, and the body region of the 1297503 charge transfer field effect transistor pTi receives the body voltage signal Li, the signal The second S/D region (the finite electrode) is located at the first end field effect transistor Psi of the unit cell and the second field field effect transistor PDi. The first end field effect transistor pSi of each unit cell 60i is The body region of the second end field effect transistor PDi is also connected to its own second S/j) region for receiving the body voltage VBi. In the present case, the first terminal field effect transistor pSi and the gate electrode of the second terminal field effect transistor pDi in each unit cell 6〇i have different connections in the first unit cell. In particular, the first terminal field effect transistor PDi gate electrode of the first cell 60 is connected to the source of the clock voltage signal V〇cp to receive the clock voltage except for the first cell. The second end field effect transistor gate electrode of 6〇i is connected to the first s/D region of the cell intracellular charge transfer field effect transistor to receive the cell input voltage VDi-Ι. Since the first-S/D region of the charge transfer field effect transistor PTi is connected to the first end field effect transistor psi, the second S/D region (source) 'except in the first cell 6〇 is in each cell The pole electrode between the second end field effect transistor & in the cell 6〇1 is also connected to the first S/D region of the first end field effect transistor Psi. 27 1297503 In addition to the 6Gn+1 in the early 7G cell, the gate electrode of the first end field effect transistor PSi in each cell 6Gi is also connected to the first S/D region of the second end field effect transistor ^. In the two-phase charge pump of the seventh figure, the gate electrode connection of the first terminal field effect transistor Psn+1 of the output cell 60 +1 can be performed according to the method according to the present invention. The gate electrode of the first-end field effect transistor is typically connected to the cell charge transfer field of the cell, and the second S/D region of the transistor Pw, that is, the two cell fronts, from the cell 60η Receiving the output voltage VDn]. Therefore, the main capacitor am is engaged between the first-end field effect transistor gate electrode and (1) the clock voltage knowledge vCKP source between when n is even; or (ii) clock voltage When the signal V(10) is between 4 odd numbers, the gate electrode of the first end field effect transistor PSn+1 can be connected to the charge transfer field effect transistor Ρτη+1 gate electrode, as shown in the seventh figure. U) is shown by a broken line to receive the gate voltage VGn+1. In this embodiment, the external capacitor is coupled to the first-end field effect transistor pSn+1 gate electrode and (1) the clock voltage signal V(10) When n is an even number; or (ii) between the clock voltage signals ^, when η is an odd number, and the seventh figure (4) again reveals that n is an even For example, in the embodiment of FIG. 7(a), the gate electrode of the first terminal field effect transistor PSn+1 is not coupled to the capacitor 匕(1) or the capacitor CGn+1 is coupled to the clock voltage vCKP. During the pump charging operation, the clock voltage signal VCKP and the clock voltage signal VCKP are periodically changed, that is, at a selected clock frequency, at a low supply voltage Vss and a high supply voltage Vdd or a close to v(10). High 28 1297503 voltage. The clock frequency is 10-25MHz, 20MHz is more representative. As shown in the eighth figure, the clock voltage signal VcKp and the clock voltage signal Yup waveform are roughly sinusoidal in the occupational power operation (4). However, the clock voltage Vckp and the clock voltage VCKP can also be reasonably approximated by a square wave as indicated by the symbols 68 and 70 in the eighth. Each pump charging phase 62i has a one-stage voltage gain contribution to the pump charging output voltage Vpp. By the illustration of the ninth figure, the system reveals the waveform of the idealized cell, the cell input voltage ^ and the body voltage VBr, and uses the square wave to represent the clock voltage signal V(10) and time. Pulse power The signal VeKp helps to understand how each pump charging phase 62i generates its phase voltage gain. In particular, Figure 7 (b) 'the ninth cell output voltage Vm, single 70 cell The waveform of the input voltage Vdm and the body voltage VBi can be specifically applied to a pump charging phase 62i, the unit cell 60i of which belongs to the first cell 60, and the output cell 60n+1. (a) In the description of the link, the operation of the first pump charging phase 62i is the same as that of each of the other pump charging phases 62i. The cell output voltage VDi, the cell input voltage VDi-i, and the body voltage yBi disclosed in the ninth figure. The waveforms are all applied to an odd number of pump charging stages 62], i.e., the capacitive element Cci of the pump charging stage 62i receives the clock voltage VcKP. Figure 7(b) shows the state of this embodiment. In the ninth figure, time tl, t2, t3 and t4 are successively increased. At time t k 'day, the pulse voltage Vckp is high (at the VDD value); and the clock voltage 歹 (10) is low (at the Vss value). In such an odd number of pump charging stages 62i, the charge transfer field effect transistor pTi of the cell 29 1297503 60i is closed with the first end field effect transistor; and the second end field effect transistor pDi is Opened. At time seven, the cell adjacent to the cell is 6〇i- and 6〇μ', and its state is inversely related to the cell 6〇i. That is, when the first effect transistors pDiM and pDi+1 are turned off, the charge transfer field effect transistors Pth and pmi and the first end field effect transistors Psi+ and ps... are turned on. The output voltage vDi of the cell 60i is located between a higher voltage value ❿ VDZi and a lower voltage value Vim. Although not disclosed in the ninth figure, it can be understood that at time t!, the output voltage VDi+1 of the next cell 60 is less than the voltage VDi. Since the charge transfer field effect transistors pTi and b are respectively turned off and on, positive charges are transferred from the capacitor Cci to the capacitor CCi + 1 via the charge transfer field effect transistor PTiH. This causes the output voltage VDi of the cell 6〇i to gradually decrease relatively during the period when the clock voltage 乂(10) is at a high value.曰 At time t!, the input voltage vDiM of the cell 60i is located between a lower piezoelectric value Vdwh and a higher voltage value VDXH. Although not shown in Fig. 9, it is conceivable that at time t i , the input voltage Vih-2 of the previous cell 60 η is greater than the voltage Vdh. Since the charge transfer field effect transistors Pn and Pth are respectively turned off and on, positive charges are transferred from the capacitor CC-2i via the charge transfer field effect transistor Ρτη to the capacitor Cci-Ι' to gradually increase the south power VDi-l . During the time t, the body voltage VBi of the cell 60i is equal to the output voltage vDi, because the second end field effect transistor PDi and the first field effect transistor pSi are respectively turned on and off: the body voltage VBi is in VDZi and VDYi Between, it will gradually decrease relatively. 30 1297503 When the cell input voltage reaches Vdxh at the same time at time t2 ', the cell output voltage and the body voltage VBi will reach Vdh at the same time. At time imitation, the clock voltage VCKP rapidly transitions (relatively) from yDD to Vss, as the simultaneous pulse voltage Ϋϋκρ rapidly transitions from Vss to Vdd. With respect to the repeated response of Vdd_VSS of the clock voltage VcKP, the capacitor Cci rapidly drops the cell output voltage vDi to approximately the same value as a low voltage VDfi. The charge transfer field effect transistor 10Ρη is turned on with the first end field effect transistor pSi; the second end field effect transistor ~ is turned off. With respect to the boosting reaction of Vdd-Vss of the clock voltage ^(10), the capacitor Cci-i causes the cell input voltage to rise rapidly to approximately the same value as a high-value voltage Vii. It is conceivable that the VDzi i system Greater than the ν· value. The value of the voltage Vdzh is less than VDYi, which is achieved instantaneously before the cell output voltage vDi is rapidly shifted downward. The capacitor Cc... simultaneously causes the output voltage vDi+1 of the next cell 60i+i to rapidly increase the v(10)-Vss brewing value, which is conceivable, and the value is greater than Vm. The charge transfer field effect transistors Pth and pTi+1 and the first end field effect transistors PsiM and Ps... are turned off; the second end field effect transistor and PDi + 1 are turned on. When the charge transfer field effect transistors PTi M and pTi"_ and the charge transfer field effect transistor pTi are turned on, positive charges are transferred from the capacitor Cci_^ from the charge transfer field effect transistor pTi to the capacitor Cci. This causes the cell output voltage VDi is gradually increased relatively, and the cell input (four)' is relatively gradually reduced. Similarly, the output voltage V of the lower cell 6()i+1 is relatively decreased. Because the first end field The effect transistor h 1297503 is turned on and off respectively with the first terminal field effect transistor PDi, and the body voltage VBi is equivalent to the cell input voltage Vdh. Therefore, at time t2, the body voltage VBi rapidly decreases from Vim. To VDzi i. At time t3, when the cell input voltage Vdh and the body voltage VBi are instantaneously lower than the VDYiM of VDZi i, the cell output voltage Vm reaches the vDXi value which is slightly higher than vDfi. The value is less than Vdyh. At time ts, the clock voltage VcKp rapidly changes from Vss to Vdd, such as the simultaneous transition of the pulse voltage from Vdd to Vss relative to the VDD_yss of the clock voltage. Pressure reaction, capacitor Cci will Unit cells quickly rise to the output voltage VDi with a voltage

Vm is about the same value. The charge transfer field effect transistor PTi is again turned off with the first end field effect aa body PSi; and the second end field effect transistor Pw is re-opened. With respect to the step-down reaction of the clock voltage vCKP2Vdd-Vss, the capacitor Cci-i rapidly drops the cell input voltage ^(1) to approximately the same value as a voltage ^^. As can be seen from the ninth figure, the Vmq is considerably smaller than the VDZi value. Capacitor Ccw simultaneously causes the next cell 6 〇... The output voltage is rapidly reduced by approximately Vdd-Vss, which is conceivable, which is less than VDZi. The charge transfer field effect transistors pTiM and Pmi and the first end field effect transistors Psh and pSi+1 are re-opened; and the second end field effect transistors PDi-ι and PDi + 1 are re-closed. When the charge transfer field effect transistor pTi is turned off and the charge transfer field effect transistor pTi+1 is turned on, the positive charge can be transferred from the capacitor Cc丄 from the charge transfer field effect transistor pTi + i to the capacitor gc...1. . Cause 32 1297503

The & cell firing voltage is relatively increasing. When the charge transfer field effect transistor pTi and the charge transfer field effect transistor Ρτη are respectively turned off: when turned on, 'positive charge is transferred from the capacitor CM to the capacitor Cci-1 via the charge transfer field effect device PT11, gradually increasing from the ancestors to the ground. The single cell input voltage Vdh is boosted. Similarly, the output of the next cell 6, 〇i+1, and the voltage VDi+1 are relatively increased. Since the second terminal field effect transistor pDi and the first terminal field effect transistor Psi are turned on and off at the time (4), the body voltage VBi, j is equivalent to the cell output voltage ~. As a result, the body voltage VB is quickly switched from Wi to VDzi. " At time (10)' voltages VDi, ^ and ^ are essentially the same as the time illusion. Therefore, the period from time ti to time I is the cycle or period of the charging operation. The clock frequency is quite important. In (4) the overall time history, the charge transfer field effect transistor PTi and the first-end field effect lightning crystal PSi are turned on, and the clock (four) w value is low; and in the (8) whole] time course" When the second end field effect transistor pDi is turned on, the clock voltage V ckp is south. What is important is that as long as the first v region (source) of the charge transfer field effect transistor Ρτί is turned on, the body electromigration ~ is equal to the cell input voltage ~1. Therefore, the more each charge transfer field effect transistor PTi and the other charge transfer field effect transistor PTi-様, effectively reach the same zero reverse bias mbadc-bias). . Whenever the field is turned off, the body voltage y 箄 - 曰曰 π is equal to the early cell output voltage hi. This can avoid the body voltage ~ generate electrical fluctuations. The stage voltage gain ^ can be defined as the average unit cell 翊 33 1297503

The difference between VlH and the average cell input voltage VDW. As shown in the ninth figure, the cell output voltage VDi has exactly the same waveform as the cell input voltage, and its magnitude and time are only shifted in half a clock cycle. Therefore, the phase voltage increase △ VDi is the difference between the cell output voltage Li and the cell input voltage Vdh in two identical regions, that is, the maximum voltage point of the vDi and Vdh waveforms. For the first time, the stage voltage gain ΔVDi is equal to • Vdd—Vss-丨Vt. Hey. Since the threshold voltage vTQ of the zero back-b i as of each charge transfer field effect transistor pTi is essentially the same, the phase voltage gain ΔVDi of each pump charge phase 62i is equal. Therefore, when the number of charging periods 62 ι - 62 η increases, the pump charging output voltage Vpp increases linearly. The charge pump in Figure 7 works extremely efficiently. The first charge transfer unit cell 60i and the output charge transfer unit cell 6〇n+ι can avoid the polarization action, which can be apparent to the relative cell 2 of the % & charge pump (h and 2〇n+1) Occurs, it will seriously reduce the operating characteristics of the Shin charge pump. Compared with the first cell 20ι of the charge pump in Fig. 6(a), the tenth figure (a) reveals a representative implementation of the first cell 60 A cross-sectional view of the example, which can be used to understand why the first cell 6 (h can avoid unnecessary polarization action. Please refer to the tenth figure (a), the charge pump of the seventh figure is lightly mixed. The p-type single crystal germanium semiconductor substrate 72 is generated by the impurity. The first cell 6〇1 supplies a moderately doped n-type well 74 to the p-type substrate 72. Six heavily doped amounts The p-type region, comprising p+ regions 76 and 78, is provided in the n-type well 74 along its upper surface, and each serves as 34 1297503 electric = transfer field effect transistor Ρ τι and side end field effect transistor h and ~ 1 £ domain., P+ region 76 is the second end field effect transistor Pd, the first flute, if pole) β p+ region 78 is the second end field effect The crystal is a S/D region (dip pole) and is electrically connected to the n-well 74n plate 72, the n-well 74 and the p+ by a heavily doped n-type contact region 80 provided in one of the n-wells 74. The region 76 serves as a collector, a base and an emitter of a binary bipolar transistor 82, wherein the transistor 82 has a parasitic collector resistance 84 and a parasitic base resistance. FIG. It is a gate electrode of the second end field effect transistor ^. Unlike the first cell 2 in the Shin charge pump for receiving the substantially fixed south supply voltage VDD, there is no gate of the extreme field effect transistor Qm. The electrode 38, the gate electrode 88 of the second end field effect transistor P1H receives the clock voltage VCKP in the first cell 6〇 of the charge pump of the seventh figure. The pulse voltage vCKP becomes high at time ts. The output voltage Vm of the first unit cell 60! of the seventh graph is increased to turn off the charge transfer field effect transistor Pn and the first end field effect transistor psl and simultaneously open the second end field effect transistor Pm. The reverse clock voltage VCKP applied to the second terminal field effect transistor pDi 閛 electrode 88 is simultaneously low, instead of the charge pump like Shin Cell 2 (in h is applied to the 场 extreme field effect transistor QD1 gate electrode 38 maintains a constant voltage VDD. Therefore, for the same power supply voltage range Vdd-Vss, the gate of the second terminal field effect transistor PD1 The voltage difference between the pole electrode 88 and the first S/D region 76 is, after the time t3 of the pump of FIG. 7 1297503, it can be inferred that when the clock voltage is higher than the Shin charge pump in the corresponding time,电压 The voltage difference between the gate electrode 38 and the source 26 of the extreme field effect transistor qd1. Even the first cell of the seventh charge pump of the seventh figure 20 ι of the gate electrode 88 of the second terminal field effect transistor Pdi and the first The difference between the electric power of an S/D region 76 is gradually increased due to the charge transfer of the second cell 6〇2 charge transfer field effect transistor Ρτ2 during the high value of the clock voltage Vckp. Decreasing, and gradually decreasing, the voltage difference between the gate electrode 88 of the second end field effect transistor Pm and the first S/D region 76 is different from the minimum value of the clock voltage Vckp during the high value period. Voltage difference between gate electrode 38 and source 26 of field effect transistor Qm During the minimum clock high voltage VcKp value. This large minimum voltage difference value ensures that the first terminal field effect transistor pD1 of the first cell 6〇1 in the charge pump of the seventh figure can be strongly turned on during the entire high value of the clock voltage VCKP. The connection of the second terminal field effect transistor pD1 gate electrode 88 and the clock voltage VCKP source ensures that the second end field effect transistor pD1 can be strongly turned on during the entire high value of the clock voltage Vm, and the second end field The first S/D region of the effect transistor h is transmitted through the channel region passing through the second end field effect transistor Pdi, the second S/D region 78 of the second end field effect transistor pD1, and the n+ contact region 8 The high conductive path of the crucible is simultaneously electrically connected to the n-well 74. This causes the body voltage V" at the base of the ρηρ transistor 82 to be substantially equal to the cell input voltage Vdi at its emitter 76. Since the base-to-emitter voltage of the transistor 82 is thus substantially equal to zero, the transistor 82 is turned off during the entire high value of the clock voltage VCKP at 36 1297503. The transistor 82 is not turned on at any other time, i.e., when the pulse voltage Vw is at a low value for the normal pumping operation. Therefore, the first cell 6〇 avoids unnecessary bipolarization, which may severely reduce its phase voltage gain and operational characteristics. Compared with the output cell 2〇πη of the Shin charge pump in the sixth figure (b), the tenth figure (b) reveals a cross-sectional view of the last output cell 6〇η+ι of the present case representing the fragrant embodiment. The figure shows why the output cell 6〇n+1 can likewise avoid unnecessary two polarizations. In conjunction with the seventh diagram (a), the tenth diagram (b) shows the supply capacitor Ccn clock voltage VCKP when n is an even number. Referring to the tenth figure (1)), the last cell 6〇 is composed of a further moderately doped n-well 9 〇 ip type substrate 72. Six heavily doped p-type regions, including p+ regions 92 and 94, are provided in „wells 90 extending on their upper surface to serve as charge transfer field effect transistors pTn+1 and side-end field effect The S/D region of the crystal Ps...盥&. The P+ region 92 is the first S/D region (source) of the first end field effect transistor %. The rape region 94 is the first end field effect transistor The second S/D region (dip pole) of PSn+1 is electrically connected to the n-well 90 by the heavily doped n-type contact region 96 of the upper surface of the well 9 p. p-region 72, n-type The well 90 and the p+ region are respectively used as the collector, base and emitter of a parasitic pnp bipolar transistor 98, which causes the parasitic pnp bipolar transistor 98 to have a parasitic collector resistance 1〇〇 and a parasitic base resistance 102. 37 1297503 In the tenth figure (b), the numbers 1〇4, l〇6 and 108 are the gate electrodes of the field effect transistors PDn + 1, Ρτη + 丨 and pSn+1, respectively. The gate electrode 58 of the output unit cell 2〇n+1 source terminal field effect transistor QSn+1 receiving the constant pump charging output voltage Vpp, the gate electrode 108 of the first end field effect transistor psn+1 In the last cell 6〇n+1 of the charge pump as shown in the seventh figure, the capacitor CcnM or the capacitor cGn+1 is coupled to the source of the clock voltage Vckp. In either case, the first end field effect transistor The voltage of the gate electrode 108 of Psn+1 changes according to the voltage VCKP. The pulse voltage Vckp becomes higher at time t2, and the input voltage vDn of the cell charge 60n+1 of the seventh figure is increased to turn off the second. When the end field effect transistor PDnH and the charge transfer field effect transistor ρΤη + ι and the first end field effect transistor psn+1 are simultaneously turned on, the clock voltage vCKP is simultaneously lowered to lower the first end field effect transistor Psn+i The voltage of the gate electrode 1 〇8 is not applied to the source terminal field effect transistor Qsn+1 gate electrode 58 as the shin charge pump output cell 2〇n+1 maintains the pump charge output voltage vpp of approximately constant value For the same power supply voltage range yDD-Vss value, the voltage difference between the gate electrode 108 of the first end field effect transistor psn+1 and the first S/D region 92 is close to the seventh diagram charge pump. After the time, the system is quite larger than the source charge field of the Shin charge pump in the corresponding time. The voltage difference between the gate electrode 58 and the source 42 of the crystal QSn+1. Although the seventh cell charge pump is the last cell 6 〇n+ι, the gate electrode 108 of the first end field effect transistor Psn+i The voltage difference value between the first S/D region 92 and the high value of the clock voltage VCKP is caused by the charge transfer FET Ρτη+ι charge transfer to cause the cell 6〇n+1 input voltage 38 1297503

Vi>n+1 gradually decreases and gradually decreases, and the voltage between the gate electrode 108 of the first end field effect transistor psn+i and the first S/D region 92 is different from the clock voltage ▽(^ during the high value period The minimum value is considerably larger than the minimum value of the voltage difference between the gate electrode 58 and the source 42 of the Shin charge pump source extreme field effect transistor QSn+1. The minimum gate to source due to this increase The voltage difference value, the seventh terminal charge pump output unit cell 6〇η+ι first end field effect transistor Psn + 1 can be strongly turned on during the whole high value of the clock voltage VCKp. The transistor Psn+i gate electrode 1〇8 and the clock voltage VcKP source are coupled by the capacitor Ccn-! or the capacitor CGn+1 to ensure the seventh diagram charge pump output unit cell 6〇n+1 first end field effect The crystal Psn+1 can be strongly turned on during the entire high value of the clock voltage VCKP, and the first S/D region 92 of the first end field effect transistor psn+1 is transmitted through the first end field effect transistor. The channel region of pSn+1, the second S/D region 94 of the first terminal field effect transistor Psn+i and the high conductive path of the n+ contact region 96 are simultaneously connected To the n-type well 90. This causes the body voltage vBn+1 at the base of the pnp transistor 98 to be substantially equal to the cell input voltage VDn at its emitter 92. Due to the base-to-emitter voltage of the parasitic transistor 98, The voltage is equal to zero, so the transistor 98 is turned off during the entire high value of the clock voltage vCKP. The transistor 98 is not turned on at any other time, that is, when the pulse voltage vCKP is at a low value for the normal pump charging operation. The output cell 6〇n+1 avoids unnecessary polarization action, otherwise the unnecessary polarization action may seriously reduce the overall pump charging voltage gain. 39 1297503 The eleventh figure is disclosed in the concept of the present case. An n-stage two-phase negative charge pump. The operation of the charge pump in FIG. 11 begins with a power supply having supply voltages ^1) and 7^, and the charge ^2 contains n+1 series arrangements The charge transfer unit cells 11〇2, ."llOn i, ΐι〇η&ιι〇η+1; respectively correspond to the charge transfer unit cell ll (h -110 „the main pump capacitance element Cci-Ccn; an external capacitor Component CGn+1; —output capacitor And a first clock voltage signal VcKN& a second clock voltage signal ▽ (: source of 〇 (both not separately disclosed), wherein the second clock voltage signal VCKN and the first time The pulse voltage 4 Vc is inversely related. The integer η value is also at least 3. Each charge transfer unit cell 110i and its corresponding main capacitive element Cei form a pump charge phase ll2i of the charge pump, wherein the value of i is from丨 changes to an integer value of n. A value close to the pump charge input voltage register Vd of the low supply voltage Vss. It is connected to an input circuit conductor 114 and is introduced into the first phase of the charging phase. Similar to the charge pump of the seventh figure, when the nth pump charging phase 112n containing the nth cell 110 is a last pump charging phase, the n+1th cell Π〇η+1 is one. An output cell coupled to an output circuit conductor 116, wherein the output circuit conductor 116 provides a pump charge output voltage signal γΝΝ having a value less than a constant value of Vss. The output capacitor Co is coupled to the output circuit conductor 116 and a It can reduce the pump charge output voltage VNN rippie between the vss sources. The charge transfer unit cell 11 (h-11 〇η+Γ is composed of enhanced η-channel insulation 12975503 gate field effect transistor, except for conduction The form of the η-channel insulated gate field effect transistor is the same as that of the seventh-stage charge pump enhanced Ρ channel insulated gate field effect transistor. Each charge transfer unit cell 110i is composed of one The charge transfer field effect transistor Νη, a first end field effect transistor NSi and a second end field effect transistor Νμ, which respectively correspond to the charge transfer field of each unit cell 6〇i of the seventh diagram charge pump Effect transistor PTi, first end field The effect transistor Psi is identical to the second end field effect transistor PSi. The charge transfer field effect transistor Nn-NTn+1 is essentially identical; the first terminal charge transfer field effect transistor Nsl-Nsn+1 is essentially The same is true, and the second terminal charge transfer field effect transistor Ndi-NDn+i is essentially the same. Field effect transistor Ντι-Ντη+1, Nsi-Nsn+1 and Ndi-Ndh+i are the other And the capacitor Cn_Ccn is interconnected with CGn+1, that is, connected by the same method as the equivalent field effect transistors pT1-pTn+1, psl_pSn+i and Pw_^ in the charge system of the seventh figure. Vm-VDn+1, gate voltage Vgi-Vgiih and body voltage VBl-VBnn are connected to field effect transistors I - Ντη + 1, Nsi-Nsn+Ι and ND1-NdhH, respectively, just like field effect transistor pn_ρ —, the relative position of Psi-Psn+1 and pD1—pDn+1. The first clock voltage signal V(10) and the second clock voltage signal %0 are connected to the capacitor according to the same connection of ^^ and ^ ( ^-"and CGn+Ι ° According to the concept of the present case, the connection of the second end field of the first unit cell 11〇1 to the Nm gate electrode of the rabbit body is different from each other. The connection of the second terminal field effect transistor Ni)i gate electrode in the cell n 〇i is the same as the connection method of the gate electrode of the second terminal field effect transistor pD1 of the seventh figure, the same as the 12975503, but different from The connection of each of the second terminal field effect transistor pDi gate electrodes, that is, the second terminal field effect transistor Ndi gate electrode is connected to the second clock voltage vCKN source. In the implementation concept of the present invention, the output unit The connection of the first terminal field effect transistor NSn + 1 gate electrode in the cell ΙΙΟ Η is also different, and it is the same as the connection method of the first terminal field effect transistor pSn+1 gate electrode of the seventh charge pump, but different from other The connection of each first end field effect transistor Psi gate electrode. Therefore, the first-end field effect transistor gate 10 electrode is typically connected to the second S/D region of the cell 1 1 On-! internal charge transfer field effect transistor Ντη-l to receive the voltage, but may also The gate electrode connected to the charge transfer field effect transistor in the cell 1 1 QnH is changed to receive the gate voltage VGn + i. By reversing the characteristics of all voltages, the charge pump of Figure 11 can be operated in the same manner as the charge pump of Figure 7. Therefore, the charge pump of FIG. 11 can avoid unnecessary polarization operation in the first charge transfer unit cell (1) and the output charge transfer unit cell 丨丨〇 η + ι, which is performed by the charge of the seventh figure. The corresponding cell in the pump is achieved in the same way as the unnecessary polarization action avoided by (10).

An eleventh (a) and twelfth (b) (collectively referred to as twelfth) system: the seventh phase of the two-phase charge pump extension application, which is based on the concept of the case The forward charge pump structure, in order to achieve further Sun ^ Liang special ^. The structure of the beginning and end of the four-phase forward charge pump is shown in the tenth-figure (a). The intermediate charge pump portion is disclosed in the tenth device as the charge pump of the seventh figure, and the twelfth diagram of the charge pump is supplied with the source supply. The power supply has a high supply voltage L 42 1297503 and a low supply voltage Vss. . The charge pump in the twelfth figure comprises η+1 charge-transfer unit cells 12 arranged in series (h, 12〇2, 12〇n&l2〇n+1; respectively corresponding to the charge transfer unit cell 12 (h) The main pump capacitance elements Cm, Cl > 2...CDn-1 and Cdh of -12〇n; n other pump capacitance elements CG1, Cg2 which also correspond to the charge transfer unit cells 12〇1-12〇η... Cgh and Cgh, for the additional (or additional) capacitive element of the soap cell 1 20n+1, Cgh+Ι; the output capacitive element CPP; and a first clock voltage signal Vckpi, a second clock voltage a source of the signal VCKP2, a third clock voltage signal Vckp3, and a fourth clock voltage signal Vcm (not separately disclosed), wherein the second clock voltage signal VcKP2 is reversed from the first clock voltage signal Vcm The third clock voltage signal VcKJ>3 is in phase with the first clock voltage signal Vcm; and the fourth clock voltage signal VcKp4 is in phase with the second clock voltage signal Vckp2. Each charge transfer unit cell 120i, The main capacitive element CDi and the other capacitive element cGi form one of the electric spring pump Stage 122i, wherein i is an integer value varying from 1 to n. Each charge transfer unit cell 120i is comprised of a charge transfer field effect transistor Pn, a first end field effect transistor pSi, and a second end field effect transistor pDi. , a voltage-equal ization field effect transistor pEi, and a diode-configured field effect transistor pRi constitute 'where i is changed from 1 to n+i. Field effect transistor Pn, psi and PDi, and field effect transistors pEi and pRi are both enhanced p-channel insulating gate elements. The voltage equalization field effect transistor Ρει— ρΕη+ι is essentially the same, and the diode is the same. The configuration field effect transistor PRi_pRn+i is essentially the same. The connection between the field effect transistor ρτι-Ρτη", psi-psn+1 and PD1-pDn+1 in the charge pump in Fig. 12 is described below. The other parts are the same as those of the charge pump shown in Figure 7. Unlike the charge pump in the seventh section of the charge pump of the seventh section of the 62i cell, the charge transfer field effect transistor is different. The i20i field effect transistor pTi gate pole is not directly connected to the field effect a second S/D region of the crystal Ρη. The second S/D region of the field effect transistor and the gate electrode are respectively connected to the first and second S/D regions of the voltage equalization field effect transistor pEi : (source and drain, respectively), wherein the gate electrode of the voltage equalization field effect transistor pEi is connected to the first S/J region of the field effect transistor Ρη. The gate electrode of the field effect transistor pTi is also connected to the first S/D region (source) of the diode-configured field effect transistor PRi. The second S/D region of the field effect transistor pTi_ is connected to the gate electrode of the diode arrangement field effect transistor pRi and the second S/D region (drain), so that the diode is configured with the field effect transistor PRi In a diode configuration architecture. Therefore, for each diode, the field effect transistor PRi becomes a rectifier. Field Effect The body regions of the transistors PEi and PRi are typically interconnected in the second S/D region of the field effect transistors Ph and PEi to receive the body voltage VBi. Field effect power: the connection between the body PEi and the PRi is applied to the output unit cell 120nH and applied to each unit cell 12 (h-120η-like. In addition to the field effect transistor Pmi, in the twelfth figure, each charge of the charge pump The transfer field effect transistor pTi has the following connections. In particular, please refer to the twelfth figure (b) of the 1297503. For each odd i value, when another capacitor Cci is connected to the gate electrode of the field effect transistor pTi When the clock voltage is ... source, the main capacitor CDi is connected between the second s/d region of the field effect transistor pTi and the source of the clock voltage Vcm. For each even value of i, when another capacitor Cci is connected to the field When the gate electrode of the effect transistor pTi and the clock voltage VcKM, the main capacitor CDi is connected between the first S/D region of the field effect transistor pTi and the source of the clock voltage Vckp2. Since each field _ effect transistor PTi The gate electrode and the second S/D region are not directly connected together, so the gate voltage vGi and the cell output voltage VlH in the cell 122i of each stage 122i are separated signals. About the output cell 12〇n +1 charge transfer field effect transistor ^ Ρτη+1 The additional capacitor CGn+1 is connected between the closed electrode of the field effect transistor pTn+1 and (i) the source of the clock signal Vcm, if η is an even number; or (ii) between the sources of the clock signal Vckm If η is an odd number, it is worth noting that the capacitor CGn+1 is connected differently than the seventh figure charge. The twelfth figure (a) reveals an embodiment in which η is even. Gate voltage VGn The +1 and pump charging output voltage Vpp (or VDn+1) is also a separate signal. The first cell 12 (h the second terminal field effect transistor pD1 gate is connected to the clock voltage Vckp2 source to Receiving the clock voltage signal Vckp2. Similar to the charge pump embodiment of the previous seventh figure, the gate electrode of the first cell field effect transistor pSn+1 of the output cell 12〇n+ι is connected to the cell 12〇ni (two cell front) charge transfer field effect transistor Ρτη-l brother S-D region 'receives the output voltage Vdh from cell 120n-l. Twelfth figure other remaining power in the charge pump The crystal/capacitor connection 45 1297503 is equivalent to the charge pump of the seventh figure. The clock power VcKPl_VcKP4 is periodically changed. The low supply voltage Vss is between a high voltage equal to or very close to the high supply voltage Vdd. The thirteenth diagram reveals that the waveform of the clock voltage Vcm-VCKP4 is between the low supply voltage Vss and the high supply voltage Vdd over time. Variations. Regarding how the clock voltages Vckpi and VcKP2 are applied to the capacitors Cdi-Cdp, the clock voltages VCKH and VCKP2 are substantially corresponding to the applications of the clock-voltage volts Vckp and the clock-voltage VCKp in the charge pump of the seventh diagram, respectively. The clock voltage Vcm and VcKP3 form a clock-signal pair, which is mainly used for the odd-numbered pump charging stages 122], 1223, and the like. In the twelfth figure (b), the pump charging phase labeled "122i" is the stage of this odd class. The clock voltages VCKP2 and VCKP4 also form a clock signal pair, which is mainly used for the even-numbered pump charging stages 1 222, 1224, and the like. In the twelfth figure (b), the pump charging phase labeled "122m" is the stage of this even class. As shown in Figure 13, the clock voltage during pump charging operation

VcKP3 is only in Vss when the clock voltage Vckpi is Vss, especially when the clock voltage Vcm is only in the Vss time interval. Similarly, during the pump charging operation, the clock voltage VCKP4 is at Vss only when the current pulse voltage VcKP2 is Vss, especially in the portion of each time interval when the clock voltage VcKP2 is only at Vss. For the complementary form, during the pump charging operation, the clock voltage Vcm is at Vdd only when the clock voltage Vckp3 is Vdd, especially in the portion of each time interval when the clock voltage Vcm is only at Vdd. Similarly, during the pump charging operation, the period 46 1297503 pulse voltage Vckp2 is also at Vdd only for the portion of each time interval when the pulse voltage VCKP4 is at VDD. In addition, more specifically, the Lu's clock voltage yCKP1 produces a high-to-low transition, which is followed by a transition from a high-to-low clock voltage VcKi>3, and a low-to-high clock voltage VCKF>3 transition. And a low to high clock voltage Vcm transition. The transition of the clock voltage VCKP3 is thus returned from VDD to Vss to Vdd 'at (a) when the transition of the pulse voltage Yew is from yDD to vss 10' and (b) when the pulse voltage VcKPl is immediately converted back to VdD . Similarly, the clock voltage Vckp2 produces a transition from high to low, followed by a transition from a high to low clock voltage VcKi > 4, a low to high clock voltage Vcm transition, and a low to high transition. The clock voltage VcKp2 changes. Therefore, the transition of the clock voltage Vckp4 is returned from VDD to vss to the Vdd value, and the transition of (a) the current pulse voltage vCKI>2 is from ^ to vss, and (b) the current pulse voltage Vckp2 is immediately changed. Back to vDD. • Using the clock waveform of the thirteenth diagram and the voltage waveform of the ninth diagram, and in conjunction with the annotation of the seventh charge pump, the operation of each pump charging phase 122i produces a one-stage voltage gain ΔνΙΗ. The clock voltage and the milk pass through the electric grid device CdI-CDn to control the first end field effect transistor psi_pSn and the second end field effect transistor pD1_pDn, substantially corresponding to the clock voltage Vckp in the seventh charge pump The pulse voltage signal Ϋϋκρ is controlled by the capacitor Cci-Cen to control the first end field effect transistor ^-匕 „the same as the second end field effect transistor hi-PDn. 思思弟弟十二图(b) implementation For example, the pump charging phase 1224 is a countable phase 'and its main capacitor Cl)i is connected to the clock electrical dust 47 1297503

The source of Vckpi, which is equivalent to the clock voltage Vckp in the charge pump of the seventh diagram. When the pulse voltage Vckpi is at a high value, the pump charging phase 122i unit cell 120i first end field effect transistor pSi and the second end field effect transistor PDi system are respectively turned off and on. Therefore, the body voltage VBi is equal to the cell output voltage VDi during the high value of the clock voltage Vckpi. This prevents the body voltage VBi from being electrically floating when the first end field effect transistor psi and the second end field effect transistor Pm are turned off and on. During this time, it is not necessary to have two polarizations to be activated. When the pulse voltage Vckpi is at a low value, the first end field effect transistor pSi and the second end field effect transistor PSi of the cell 120i of the chestnut charging stage 122i in the twelfth diagram (b) are respectively turned on and off, whereby The body voltage VBi is equal to the cell input voltage Vdh. The charge transfer field effect transistor Pn of each pump charge phase 122i (whether it is an odd number stage or an even number stage) is essentially only turned on when the first end field effect transistor psi is turned on at this stage. Therefore, when the field effect transistor PTi is turned on at this stage, the body voltage VBi of each charging phase 122i is equal to the voltage Vdh of the first S/D region of the field effect transistor pTi at that stage. This allows each charge transfer field effect transistor PTi to effectively achieve the same zero back-bias threshold voltage yT0 as every other charge transfer field effect transistor pTi. The cell input voltage Vdh of each stage 122i cell 120i exceeds the cell output voltage Vim when the first terminal field effect transistor Psi is turned on at this stage. As discussed below, each stage of the I22i charge transfer field effect transistor PTi will only be physically activated during each of the gate periods during which the first end field effect transistor Psi is turned on. Because of the first end field effect transistor 48 1297503

During each time period when Psi is turned on, each (8) gate voltage yGj of the white slave 122i is equal to the early cell voltage VDi_, so the first end field effect transistor PS i is turned on in each time interval interval. However, the charge transfer field effect transistor p T i is turned off, and the body voltage VBi_ of each stage 122i can avoid reaching one in each time-course portion of the field effect transistor Psi turning on the i_% utility body pTi off, which may cause unnecessary The degree of voltage of the two polarizations. Field effect transistor Pm gate voltage to clock voltage ... source connection, equivalent to the seventh figure charge pump in the field effect transistor pD1 gate voltage to the clock voltage signal, κρ source link, can avoid the tenth The first charge transfer unit cell 1201 in the charge pump of FIG. 2 generates an unnecessary two polarization operation. Referring to the diagram in the tenth figure (a), and in conjunction with the seventh figure charge pump first charge transfer unit cell 6 (h, the clock voltage yCKP and the clock voltage ycKp are configured to be converted to the tenth figure (a) The pulse voltages VcKH and VCKP2 can explain how to avoid unnecessary polarization. The gate electrode of the first terminal field effect transistor PsnH to the field effect transistor Pth the second S/D region passes through the capacitor Cdh-1 to the clock voltage Vckpi. The connection corresponds to the connection between the gate electrode of the charge source FET PSn+1 of the seventh figure to the second S/D region of the field effect transistor pTnM through the capacitor Ccn-i to the clock voltage Vcm. The output charge transfer unit cell 12〇n+1 in the twelve-character charge pump generates unnecessary polarization operation. Combined with the diagram in the figure (b) of the tenth figure, in conjunction with the seventh diagram, the charge pump outputs the charge transfer unit cell 6〇n. The +1 medium field effect transistor Psn + Ι gate electrode is coupled to the clock voltage VcKP source through the capacitor Ccn-1 and the converted clock voltage Vckp and the clock voltage VCKP are the clock voltage VcKPl corresponding to the tenth figure (b). With Vcm configuration instructions, replace capacitors with Cdh 49 1297503

Ccn ^ can explain how the charge transfer unit cell can avoid unnecessary polarization.筮^__ τ The charge pump of one figure can prevent the polarization from being activated during the charging of the whole pump. Referring again to Fig. 12(b), an odd-numbered stage 120' is disclosed, and the electric devices Cj)i and ^ are respectively receiving the clock voltages ^ρι and VCI7, and the charge transfer field effect transistors Pn are substantially only It is turned off when the first-end field effect battery body pSl is turned off, because the clock voltage is only at a high value when the clock voltage W is at a high value. In particular, the charge transfer field effect body PTi is only in the time period during which the first end field effect transistor Psi is turned off, and the time is closed. The clock power is only during the time period when each clock voltage is in the south value. It is only at a high value. Please refer to the thirteenth figure, which discloses the successive time periods tA, tB, tG, tD, tE, tF, _tH. Referring to Fig. 12(b) and Fig. 13, in the time condition, after the clock voltage Vcrn is high, the clock voltage VcKi > 4 immediately becomes high, so the clock voltage VcKP3 also becomes high. Although the clock voltage Vcm is at a low value at time tA, the charge transfer field effect transistors ΡηΜ and ρη ι are turned off due to the clock voltage VcKP4 being at a high value. The charge transfer field effect transistor PTi and the first field effect transistor Psi are also turned off due to the clock voltages VCKP1 and Vcm being at a high value at time =, then the single cell input voltage Vdh of the field effect transistor pEi gate electrode The pin is smaller than the first S/D region of the field effect transistor pEi, and the cell output voltage VDi of the (source) is such that the voltage equalizes the field effect: the body PEi is turned on. The second end field effect transistor PDi is turned on. During time tA, the body voltage VBi is thus equal to the cell output voltage. During time tA, the gate voltage VGi of the first s/D region (source) 50 1297503 of the field effect transistor pRi is smaller than the diode arrangement field effect transistor pRi gate electrode and the second S/D region (dip pole) The unit cell output voltage VDi at the junction. Thus the diode is configured to turn off the field effect transistor pRi. Because the gate voltage VVi is also connected to the second S/D region (no pole) of the voltage equalization field effect transistor pEi, the positive charge is equal to the lower plate transmission voltage of the capacitor (5), and the % effect transistor pEi to the capacitor CGi Lower plate to reduce the difference between yGi and Vm. Preferably, the gate 10 voltage is substantially equal to the cell output voltage VDi before the subsequent clock voltage VcKpl becomes low. In other words, the voltage equalization field effect transistor pEi is reduced by less than the voltage difference between the charge transfer field effect transistor PTi gate electrode and the second S/D region, and is equalized to the charge transfer field effect transistor pTi. The voltage of the gate electrode and the second S/D region, wherein the state of the charge transfer field effect transistor pTi is turned on. At time tB, the pulse voltages VCKpi and VCKp3 are still high.

When the value is, the clock voltage VcKi > 4 becomes lower. The charge transfer field effect transistor pTiM and Ρτ “ι are both turned on. The charge transfer field effect transistor pTi and the first end field effect transistor PSi remain off. The second end field effect transistor pDi remains on. Clock voltage Vckp2 At time tB, the transition to a low value is performed, and the positive charge is transmitted to the capacitor CDi i through the charge transfer field effect transistor pTii to increase the early cell turn-in voltage Vdh, and the voltage vDi_2 is decreased in a corresponding manner. The body voltage VBi continues. Equivalent to the cell input voltage VDil, and thereby relatively gradually increased. Positive charge is also transmitted from the capacitor CDi through the charge transfer % effect transistor pTi+1 to reduce the cell output voltage, 51 1297503 ~ close to each other 'but wide, and The electric calendar equals the field effect 2: /1 continues to pay respect. If the cell powers out! Π二二等, 闭极电® Vci and unit

Lower unit wheel center; two (four)... value = time;; hour:: port r are still at high complex value. Charge Transfer Field Effect Transistor =:: Turns off. The charge transfer field effect transistor PTi and the bipolar rp. mesh wide effect transistor PRi remain off. The voltage equalization field effect crystal El J must be kept on continuously to reduce the voltage difference between the gate voltage vGi and the cell output, vDi. The first end field effect transistor h and the second end field effect transistor pDi are respectively kept off and on.

At time tD, the clock voltage VCKP1 goes low when the clock voltage VCKP2 goes high at the same time. The cell output voltage VDi quickly drops to a value approximately Vdd-Vss. The cell input voltage Vmm rises rapidly to approximately VDD to VSS, just like the voltage Vmh. The first end field effect transistor psi is turned on when the second end field effect transistor Pin is turned off. The body voltage VBi is rapidly reduced and becomes equivalent to the value of the cell input voltage VjH i . The charge transfer field effect transistor pTi remains off because the clock voltage Vckp3 is still at a high value during time tD. The charge transfer field effect transistor Ρπμ and pTi+1 also remain off. Before the arrival time tD, the voltage equalization field effect transistor pEi has made the voltages VVi and VDi extremely close to each other, 52 1297503% pulse voltages VcKP1 and Vcm make the voltage equalization field effect transistor PEi gate electrode in time tD The cell input voltage VDi! exceeds the cell output voltage VDi of the first S/D region (source) of the voltage equalization % effect transistor pEi. This voltage equalization field effect transistor pEi is thus turned off. The clock voltage Vcm also reduces the cell output voltage vDi of the Pm gate electrode of the diode-configured field effect transistor at least below the first S/D region of the pole-configured field effect transistor PRi (source) in the time tD. The gate voltage Vci is usually greater than the threshold voltage Vtr of the field effect transistor pRi (negative). The diode configuration field effect transistor pRi thus turns on at time tD. Positive charge is transferred from capacitor CGi through diode to field effect transistor PRi to capacitor CDi. The gate voltage Vei drops when the cell output voltage vDi rises. The diode configuration field effect transistor PRi is thus reduced by the voltage difference between the voltages Vu and VDi when the charge transfer field effect transistor pTi is turned off. Because the gate voltage VGi must be greater than the cell output voltage VDi, at least one threshold voltage Vtr, so that the diode is placed on the field effect transistor PRi and its voltage-reducing action is performed, so The diode configuration field effect transistor PRi does not cause the voltage difference value between VGa and VDi to be less than Vtr. When a positive charge is transmitted through the diode configuration field effect transistor PRi, removal of the positive charge from the capacitor CGi results in an increase in the pass voltage of the capacitor Is CGi from its own lower plate to its souther plate. Capacitor cGi tooth voltage increase value is Δ VCG. In a more representative embodiment the ΔVcG value is equal to 2 volts. Since the gate voltage VGi decreases at time tD, the charge transfer field effect 53 1297503 transistor Ρn can be turned off at time tD even if the clock voltage VcKp3 is at a good value. According to this, some positive power is transmitted from the capacitor n CDi" to the capacitor CDi through the charge transfer field effect transistor pTi. When the cell output voltage VDi rises slightly, the cell input voltage VDi-1 is thus slightly lowered. At time tE, the clock voltage ycK3 goes low. The gate voltage V (ji# speed drops to a value of approximately Vdd-Vss, which causes the charge transfer field effect transistor pTi to be turned on when it is not turned on or more conductive when it is turned on. The diode is configured to field-effect transistor Ρη Closed because the diode configuration field effect transistor Pri causes the electric barometer C (?i penetration voltage to increase by △ yCG value, the value of the gate voltage yGi is slightly lower than the value when the diode configuration field effect transistor pRi is not applied. A value of Δν^. The decrease of the value of the gate voltage VGi causes the conduction value of the charge transfer field effect transistor PTi to be increased more than if the diode configuration field effect transistor PRi is not applied. Therefore, the diode placement field The effect transistor pRi has a function of increasing the conduction of the electro-transfer field-effect transistor pTi when it is turned on. ', • The current pulse voltage Vcm becomes a low value at time tE, the first end field effect transistor psi and the The second terminal field effect transistor pDi is kept on and off respectively (to turn on the gate voltage VGi voltage drop when the charge transfer field effect transistor pTi is not turned on; or in the charge transfer field effect power) When the crystal Ρn is turned on, its conduction amount is increased). The charge transfer field effect transistors Ρη-ι and Ρτπι remain in a closed state. The positive charge is thus transferred from the capacitor CDi-1 through the charge transfer field effect transistor pTi to the capacitor cDi because the conduction flux of the charge transfer field effect transistor PTi is relatively low. The application of the diode to configure the field effect transistor PRi is even more increased, so more charge is transmitted through the 1297503 charge transfer field effect transistor PTi, which is higher than when the diode configuration field effect transistor PRi is not applied. This can be increased. Charge-pumping efficiency. Although the positive charge may have flowed from the capacitor CDil through the charge transfer field effect transistor PTi to the capacitor CDi from time tD to time, the time tE to the time T voltage v_ period is The positive charge is transmitted by the capacitor CDi i through the charge transfer field effect transistor pTi to the main period of the capacitor CDi, and is closer to the target of achieving high pump charging efficiency. When the cell output voltage vDi starts to gradually increase The single π cell input voltage ^^ starts to gradually decrease in relativeivity. During the clock, the voltage VCKi>3 is at a low value, although a high pump charge is desired. The electrical efficiency time is quite long, but the time is still short until the voltage ^ and ^ (1) are not close to each other. The voltage Li-1 voltage drop is not enough to start the voltage equalization field effect transistor PEi. The voltage equalization field effect transistor pEi Therefore, it remains off. The body voltage VBi continues to be equal to the value of the cell input voltage VDi!, and the dust drop is relatively reduced. When the cell input voltage VlHM is greater than the cell output voltage, the clock voltage Vcm It changes back to a high value at time tF. The charge transfer field effect transistor pTi is turned off to temporarily maintain the cell input voltage VDi ιλ at the cell output voltage VDi. The field effect transistors Pth, pmi, pDi and PEl remain off' while the field effect transistors PSi and pRi remain on. At time tc, the clock voltage Vckpi goes high when the clock voltage [κρ2 changes back to a low value. The cell output voltage Vm rises rapidly to a value approximately equal to Vdd-Vss. The cell input voltage VDi-Ι is quickly reduced to a value of about 55 Ϊ 297503, and VDi+i is also the same. When the first end field is effective, the Japanese body? ^ With the pole tube configuration field effect electric crystal 埒 曰Μ η ΓΚ , ΓΚ 犄 犄 犄 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟The body voltage v is the value of the cell output voltage VDi. The electric line is equivalent. Since the clock voltage v(10) is still at a high value, the charge transfer effect transistor PTi] and pTi + 1 are turned off. On the gate electrode of the voltage equalization field effect transistor pEi, the cell input voltage is approximately equal to the value of V^Vss~! When it is large enough, the voltage equalization field effect transistor PEi can be activated. At time tG, the low to high clock voltage VCKP1 transition causes the cell output voltage VDi to exceed the value of the gate voltage. The positive charge is thus transmitted from the capacitor CDi through the voltage equalization field effect transistor pEi to the capacitor CGie voltage equalization field effect transistor pEi and then begins to perform its equalization voltage and function.

The voltages VDi, VMM, and VGd VBi at time tH are the same as those at time tA. The time interval from time tA to time tH is the cycle or period of the twelveth charge pump operation. The variations in voltages VDi, VDid, Vei, and VBi are substantially the same in cell 120i of each pump charging phase 122i. Since the threshold voltage VTe of the zero back-bias of each charge transfer field effect transistor is essentially the same, then the voltage gain of each stage of the pump charging phase 122i is equal. As shown in the charge pump of the seventh figure, the pump charge output voltage VPP of the charge pump of Fig. 12 increases linearly as the number of stages of pump charging increases, to achieve high efficiency pump charging operation. The charge transfer field effect transistor pTi is a relatively large field effect transistor compared to the first end field effect transistor psi and the second end field effect transistor 56 1297503 PDi. That is, it can be inferred that the charge transfer field effect transistor pTi has a larger aspect ratio than the first end field effect transistor Psi and the second end field effect transistor pDi. Thus, the turn-off of the charge transfer field effect transistor pn is naturally slower than the first end field effect transistor Psi and the second end field effect transistor pΜ. The diode configuration field effect transistor PRi and the voltage equalization field effect transistor pEi are substantially prevented from being transmitted to the capacitor Cmm through the charge transfer field effect transistor pTi in the charge transfer field effect transistor ρη φ shutdown procedure. In order to avoid the reverse charge transfer of the charge transfer field effect transistor pTi at startup, the use of a four-phase clock system including a diode-configured field effect transistor pRi and a voltage equalization field effect transistor pEi in place of the two-phase clock system will enable The cell pump charging efficiency is increased. The fourteenth figure reveals the n-phase four-phase forward charge pump structure of another concept of the present invention. The charge pump in Fig. 14 includes a charge transfer unit cell 1 20l-120n + l, a main pump capacitor element CD1-CDn, another chestnut capacitor element CG1-CGn, another capacitor element cGn+1, and an additional capacitor. The component Cdh+i, the output capacitive component Cpp; and the source of the first clock voltage Vckpi, the second clock voltage Vcm, the third clock voltage VCKP3, and the fourth clock voltage VCKP4 (not separately disclosed). In addition to outputting the charge transfer unit cell 12〇n+1 and the side applied capacitance element CDn+1, the charge transfer unit cell 120l-120n+1 and the capacitance elements Cm-CDn, CgI-CGn+l and FIG. The Cpp junction is the same as the charge pump in Fig. 12, and is operated by the VDD and Vss power supply equivalent to the clock voltage VCKP1-VCKP4 in the charge pump of the twelfth graph. In the charge pump of Fig. 14, each of the charge transfer units 57 1297503 cells 120i, the main capacitive element CDi and the further capacitive element CGi form a pump charge phase 122i of the charge pump, wherein the value of i varies from i to η The integer value. In the fourteenth charge pump, the cell unit 12〇η+ι, the second S/D region (drain) of the charge transfer field effect transistor ρτη+1 is not electrically connected to the voltage equalization field effect. The first S/D region (source) of the transistor pEn+1 and the second S/D region (drain) of the diode-configured field effect transistor pRn+1, which are not the same as the twelfth diagram charge pump system Electrically connected to the first S/D region of the voltage equalization field effect transistor PEn+1 and the second S/D region of the diode configuration field effect transistor Pr... thus the charge transfer field effect of the fourteenth charge system The PTn+1 of the crystal: S/D is not directly electrically connected to the gate electrode of the charge transfer field effect transistor PTn+1. This can make the gate voltage vGn+1 and the pump in the charge pump of Fig. 14. Charging output voltage Vpp (or become a completely separated signal. In the fourteenth figure, the first end of the charge pump output cell 12〇n+1 field circuit transistor *PSn+1 gate electrode is electrically connected to the voltage equalization field The first S/D region of the effect transistor PEn+1 and the diode configure the second S/D region of the field effect transistor &..., unlike the twelfth diagram charge pump system to electrically connect it to the electricity. The second S/D region of the field-effect transistor Pth. The external capacitive element c_ is connected to the voltage equalization field effect transistor % first s/d region and the diode arrangement field effect transistor pRn+i second S/ Between the intersection of the D region and (1) the source of the clock voltage V, if n is an even number; or ((1) between the sources of the clock voltage w, if an odd number. The fourteenth embodiment reveals that the embodiment of -η is even The other link 58 1297503 and the cell 12〇n+1 in the charge pump of the fourteenth figure are the same as those of the charge pump of the twelfth figure. See the charge pump of Fig. 12, the charge of the fourteenth figure. The pump is based on the first charge transfer unit cell 120! The connection between the second terminal field effect transistor Pm open-circuit voltage and the clock voltage Vm>2 source can avoid unnecessary two-polarization actuation, and the connection relationship is as shown in the tenth figure (a In the seventh diagram, the first charge transfer unit cell 60 of the charge pump can avoid unnecessary two polarization operations; and then convert the clock voltage Vckp and the clock voltage VCKP into the tenth figure _ (a) Clock voltage VcKPl and VGKP2 configuration description. First end field effect transistor Psn+1 gate electrode transmission capacitor CDnH Coupling to the clock voltage Vcm source (when η is even; η is odd is the source of the clock voltage VCKP2), compared to the first end field effect transistor Psn+1 gate electrode through capacitor in the seventh charge pump Cgh+1 to clock voltage Vckp source (when η is ... even number; η is an odd number is the source of the clock voltage Vckp), based on which can avoid the fourteenth charge output charge transfer unit cell 12〇n+1 It is not necessary to move the two movements, and the connection relationship is as shown in the figure (b) of the tenth figure. In the seventh _ seven figure, the electric power is output, and the unnecessary poles of the early cell 6 On + 1 are transferred. The actuation can be avoided. In this case, the first-end field effect transistor Psn + 1i gate electrode is coupled to the clock voltage Vckp source through the capacitor CGn + l (when η is even; η is odd when the clock is Voltage VCKP source) If the clock voltage Vckp and ▽(10) are replaced by the clock voltages VcKP1 and VcKP2 corresponding to the tenth figure (b), and the capacitor cGn+1 is replaced by Ccn + l, the output charge can be explained by How to transfer unit cells to avoid unnecessary polarization. The charge pump of Figure 12 is protected against bipolarization during charging of the overall pump. 59 1297503 The fifteenth (a) and fifteenth (b) (collectively referred to as the fifteenth figure) reveals the extended application of the two-phase charge pump of the eleventh figure, which is a four-phase negative according to the concept of the present case. To the charge pump structure. Similar to the twelfth figure (a), the structure of the beginning and end of the four-phase negative charge pump is disclosed in Fig. 15(a). Figure 15 (b) reveals the intermediate charge pump section as shown in Figure 12 (b). The fifteenth diagram of the operation of the charge pump is started by a power supply having a high supply voltage Vdd and a low supply voltage Vss. The charge pump in the fifteenth figure comprises n+1 series of charge transfer unit cells 13 (h, 13〇2, . . . UOh, 13〇„ and l3〇n+1; respectively corresponding to charge transfer The unit cell 13 (the main pump capacitance element Cim-Cdh of h-13〇n; the same capacitance element Cgi-Cgh corresponding to the charge transfer unit cell 130ι_13〇n, for the unit cell 13另外n+ι additional (or additional) capacitive element CGn+1; - output capacitive element cNN; and a first clock voltage signal VCKN1, a second clock voltage signal, a third clock voltage signal a source of Vcm and a fourth clock voltage signal Vc〇4 (not separately disclosed), wherein the second clock voltage signal is inversely related to the first clock voltage signal VcKN1; the third clock voltage signal Vckn3 is The first clock voltage signal VcKN1 is partially in phase; and the fourth clock voltage signal VcKN4 is in phase with the first clock voltage signal VcKN2. Each of the charge transfer unit cells 130i, the corresponding main capacitive element Cm and the corresponding additional capacitor Element CGi forms one of the charge pump pump charging stages 132i, where the value of i In order to change from 1 to an integer value of η, a pump charging input voltage signal Vdo 60 1297503 equal to the low supply voltage Vss is connected to the first unit cell 1301 of the first pump charging stage 1321. The charge pump of the figure is the same. When the nth pump charging phase 132n containing the nth cell 13〇n is a last pump charging phase, the n+1th cell 13〇πη is a connection to an output. An output cell of the circuit conductor 136, wherein the output circuit conductor 136 can provide a pump charge output voltage signal Vm having a value less than a constant value of vss. The output capacitor Cnn is coupled to the output circuit conductor 136 and the Vss supply voltage The charge transfer unit cell 13 (h-13〇nH is composed of an enhanced n-channel insulated gate field effect transistor, except that the conduction form is reversed, the enhanced n-channel insulated gate field effect transistor and The twelfth diagram of the charge pump enhanced Ρ channel insulated gate field effect transistor has the same configuration. Each charge transfer unit cell 130i is composed of a charge transfer field effect transistor NTi and a first end field effect transistor NSi. With one The two-terminal field effect transistor Νμ, a voltage equalization field effect transistor NEi and a diode configuration field effect transistor & constitute 'they can correspond to the twelfth figure charge chest h, ^, PDi, ~ and ~ The voltage equalization field effect transistor NE1-NEn+1 is essentially identical, and the diode configuration field effect transistor H is exactly the same. 4 Field effect transistor Μ (τ (4) l, Nsi a Nsn+1, heart

Connected with the other and the capacitor Can "NI" is connected as shown in the above twelfth figure ^ ^ 乂 P ▲, (four) a ' method. The same voltage and voltage vD1, vv, Rn+1 are connected to 61 1297503 In the field effect transistor Ντ广Ντη+〗, Ns〗-NSn+丨, nd丨-Νι> π·η, Ne丨in+丨 and NR1-NRn+1 'Like the field effect transistor Ρτι_Ρτη+ι, psi_psn+i, The relative position of the two ΡΕ1-ΡΕη+ι and PR1-PRn+. The clock electrical waste signal H, Vc〇2, Vcm and V-plane source are connected to the capacitor Cdi-Cdii+Ι and Cci according to the same source of Vcm_VcKp4. -Cgii+Ι.

According to the concept of the present invention, the connection of the second end field effect transistor Nih gate electrode in the first unit cell 13〇 is different from the connection of each of the second end field effect transistor NDi gate electrodes, and Twelve-character charge pump = two-terminal field effect transistor pD1 gate electrode connection method is the same, but different from each other second-end field effect transistor pDi gate electrode connection, that is, the fifteenth figure charge pump The second end field effect transistor Npl gate electrode is connected to the source of the reverse clock voltage VCKN2. In the implementation concept of the present invention, the connection of the first terminal field effect transistor Nsn+1 gate electrode in the output single cell 70〇n+1 is also different from the connection of each other first end field effect transistor Nsi gate electrode. It is the same as the connection method of the first-stage field effect transistor Psn+1 gate electrode of the charge pump of the twelfth figure, but different from the connection of the other PSi gate electrode of each second-end field effect transistor. Therefore, the first-end field effect transistor Nsn+1 inter-electrode is typically connected to the second S/D region of the charge transfer field effect transistor ΝΤη-ι in the cell 131 to receive the voltage Vdw from the cell cell 1 . The clock voltage signals VCKN1 - VcKN4 are varied between the low supply voltage Vss and the high supply voltage Vdd shown in Fig. 16. Comparing the sixteenth and thirteenth graphs, the clock voltage signal VCKN1_VCKN4 is inversely related to Vckp, -VCKP4 applied to the charge pump of the twelfth figure, respectively. 62 1297503 Replaces all reversed voltage characteristics. The fifteenth figure charge pump operates in the same way as the charge pump of Figure 12. Therefore, the fifteenth graph charge pump can be used in the twelfth graph charge pump to avoid the same method in which the first charge transfer unit 701201 and the output charge transfer unit cell 12〇η+1 are undesirably polarized. To avoid unwanted bipolarization in the first charge transfer unit cell 130ι and the output charge transfer unit cell ι3〇η+ι; however, the same method is also used in the seventh graph charge pump to avoid the first charge transfer. Unwanted bipolarization occurs in cell 6〇1 and output charge transfer cell 6〇η+1. The seventeenth figure reveals another n-stage four-phase negative charge pump structure in this case. The charge pump in Fig. 17 includes a charge transfer unit cell 13 (h-13〇η+1; main pump capacitance element Cdi-Cj)n; another pump capacitance element cG1-cGn; and another capacitance element CGn+ l; additional capacitive element cDn+i, · output capacitive element c〇; and source of clock voltage signal Vckni-Vckn4 (not separately disclosed). In addition to the output charge transfer unit cell 13〇η+ι and the additional capacitive element CDn+1, the charge transfer unit cell 13 (h-13〇n+1 and the capacitive element cD1-Ci>n, in the charge pump of the seventeenth diagram, CG1-匕„+1 and C〇 are both connected in the same way as the fifteenth figure, and are equivalent to the fifteenth figure charge.

Vc〇^Vc〇4^. In the charge pump of the seventeenth diagram, each charge transfer unit cell 13 (h, the corresponding main capacitive element Cm and the corresponding additional capacitive element core form the charge pump-charge phase 132i, wherein the value of i is also from i Change to the integer value of η. About the seventeenth figure charge (four) of the output charge transfer unit cell 63 1297503 13〇η+1 and the additional capacitive element CDn+1, the seventeenth charge pump in the charge transfer field effect transistor Ντη +1 second S/D region (drain), voltage equalization field effect transistor Neh+1 first S/D region (source), diode configuration field effect transistor NRn+1 second 3/0 region ( The connection between the drain electrode and the first terminal field effect transistor 11+1 gate electrode is different from the charge transfer field effect transistor Ντη+1 second S/D region and voltage equalization field in the charge pump of the fifteenth figure. The effect transistor NEn+1 first S/D region, the diode configuration field effect transistor ΝβΝ+1 second s/D region• domain and the first end field effect transistor Nsn+i gate electrode connection. Four-character charge pump charge transfer field effect transistor pTn+1 second S/D region, voltage equalization field effect transistor ΡΕη+1 first S/D region, two pole The connection between the second S/D region of the field effect transistor Pmi and the pSn+1 gate electrode of the first end field effect transistor is also different from that of the twelfth figure. Figure 17 shows the internal and external capacitive elements of the charge pump Ci&gt ;n+1 is connected to the voltage equalization field effect transistor NEn+l first S/D region and diode configuration field effect transistor NRn+i second s/D region • junction and (i) clock voltage Between VcKN1 sources, if n is an even number; or (Π) between clock source sources, if ^ is an odd number. Figure 17 reveals an embodiment in which η is an even number. Therefore, the charge in the seventeenth figure The gate voltage vCn+1 in the pump and the pump charging output voltage Vnn (or VDn+i) are separate signals, and in the charge pump of the seventeenth figure, the other connection and the single π cell 13〇n+1 The cross-connection is the same as that of the charge pump of the fifteenth figure. Replacing all the reversed voltage characteristics, the charge pump of the seventeenth figure is the same as the charge pump of the fourteenth figure. Therefore, the seventeenth figure" The charge pump uses the charge pattern of the fourteenth diagram to avoid the first charge transfer unit cell 2〇1 and the output charge transfer unit cell 12〇η+ι 64 1297503 The same method of dual polarization actuation to avoid unwanted bipolarization in the first charge transfer unit cell 130ι and the output charge transfer unit cell 3ΐη+ι; however, the same method is also used in the seventh figure. The charge pump is used to avoid unwanted bipolarization in the first charge transfer unit cell 6 (h and the output charge transfer unit cell 6 OnH. When the present invention is illustrated by a specific reference embodiment, the purpose of the description is only The examples are provided, but are not intended to limit the scope of the claims. For example, in a diode configuration, the gate electrode of each voltage equalization field effect transistor hi or Nei can be connected to its second s/d region (bungee ) to receive the gate voltage VCi. In this case, when the charge transfer field effect transistor Pn or NTi is turned off but does not cause the voltages Vci and vDi to become equal to each other, the field effect transistor pEi or NEi lowers the gate voltage Vci and the cell output voltage Vi) The difference between the two. Instead, the field effect transistor pEi or the cell output voltage VDi is substantially equivalent to the gate voltage V (Ji plus the threshold voltage Vte of the field effect transistor PEi or NEi. Thus, the field effect transistor PEi or NEi is charged When the transfer field effect transistor pTi or NTi is turned off, it essentially reduces the difference between the voltage VVi and VDi to VTE. The clock voltages Vcm and Vcn>3 can simultaneously make a low-to-high transition, rather than the time voltage Vckpi is low. At the time of value, Vcm performs a low-to-high transition. Similarly, the clock voltages Vcm and Vcm can simultaneously make a low-to-high transition', rather than when the time voltage Vcm is at a low value, the \TCKP4 undergoes a low-to-high transition. In the complementary method, the clock voltage Vc〇i can be made high-to-low transition at the same time, and not when the time voltage Vckni is at a high value, Vc〇4 undergoes a high-to-low transition, and the clock voltage is 〇2. With Vckn4 65 1297503, you can make a high to low transition at the same time.

Revised in the seventh, twelfth and fourteenth above

The connection of Pl>n can also be different from the revealed charge. The connection of some of the side-end field effect transistors Pm-1^ and Pdz- can be removed to change the charge pump structure shown in the seventh, twelfth and fourteenth above. These similarities can be found in the eleventh diagram of the fifteenth and seventeenth diagrams of the charge pump structure. Although the connection of the second terminal field effect transistor pD1 or Ndi gate electrode to the first end field effect transistor Psn + 1 or NsnH gate electrode is different from that of the other second end field effect transistor pDi or Nl) The pole electrode and the other first end field, the effect transistor Psn+i or Nsw gate electrode, but each second end field effect I body PDi or NDi gate electrode connection can be the same as the charge pump change in this case, on the spot The connection of the effect transistor PSn+1 or NSn+1 gate electrode is different from the connection of each field effect transistor PSn+i or NSn+i gate electrode. Similarly, each field effect transistor PSn + 1 or NsnH gate electrode connection can be the same as the variation of the electric street pump in this case, and the connection of the field effect transistor pDi or Ndi gate electrode is different from each field effect transistor pDi or NDi. When the gate electrode is connected. The present invention has been described in detail by the above-described embodiments, and may be modified by those skilled in the art, without departing from the scope of the appended claims. 66 1297503 [Simple description of the diagram] The first, third and fourth diagrams show the circuit diagrams of three traditional charge pumps. The first figure is an idealized clock voltage pattern disclosed in the first, third and fourth charge pumps. The fifth figure is revealed in the first, third and fourth figures of the charge pump, the relationship between the pump charge output voltage and the number of stages. Referring to the sixth (a) and sixth (b) drawings, a circuit diagram/structure cross-section of the first and output unit cells of the fourth charge pump is disclosed. Fig. 7(a) and Fig. 7(b) are circuit diagrams showing the two-phase forward charge pump of the preferred embodiment of the present invention. Fig. 8 is a schematic diagram showing the clock voltages of the charge pump of the seventh diagram (3) and the seventh diagram (b). Fig. 9 is a schematic diagram showing various voltages including an idealized clock voltage in the charge pump of the seventh diagram (^) and the seventh diagram (b). Fig. (&) and Fig. 10(b) show the circuit diagram/structure cross-section of the first and second output cells of the charge pump in the seventh (a) and seventh (b). The tenth-figure is a circuit diagram showing the two-phase negative charge of the preferred embodiment of the present invention. Twelfth (a) and twelfth (b) are circuit diagrams showing a four-phase forward charge pump of the preferred embodiment of the present invention. The eleventh figure is a schematic diagram of the idealized clock voltage of the twenty-fifth (4) and the twelfth (8) charge pump. 67 1297503 Fig. 14 is a circuit diagram showing a four-phase forward charge pump of another preferred embodiment of the present invention. Fig. 15(a) and Fig. 15(b) are circuit diagrams showing the four-phase negative charge of the preferred embodiment of the present invention. Figure 16 is a schematic diagram showing the idealized clock voltage of the charge pump of Figure 15 (a) and Figure 15 (b). Figure 17 is a φ circuit diagram of a four-phase negative charge pump of another preferred embodiment of the present invention.

68 1297503 Main component symbol description 22 Substrate 24 η-type well 26 Ρ+region 28 Ρ+region 30 η+contact region 32 parasitic ρηρ bipolar transistor 34 parasitic collector resistance 36 parasitic base resistance 40 η-well 42 Ρ+ region 44 Ρ+region 46 η+contact region 48 parasitic ρηρ bipolar transistor 50 parasitic collector resistance 52 parasitic base resistance 54 gate electrode 58 gate electrode 64 input circuit conductor 66 output circuit conductor 68 square wave of clock voltage signal 70 Reverse wave voltage signal square wave 72 Substrate 74 η-type well 82 Parasitic ρηρ bipolar transistor 84 Parasitic collector resistance 86 Parasitic base resistance 88 Gate electrode 90 η-type well 94 Second S/D region 96 η+ Contact area 98 parasitic ρηρ bipolar transistor 69 1297503 100 102 114 116 134 136 104, 106 and 108 110ι-110π+ι 110i 112i 1 2〇1 - 1 20n + l 120i 122i 1 30l~l 30n+l 130i 132i 20i 20nfl 6〇1 - 60n+l 60i 62i-62n 62i 76 and 78 92 and 94 Cl -Cn Cci -Ccn Cci CdI - CDn CDi CgI -Ccn+1 C〇i Ci VCK VCKN parasitic collector resistance parasitic base resistance input Circuit conductor Out circuit conductor input circuit conductor output circuit conductor gate electrode charge transfer unit cell charge transfer unit cell pump charge phase charge transfer unit cell charge transfer unit cell pump charge phase charge transfer unit cell charge transfer unit cell pump charge phase charge transfer unit cell output Cell charge transfer unit cell charge transfer unit cell pump charge phase pump charge phase P+ region P+ region capacitance main pump capacitance element main capacitance element main pump capacitance element main capacitance element additional capacitance element additional capacitance element capacitance reverse clock voltage second Clock voltage signal 1297503

VCKP second clock voltage signal Cnn output capacitor element Co output capacitor Cpp output capacitor element Dl-Dn PN diode Di diode Dn.l PN diode Nl)l -NDn.l second end field effect transistor Ndi second end field effect transistor ΝεΙ-Νεπ+1 voltage equalization field effect transistor NEi voltage equalization field effect transistor NrI-Nrii+I diode configuration field effect transistor Nri diode configuration field effect transistor Nsi first end Field effect transistor Ντί -Ντη+1 Charge transfer field effect transistor Ντί Charge transfer field effect transistor PdI -PDn+1 Second end field effect transistor Pdi Second end field effect transistor Pei - Ρεπ+ι Voltage equalization Field effect transistor PEi voltage equalization field effect transistor PrI -PRn+1 diode configuration field effect transistor PRi diode configuration field effect transistor Psi -Psn+1 first end field effect transistor Psi first end field effect transistor Ρτΐ -Ρτη+1 Charge transfer field effect transistor Pli Charge transfer field effect transistor Ql -Qn+1 Field effect transistor QdI-Qdii+1 汲Extreme field effect transistor Qi Field effect transistor Qsi-Qsn + l Source terminal Field effect transistor Qti charge transfer transistor QTi + 1 charge transfer electric field effect transistor tl, t2, t3 and t4 time interval interval tA ' tB, tc ' tD, tE, time interval 71 1297503 tF, tG and tH VBi Vbii+1 Vck VcKN VcKNl VCKN2 VCKN3 VCKN4 Vckp Vckpi VCKP2 VcKP3 VCKP4 Vdo Vdd VDi Vdi-1 Vdh VDn+1 VDWi-1 VdXi-1 VDYi Vdzi Vgi VGn+1 Vpn Vpp Vs Vto Vti Δ Vdi body voltage body voltage clock voltage first clock voltage signal first clock Voltage signal second clock voltage signal third clock voltage signal fourth clock voltage signal first clock voltage signal first clock voltage signal second clock voltage signal third clock voltage signal fourth clock voltage signal Input voltage signal South supply power supply output voltage input voltage input voltage output voltage lower piezoelectric higher voltage lower voltage higher voltage gate voltage signal gate voltage diode turn-on voltage output voltage low supply voltage threshold voltage threshold voltage stage Voltage gain 72

Claims (1)

1297503 X. The scope of application for patents: 1.  A charge pump structure having a structure comprising: n+1 a plurality of charge transfer unit cells, which are successively labeled as first to (n+1)th unit cells, wherein the η system is at least 3, and the plurality of unit cells A plurality of field-effect transistors of the same polarity are included, and each field-effect transistor has a gate electrode and first and second source/drain electrodes separated from the channel portion of the body region ("S/D ") region; each of the cells includes (a) a charge transfer field effect transistor; (b) a first end field effect transistor, the first and second S/D regions are coupled to the a first S/D region and a body region of the charge transfer field effect transistor; (c) a second end field effect transistor having first and second S/D regions coupled to the charge transfer field effect transistor, respectively a second S/D region and a body region; and the plurality of cell cells, except for the (n+1)th cell cell coupled to the first S/D region of the cell intracellular charge transfer field effect transistor All of the second S/D regions of the charge transfer field effect transistor are arranged in series; a first and second clock signal source, The first and the second clock signals are opposite to each other, and the gate voltages of the first end field effect transistor and the second end field effect transistor are coupled to the (a) first cell, respectively a second S/D region of the charge transfer field effect transistor of the first cell and the second clock signal source; (b) the (n+1)th cell is coupled to the charge pump respectively a selected region and a first S/D region of the charge transfer field effect transistor of the (n+1)th cell; and (c) in each of the remaining cells, respectively, to the remaining a cell intracellular 73 1297503, the second and first S/D regions of the charge transfer field effect transistor; and η a plurality of main capacitive elements, respectively coupled to the first to the second single τ cells, each of which a primary capacitive element is coupled between the second S/D region of the corresponding charge transfer field effect transistor and (i) the first clock signal source, and the corresponding cell is an odd number When a single cell is 70; or (ϋ) between the sources of the second clock signal, the corresponding cell is an even number of cells . 2. The charge pump structure of claim 1, wherein the gate electrode of the first end field effect transistor in the (n+1)th cell is electrically coupled to the first (n-1) a second S/D region of the charge transfer field effect transistor within the cell. 3. The charge pump structure of claim 2, wherein the main capacitive element corresponding to the (n-1)th cell is coupled to the (n+1)th cell. Between the gate electrode of one end field effect transistor and (i) the source of the first clock signal, when η is an even number; or (ii) between the sources of the second clock signal, when η is an odd number . 4. The charge pump structure of claim 1, wherein the gate electrode and the second S/D region of the charge transfer field effect transistor in the (n+1)th cell are substantially in contact with each other Removing the electrical coupling; and electrically coupling the gate electrode of the first end field effect transistor to the (n+1)th cell in the (n+1)th cell to the charge transfer field effect transistor The gate electrode. 5. The charge pump structure of claim 4, further comprising an external capacitive element that is coupled to the charge of the (n+1)th cell to the gate electrode of the field effect transistor 74 1297503 And (1) between the source of the first clock signal, when η is an even number; or (ii) the source of the second clock signal, when η is an odd number. The charge pump structure of claim 1, further comprising an external capacitive element coupled to the gate electrode of the first end field effect transistor of the (n+1)th cell and (1) the first - _ pulse signal source, when η is an even number; or (ii) between second clock signal sources, when η is an odd number. The charge pump structure of claim 6, wherein the gate electrode-S/D region of the charge transfer field effect transistor of the (^+1)th cell is not directly electrically coupled to each other; The charge pump structure further includes at least one external field effect transistor, and the first and the second S/D regions of the external field effect transistor are respectively coupled to the (n+1)th cell intracellular charge transfer % effect a gate electrode of the transistor and a gate electrode of the first end field effect transistor in the first (in 1) cell. The charge system structure of claim 1, further comprising a circuit loop for providing a gate electrode (a) of the charge transfer field effect transistor - a control signal synchronized with the first clock signal, Each odd number of cells is intracellular; and (b) - a control signal synchronized with the second clock signal in each of the even number of cells. 9. The charge pump structure of claim 8, wherein the body region of each of the first end field effect transistors is electrically coupled to its second S/D region. [10] The charge pump structure of claim 1, wherein the first to the nth unit cell, the drain electrode of each of the charge transfer field effect transistors is connected to the The first-S/D region of the charge transfer field effect transistor. 11. The charge pump structure of claim 1, further comprising: a first clock k and a fourth clock signal source, which are different from the first and second clock signal sources And the four clock signals substantially vary between a first voltage value and a second voltage value; wherein the third time signal is substantially only when the first clock signal is at the first time during the pump charging operation Each time step portion of the voltage value is substantially at the first voltage value; and the fourth clock signal is substantially only when the second clock signal is at the first voltage value during a pump charging operation Each time-phase portion is substantially at the first voltage value; and n+1 a plurality of additional capacitive elements respectively corresponding to n+1 plurality of unit cells, wherein each of the additional capacitive elements is coupled thereto Corresponding to the early electrode cell between the gate electrode of the transfer field effect transistor and (i) the source of the second clock signal, when the corresponding cell is an odd number of cells; or (ii) Between four sources of clock signals, the corresponding unit cell is an even number of Cells. 12. The charge pump structure of claim 11, wherein the gate electrode of the first end field effect transistor in the (n+1)th cell is electrically coupled to the (n-1) The second S/D region of the charge transfer field effect Thunder body in a cell. 13. The charge pump structure of claim 12, wherein 76 1297503 corresponds to the main capacitive element of the (n-1)th cell, coupled to the (n+1)th cell Between the gate electrode of the first end field effect transistor and (i) the source of the first clock signal, when η is an even number; or (ii) the source of the second clock signal, at η An odd number. 14. The charge pump structure of claim U, further comprising an external capacitive element coupled to the gate electrode of the first k field effect transistor of the (n+1)th cell (i) between the sources of the first clock signal, when η is an even number; or (ϋ) between the sources of the second clock signal, when η is an odd number. The charge pump structure of claim 14, wherein the gate electrode and the S/D region of the charge transfer field effect transistor of the (n+1)th cell are not directly electrically coupled to each other; The charge pump structure further includes at least one external field effect transistor, and the first and second S/D regions of the external field effect transistor are combined to the (n+1)th unit intracellular charge. Transmitting a gate electrode of the field effect transistor and a gate electrode of the first end field effect transistor in the (n+1)th cell. [6] The charge pump structure described in the scope of the patent scope, wherein: s /;: the body region of the domain end field effect transistor is electrically coupled to the seventh.   The charge-fruit structure described in item 11 of the ninth range, wherein the first, clock signal is only in the third substantially the first λ-8 when the signal of the Raytheon pulse is at the fourth time The part of the process is only: the time is only in the fourth 瞎: the second-clock is in the pump charging operation, the clock h is in the second singular value, t 77 1297503 two-time-phase part At substantially the second voltage value. The first: as in the case of the application: the charge pump structure described in the eleventh item, wherein the value two:: When the charging operation is performed, substantially the second voltage value is converted into the first bud two & ν private! During the charging operation, the real f 2=(31)# the first-clock signal is at the pressure value and (10) the second electrical waste value is converted to the first electric priest* the first clock signal is then converted back to the The second voltage a occurs; and the fourth clock signal is in the pump charging operation, the substantial pressure value is converted to the first voltage value is (a2) when the rotation; during the charging operation, substantially by the second voltage value The electrical age and (10) occur when the second clock signal then transitions back to the second voltage value. 19. The charge pump structure of claim 5, wherein the third clock signal is substantially converted from the second (four) to the first voltage value and returned to the first time during pump charging operation The second voltage value is (8), although the first clock signal is in the pump charging operation, substantially converted from the second voltage value to the first electric value and (10) when the first clock signal is immediately converted back to the second Between the voltage values occurring; and the fourth clock signal is substantially converted from the second voltage value to the first voltage value and returned to the second voltage value during the pump charging operation (a2) when the first The two-clock signal is substantially converted from the second electrical value to the first voltage value and (b2) when the second clock signal is subsequently converted back to the second electrical value. The charge pump structure of claim 11, wherein the charge transfer field effect crystal system in each of the cells is turned on by the other capacitive element corresponding to 78 1297503, in response to (i) The third clock signal is converted from the second voltage value to the first voltage value when the unit cell is an odd number of unit cells; or (ii) the fourth clock signal is converted by the second voltage value For the first voltage value, when the unit cell is an even number of unit cells. 21. The charge pump structure of claim 11, further comprising a uniform circuit such that the charge transfer field effect transistor in the cell is more strongly turned on when it is turned on. The charge pump structure of claim 21, wherein the causing circuit, in each of the first to the nth unit cells, is coupled to the unit cell for the charge transfer Between the gate electrode of the field effect transistor and the second S/D region. The charge pump structure of claim 22, wherein the causing circuit, in the (n+1)th cell, is coupled to the (n+1)th cell. Transfer the gate electrode of the field effect transistor to the area of the ^S/D area. [24] The charge pump structure of claim 22, wherein the causing circuit 'in the (n+1)th cell is coupled to the (n+1)th cell in the charge The gate electrode of the field effect transistor and the gate electrode of the first end field effect transistor are transferred. The charge pump structure of claim 24, further comprising an external capacitive element coupled to the gate electrode of the first end field effect transistor of the (n+1)th cell (i) between the sources of the first clock signal, when n is an even number; or (ii) between 79 1297503 sources of the second clock signal, when η is an odd number. 26. The charge pump structure of claim 25, wherein the gate electrode and the second S/D region of the charge transfer field effect transistor of the (n+1) cell are not directly electrically connected to each other. coupling. 27. The charge pump structure of claim 22, wherein each of the cells causes the circuit to include a rectifier. The charge pump structure of claim 11, wherein φ further comprises a circuit loop in each of the first to the nth unit cells, so that the charge is in the unit cell When the transfer field effect transistor is turned off, 'the voltage difference between the voltage on the gate electrode of the charge transfer field effect transistor and the second S/D region is reduced. The charge pump structure of claim 28, wherein in each of the first to the nth unit cells, a circuit is included in the cell to cause the charge transfer in the cell. The field effect transistor can be turned on more strongly when it is turned on. 30. The charge pump structure of claim 5, wherein each of the first to the nth unit cells further comprises a diode-configured field effect transistor, the first S/ a D region is coupled to the gate electrode of the charge transfer field effect transistor in the cell; and a gate electrode and a second S/D region are coupled to the cell intracellular cell. Two S/D areas. 31. The charge pump structure of claim 11, wherein each of the first to the nth unit cells further comprises a voltage equalization field effect transistor, the first S/D The region, the gate electrode 盥1297503 two S/D regions are respectively coupled to the second S/D region, the first S/D region and the gate electrode of the charge transfer field effect transistor in the cell. 32.  The charge pump structure of claim 31, wherein each of the first to the nth unit cells further comprises a diode-displaced field effect transistor, the first S/D region thereof. Is coupled to the gate electrode of the charge transfer field effect transistor in the unit cell; and the gate electrode and the second S/D region are jointly coupled to the unit cell, the charge transfer φ field effect transistor Two S/D areas. 33.  A charge pump structure having a structure comprising: n+1 a plurality of charge transfer unit cells, respectively labeled as first to '(n+1)th cell, wherein n is at least 3, and the plurality of cells: The cell comprises a plurality of field-effect transistors of the same polarity, and each field-effect transistor has a gate electrode and first and second source/drain electrodes separated by a channel portion of the body region ("S /D") region; each cell contains (a) a charge transfer field effect transistor; (b) a first end field effect 10 transistor, the first and second S/D regions are respectively a first S/D region and a body region coupled to the charge transfer field effect transistor; (c) a second end field effect transistor having first and second S/D regions coupled to the charge transfer field, respectively a second S/D region and a body region of the effect transistor; and the plurality of cell cells, except the (n+1)th cell cell coupled to the first S/D of the intracellular charge transfer field effect transistor Outside the region, the second S/D regions of the charge transfer field effect transistor are arranged in series; a first and a second clock Source, the first and the second clock signals are opposite to each other, and the gate voltage of the first end field effect transistor and the second end field effect 81 1297503 transistor is in (a) the first unit cell a second S/D region of the charge transfer field effect transistor coupled to the first cell and a selected region of the charge pump; (b) the (n+1)th cell, First gate electrodes of the charge transfer field effect transistor of the (n-1)th cell And (c) in each of the remaining unit cells, respectively coupled to the second and first S/D regions of the charge transfer field effect φ transistor in the remaining unit cell; and η a plurality of main capacitive elements Correspondingly coupled to the first to nth cell respectively, wherein each of the main capacitive elements is coupled to the corresponding one, the second S/D region of the charge transfer field effect transistor in the cell and (i): The first clock signal is between 溽, when the corresponding unit cell is an odd number* unit cell; or (ii) Between two o'clock clock signal sources, to the corresponding cell is a cell even-numbered unit cells. 34.  The charge pump structure of claim 33, wherein the primary capacitive element corresponding to the (n-1)th cell is coupled to the (n+1)th cell, the first Between the gate electrode of the end field effect transistor and (i) the source of the first clock signal, when η is an even number; or (ii) the source of the second clock signal, when η is an odd number. 35.  The charge pump structure of claim 33, further comprising a circuit loop for providing a gate electrode (a) of the charge transfer field effect transistor - a control signal synchronized with the first clock signal, Each of the odd number of cells is intracellular; and (b) - a control signal synchronized with the second clock signal in each of the even number of cells. 82 1297503 36.  The charge pump structure of claim 33, wherein a gate electrode of the charge transfer field effect transistor is connected to the charge transfer in each of the first to the nth unit cells The second S/D region of the field effect transistor. 37.  The charge pump structure of claim 36, further comprising an external capacitive element coupled to the gate electrode of the charge transfer field effect transistor of the (n+1)th cell and (i) the first The source of a clock signal is between η is an odd number; or (ii) is the source of the second clock signal when η is an even number. 38.  The charge pump structure of claim 33, further comprising: - a third clock signal and a fourth clock signal source, which are different from - the first and second clock signal sources And the four clock signals are each varied between a first voltage value and a second voltage value; wherein the third clock signal is in a pump charging operation, only when the first clock signal is at the first voltage value* Each time-phase portion is only at the first voltage value; and the fourth clock signal is in the pump charging operation only when each time-course portion of the second clock signal is at the first voltage value The first voltage value; and n+1 a plurality of additional capacitive elements respectively corresponding to n+1 a plurality of unit cells, wherein each of the additional capacitive elements is coupled to the corresponding unit cell and the charge transfer field effect Between the gate electrode of the transistor and (i) the source of the third clock signal, when the corresponding cell is an odd number of cells; or (ii) between the sources of the fourth clock signal, The unit cell is an even number of unit cells. 83 1297503 39.  a charge pump structure, the structure comprising: n+1 a plurality of charge transfer unit cells, respectively labeled as first to (n+1)th cell respectively, wherein the η system is at least 3, and the plurality of cells The cell comprises a plurality of field-effect transistors of the same polarity, and each of the field-effect transistors has a gate electrode and a first source and a second source/drain which are separated from the channel portion of the body region ("S/ D") region; each cell contains (a) - charge transfer field effect transistor; (b) - first end field φ effect transistor, the first and second S / D regions are respectively coupled To the first S/D region and the body region of the charge transfer field effect transistor; and (c) a second end field effect transistor having first and second S/D regions coupled to the charge transfer field, respectively a second S/D region of the effect transistor and a body region-domain; and the plurality of cells, except for the (n+1)th cell line coupling, to the first cell charge transfer field effect transistor Outside the S/D region, the second S/D regions of the charge transfer field effect transistor are arranged in series; the (n+1)th cell The gate electrode and the second S/D region of the charge transfer field effect transistor are electrically coupled to each other; a first and second clock signal source, the first and second clock signals are opposite to each other And the gate voltage of the first end field effect transistor and the second end field effect transistor is (a) in the first unit cell, and the charge transfer field effect transistor is respectively coupled to the first unit cell a second S/D region and a selected region of the charge pump; (b) the (n+1)th cell is coupled to the charge transfer field of the (n+1)th cell a gate electrode of the effect transistor and a first S/D region of the charge transfer field effect transistor of the (n+1)th cell; and (c) a cell of each remaining cell 84 1297503 And ???the second and first S/D regions of the charge transfer field effect transistor in the remaining unit cells; and η a plurality of main capacitive elements respectively coupled to the first to nth unit cells, wherein each a primary capacitive element is coupled to the second S/D region of the charge transfer field effect transistor in the corresponding cell And (i) between the first clock signal source, when the corresponding unit cell is an odd number of unit cells; or (ii) between the second clock signal sources, and the corresponding unit cell is a An even number of unit cells. 40.  The charge pump structure of claim 39, further comprising: an external capacitive element coupled to the gate electrode of the (n+1)th cell of the charge bar shift field effect transistor and (i) the The first clock signal source - between when η is an even number; or (ii) between the second clock signal sources when η is an odd number. 41.  A charge pump structure comprising: n+1 a plurality of charge transfer unit cells, respectively labeled as first to the (n+1)th cell, wherein the η system is at least 3, and the plurality of cells The cell comprises a plurality of field-effect transistors of the same polarity, and each of the field-effect transistors has a gate electrode and a first source and a second source/drain which are separated from the channel portion of the body region ("S/ D") region; wherein each cell contains (a) a charge transfer field effect transistor; (b) a first end field effect transistor, the first and second S/D regions are respectively coupled to a first S/D region and a body region of the charge transfer field effect transistor; and (c) a second end field effect transistor having first and second S/D regions coupled to the charge transfer field effect, respectively a second S/D region of the transistor and a body region 85 1297503 domain; and the plurality of cell cells, except the (n+1)th cell cell system coupled to the first S of the cell intracellular charge transfer field effect transistor Outside the /D region, the second S/D regions of the charge transfer field effect transistor are arranged in series; the (n+1)th The gate electrode and the second S/D region of the charge transfer field effect transistor in the cell are substantially electrically disconnected from each other; the first """ and the first clock"is source" - the second clock signal is opposite to each other; a third and fourth clock signal source is different from the first and second clock signal sources; and the four clock signals are substantially Each of the first and second voltage values is varied; wherein the third clock signal is substantially only during each time interval of the first clock signal when the first clock signal is at the first voltage value during the charging operation At substantially the first voltage value; and the fourth clock signal is substantially only in a portion of each time step when the second clock signal is at the first voltage value during a pump charging operation a first voltage value; η a plurality of main capacitive elements respectively coupled to the first to nth unit cells, wherein each of the main capacitive elements is coupled to the corresponding unit cell, the charge transfer field effect transistor Two S/D regions and (between the brother and the clock source) When the corresponding unit cell is an odd number of unit cells; or (ii) between the second clock signal sources, the corresponding unit cell is an even number of unit cells; n+1 a plurality of additional capacitor elements, Corresponding to n+1 a plurality of unit cells, wherein each of the additional capacitive elements is coupled to the gate electrode of the charge transfer field effect transistor in the corresponding unit cell and (i) the 86 1297503 three-hour pulse Between the signal sources, when the corresponding unit cell is an odd number of unit cells; or (ii) between the fourth clock signal sources, the corresponding unit cell is an even number of unit cells; and an external capacitive element Connected to (i) between the sources of the first clock signal, when η is an even number; or (ii) the source of the second clock signal, when η is an odd number; the first end field effect transistor And a gate voltage of the second end field effect transistor in (a) the first cell, respectively coupled to the second S/D region of the charge transfer field effect transistor of the φ first cell a selected area in the charge pump; (b) in the (n+1)th cell, respectively The charge transfer field effect-crystal coupled to the (n+1)th cell is coupled to the first S/D region; and (c) is coupled to each of the remaining cells The charge to the remaining unit cell • the second and first S/D regions of the field effect transistor. 42.  The charge pump structure of claim 41, wherein the gate electrode and the second S/D region of the charge transfer field effect transistor of the (n+1)th cell are not directly electrically connected to each other. Coupling; and the charge pump structure t further includes at least one external field effect transistor, and coupling the first and second S/D regions of the external field effect transistor to the (n+1)th cell respectively a gate electrode of the charge transfer field effect transistor and a gate electrode of the first end field effect transistor in the (n+1)th cell. 43.  a charge pump structure, the structure comprising: n+1 a plurality of charge transfer unit cells, respectively labeled as first to (n+1)th cell respectively, wherein the η system is at least 3, and the plurality of cells The cell comprises a plurality of in-polar field effect transistors, and each field effect transistor 87 1297503 has a gate electrode and a first and a second source/drain separated from a channel portion of the body region (" S/D") region; each cell contains a charge transfer field effect transistor; and each of the first and (n+1)th cells further comprises (a) - first end field effect a first phase of the first and second S/D regions coupled to the first S/D region and the body region of the charge transfer field effect transistor; and (b) a second end field effect transistor, the first of which And a second S/D region coupled to the second S/D region and the body region of the charge transfer φ field effect transistor, respectively; and the plurality of unit cells, except the (n+1)th cell line coupled to Immediately adjacent to the first S/D region of the intracellular charge transfer field effect transistor, the first is the charge transfer field effect transistor The S/D regions are arranged in series; - a first and a second clock signal source, the first and second clock signals are opposite to each other, and the first end field effect transistor and the second end field effect a gate voltage of the transistor in (a) the first cell, respectively coupled to the second S/D • region of the charge transfer field effect transistor of the first cell and the second clock signal source; And (b) the (n+1)th cell is coupled to a selected region of the charge pump and the first S/ of the charge transfer field effect transistor of the (n+1)th cell; a D region; and η a plurality of main capacitive elements respectively coupled to the first to nth unit cells, wherein each of the main capacitive elements is coupled to a second of the corresponding unit cells of the charge transfer field effect transistor Between the S/D region and (i) the source of the first clock signal, when the corresponding cell is an odd number of cells; or (ii) between the sources of the second clock signal, in the corresponding 88 1297503 The unit cell is an even number of unit cells. 44. The charge pump structure of claim 43, wherein a gate electrode of the first end field effect transistor in the (n+1)th cell is electrically coupled to the first (n-1) a second S/D region of the charge transfer field effect transistor within the cell. 45.  The charge pump structure of claim 44, wherein the main capacitive element corresponding to the (n-1)th cell is coupled to the first (n+1)th cell, the first Between the gate electrode of the end field effect transistor and (i) the source of the first clock signal, when η is an even number; or (ii) the source of the second clock signal, when η is an odd number. 46. The charge pump structure of claim 43, wherein the gate electrode and the second S/D region of the charge transfer field effect transistor in the (n+1)th cell are substantially Electrical coupling is removed from each other; and the gate electrode of the first end field effect transistor in the (n+1)th cell is electrically coupled to the (n+1)th cell to the charge transfer field effect The gate of the crystal * gate electrode. 47. The charge pump structure of claim 46, further comprising an external capacitive element coupled to the gate electrode of the charge transfer field effect transistor of the (n+1)th cell and (i) the first Between one source of a clock signal, when η is an even number; or (^) between sources of the second clock signal, when η is an odd number. 48. The charge pump structure of claim 43, wherein the external capacitive element is coupled to the gate electrode of the first field effect transistor of the (n+1)th cell (i) between 89 1297503 of the first clock signal source, when η is an even number; or (π) between the sources of the second clock signal, when η is an odd number. 49. The charge pump structure of claim 48, further comprising at least one external field effect transistor, and coupling the first and second S/D regions of the external field effect transistor to the first ( η+1) the gate electrode of the intracellular charge transfer field effect transistor and the gate electrode of the first end field effect transistor in the (n+th) cell. 50. The charge pump structure of claim 43, further comprising a circuit loop for providing a gate electrode (a) of the charge transfer field effect transistor - controlling synchronization with the first clock signal a signal, in each odd number of cells; and (b) a control signal synchronized with the second clock signal, in each even number of cells. The charge pump structure of claim 43, wherein a gate electrode of the first end field effect transistor in the (n+1)th cell is electrically coupled to the (n-1) a second S/D region of the charge transfer field effect transistor within the cell. 52. The charge pump structure of claim 43, further comprising a third clock signal and a fourth clock signal source, which are different from the first and second clock signal sources; And the four voltages are each varied between a first voltage value and a second voltage value; wherein the first “唬” is substantially only when the first clock signal is at the first voltage value during the pump charging operation. The partial voltage is substantially at the first voltage value; and the fourth clock signal is substantially only 1297503 when the pump is charging, and only when the second clock signal is at the first voltage value. Substantially the first voltage value; and n+1 a plurality of additional capacitive elements respectively corresponding to n+1 a plurality of unit cells, wherein each of the additional capacitive elements is coupled to the corresponding unit cell Between the gate electrode of the transfer field effect transistor and (i) the source of the third clock signal, when the corresponding cell is an odd number of cells; or (ii) between the sources of the fourth clock signal, The corresponding unit φ cell is an even number of unit cells. 53.  a charge pump structure, the structure comprising: n + l a plurality of charge transfer unit cells, respectively labeled as first to (n + l) unit cells, wherein the η system is at least 3, and the plurality of single ♦ - The cell is a plurality of in-polar field effect transistors, and each field effect transistor has a gate electrode and a first and second source/drain (separated from a channel portion of the body region) "S/D" region; each cell contains a charge transfer field effect transistor; and each of the first and (n + 1)th cells further contains (a) - the first end field The first and second S/D regions of the effect transistor are respectively coupled to the first S/D region and the body region of the charge transfer field effect transistor; and (b) the second end field effect transistor, The first and second S/D regions are respectively coupled to the second S/D region and the body region of the charge transfer field effect transistor; and the plurality of cells are except for the (n+1)th cell system Coupling to the second S/D of the charge transfer field effect transistor outside the first S/D region of the intracellular charge transfer field effect transistor The fields are arranged in series; a first and a second clock signal source, the first and second clocks 1297503 signals are opposite to each other, and the first end field effect transistor and the second end field effect transistor are gated The pole electrode is coupled to the second S/D region of the charge transfer field effect transistor of the first cell and the selected region of the charge pump in (a) the first cell; and (b) a (n+丨) unit cell in which the second S/D region of the charge transfer field effect transistor of the (n-1)th cell is coupled to the (n+i)th cell a first S/D region of the charge transfer field effect transistor; and η a plurality of main capacitive elements respectively coupled to the first to nth unit cells, wherein each of the main capacitive elements is coupled to the corresponding unit Between the second S/D region of the charge transfer field effect transistor and (i) the source of the first clock signal, when the corresponding cell is an odd number of cells; or (ii) the second Between the source of the clock signal, the corresponding unit cell is an even number of unit cells. 54. The charge pump structure of claim 53, wherein the main capacitive element corresponding to the (n-1)th unit cell is lightly coupled to the (n+1)th unit cell. Between the gate electrode of the first end field effect transistor and (i) the source of the first clock signal, when η is an even number; or (ii) the source of the second clock signal, where η is an odd number Time. 55. The charge pump structure of claim 53, further comprising a circuit loop for providing a gate electrode (a) of the charge transfer field effect transistor - a control signal synchronized with the first clock signal , in each odd number of cells; and (b) - a control signal synchronized with the second clock signal in each of the even number of cells. 56. The charge pump structure as described in claim 53 of the patent application, further comprising 92 1297503 comprising a third clock signal and a fourth clock signal source, the basin is = first and the second clock signal source And the fourth time division value = between - the first and the second voltage value; wherein the third clock j is in the chest charging operation 'substantially only the first clock signal is at the first voltage Each time-phase portion of the value is substantially at the first voltage value; and the fourth clock signal is in the pump charging operation, ♦ only when the second clock signal is at the first voltage value Each time-phase portion is substantially at the first voltage value; and n+1 a plurality of additional capacitive elements respectively corresponding to n+1 a plurality of 'cells, wherein each of the additional capacitive elements is coupled to Corresponding to: between the gate electrode of the charge transfer field effect transistor in the cell and (i) the source of the βth three-clock signal, when the corresponding early cell is an odd number of cells; or Ii) between the sources of the fourth clock signal, the corresponding unit cell is an even number Unit cell. 93