1296444 九、發明說明： #【發明所屬之技術領域】 Λ 本發明涉及一種薄膜電晶體基板及其製造方法。 【先前技術】 由於液晶顯示裝置具輕、薄、省電等特點，其廣泛應 用於桌上型電腦、膝上型電腦、個人數字助理（pers〇nal Digital Assistant，PDA)、便攜式電話、電視及多種辦公自 動化與視聽設備中。液晶顯示裝置之主要元件係液晶面 _板。液晶面板一般包括一薄膜電晶體基板、一彩色濾光片 基板及夾於該薄膜電晶體基板與該彩色濾光片基板之間之 液晶層。其中，薄膜電晶體基板驅動液晶顯示面板每一液 晶像素點’以實現高速度、高輝度及高對比度之晝面顯示。 請參閱圖1，係一種先前技術薄膜電晶體基板之結構 示意圖。該薄膜電晶體基板100包括一基板11〇、一石夕薄 膜120、一絕緣層130及一閘極金屬層wo。該閘極金屬層 140覆蓋部份絕緣層13〇，該絕緣層13〇、矽薄膜120及基 _板110依次層疊設置。該絕緣層130係薄膜電晶體基板1〇〇 之閘極絕緣層。該矽薄膜120二端藉由佈植磷離子分別形 成一源極121及一汲極122。另外，該閘極金屬層14〇、源 極121及汲極122分別藉由導線（圖未示）與外部引腳（圖未 示）電性連接。 當該薄膜電晶體基板100工作時，外加電壓藉由各導 線施加於該閘極金屬層14〇、源極121及汲極122。其中， 該閘極金屬層140之閘極電壓能透過絕緣層13〇，於矽薄 膜120表面感應出一通道123,並藉由該源極121及汲極 1296444 122間之電位差，使通道123内產生電流。 ‘ 請參閱圖2，係圖1中薄膜電晶體基板100製造方法 . 之流程圖，其包括： 步驟S10 :提供一基板110。 步驟S11 :於該基板110上依序沈積一矽薄膜120、一 絕緣層130、一閘極金屬層140及一光阻層。 步驟S12 :提供一光罩，藉由該光罩對該光阻層進行 曝光、顯影，從而形成一光阻圖案。 _ 步驟S13 :蝕刻該閘極金屬層140，使其與光阻圖案 一致。 步驟S14 :於該矽薄膜120二端佈植磷離子，形成一 源極121及一汲極122。 步驟S15 :去除光阻圖案。 由於該絕緣層130之絕緣性右限，且於電晶體關閉之 狀態下，該閘極金屬層140與源極121及汲極122間易產 生漏電流。該漏電流影響該薄膜電晶體基板100之工作特 ⑩性，特別當薄膜電晶體基板100為關時，該漏電流會影響 電訊號之精確性，降低薄膜電晶體基板100之可靠性，從 而影響顯示品質。 【發明内容】 有鑑於此，有必要提供一種可靠性高之薄膜電晶體基 板。 還提供該薄膜電晶體基板之製造方法。 一種薄膜電晶體基板，其包括依次層疊設置之一基 板、一石夕薄膜、一絕緣層及一金屬層，其中，該絕緣層包 1296444 括一第一絕緣層及一第二絕緣層，該第二絕緣層覆蓋部份 第一絕緣層。 刀 該金屬層係該薄膜電晶體基板之閘極，該矽薄膜二端 相對形成有一源極及一没極，該源極及没極間具有—通、曾 區’該通道區長度與閘極長度一致。 一種薄膜電晶體基板製造方法，其包括以下步驟提 供一基板；於該基板上依序沈積一矽薄膜、一第一絕緣層、 了第一金屬層及一第一光阻層；提供一第一光罩，藉由曰誃 第一光罩對該第一光阻層進行曝光、顯影，形成一第一 阻圖案；蝕刻該第一金屬層，使其與該第一光阻圖案一致“· 於該第一絕緣層未被該第一光阻圖案覆蓋之區域沈積一第 :絕^去除該第一光阻圖案’該第二絕緣層覆蓋 弟一絕緣層。 | w 一種薄膜電晶體基板製造方法，其包括以下步驟 供一基板；於該基板上依序沈積—料膜、—第—絕緣21296444 IX. Description of the invention: # [Technical field to which the invention pertains] Λ The present invention relates to a thin film transistor substrate and a method of manufacturing the same. [Prior Art] Since the liquid crystal display device is light, thin, and power-saving, it is widely used in desktop computers, laptop computers, personal digital assistants (PDAs), portable phones, televisions, and the like. A variety of office automation and audiovisual equipment. The main components of the liquid crystal display device are liquid crystal panels. The liquid crystal panel generally includes a thin film transistor substrate, a color filter substrate, and a liquid crystal layer sandwiched between the thin film transistor substrate and the color filter substrate. Wherein, the thin film transistor substrate drives each liquid crystal pixel dot of the liquid crystal display panel to realize high-speed, high-luminance and high-contrast kneading display. Referring to Figure 1, there is shown a schematic view of the structure of a prior art thin film transistor substrate. The thin film transistor substrate 100 includes a substrate 11A, a lithography film 120, an insulating layer 130, and a gate metal layer wo. The gate metal layer 140 covers a portion of the insulating layer 13A, and the insulating layer 13, the germanium film 120, and the base plate 110 are laminated in this order. The insulating layer 130 is a gate insulating layer of the thin film transistor substrate 1A. The two ends of the tantalum film 120 respectively form a source electrode 121 and a drain electrode 122 by implanting phosphorus ions. In addition, the gate metal layer 14A, the source electrode 121 and the drain electrode 122 are electrically connected to external pins (not shown) by wires (not shown). When the thin film transistor substrate 100 is in operation, an applied voltage is applied to the gate metal layer 14, the source 121, and the drain 122 by wires. The gate voltage of the gate metal layer 140 can pass through the insulating layer 13 〇, and a channel 123 is induced on the surface of the germanium film 120, and the potential difference between the source electrode 121 and the drain electrode 1296444 122 is used to make the channel 123 Generate current. ‘Please refer to FIG. 2 , which is a flowchart of a method for manufacturing a thin film transistor substrate 100 in FIG. 1 , which includes: Step S10 : providing a substrate 110 . Step S11: sequentially depositing a thin film 120, an insulating layer 130, a gate metal layer 140, and a photoresist layer on the substrate 110. Step S12: providing a photomask by exposing and developing the photoresist layer to form a photoresist pattern. Step S13: The gate metal layer 140 is etched to conform to the photoresist pattern. Step S14: Phosphorus ions are implanted at both ends of the tantalum film 120 to form a source electrode 121 and a drain electrode 122. Step S15: removing the photoresist pattern. Due to the insulating right limit of the insulating layer 130, and the state in which the transistor is turned off, leakage current is easily generated between the gate metal layer 140 and the source electrode 121 and the drain electrode 122. The leakage current affects the working characteristics of the thin film transistor substrate 100. Especially when the thin film transistor substrate 100 is off, the leakage current affects the accuracy of the electrical signal, and reduces the reliability of the thin film transistor substrate 100, thereby affecting Display quality. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a highly reliable thin film transistor substrate. A method of manufacturing the thin film transistor substrate is also provided. A thin film transistor substrate comprising a substrate, a lining film, an insulating layer and a metal layer, wherein the insulating layer package 1296444 includes a first insulating layer and a second insulating layer, the second The insulating layer covers a portion of the first insulating layer. The metal layer is a gate of the thin film transistor substrate, and the two ends of the germanium film are oppositely formed with a source and a gate, and the source and the gate have a length and a gate of the channel region The length is the same. A method for manufacturing a thin film transistor substrate, comprising the steps of: providing a substrate; sequentially depositing a germanium film, a first insulating layer, a first metal layer and a first photoresist layer on the substrate; providing a first The first mask layer is exposed and developed by the first mask to form a first resistance pattern; the first metal layer is etched to be consistent with the first photoresist pattern. The first insulating layer is not deposited in a region covered by the first photoresist pattern: the first photoresist pattern is removed, and the second insulating layer covers the first insulating layer. | w A method for manufacturing a thin film transistor substrate The method includes the following steps for a substrate; sequentially depositing a film on the substrate, the first insulating layer 2
及第一光阻層；提供一第一光罩，藉由該第一朵罝安9 第一光阻芦進杆瞌氺ms s., '^第光罩對該 :層進订曝先、顯影，形成-第-光阻圖案；於該 续展.土一^ 案覆蓋之區域沈積-第二絕 = 光阻圖案，該第二絕緣層覆蓋部份第- 、，邑緣層，於該第一絕緣層未被第_ 第二絕緣層上依Hit m 層覆Κ部份及該 深瓚上依序沈積-閘極金 供-第二光罩，藉由該第二光:及第-先阻層，k 光、顯妒，形杰一楚丄尤罩對該第二光阻層進行曝 其與該第二光阻圖案H卜刻該間極金屬層，使 相較於先前技術，由於第二光阻圖案。 该相電晶縣板於其第-絕 8 1296444 ，緣層上進一步沈積有一第二絕緣層，該第二絕緣層增加源 • 極及汲極鄰近通道區之二端與閘極間之絕緣層厚度，增大 . 電阻。故相對於一定閘極電壓，該閘極與源極及汲極之間 之耦合電場較小，源極及汲極鄰近通道區兩端之電場亦較 小，故漏電流小，由漏電流所產生之不良影響降低，提高 薄膜電晶體基板之可靠性。 【實施方式】 請參閱圖3,其係本發明薄膜電晶體基板第一實施方 • 式之結構示意圖。該薄膜電晶體基板200包括一基板210、 一矽薄膜220、一第一絕緣層230、一第二絕緣層240、一 第一金屬層250及一第二金屬層260。 該第一絕緣層230、矽薄膜220及基板210依次層疊 設置。該第二絕緣層240覆蓋部份第一絕緣層230，並於 該第一絕緣層230上形成一開口。該第一金屬層250嵌入 該開口，並覆蓋第一絕緣層230。該第二金屬層260覆蓋 該第一金屬層250及鄰近該第一金屬層250之部份第二絕 • 緣層240。另外，該第一金屬層250係與第二金屬層260 歐姆接觸並一起組成閘極270。該矽薄膜220二端分別形 成有一源極221及一汲極222。另外，該薄膜電晶體基板 200之閘極270、源極221及汲極222分別與外接引腳（圖 未示）電性連接，該源極221及汲極222之間具一通道區 223,該通道區223長度與該第二金屬層260之長度一致。 當該薄膜電晶體基板200工作時，外接電路藉由導線 施加電壓於該閘極270、源極221及汲極222之上。其中， 該閘極270上之閘極電壓透過絕緣層230，於通道區223 9 1296444 ，表面耦合出一通道，並藉由該源極221及汲極222間之電 - 位差，使通道區223内產生電流。 ' 由於該薄膜電晶體基板200於其第一絕緣層230上進 一步沈積有一第二絕緣層240，該第二絕緣層240增加源 極221及汲極222鄰近通道區223之二端與閘極270間之 絕緣層厚度，增大電阻。故相對於一定閘極電壓，該閘極 270與源極221及汲極222之間之耦合電場較小，源極221 及汲極222鄰近通道區223兩端之電場亦較小，故漏電流 • 小，由漏電流所產生之不良影響降低，提高薄膜電晶體基 板200之可靠性。另外，由於該第二絕緣層240增加源極 221及汲極222二端與閘極270之間之絕緣層厚度，因此 當閘極電壓一定時，該通道區223鄰近該源極221及汲極 222二端之電場較小，故能改善該汲極222附近之碰撞游 離效應（impact ionization effect)，並降低薄膜電晶體基板 200發生浮體效應（floating body effect)之可能性，從而提 升薄膜電晶體基板200之可靠性。 • 請一併參閱圖4，其係圖3中薄膜電晶體基板200製 造方法之流程圖，其包括： 步驟S20 :提供一基板210，該基板210係不可繞之 透明玻璃基板。 步驟S21 ··於該基板210上依序沈積一矽薄膜220、 一第一絕緣層230、一第一金屬層250及一第一光阻層 251，請參閱圖5。 該石夕薄膜220為非晶石夕（Amorphous)，該第一絕緣層 230係二氧化矽，該第一金屬層250係銀。 1296444 步驟S22 ··提供一第一光罩，藉由該第一光罩對該第 一光阻層251進行曝光、顯影，從而形成一第一光阻圖案。 ，步驟S23 :蝕刻第一金屬層250，使其與第一光阻圖 案一致，請參閱圖6。 步驟S24 ·藉由液相沈積法於該第一絕緣層230上未 被第一光阻圖案覆蓋之區域沈積一第二絕緣層24〇，該第 二絕緣層240係含氟二氧化矽，其厚度小於第一金屬層 250。 曰 該液相沈積反應原理如下，於2〇°C至50°C之内，加入 足量二氧化矽至氫氟矽酸溶液中並攪拌至飽和，過濾未溶 解之二氧化矽，得到飽和氫氟矽酸，其反應方程式為， Η’6+2/ί2〇·^·〇2+6册。然後，如該反應方程式所示於該飽 和氫氟矽酸中加入水，改變反應進程，使得氫氟矽酸溶液 超飽和而析出二氧化矽，從而沈積出含氟二氧化矽薄膜。 由於第一光阻層251表面有斥水性，氫氟矽酸不會附著其 上進行反應’故第一光阻層251表面不會形成含氟二氧 矽薄膜，請參閱圖7。 步驟S25 ··去除第一光阻圖案。 ，步驟S26:於該第二絕緣層24〇及第一金屬層25〇上 一併依序沈積一第二金屬層26〇與一第二光阻層261，於 參閱圖8。 # 該第二金屬層260亦係銀，其與第一金屬 姆接觸，且厚度與該第一金屬層25〇之厚度一致。糸& 步驟S27 :提供-第二光罩，藉由該第二光罩對該第 二光阻層261進行曝光、顯影，從而形成一第二光阻圖案。 11 1296444 步驟S28 :蝕刻該第二金屬層260，使其與第二光阻 • 圖案一致，請參閱圖9。 \ 該第二金屬層260包覆第一金屬層250，並部份覆蓋 鄰近該第一金屬層250之第二絕緣層240,且該第一、二 金屬層250、260 —併構成閘極270。 步驟S29 :於該矽薄膜220二端佈植磷離子，以形成 一源極221及一汲極222，該源極221及汲極222之間具 一通道區223，請參閱圖10。 鲁步驟S210:去除第二光阻圖案，並藉由導線使得該薄 膜電晶體基板200之閘極270、源極221及汲極222分別 與外接引腳（圖未示）電性連接。 請參閱圖11，其係本發明薄膜電晶體基板第二實施方 式之結構示意圖。該薄膜電晶體基板300包括一基板310、 一矽薄膜320、一第一絕緣層330、一第二絕緣層340及一 閘極金屬層350。其中，該第一絕緣層330、矽薄膜320 及基板310依次層疊設置。該第二絕緣層340覆蓋部份第 • 一絕緣層330，並於該第一絕緣層330上形成一開口。該 閘極金屬層350嵌如該開口，並覆蓋第一絕緣層330且部 份覆蓋第二絕緣層340。另外，該矽薄膜320二端藉由佈 植鄰離子分別形成有一源極321及一汲極322，且該源極 321及汲極322間具一通道區323。 該薄膜電晶體基板300與薄膜電晶體200相似，其第 一絕緣層330上亦沈積有一第二絕緣層340，故該薄膜電 晶體基板300源極321及汲極322鄰近通道區323之二端 與閘極間之絕緣層厚度較厚。故相對於一定閘極電壓，該 12 1296444 閘極與源極321及汲極322之間之耦合電場較小，源極321 ^ 及汲極322鄰近通道區323兩端之電場亦較小，故漏電流 , 小’由漏電流所產生之不良影響降低’該薄膜電晶體基板 300之可靠性高。 請參閱圖12,其係本發明薄膜電晶體基板300製造方 法之流程圖，其包括： 步驟S30 :提供一基板310，該基板310係不可繞之 透明玻璃基板。 ⑩步驟S31 :於該基板310上依序沈積一矽薄膜320、 一第一絕緣層330及一第一光阻層341，請參閱圖13。 該矽薄膜320係非晶矽，該第一絕緣層330係二氧化 石夕。 步驟S32:提供一第一光罩，藉由該第一光罩對該第 一光阻層341進行曝光、顯影，從而形成一第一光阻圖案。 步驟S33 :藉由液相沈積法沈積第二絕緣層340於該 第一絕緣層330上未被第一光阻層341覆蓋之區域，請參 ⑩閱圖14。 該第二絕緣層340係含氟二氧化矽，其反應原理與本 發明薄膜電晶體基板200之第二絕緣層240形成之原理一 致。 步驟S34 :去除該第一光阻圖案，請參閱圖15。 步驟S35 :於該第二絕緣層340及該第一絕緣層330 上未被第二絕緣層340覆蓋之部份一併沈積一閘極金屬層 350及一第二光阻層351，請參閱圖16。 步驟S36:提供一第二光罩，藉由該第二光罩對該第 13 1296444 二光阻層351進行曝光、顯影，從而形成一第二光阻圖案。 ； 步驟S37 :蝕刻該閘極金屬層350，使其與第二光阻 鹹. ^ 圖案一致，請參閱圖17。 該閘極金屬層350覆蓋第一絕緣層330未被第二絕緣 層340覆蓋之部份且覆蓋部份第二絕緣層34〇。 步驟S38 :於該矽薄膜320二端佈植磷離子，以形成 一源極321及一汲極322。 步驟S39 :去除第二光阻圖案，並藉由導線使得該薄 馨膜電晶體基板之閘極、源極321及没極322分別與外接引 腳電性連接（圖未示），該矽薄膜320之源極321及汲極322 之間具一通道區323，該通道區323長度與該閘極金屬層 35〇之長度一致，請參閱圖18。 由於該薄膜電晶體基板於其第一絕緣層上進一步沈積 有一第二絕緣層，該第二絕緣層增加源極及汲極鄰近通道 區之二端與閘極間之絕緣層厚度，增大電阻。故相對於一 定閘極電壓，該閘極與源極及汲極之間之耦合電場較小， 源極及没極鄰近通道區兩端之電場亦較小，故漏電流小， 由漏電流所產生之不良影響降低，提高薄膜電晶體基板之 可靠性。 另外’該薄膜電晶體基板亦可為非透明或可繞性基 板。該矽薄膜可為多晶矽（P〇1y_crystalline Si)。該第一、二 金屬層亦可為銅、鉬、鋁及鉻或其合金，且二者之厚度及 材料均可相異。該第二絕緣層不限定於含氟二氧化矽，可 為其他絕緣物質，如氧化矽及有機絕緣物質。該含氟二氧 化矽亦可由矽酸與氫氟矽酸反應沈積所得。 1296444 k 綜上所述，本創作確已符合發明專利之要件，爰依法 ^ 提出申請專利。惟，以上所述者僅係本發明之較佳實施方 二式，本發明之範圍並不以上述實施方式為限，舉凡熟習本 案技藝之人士援依本發明之精神所作之等效修飾或變化， 皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係一種先前技術薄膜電晶體基板之結構示意圖。 圖2係圖1所示薄膜電晶體基板製造方法之流程圖。 參圖3係本發明薄膜電晶體基板第一實施方式之結構示意 . 圖。 圖4係圖3所示薄膜電晶體基板製造方法之流程圖。 圖5至圖10係圖4所示流程圖之各主要步驟之示意圖。 圖11係本發明薄膜電晶體基板第二實施方式之結構示意 圖。 圖12係圖11所示薄膜電晶體基板製造方法之流程圖。 圖13至圖18係圖12所示流程圖之各主要步驟之示意圖。 • 【主要元件符號說明】 薄膜電晶體基板 200 > 300 基板 210、310 矽薄膜 220 ^ 320 源極 221、321 汲極 222、322 通道區 223、323 第一絕緣層 230 > 330 第二絕緣層 240 > 340 第一金屬層 250 第一光阻層 251、341 第二金屬層 260 第二光阻層 26卜 351 閘極 270 閘極金屬層 350 15And a first photoresist layer; providing a first photomask, wherein the first photo-shield is inserted into the rod 瞌氺ms, the first photomask is: Developing, forming a -th-resist pattern; depositing in the region covered by the renewal - soil - second photoresist = photoresist pattern, the second insulating layer covering a portion of the -, and the edge layer, The first insulating layer is not deposited on the second insulating layer according to the cover layer of the Hit m layer and sequentially deposited on the deep germanium - the gate gold supply - the second photomask, by the second light: and - The first resistive layer, the k-light, the sensible smear, and the second photoresist layer are exposed to the second photoresist layer to engrave the inter-polar metal layer, so that compared with the prior art, Due to the second photoresist pattern. The phase of the electromorphic plate is further deposited on the edge layer of the first layer of the first layer of the first layer, the second insulating layer, the second insulating layer increases the insulating layer between the two ends of the source and the drain adjacent to the channel region and the gate. Thickness, increase. Resistance. Therefore, the electric field of the coupling between the gate and the source and the drain is relatively small with respect to a certain gate voltage, and the electric field at both ends of the source and the drain adjacent to the channel region is also small, so the leakage current is small, and the leakage current is The adverse effects are reduced and the reliability of the thin film transistor substrate is improved. [Embodiment] Please refer to Fig. 3, which is a schematic structural view of a first embodiment of a thin film transistor substrate of the present invention. The thin film transistor substrate 200 includes a substrate 210, a germanium film 220, a first insulating layer 230, a second insulating layer 240, a first metal layer 250, and a second metal layer 260. The first insulating layer 230, the tantalum film 220, and the substrate 210 are laminated in this order. The second insulating layer 240 covers a portion of the first insulating layer 230 and forms an opening on the first insulating layer 230. The first metal layer 250 is embedded in the opening and covers the first insulating layer 230. The second metal layer 260 covers the first metal layer 250 and a portion of the second insulating layer 240 adjacent to the first metal layer 250. In addition, the first metal layer 250 is in ohmic contact with the second metal layer 260 and together constitutes the gate 270. The two ends of the germanium film 220 are respectively formed with a source electrode 221 and a drain electrode 222. In addition, the gate 270, the source 221 and the drain 222 of the thin film transistor substrate 200 are electrically connected to external pins (not shown), and a channel region 223 is defined between the source 221 and the drain 222. The length of the channel region 223 coincides with the length of the second metal layer 260. When the thin film transistor substrate 200 is in operation, an external circuit applies a voltage to the gate 270, the source 221, and the drain 222 via a wire. The gate voltage on the gate 270 is transmitted through the insulating layer 230, and a channel is coupled to the surface of the channel region 223 9 1296444. The channel region is formed by the electrical-difference between the source electrode 221 and the drain electrode 222. A current is generated in 223. Since the thin film transistor substrate 200 further has a second insulating layer 240 deposited on the first insulating layer 230, the second insulating layer 240 increases the source 221 and the drain 222 adjacent to the two ends of the channel region 223 and the gate 270. The thickness of the insulating layer between them increases the resistance. Therefore, the electric field of coupling between the gate 270 and the source 221 and the drain 222 is small relative to a certain gate voltage, and the electric field between the source 221 and the drain 222 adjacent to the channel region 223 is also small, so leakage current • Small, the adverse effects caused by leakage current are reduced, and the reliability of the thin film transistor substrate 200 is improved. In addition, since the second insulating layer 240 increases the thickness of the insulating layer between the source 221 and the drain 222 and the gate 270, the channel region 223 is adjacent to the source 221 and the drain when the gate voltage is constant. The electric field at the second end of 222 is small, so that the impact ionization effect near the drain 222 can be improved, and the possibility of floating body effect of the thin film transistor substrate 200 is reduced, thereby improving the thin film electricity. The reliability of the crystal substrate 200. Please refer to FIG. 4, which is a flow chart of a method for manufacturing the thin film transistor substrate 200 of FIG. 3, which includes: Step S20: providing a substrate 210 which is a non-transparent transparent glass substrate. Step S21: A thin film 220, a first insulating layer 230, a first metal layer 250 and a first photoresist layer 251 are sequentially deposited on the substrate 210. Referring to FIG. The Shishi film 220 is amorphous, and the first insulating layer 230 is ruthenium dioxide, and the first metal layer 250 is silver. 1296444 Step S22: A first photomask is provided, and the first photoresist layer 251 is exposed and developed by the first photomask to form a first photoresist pattern. Step S23: etching the first metal layer 250 to be consistent with the first photoresist pattern, see FIG. Step S24. Depositing a second insulating layer 24 by a liquid deposition method on a region of the first insulating layer 230 that is not covered by the first photoresist pattern. The second insulating layer 240 is a fluorine-containing germanium dioxide. The thickness is smaller than the first metal layer 250.原理 The principle of the liquid deposition reaction is as follows: within a range of 2 ° C to 50 ° C, a sufficient amount of cerium oxide is added to the hydrofluoric acid solution and stirred to saturation, and the undissolved cerium oxide is filtered to obtain saturated hydrogen. Fluorine acid, the reaction equation is Η'6+2/ί2〇·^·〇2+6. Then, water is added to the saturated hydrofluoric acid as shown in the reaction equation to change the progress of the reaction, so that the hydrofluoric acid solution is supersaturated to precipitate cerium oxide, thereby depositing a fluorine-containing cerium oxide film. Since the surface of the first photoresist layer 251 is water repellent, hydrofluoric acid does not adhere to the reaction, so that the surface of the first photoresist layer 251 does not form a fluorine-containing dioxane film, see Fig. 7. Step S25 · removing the first photoresist pattern. Step S26: sequentially depositing a second metal layer 26 and a second photoresist layer 261 on the second insulating layer 24 and the first metal layer 25, as shown in FIG. # The second metal layer 260 is also silver, which is in contact with the first metal and has a thickness that is consistent with the thickness of the first metal layer 25A.糸 & Step S27: providing a second photomask by exposing and developing the second photoresist layer 261 to form a second photoresist pattern. 11 1296444 Step S28: Etching the second metal layer 260 to conform to the second photoresist pattern, see FIG. The second metal layer 260 covers the first metal layer 250 and partially covers the second insulating layer 240 adjacent to the first metal layer 250, and the first and second metal layers 250, 260 - and constitute the gate 270 . Step S29: Phosphorus ions are implanted at the two ends of the tantalum film 220 to form a source electrode 221 and a drain electrode 222. The source electrode 221 and the drain electrode 222 have a channel region 223. See FIG. Step S210: removing the second photoresist pattern, and electrically connecting the gate 270, the source 221 and the drain 222 of the thin film transistor substrate 200 to external pins (not shown) by wires. Referring to Fig. 11, there is shown a schematic structural view of a second embodiment of the thin film transistor substrate of the present invention. The thin film transistor substrate 300 includes a substrate 310, a germanium film 320, a first insulating layer 330, a second insulating layer 340, and a gate metal layer 350. The first insulating layer 330, the tantalum film 320, and the substrate 310 are stacked in this order. The second insulating layer 340 covers a portion of the first insulating layer 330 and forms an opening on the first insulating layer 330. The gate metal layer 350 is embedded in the opening and covers the first insulating layer 330 and partially covers the second insulating layer 340. In addition, a drain electrode 321 and a drain 322 are formed on the two ends of the germanium film 320 by a neighboring ion, and a channel region 323 is defined between the source electrode 321 and the drain electrode 322. The thin film transistor substrate 300 is similar to the thin film transistor 200, and a second insulating layer 340 is also deposited on the first insulating layer 330. Therefore, the source 321 and the drain 322 of the thin film transistor substrate 300 are adjacent to the two ends of the channel region 323. The thickness of the insulating layer between the gate and the gate is thick. Therefore, the coupling electric field between the gate of the 12 1296444 gate and the source 321 and the drain 322 is small relative to a certain gate voltage, and the electric field between the source 321 ^ and the drain 322 adjacent to the channel region 323 is also small, so Leakage current, small 'degraded adverse effect due to leakage current' The reliability of the thin film transistor substrate 300 is high. Referring to FIG. 12, which is a flow chart of a method for fabricating a thin film transistor substrate 300 of the present invention, the method includes the following steps: Step S30: providing a substrate 310 which is a non-transparent transparent glass substrate. 10 Step S31: A germanium film 320, a first insulating layer 330 and a first photoresist layer 341 are sequentially deposited on the substrate 310. Please refer to FIG. The tantalum film 320 is amorphous, and the first insulating layer 330 is made of silica. Step S32: providing a first mask, and exposing and developing the first photoresist layer 341 by the first mask to form a first photoresist pattern. Step S33: depositing a second insulating layer 340 on the first insulating layer 330 by a liquid deposition method, which is not covered by the first photoresist layer 341, please refer to FIG. The second insulating layer 340 is a fluorine-containing cerium oxide, and the principle of the reaction is the same as that of the second insulating layer 240 of the thin film transistor substrate 200 of the present invention. Step S34: Removing the first photoresist pattern, please refer to FIG. Step S35: depositing a gate metal layer 350 and a second photoresist layer 351 on the second insulating layer 340 and the portion of the first insulating layer 330 that is not covered by the second insulating layer 340. 16. Step S36: providing a second mask, and exposing and developing the 13th 296444 second photoresist layer 351 by the second mask to form a second photoresist pattern. Step S37: etching the gate metal layer 350 to be consistent with the second photoresist salt. ^ pattern, see FIG. The gate metal layer 350 covers a portion of the first insulating layer 330 that is not covered by the second insulating layer 340 and covers a portion of the second insulating layer 34A. Step S38: Phosphorus ions are implanted at the two ends of the tantalum film 320 to form a source 321 and a drain 322. Step S39: removing the second photoresist pattern, and electrically connecting the gate, the source 321 and the gate 322 of the thin film transistor substrate to the external pins by wires (not shown), the germanium film A source region 323 is defined between the source 321 and the drain 322 of 320. The length of the channel region 323 is the same as the length of the gate metal layer 35, as shown in FIG. Since the thin film transistor substrate further deposits a second insulating layer on the first insulating layer, the second insulating layer increases the thickness of the insulating layer between the two ends of the source and the drain adjacent to the channel region and the gate, and increases the resistance. . Therefore, the coupling electric field between the gate and the source and the drain is small relative to a certain gate voltage, and the electric field at both ends of the source and the immersion adjacent to the channel region is also small, so the leakage current is small, and the leakage current is The adverse effects are reduced and the reliability of the thin film transistor substrate is improved. Further, the thin film transistor substrate may be a non-transparent or recyclable substrate. The tantalum film may be polycrystalline germanium (P〇1y_crystalline Si). The first and second metal layers may also be copper, molybdenum, aluminum, and chromium or alloys thereof, and the thickness and material of the two may be different. The second insulating layer is not limited to fluorine-containing cerium oxide, and may be other insulating materials such as cerium oxide and organic insulating materials. The fluorine-containing cerium oxide can also be obtained by reacting citric acid with hydrofluorodecanoic acid. 1296444 k In summary, this creation has indeed met the requirements of the invention patent, and has applied for a patent in accordance with the law. However, the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make equivalent modifications or changes in accordance with the spirit of the present invention. , should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a prior art thin film transistor substrate. 2 is a flow chart showing a method of manufacturing the thin film transistor substrate shown in FIG. 1. Fig. 3 is a schematic view showing the structure of a first embodiment of the thin film transistor substrate of the present invention. 4 is a flow chart showing a method of manufacturing the thin film transistor substrate shown in FIG. 5 to 10 are schematic views of the main steps of the flow chart shown in FIG. Figure 11 is a schematic view showing the structure of a second embodiment of the thin film transistor substrate of the present invention. 12 is a flow chart showing a method of manufacturing the thin film transistor substrate shown in FIG. 13 to 18 are schematic views of the main steps of the flow chart shown in FIG. • [Major component symbol description] Thin film transistor substrate 200 > 300 substrate 210, 310 矽 film 220 ^ 320 source 221, 321 drain 222, 322 channel region 223, 323 first insulating layer 230 > 330 second insulation Layer 240 > 340 First Metal Layer 250 First Photoresist Layer 251, 341 Second Metal Layer 260 Second Photoresist Layer 26 351 Gate 270 Gate Metal Layer 350 15