l2955l〇 ^、發明說明： 【發明所屬之技術領域】 饮、、，本發明係有關一種薄膜電晶體陣列基板，更特別為有 肖除晝素電極區域微粒殘餘之薄膜電晶體陣列及其製 程方法。 【先前技術】The invention relates to a thin film transistor array substrate, and more particularly to a thin film transistor array having a microparticle residue in a ruthenium electrode region and a process method thereof . [Prior Art]
溥膜電晶體液晶顯示器（TFT LCD)相較於扭轉向列 _ (TN)、超扭轉向列（STN)等液晶顯示器(lcd)，因tFTLCD 為主動式矩陣（Active Matrix)驅動，所以具有省電、晝質 ^響應速度快專優點，故逐漸成為液晶顯示器中的主 流。其中，該主動式矩陣驅動技術又以非晶矽薄膜電晶體 、 元件（a-SiTFT)為主流。 非晶矽薄膜電晶體之構造以閘極電極在上層或間極 電極在下層來區分，其中每種構造又依每層結構而有交錯 型（staggered)構造和同平面型（coplanar)構造，分別為（a) 鲁 同平面結構、（b)逆同平面（inverted coplanar)結構、（c)交錯 型結構、⑷逆交錯型（inverted staggered)結構。每種結構 都有其應用與設計，然而，其中逆交錯型結構則廣泛地被 '非晶石夕TFT製造業者所採用。以下相關製程及設計說明， 皆以逆交錯型結構為說明例。 4膜電晶體陣列基板製程，主要依電路設計需求，將 不同性質的薄膜材料反覆進行薄膜沉積、黃光、蝕刻等， 完成LCD的下玻璃基板，再配合另一片上面有彩色濾光片 • 的上玻璃’將兩片玻璃間進行液晶的注入，藉此完成該 1295510 LCD面板。再將該TFT LCD面板貼附偏光片、裝上驅動 1C及黾路板和背光源，再進行機殼模組組裝及包裝^" 完成成品。 、程始 薄膜電晶體之製程包括：首先以薄膜製程將破噂表面 鍍上一層金屬後，接著利用黃光及蝕刻製程形成薄膜電晶 體之閘極，隨後再以連續化學氣相沉積（chemical Deposition ; CVD)以形成保護閘極區域之矽化合物、主動 區域之非晶石夕（a_Si)、η型非晶石夕(n+a_si)。接著利用黃光 及蝕刻製程分別形成絕緣層、非晶矽層及毆姆接觸層，其 中戎絕緣層為矽化合物如氧化矽、氮化矽等。隨後再利用 薄膜製程以濺鍍鍍上一層金屬後，接著利用黃光及蝕刻製 私形成薄膜電晶體之源極及汲極，然後再進行蝕刻以定義 薄膜電晶體的後通道，隨後再以化學氣相沉積形成薄膜電 晶體之保護層，並形成-接觸孔，最後再以薄膜製程賤艘 上一層氡化銦錫（indium tin oxide ;汀0)層後，接著利用普 光及姓刻製程形成薄膜電晶體晝素電極。 其中製作主動區域之非晶矽層過程中，容易產生a_si 微粒殘餘(panicle residue)於晝素電極區域，而t亥微粒殘餘 是-般_電晶體㈣陷之-。也由於此製程所產生的 a-Si微粒殘餘比一般的微粒殘餘較難以測試，特別是當 a-Si微粒殘餘發生的位置在晝素電極區域時，哕 將與晝素電極將產生弱電容偶合效岸，降 汉餘 认由方 又應|牛低忒缚膜電晶體 的艮竿。 【發明内容】 1295510 麦是，本發明之主要目的係在一般的薄膜電晶體 中’在不改變製程的情況下，可以有效的消除薄膜電晶體 =列基板中晝素電極下的㈣微粒殘餘，提高薄膜電晶# 陣列基板的良率，並且降低在晝素電極區域的絕緣丑 度，增加該區域的穿透度。 日子 本發明係-薄膜電晶體結構及其製释方法，針對 非晶石夕之薄膜電晶體矩陣玻璃基板及其製程，可有效消除 • 非晶矽微粒殘餘。對於該薄膜電晶體之製程，首先以薄膜 製程將玻璃表面鑛上-層金屬後，利用黃光及餘刻製程形 成薄膜電晶體之閘極，隨後再以連續化學氣相沉積以形成 •保護閘極區域之石夕化合物、主動區域之养晶石夕㈣心㈣ :非晶石夕(n+a-Si)，接著利用黃光及餘刻製程分別形成絕緣 層、非晶梦層及殿姆接觸層，其中該絕緣層為石夕化合物如 氧化矽、氮化矽等。隨後再利用薄膜製稃以濺鍍鍍上一層 金屬後，接著利用黃光及姓刻製程形成薄膜電晶體之源極 鲁及及極區域的圖樣，然後再進行姓刻以定義薄膜電晶體的 後通迢，隨後再以化學氣相沉積形成薄膜電晶體之保護 層0 然後透過一光罩定義該保護層表面上之光阻層厚 度，該薄光阻層係藉由該光罩之複數個町透光之狹缝，利 用狹縫光罩的光學繞射原理來控制曝光量，可控制該光阻 層經顯影後在該保護層表面上不同厚度，使陣列基板中該 晝素電極區域上之光阻層較未顯影區度薄。 人 隨後進⑽刻製程，藉由光阻層不同的厚度，達到選 1295510 擇性蝕刻的效果。沒有光阻層覆蓋的區域將直接蝕刻到金 屬層，而薄光阻的畫素電極區域則在光阻層被蝕刻後，繼 續蝕刻該保護層，最後蝕刻該絕緣層，使該區域之絕緣層 形成一第一絕緣層，該第一絕緣層之厚度較該絕緣層之厚 度薄，此時該絕緣層上有非晶矽微粒殘餘也將於此蝕刻製 程階段被一併蝕刻完全。最後再以薄膜製程濺鍍上一層金 屬氧化物，接著利用黃光及蝕刻製程形成晝素區域之圖 樣，完成該薄膜電晶體陣列基板。 【實施方式】 茲有關本發明之詳細内容及技術說明，現配合圖式說 明如下： 本發明係針對一薄膜電晶體陣列基板及其製程方 法，可有效消除薄膜電晶體陣列基板之非晶矽微粒殘餘。 以應用於逆交錯型結構為例，本發明之薄膜電晶體陣列基 板及製程方法說明如下： (a) 請參閱「第1圖」，先於一基板11表面上沈積一 第一金屬層，並接著利用黃光/及餘刻製程形成該第一金屬 層之圖樣，其中該第一金屬層圖樣包含有電晶體之閘極電 極121、儲存電容之下電極122及一連接墊之墊電極123。 (b) 請參閱「第2圖」，隨後再以化學氣相沉積於該基 板11上依序連續成膜一矽化合物之絕緣層13卜電晶體之 主動層區域30之一非晶矽層132,及一 η型非晶矽（n+a-Si) 所形成之歐姆接觸層133，並利用黃光及蝕刻製程形成該 主動層區域3 0之圖樣。其中該絕緣層為石夕化合物如氧化 1295510 矽、氮化矽等。 =參閱「第3圖」’再以_沈積一第二全屬芦 之先及蝕刻製程形成該形成該第二金屬展二 之圖樣。其中該第二金屬層14 蜀層14 極及綱極’及健存電容之上電極及 利用金屬層14之圖樣 、 形成該電晶體之後通道。 ^以+導體膜’ (d)凊簽閱「第4圖」，於 合物形成-保護層15。2王面沈積石夕化 化石夕、氮切等。线相Μ為魏合物如氧 ⑷請參閱「第5圖」，再於該基板u上全 二了’經曝光顯影後，使該晝素 上:： 域之光阻層薄，形成一薄光阻層： 囷」所不）。請參閱「第1〇圖」，係本發 =上複數個可透光之狹縫211，利用該狹縫211形成— 此可、y(=mask)’利用光學繞射原理來控制曝光量，如 區域I ϋ區域曝出不同厚度的光阻，控制該晝素電極 Γ 5 錢阻層41之厚度。喊薄光阻層41之厚度 文控於後續製程該絕緣層之保留厚度。 又 节光罩第金11圖」’本發明之另一光罩型態之示意圖。 二W之旦素電極㊣21亦可是一灰階圖案212，利用 ΓΓΙ白火階程度控制曝光量，使該晝素電極區域31之 層40成為薄光阻層4卜而該光罩20上之接觸孔區域 1295510 22與連接墊開孔 及連接墊電極123 ^出該儲存1容之接觸孔32， <接觸窗33。 ⑴請參閱「第7 製程，對無光阻層區域A liquid crystal display (TFT LCD) is a liquid crystal display (lcd) such as a twisted nematic (TN) or a super twisted nematic (STN). Since the tFTLCD is an active matrix (Active Matrix), it has a province. The advantages of electric and enamel ^ fast response speed have gradually become the mainstream in liquid crystal displays. Among them, the active matrix driving technology is dominated by amorphous germanium thin film transistors and components (a-SiTFT). The structure of the amorphous germanium film transistor is distinguished by the gate electrode being in the upper layer or the interpole electrode in the lower layer, wherein each structure has a staggered structure and a coplanar structure according to each layer structure, respectively. It is (a) a plane structure, (b) an inverted coplanar structure, (c) a staggered structure, and (4) an inverted staggered structure. Each structure has its application and design, however, the inverse staggered structure is widely adopted by the 'Amorphous 夕 TFT manufacturers. The following related processes and design specifications are all illustrated by an inverse staggered structure. 4 film transistor array substrate process, mainly according to the circuit design requirements, the film material of different properties is repeatedly deposited by thin film deposition, yellow light, etching, etc., complete the lower glass substrate of the LCD, and then match the color filter on the other piece. The upper glass 'inserts the liquid crystal between the two sheets of glass to complete the 1295510 LCD panel. Then attach the TFT LCD panel to the polarizer, install the driver 1C and the circuit board and the backlight, and then assemble and package the chassis module ^" to complete the finished product. The process of the film-forming film transistor includes: firstly plating a surface of the broken surface with a thin film process, and then forming a gate of the thin film transistor by using a yellow light and an etching process, followed by continuous chemical vapor deposition (chemical Deposition) CVD) to form a germanium compound that protects the gate region, amorphous austenite (a_Si), and n-type amorphous rock (n+a_si) in the active region. Then, an insulating layer, an amorphous germanium layer and a ohmic contact layer are respectively formed by using a yellow light and an etching process, wherein the germanium insulating layer is a germanium compound such as hafnium oxide or tantalum nitride. Subsequently, a thin film process is used to deposit a layer of metal by sputtering, and then the source and the drain of the thin film transistor are formed by using yellow light and etching, and then etching is performed to define a back channel of the thin film transistor, followed by chemistry. Vapor deposition to form a protective layer of the thin film transistor, and forming a contact hole, and finally depositing a layer of indium tin oxide (Ting 0) on the film process, and then forming a film by using a Puguang and surname process Electrode halogen electrode. In the process of fabricating the amorphous germanium layer in the active region, it is easy to generate a_si particle residue in the halogen electrode region, and the t-ray particle residue is--the transistor (four) trapped. Also, the a-Si particle residue generated by this process is more difficult to test than the general particle residue, especially when the a-Si particle residue occurs in the halogen electrode region, the germanium electrode and the halogen electrode will have a weak capacitance coupling. The effect of the shore, the reduction of the Han Yu recognized by the party should also | SUMMARY OF THE INVENTION 1295510 Mai is, the main purpose of the present invention is to effectively eliminate the (four) particle residue under the halogen electrode in the thin film transistor = column substrate in a general thin film transistor. Increasing the yield of the thin film electro-crystal array substrate, and reducing the insulation ugliness in the pixel region, increasing the transmittance of the region. The invention is a thin film transistor structure and a method for preparing the same, and can effectively eliminate the residual of amorphous germanium particles for the amorphous thin crystal transistor matrix glass substrate and the manufacturing process thereof. For the process of the thin film transistor, the surface of the glass is firstly deposited with a metal film by a thin film process, and the gate of the thin film transistor is formed by a yellow light and a remnant process, followed by continuous chemical vapor deposition to form a protective gate. The stone compound of the polar region, the spargite of the active region (four) heart (four): amorphous stone eve (n+a-Si), and then the yellow layer and the remaining process are used to form the insulating layer, the amorphous layer and the temple. a contact layer, wherein the insulating layer is a compound such as cerium oxide, tantalum nitride or the like. Subsequently, a thin layer of metal is sputter-coated with a thin film, and then a pattern of the source and the polar region of the thin film transistor is formed by using a yellow light and a process of engraving, and then the pattern is defined to define the thin film transistor. Afterwards, the protective layer 0 of the thin film transistor is formed by chemical vapor deposition, and then the thickness of the photoresist layer on the surface of the protective layer is defined by a mask, and the thin photoresist layer is transparent to the plurality of passes of the mask. The slit is controlled by the optical diffraction principle of the slit mask to control the thickness of the photoresist layer on the surface of the protective layer after being developed, so that the photoresist on the surface of the halogen electrode in the array substrate The layer is thinner than the undeveloped area. The person then enters the (10) engraving process to achieve the selective etching effect of 1295510 by the different thickness of the photoresist layer. The region not covered by the photoresist layer will be directly etched to the metal layer, and the photoresist region of the thin photoresist is further etched after the photoresist layer is etched, and finally the insulating layer is etched to form an insulating layer of the region. The first insulating layer has a thickness thinner than the thickness of the insulating layer. At this time, the residual amorphous germanium particles on the insulating layer are also completely etched at the etching process. Finally, a metal oxide is sputtered on the thin film process, and then the thin film transistor array substrate is completed by using a yellow light and an etching process to form a pattern of the halogen region. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The detailed description and technical description of the present invention will now be described as follows: The present invention is directed to a thin film transistor array substrate and a method for fabricating the same, which can effectively eliminate amorphous germanium particles of a thin film transistor array substrate. Residual. Taking the reverse staggered structure as an example, the thin film transistor array substrate and the manufacturing method of the present invention are described as follows: (a) Referring to FIG. 1 , a first metal layer is deposited on the surface of a substrate 11 and Then, the first metal layer pattern is formed by using a yellow light/and a photoresist process, wherein the first metal layer pattern includes a gate electrode 121 of the transistor, a lower electrode 122 of the storage capacitor, and a pad electrode 123 connected to the pad. (b) Please refer to "Fig. 2", followed by chemical vapor deposition on the substrate 11 to sequentially form an insulating layer 13 of a compound, and an amorphous layer 132 of the active layer region 30 of the transistor. And an ohmic contact layer 133 formed of an n-type amorphous germanium (n+a-Si), and the pattern of the active layer region 30 is formed by a yellow light and an etching process. The insulating layer is a compound such as oxidized 1295510 lanthanum, tantalum nitride or the like. = Refer to "Fig. 3" and then form a pattern of the second metal exhibit 2 by depositing a second all-around reed and etching process. The second metal layer 14 has a 14-pole and a drain electrode and a drain capacitor upper electrode and a pattern of the metal layer 14 to form a channel after the transistor. ^ "Fig. 4" is signed with the + conductor film '(d) ,, and the composition is formed into a protective layer 15. 2 The king's surface is deposited with a scorpion, a fossil, and a nitrogen cut. The phase phase is Wei compound such as oxygen (4), please refer to "Fig. 5", and then on the substrate u, after the exposure and development, the halogen layer on the surface is: thin, forming a thin photoresist Layer: 囷" is not). Please refer to the "1st drawing", which is a plurality of slits 211 which can be transmitted through the slit 211, and the y (=mask)' is used to control the exposure amount by using the optical diffraction principle. If the photoresist of different thickness is exposed in the region I ϋ, the thickness of the germanium electrode Γ 5 money resist layer 41 is controlled. Shrinking the thickness of the thin photoresist layer 41 The thickness of the insulating layer remaining in the subsequent process is controlled. A further reticle pattern of the present invention. The second W-electrode positive electrode 21 may also be a gray-scale pattern 212. The exposure amount is controlled by the degree of white-hotness, so that the layer 40 of the halogen electrode region 31 becomes the thin photoresist layer 4 and the contact hole region 1295510 on the photomask 20 22, the connection pad opening and the connection pad electrode 123 are out of the storage contact hole 32, <contact window 33. (1) Please refer to "7th process, for areas without photoresist layer
被姓刻，且外露該處之第—^^處之保護層15已 123之接觸窗33處之伴;:= 層14，且該連接墊電極 第-金屬層U。第^曰15亦被钱刻’且外露該處之 使該晝素電極區⑽夕彳^階段勘㈤薄光阻層41， /上區域31之保護層15外露。 之保護層15 H皮刻階段’此階段該晝素電極區域31 為選㈣Μ 且過料至該絕緣層131。此時因 全屬Γ，該接觸孔32與接觸窗33處因為已接觸到 ^所以將不再被繼續蝕刻。藉此，本步^ 程完成後’可除去該畫素電極區域31之保護It is engraved by the surname, and the protective layer 15 at the first place is exposed to the contact at the contact window 33 of 123; := layer 14, and the connection pad electrode is the metal layer U. The first layer 15 is also engraved and exposed to expose the protective layer 15 of the thin electrode layer 41, the upper photoresist layer 41, and the upper photoresist layer. The protective layer 15 H is in the etch stage. At this stage, the halogen electrode region 31 is selected (4) and passed to the insulating layer 131. At this time, since the contact hole 32 and the contact window 33 are already in contact with each other, the contact hole 32 and the contact window 33 are no longer etched. Thereby, after the step is completed, the protection of the pixel electrode region 31 can be removed.
又：會肩除該區域的絕緣層131，同時該絕緣層^ J 為所產生的心微粒殘餘也將被一併钱刻去除，如 弟 」所示，使该晝素電極區域31之絕緣層131來 成一第一絕緣層1311，且該第一絕緣層1311之厚度較該 絕緣層131之厚度薄。 人 (h)再瘛鍍沈積一金屬氧化物層16 ，如「第9圖」所 示。其中該金屬氧化物層16的材質係選自銦錫氧化物 (ITO)、銦鋅氧化物（ίζ〇)及鋁鋅氧化物（AZO )至少其中之 一。並接著利用黃光及蝕刻製程形成該金屬氡化物層16 之圖案。其中該金屬氧化物層16於該畫素電極區域31形 1295510 成晝素電極，也透過該接觸孔32與接觸窗33分別與該儲 存電容之上電極及連接墊電極123電性連接，完成該薄膜 電晶體陣列基板。 所以’本發明在一般的a-Si薄艇電晶體製程中，在不 改變製程的情況下，可以有效的消除a-Si薄膜電晶體陣列 基板中畫素電極下的a-Si微粒殘餘，解決該a-Si微粒與畫 素電極產生弱電容偶合效應之情形，提高薄膜電晶體陣列 基板的良率。 且該薄膜電晶體陣列基板中，該晝素電極區域31之 絕緣層131厚度變薄形成該第一絕緣層1311，且該晝素電 極區域31無該保護層15，所以可以增加該畫素電極區域 31的穿透度。 惟上述僅為本發明之較佳實施例而已，並非用來限定 本發明實施之範圍。即凡依本發明申請專利範圍所做的均 等變化與修飾，皆為本發明專利範圍所涵蓋。 ί29551〇Moreover, the insulating layer 131 of the region will be removed, and the residual of the core particles generated by the insulating layer will be removed together, as shown by the younger one, so that the insulating layer of the halogen electrode region 31 is provided. 131 is formed into a first insulating layer 1311, and the thickness of the first insulating layer 1311 is thinner than the thickness of the insulating layer 131. The person (h) is further deposited with a metal oxide layer 16 as shown in Fig. 9. The material of the metal oxide layer 16 is selected from at least one of indium tin oxide (ITO), indium zinc oxide (Å3), and aluminum zinc oxide (AZO). A pattern of the metal halide layer 16 is then formed using a yellow light and an etch process. The metal oxide layer 16 is electrically connected to the storage capacitor upper electrode and the connection pad electrode 123 through the contact hole 32 and the contact window 33, respectively. Thin film transistor array substrate. Therefore, the present invention can effectively eliminate the residual of a-Si particles under the pixel electrode in the a-Si thin film transistor array substrate in the general a-Si thin boat transistor process without changing the process. The a-Si microparticle and the pixel electrode produce a weak capacitive coupling effect, which improves the yield of the thin film transistor array substrate. In the thin film transistor array substrate, the thickness of the insulating layer 131 of the halogen electrode region 31 is thinned to form the first insulating layer 1311, and the halogen electrode region 31 does not have the protective layer 15, so the pixel electrode can be increased. The penetration of the area 31. The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. That is, the equivalent changes and modifications made by the scope of the patent application of the present invention are covered by the scope of the invention. 2929551〇
1 I 【圖式簡單說明】 =圖’係本發明基板上形成該第 — :2圖，係本發明形成電晶體主動；:層^ J 3圖，係本發明形成該第二金屬；忿 第5m ^積保護層之示意圖。 圖，係於保護層上塗佈光阻 =圖，，係該光阻層被定義後之示意圖：圖。 Θ係本發明蝕刻該保護層之示音圖 口 ::系本，至該絕緣層之;意固圖。 咖°係本發明形成金屬氧化物圖安之-立闽 =圖’係本發明之光罩型態之示：圖7』。 【主要元件符號說明】先罩型怨之不意圖。 11 :基板 =閘極電極 122:下電極 U3 :墊電極 13ι :絕緣層 1311 ·第一絕緣層 132 ·非晶秒層 133 :歐姆接觸層 14 ·第二金屬層 15 :保護層 16 :金屬氧化物 20 ··光罩 21 :晝素電極區 12 1295510 211 :狹缝 212 :灰階圖案 30 :主動層區域 31 ·晝素電極區域 40 :光阻層 41 :薄光阻層1 I [Simple description of the drawing] = Figure ' is formed on the substrate of the present invention, the first: 2, which is the active form of the present invention; the layer J J 3 is formed by the present invention; Schematic diagram of the 5m ^ product protective layer. Figure, is the coating photoresist on the protective layer = map, is the schematic diagram after the photoresist layer is defined: Figure. The present invention etches the sound-receiving layer of the protective layer: the system, to the insulating layer; The invention forms a metal oxide in the form of a metal oxide. The figure is shown in Fig. 7. [Main component symbol description] The first cover type is not intended. 11 : substrate = gate electrode 122 : lower electrode U3 : pad electrode 13 1 : insulating layer 1311 · first insulating layer 132 · amorphous second layer 133 : ohmic contact layer 14 · second metal layer 15 : protective layer 16 : metal oxide Matte 20 · Photomask 21 : Alizarin electrode region 12 1295510 211 : Slit 212 : Gray scale pattern 30 : Active layer region 31 · Alizarin electrode region 40 : Photoresist layer 41 : Thin photoresist layer