TWI294141B - Method for detecting semiconductor manufacturing conditions - Google Patents

Method for detecting semiconductor manufacturing conditions Download PDF

Info

Publication number
TWI294141B
TWI294141B TW95109327A TW95109327A TWI294141B TW I294141 B TWI294141 B TW I294141B TW 95109327 A TW95109327 A TW 95109327A TW 95109327 A TW95109327 A TW 95109327A TW I294141 B TWI294141 B TW I294141B
Authority
TW
Taiwan
Prior art keywords
wafer
regions
graphics
critical dimension
pattern
Prior art date
Application number
TW95109327A
Other languages
Chinese (zh)
Other versions
TW200737295A (en
Inventor
Wen-Zhan Zhou
Jin Yu
Kai-Hung Alex See
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW95109327A priority Critical patent/TWI294141B/en
Publication of TW200737295A publication Critical patent/TW200737295A/en
Application granted granted Critical
Publication of TWI294141B publication Critical patent/TWI294141B/en

Links

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Description

1294141 * f 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種判斷半導體製程參數的方法,尤指一種 藉由散射臨界尺寸量測法來判斷晶圓曝光時之各製程參數 的設定值的方法。 【先前技術】 隨著半導體製程技術的進步,先進微影技術已使得線寬尺 寸突破至100奈米以下的半導體元件量產。然而當半導體元件的 尺寸不斷的縮小,例如以場效電晶體而言,其通道長度、 接面深度和閘極隔離層厚度等關鍵尺寸(critical dimension) 都會隨製程而縮小;而這些關鍵尺寸在半導體製造過程中 必須精確的控制,因為這些關鍵尺寸的些微變化,將可能 造成整個半導體元件的特性改變許多。因此,未來先進製程 裡關鍵尺寸的量測更加重要,快速且高重覆性的量測方法將會大 篁用於製程線上檢測,而量測的準確性將直接影響產品元件的良 率和可靠性。1294141 * f IX. Description of the Invention: [Technical Field] The present invention relates to a method for determining semiconductor process parameters, and more particularly to a method for determining process parameters during wafer exposure by scattering critical dimension measurement The method of setting the value. [Prior Art] With advances in semiconductor process technology, advanced lithography technology has enabled mass production of semiconductor components with line widths down to 100 nm. However, as the size of semiconductor components continues to shrink, for example, in field-effect transistors, critical dimensions such as channel length, junction depth, and gate isolation thickness are reduced with the process; these critical dimensions are Precise control must be made in the semiconductor manufacturing process, as slight changes in these critical dimensions will likely result in many changes in the properties of the entire semiconductor component. Therefore, the measurement of critical dimensions in advanced processes is more important in the future. Fast and highly repetitive measurement methods will be used for process line inspection, and the accuracy of measurement will directly affect the yield and reliability of product components. Sex.

近幾年在半導體製程控制具有潛力的檢測技術包括先進亮場 顯微術(Bright_field Microscopy),掃描式電子顯微術(SEMDetection techniques that have potential in semiconductor process control in recent years include advanced bright field microscopy (Bright_field Microscopy), scanning electron microscopy (SEM)

Scanning Electron Microscopy),散射術(Scatterometry),及原子力 顯微術(Atomic Force Microscopy,AFM)等。其中散射儀技術不管 在關鍵尺寸量測或者輪廓解析的應用上都獲致快速的進步。這項 6 1294141 技術還可以提供其域觸無法提供的魏,除了線寬的關鍵尺 寸里測之外’這項技術也能提供間^_h)、側則度(恤福 angles)、高度、以及底層薄臈厚度等結構細節。因此近來光學關 鍵尺寸制已經麵胁光料製造,肋提供_尺寸量測與 稷雜輪廓分析的方法。在光罩製造過程情由光學方法測定重要 關鍵尺忖的優點在於:對光阻不具破壞性,且可以量測小至約奶 奈米的光娜構_财,此核設時之廠務端賴需求低。 散射儀的量測原理是光束入射於等距式細㈣咖gratings), 其散射光的亮度(Intensity)P4縣人射肖度變化紐長變化而被記 錄為不同的特性圖譜(Sig她re) ’即亮度對角度或波長變化圖 (Reflectance vs.angle/wavelength) 〇 伤’包含正向量測和逆向分析。正向量測是指散射儀硬體量測雷 射光被周雛細散射的圖譜,而逆向分析是指㈣論建立的模 型軟體對®譜的分析輯以提供制結構紐據。逆向分析比對 部份通常有有兩種方法’第-種是时料庫比對法,係以一繞射 理論建立的資料庫,當實驗量爾到-散射數據,即把它與資料 庫的數據進行比對’找丨最接近的模S數據。此模^數據所代表 的結構參料為散射鑛測得的結構參數。第二種是用迴歸分析 法’係將由散射儀機台量測出的散射圖譜資料與及時輸入結構參 數所計算出的理論圖譜以最佳化搜尋演算法即時進行曲線比對, 根據昼測圖邊與理論推异圖譜之間的差異再逐次修改輸入的結 構參數直到差異降至允許範圍内。 1294141 :、、i而,在先如技術中,僅以控制曝光能量來調整光阻圖案上的 關鍵尺寸’而分析聚録製程巾對_尺寸所造成的影響。而其 •中的炎數,例如曝光後烘烤溫度和曝光能量所造成的照亮 狀況等因素,所造成的影響則難以從中區隔。 【發明内容】 。判斷半導體曝光條件的方法,包含有提供一具有複數個 圖形區之鮮,各該圖形區具錢數個線條,該複數個圖 形區之線條間距係為相異;依據複數組設定值相異的製程 參數經由該光罩對複數個晶圓曝光,以於各該晶圓上形成 複數個線條間距相異之圖形區;量測各該晶圓上之各個圖 形區的一臨界尺寸;建立該複數個晶圓上之複數個圖形區 的線條間距與相職之複數舰界尺相複數組對應關 係各該晶圓上之複數個圖形區的線條間距與相對應之複 數個臨界尺寸係建立有一組對應關係;經由該光罩對一預 測晶圓曝光,以於該預測晶圓上形成複數個線條間距相異 之圖形區;量測該預測晶圓上的各該圖形區的一臨界尺 寸,建立該預測晶圓上的該複數個圖形區的線條間距與相 對應之複數個臨界尺寸的一組對應關係;由所建立之該複 數組對應關係中,找出一組對應關係,其係最近似於該預 測晶圓所建立之該組對應關係;以及找出之該組對應關 係,判斷當該預測晶圓進行曝光時所使用之該複數個製程 參數的設定值。 1294141 【實施方式】 隨著半導體製程的進步’半導體元件的尺寸不斷的縮小,使鄰 近效應(proximity effect)越來越重要,而鄰近效應可由光微影過程 中的某些參數所影響,例如照明設定、離焦(def〇cus)、曝光後烘烤 狀態及光阻的特性等,這些參數對鄰近效應有者不同的影響,本 發明將分別分析這些參數對鄰近效應的影響,而能在半導體製造 過程中更精確的發現及修正問題。 請參照第1圖’第1圖為本發明中用於散射酸尺寸量測法 (scatterometry critical dimensi〇n metrol〇gy )之一晶圓 3 卜晶圓 31包含有用以製造積體電路之複數個晶片恤)42,而複數個切割 線42A係用以區隔複數個晶片42,並在製造程序完成後沿著切割 線42A將各個晶片42分離;一校準凹槽37係用以在製造過程中 初步的校準晶圓31的位置;此外,—圖斜列61包含有九拇搁 圖案.,其中栅攔圖案的尺寸、形狀、數目、在晶片上的位 置和拇攔_的方向等’时因設計而改變而不限於第丨圖所示。 請,時參照第2圖和第3圖,第2 _本發日种使用散射關鍵尺 寸罝測法I測之裝置示意圖,其中一散射儀%包含有一光源乃 及一侧器75 ;圖中之柵攔圖案可為任-第1圖㈣攔圖案 光阻層38形成於一薄膜層36之上,而複數個光阻結 構徽構成了栅攔圖案6〇,光阻結構38a有一厚度μ、一側壁 S宰度Ο,而光阻結構取間的間隔52則決定了拇搁 圖杗⑼的關鍵尺寸。扁夫f 本圖中光阻圖案之厚度65、側壁角度63、 1294141 間距64、及間隔52皆可因設計考量而有所不同。此為量測裝置的 設定,而散射儀的量測原理為本領域者熟知,故不多做贅述。散 射關鍵尺寸量赚之量_訊值非常低,其量測雜訊之三個標準 差約為w奈米,因此非常適合本發明之方法。然而本發明之方法 不僅限於侧㈣_尺寸量耻,购制雜贿相當於此量 測雜訊值的關鍵尺寸量測法皆適用於本發明之方法。 _ 冑分析級騎程巾的參_辟,在本㈣之—實施例中使 用-個鄰近輪廓誤差標記(Pr〇ximity pr〇flle £贿地⑽啤 量化這些參數㈣響,鄰近輪廓誤·記域為基轉近輪廊與 偏移後之鄰近輪靡的差值,而這些鄰近輪廓可由如第2圖之散射 關鍵尺寸制法所制而推算所得,如第4圖所示,第4圖為分 析某-變數而使用不同間距對關鍵尺寸做圖,其包含有_量測光 阻、Μ冓頂觸基準鄰近輪廊曲線134、—制光阻結構底部的基準 _ _近輪廓曲線132、—量測光崎獅部賴移狀鄰近輪廓曲線 138及-制光阻結構底部的偏移後之鄰近輪廓曲線136。而將第 4圖中篁測光阻結構頂部的基準鄰近輪廓曲線134和量測光阻結 構頂ap的偏移後之鄰近輪廓曲線138的差值,以及量測光阻結構 底部的基轉近輪廓崎132和-制光阻結構底部的偏移後之 鄰近輪廓曲線136的差值做圖,即可產生如第5圖的一量測光阻 、結構頂部的鄰近輪廓誤差標記144及-制光阻結構底部的鄰近 輪廓誤差標記H2。將每-製程變數依此方法產生獨特之鄰近輪靡 蜈差標記,然後將這些鄰近輪廓誤差標記建立為一資料庫,如第6 1294141 圖所示’當欲追蹤造成製程偏移的原因時,可將此時之鄰近輪廊 误差標記11G與資料料各種製程魏之鄰近輪廓縣標記⑶ 做比對’峨出造成製程偏移的參數。此外,鄰近輪廓曲線亦可 以一二元方程式表示,故鄰近輪廓誤差標記亦可用代表基竿鄰近 輪腐之-70方程式與代表偏移後之鄰近輪廓之二元方程式的差值 來表示。請同時參照第7圖、第8圖及第9圖,本發明之步驟可 歸納如下·· 步驟901 :開始; 步驟902 ·提供一具有複數個圖形區560A-560I之光罩 5〇〇,圖形區560A-560I具有複數個線條且線條 間距係為相異,並對晶圓31曝光,以於晶圓31 上形成複數個線條間距相異之圖形區6〇a-60i ;Scanning Electron Microscopy), Scatterometry, and Atomic Force Microscopy (AFM). Among them, scatterometer technology has made rapid progress in both critical dimension measurement and contour analysis applications. The 6 1294141 technology can also provide Wei, which is not available in its domain, except for the critical dimensions of the line width. 'This technology can also provide room ^_h), side degree (angles), height, and Structural details such as the thickness of the bottom layer. Therefore, optical close-size systems have recently been manufactured in the form of glare, and ribs provide methods for sizing and analyzing contours. In the reticle manufacturing process, the optical key method is used to determine the important key points. The advantage is that it is not destructive to the photoresist, and can measure the lightness of the milk to the nanometer, which is the factory side of the verification. Lai demand is low. The measurement principle of the scatterometer is that the light beam is incident on the equidistant fine (four) coffee gratings, and the intensity of the scattered light (Intensity) is recorded as a different characteristic map (Sig her re). 'The brightness versus angle or wavelength change graph (Reflectance vs. angle/wavelength) 〇 injury' includes positive vector and reverse analysis. The positive vector measurement refers to the scatterometer hardware measuring the spectrum of the laser light scattered by the circumstance, and the reverse analysis refers to the analysis of the model software established by the (4) theory to provide the structural data. There are usually two methods for comparing the opposite parts of the analysis. The first is the database comparison method, which is a database established by a diffraction theory. When the experiment is to scatter data, it is combined with the database. The data is compared to 'find the closest modulo S data. The structural reference represented by this modulus data is the structural parameter measured by the scattering ore. The second is to use the regression analysis method to compare the scatter spectrum data measured by the scatterometer machine with the theoretical map calculated by timely inputting the structural parameters to optimize the search algorithm for immediate curve comparison. The difference between the edge and the theoretical dissimilarity map then modifies the input structural parameters one by one until the difference falls within the allowable range. 1294141:, i, in the prior art, only by controlling the exposure energy to adjust the critical dimension on the photoresist pattern' to analyze the effect of the poly recording towel on the size. The effects of the number of inflammations, such as the post-exposure bake temperature and the exposure energy caused by the exposure energy, are difficult to distinguish from. SUMMARY OF THE INVENTION The method for determining a semiconductor exposure condition includes providing a plurality of graphics regions, each of the graphics regions having a plurality of lines, and the line spacing of the plurality of graphics regions is different; the setting values according to the complex array are different. The process parameters are exposed to the plurality of wafers through the reticle to form a plurality of pattern regions having different line spacings on the wafers; measuring a critical dimension of each of the pattern regions on the wafer; establishing the plurality Corresponding relationship between the line spacing of the plurality of graphics areas on the wafer and the complex array of multiple battleships, each of which has a set of line spacings of the plurality of graphics areas on the wafer and a corresponding plurality of critical dimensions Corresponding relationship; exposing a predicted wafer through the reticle to form a plurality of pattern regions having different line spacings on the predicted wafer; measuring a critical dimension of each of the pattern regions on the predicted wafer, establishing Corresponding relationship between a line spacing of the plurality of graphics regions on the predicted wafer and a plurality of corresponding plurality of critical dimensions; and finding a pair of pairs from the corresponding correspondence of the complex arrays Relation, which most approximate line corresponding to the group of the pre-established relationship between the measured wafer; and a set value of the set corresponding relationship, determines the use of the prediction when the wafer is exposed to the plurality of process parameters to find out. 1294141 [Embodiment] As the semiconductor process progresses, the size of semiconductor components continues to shrink, making the proximity effect more and more important, and the proximity effect can be affected by certain parameters in the photolithography process, such as illumination. Setting, defocusing (def〇cus), post-exposure bake state, and photoresist characteristics, these parameters have different effects on the proximity effect, and the present invention will separately analyze the influence of these parameters on the proximity effect, and can be in the semiconductor More accurate discovery and correction issues during the manufacturing process. Please refer to FIG. 1 'Fig. 1 is a wafer 3 for wafer scatterometry critical dimensi〇n metrol〇gy. The wafer 31 contains a plurality of useful circuits for manufacturing integrated circuits. A wafer shirt 42 is provided, and a plurality of cutting lines 42A are used to separate the plurality of wafers 42 and separate the individual wafers 42 along the cutting line 42A after the manufacturing process is completed; a calibration groove 37 is used in the manufacturing process. Preliminary calibration of the position of the wafer 31; in addition, the oblique column 61 includes a nine-shoulder pattern. The size, shape, number of the barrier pattern, the position on the wafer, and the direction of the thumb _ The design changes and is not limited to the figure shown in the figure. Please refer to Fig. 2 and Fig. 3, the second _ this day is a schematic diagram of the device using the scattering key size spectrometry I, wherein one scatterometer % includes a light source and a side device 75; The barrier pattern can be formed on any of the film layers 36, and the plurality of photoresist structures are formed on the film layer 36. The photoresist structure 38a has a thickness μ and a The side wall S is Ο, and the spacing 52 between the photoresist structures determines the critical dimension of the thumb rest (9). The thickness of the photoresist pattern 65, the side wall angle 63, the 1294141 pitch 64, and the spacing 52 in this figure may vary depending on design considerations. This is the setting of the measuring device, and the measuring principle of the scatterometer is well known in the art, so it will not be repeated. The amount of scattered key size is very low. The three standard deviations of the measured noise are about w nanometers, so it is very suitable for the method of the present invention. However, the method of the present invention is not limited to the side (four) _ size shame, and the key size measurement method for purchasing the bribe equivalent to the measured noise value is applicable to the method of the present invention. _ 胄 Analytical-level riding towel, in the (4) - the use of a neighboring contour error mark (Pr〇ximity pr〇flle £ bribe (10) beer quantify these parameters (four) ring, adjacent contour error The domain is the difference between the near-wheel corridor and the adjacent rim after the offset, and these adjacent contours can be calculated by the scattering key dimension method as shown in FIG. 2, as shown in FIG. 4, FIG. For the analysis of a certain variable, the key dimension is plotted using different pitches, which includes a _measuring photoresist, a top touch reference adjacent porch curve 134, a reference _ _ near contour curve 132 at the bottom of the photoresist structure, - Measure the adjacent contour curve 136 of the shifting adjacent contour curve 138 and the bottom of the photoresist structure. The reference adjacent contour curve 134 and the measurement of the top of the photoresist structure in Fig. 4 The difference between the adjacent contour curve 138 after the offset of the top ap of the photoresist structure, and the difference between the base of the photoresist structure at the bottom of the photoresist structure and the offset of the adjacent contour curve 136 of the bottom of the photoresist structure The value is plotted to produce a photometric resistance, structure as shown in Figure 5. The adjacent contour error mark 144 and the adjacent contour error mark H2 at the bottom of the photoresist structure. The per-process variable generates unique adjacent rim difference marks according to this method, and then these adjacent contour error marks are established as one data. The library, as shown in Figure 6 1294141, 'When you want to track the cause of the process offset, you can compare the adjacent corridor error mark 11G at this time with the neighboring contour county mark (3) of the data processing various processes. The parameter that causes the process offset. In addition, the adjacent contour curve can also be represented by a binary equation, so the adjacent contour error mark can also be represented by a binary equation representing the base equation of the adjacent wheel rot and the adjacent contour representing the offset. The difference is shown. Please refer to FIG. 7 , FIG. 8 and FIG. 9 at the same time, the steps of the present invention can be summarized as follows: Step 901: Start; Step 902 • Provide a mask with a plurality of graphic areas 560A-560I 5, the graphics area 560A-560I has a plurality of lines and the line spacing is different, and the wafer 31 is exposed to form a plurality of pattern areas 6 having different line spacings on the wafer 31. a-60i;

步驟9〇3 ·使用散射關鍵尺寸量測法量測圖形區60A-60I 之臨界尺寸,並依據圖形區560A-560I的線條間 距與相對應的臨界尺寸製作一鄰近輪廓曲線; 步驟904 ·右改變製程參數則重複步驟撤,否則繼續步驟 905 ; 步驟905 :將各種製程參數之鄰近輪廓曲線與基準鄰近輪 廊曲線的差值製作成鄰近輪廊誤差標記資料庫; y驟6若奴刀析一待測之製程則至步驟9〇7,否則繼續 步驟911 ; 步驟907 :、經由光f 對—預測晶圓631曝光,以於預 測曰a圓631上形成複數個線條間距相異之圖形 11 -1294141Step 9〇3·Measure the critical dimension of the pattern areas 60A-60I using the scattering key size measurement method, and make an adjacent contour curve according to the line spacing of the pattern areas 560A-560I and the corresponding critical size; Step 904 • Change right The process parameters are repeated step by step, otherwise step 905 is continued; Step 905: the difference between the adjacent contour curve of the various process parameters and the reference adjacent corridor curve is made into a database of adjacent wheel gallery error marks; The process to be tested then proceeds to step 9〇7, otherwise step 911 is continued; step 907: exposure of the predicted wafer 631 via the light f to form a plurality of patterns 11 of different line spacings on the predicted 曰a circle 631. 1294141

區 660A-660I 步驟9〇8:使用散射關鍵尺寸量剛法量測預測晶圓631上 之圖形區660A-660I之臨衣 上 560A_560I㈤線條1 ^寸,並依據圖形區 -鄰近輪㈣線;、、應的臨界尺寸製作 步驟909:將預測晶圓63丨之鄰 廊曲線的纽料成鄰近輪 步㈣:將預測晶圓631之鄰近輪廓誤差標:與鄰 廓誤差標記資料庫相比對, 近輪 a , ± 以分析出預測晶圓 糾進订曝光時所使用之製程 步驟911 :結束。 又疋值, 在本細种’步雜物轉建立可事先製作並 儲存,而不絲次輯皆需要建立,此外此方式亦可以應用 於線上作業時作即時的分析。而在第7圖和第8圖中之曝光程序 僅為示意圖’實際曝光程序可能包含使用光源別對複數個 光罩及曝光系統580對晶圓曝光及钱刻等過程來產生晶圓 31和631上之圖形。 在本發明之另一實施例中直接採用散射關鍵尺寸量測法所量 測得之頻譜來量錢些錄,此較_譜較誤差標記伽伽 Proximity Error Signature)定義為基準頻譜與偏移後之頻譜的差 值’而這些鱗可由如第2狀赫繼尺寸量測法所量測。將 12 1294141 2頻稍鱗後之賴縣錄®,即可產生如麵鄰近誤差 j °然6將每—製雜數域賴鍵尺寸量測法所量測得之 頻2建立為—頻譜鄰近誤差標記資料庫,如第ig圖所示,當欲追 成製程偏移的原因時’可將此時之頻譜鄰近誤差標記綱與 二料庫t各種製程變數之頻譜鄰近誤差標記22〇做比對,而找出 k成製程偏移的參數。請同時參照第7圖、第8圖及第1】圖,本 發明之步驟可歸納如下: 步驟1101 :開始; 步驟11G2:提供—具有複數烟形56GA-56GI之光罩500, 圖形區56〇Α·56〇Ι具有魏個祕線條間距係為 相異,並對晶圓31曝光,以於晶圓31上形成複 數個線條間距相異之圖形區6〇Α_6〇Ι ; V驟1103 ·使用散射關鍵尺寸量測法量測圖形區嫩__ 之臨界尺寸’並依據圖形區56〇Α_56〇Ι的線條間 距與相對應的臨界尺寸製作一頻譜曲線; 步驟U04 :若改縣程參數則重複步驟·,否則繼續步 驟 1105 ; 步驟:將各種製程參數之_曲線與基準頻譜曲線的 差值製作成頻譜鄰近誤差標記資料庫; 步驟:紐分析-待測之製程則至步驟·,否則繼 續步驟1111 ; 步驟經由光罩500對-預剛晶圓631曝光,以於預 測晶圓631上形成複數個線條間距相異之圖形 13 1294141 區 660A-660I ; 步驟1108 :使用散射關鍵尺寸量測法量測預測晶圓631上 之圖形區660A-6 601之6¾界尺寸,並依據圖形區 560A-560I的線條間距與相對應的臨界尺寸製作 一頻譜曲線; 步驟1109 ·•將預測晶圓631之頻譜曲線與基準頻譜曲線的 差值製作成頻譜鄰近誤差標記; _ 步驟iiio :將預測晶圓631之頻譜鄰近誤差標記與頻譜鄰 近誤差標§己資料庫相比對,以分析出預測晶圓 631進行曝光時所使用之製程參數的設定值; 步驟1111 ··結束。 在本實施例中,步驟1101-步驟Π05的資料庫建立可事先製作 並儲存,而不需每次比對皆需要重複建立,此外此方式亦可以應 i 用於線上作業時作即時的分析。在此實施例中,直接以量測得之 頻譜比對,而不需將頻譜轉換成關鍵尺寸的輪廓。 本發明之紐能在半導體觀過程巾分析各鮮@參數對製 程的影響,而能偵測出製程參數的改變,而使用輪廓分析及頻譜 分析的方法’在使用不同的關鍵尺寸量測法比對時將更有彈性。 以上所述僅為本發日狀較佳實關,凡依本發料請專利範 圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 14 1294141 【圖式簡單說明】 第1圖為本發明中用於量測關鍵尺寸之晶圓的示意圖。 第2圓為本發明中使用散射關鍵尺寸量測法量測之示意圖。 第3圖為第1圖之晶圓上用於量測關鍵尺寸之栅攔圖案。 第4圓為依據第2圖量測出之數值所得之鄰近輪廓曲線。 第5圖為依據鄰近輪廓曲線之差撕製之鄰近輪棘差標記曲線。Zone 660A-660I Step 9〇8: Use the scatter key dimension to measure the predicted area 660A-660I on the wafer 631 on the 560A_560I (five) line 1 ^ inch, and according to the graphics area - adjacent wheel (four) line; The critical dimension manufacturing step 909: the neighboring curve of the predicted wafer 63 is adjacent to the round step (4): the adjacent contour error of the predicted wafer 631 is compared with the adjacent error mark database. The near wheel a, ± is used to analyze the process step 911 used to predict the wafer correction exposure: end. It is also depreciated. In this subtle step, the creation of the debris can be created and stored in advance, and it is not necessary to create it. In addition, this method can also be applied to online analysis for immediate analysis. The exposure procedures in Figures 7 and 8 are only schematic diagrams. The actual exposure procedure may involve the use of a light source, a plurality of reticle and exposure system 580 wafer exposure and etching processes to produce wafers 31 and 631. The graphic on it. In another embodiment of the present invention, the spectrum measured by the scatter key size measurement method is directly used for recording, and the _ spectral error gamma Proximity Error Signature is defined as the reference spectrum and the offset. The difference in the spectrum' and these scales can be measured by the second shape measurement method. After 12 1294141 2 frequency scales the Lai County Record®, you can generate the proximity error j ° 6 and the frequency 2 measured by the measurement method of each key field is established as - spectrum proximity The error mark database, as shown in the ig diagram, when the cause of the process offset is to be chased, can be compared with the spectral proximity error flag of the various process variables of the two libraries. Right, and find the parameters of the k-process offset. Referring to FIG. 7, FIG. 8 and FIG. 1 simultaneously, the steps of the present invention can be summarized as follows: Step 1101: Start; Step 11G2: Provide - a photomask 500 having a plurality of smoke-shaped 56GA-56GI, graphic area 56〇 Α·56〇Ι has Wei's secret line spacing is different, and the wafer 31 is exposed to form a plurality of pattern areas with different line spacings on the wafer 31. 6〇Α_6〇Ι; V1103 · Use The scattering key size measurement method measures the critical dimension of the pattern area __ and creates a spectrum curve according to the line spacing of the pattern area 56〇Α_56〇Ι and the corresponding critical size; Step U04: repeat if the county parameter is changed Step · Otherwise, proceed to step 1105; Step: Make the difference between the curve of the various process parameters and the reference spectrum curve into a spectrum proximity error flag database; Step: New analysis - the process to be tested goes to step ·, otherwise continue the step Step 1111: The pre-rigid wafer 631 is exposed through the mask 500 to form a plurality of patterns 13 1294141 regions 660A-660I having different line spacings on the prediction wafer 631; Step 1108: Using a scattering key dimension measurement method Prediction wafer 631 The pattern area 660A-6 601 is 63⁄4 bounded, and a spectral curve is formed according to the line spacing of the graphics area 560A-560I and the corresponding critical dimension; Step 1109 ·• The spectral curve of the predicted wafer 631 and the reference spectrum curve The difference is made into a spectral proximity error flag; _ Step iiio: comparing the spectral proximity error flag of the predicted wafer 631 with the spectral proximity error metric database to analyze the process used to predict the exposure of the wafer 631 The set value of the parameter; Step 1111 ·· End. In this embodiment, the database establishment of step 1101 - step Π05 can be created and stored in advance, without the need to repeatedly establish each comparison, and this method can also be used for immediate analysis when used for online operations. In this embodiment, the measured spectral alignments are directly measured without the need to convert the spectrum to a critical size profile. The utility of the invention can analyze the influence of each fresh parameter on the process in the semiconductor process process, and can detect the change of the process parameter, and use the method of contour analysis and spectrum analysis to use different key dimension measurement methods. It will be more flexible. The above description is only for the purpose of this issue, and the equivalent changes and modifications made by the patent scope of the present invention are all covered by the present invention. 14 1294141 [Simplified Schematic] FIG. 1 is a schematic view of a wafer for measuring critical dimensions in the present invention. The second circle is a schematic diagram of the measurement using the scattering critical dimension measurement method in the present invention. Figure 3 is a grid pattern for measuring critical dimensions on the wafer of Figure 1. The fourth circle is the adjacent contour curve obtained from the value measured in the second figure. Figure 5 is a graph showing the adjacent wheel spine mark based on the difference between adjacent contour curves.

第6圖為將待測鄰近輪廓誤差標記與資料庫中之鄰近輪廊誤差 標記比對之示意圖。 第7圖為晶圓曝光之示意圖。 第8圖為待測晶圓曝光之示意圖。 =圖為利用鄰近輪廓誤差標記_製程變動之流程圖。 圖為將待測頻譜鄰近誤差標記與簡庫中之頻譜鄰近誤 差標記比對之示意圖。 第11圖為利用頻譜鄰近誤差標記_製程變動之流程圖。Figure 6 is a schematic diagram of comparing adjacent error signatures to be tested with adjacent corridor error markers in the database. Figure 7 is a schematic diagram of wafer exposure. Figure 8 is a schematic diagram of wafer exposure to be tested. = The figure is a flow chart using the adjacent contour error flag _ process variation. The figure shows a schematic diagram of comparing the adjacent error signature of the spectrum to be measured with the spectral proximity error marker in the simple library. Figure 11 is a flow chart using the spectral proximity error flag _ process variation.

【主要元件符號說明】[Main component symbol description]

31 36 37 38 38A 42 42A 晶圓 薄膜層 校準凹槽 光阻層 光阻結構 晶片 切割線 15 1294141 _31 36 37 38 38A 42 42A Wafer Thin film layer Calibration groove Photoresist layer Photoresist structure Wafer Cutting line 15 1294141 _

52 光阻結構間的間隔 60、60A-60I 晶圓上之概搁圖案 61 圖案陣列 62 側壁 63 侧壁角度 64 光阻結構間的間距 65 厚度 73 光源 74 散射儀 75 偵測器 110 待測之鄰近輪廓誤差標記 120 鄰近輪廓誤差標記之資料庫 132、134、136、138 鄰近輪廓曲線 142 、 144 鄰近輪廓誤差標記 210 待測之頻譜鄰近誤差標記 220 頻譜鄰近誤差標記之資料庫 500 光罩 560A-560I 光罩上之柵欄圖案 570 光源 580 曝光系統 631 待測晶圓 660A-660I 晶圓上之桃爛圖案 1652 Interval between photoresist structures 60, 60A-60I Overlay pattern on the wafer 61 Pattern array 62 Sidewall 63 Sidewall angle 64 Spacing between photoresist structures 65 Thickness 73 Light source 74 Scatterometer 75 Detector 110 To be tested Proximity Profile Error Marker 120 Proximity Profile Error Marker Database 132, 134, 136, 138 Proximity Contour Curve 142, 144 Proximity Profile Error Marker 210 Spectrum To Be Detected Near Error Marker 220 Spectrum Adjacent Error Marker Database 500 Photomask 560A- 560I Fence on Fence Pattern 570 Light Source 580 Exposure System 631 Wafer to Be Tested 660A-660I Peach Pattern on Wafer 16

Claims (1)

^ 1294141 十、申請專利範圍: h —種判斷半導體曝光條件的方法,包含有: ⑻提供—具有複數個圖形區之光罩,各該圖形區具有 複數個線條,該複數_形區之線條間距係為相異; (b)依據複數組⑤定值相異的製程參數經由該光罩對複 數個晶圓曝光,以於各該晶圓上形成複數個線條間 距相異之圖形區; _ ⑷量測各該晶圓上之各個圖形區的-臨界尺寸; ⑷建立該複數個晶圓上之複數個圖形區的線條間距與 相對應之複數個臨界尺寸的複數組對應關係,各該 S曰圓上之複數個圖形區的線條間距與相對應之複數 個臨界尺寸係建立有一組對應關係,· (e)經由该光罩對一預測晶圓曝光,以於該預測晶圓上 形成複數個線條間距相異之圖形區; 驗 (f)量測該預測晶圓上的各該圖形區的一臨界尺寸; (g) 建立該預測晶圓上的該複數個圖形區的線條間距與 相對應之複數個臨界尺寸的一組對應關係; (h) 由步驟(d)所建立之該複數組對應關係中,找出一組 對應關係,其係最近似於步驟(g)所建立之該組對應 關係;以及 (Ο依據步驟(h)所找出之該組對應關係,判斷當該預測 晶圓進行曝光時所使用之該複數個製程參數的設 ’ 定值。 17 1294141 2. 如請求項1所述之方法,另包含步驟⑴:依據步驟(d) 所建立的各組對應關係,建立對應於該組對應關係之 線條間距與臨界尺寸的一二元方程式。 3. 如請求項2所述之方法,其中步驟(h)係為由步驟⑴所 建立之該複數個二元方程式中,找出一二元方程式, 其係最吻合於步驟(g)所建立之該組對應關係。 4. 如請求項2所述之方法,另包含步驟(k):依據步驟(g) 所建立的該組對應關係,建立對應於該組對應關係之 線條間距與臨界尺寸的一二元方程式。 5. 如請求項4所述之方法,其中步驟(h)係由步驟⑴所建 立之該複數個二元方程式中,找出一二元方程式,其 係最吻合於步驟(k)所建立之該二元方程式。 6. 如請求項4所述之方法,另包含下列步驟: (l) 根據於步驟⑴建立之各該二元方程式與一標準二 元方程式之差產生一臨近輪廓誤差標記曲線; (m) 根據於步驟(k)建立之該二元方程式與該標準二元 方程式之差產生一臨近輪廓誤差標記曲線;以及 (η)由步驟⑴所產生之該複數個臨近輪廓誤差標記曲 線中,找出一臨近輪廓誤差標記曲線,其係最吻合 18 1294141 於步驟(m)所產生之該臨近輪廓誤差標記曲線。 7. 如請求項1所述之方法,其中步驟(c)係量測各該晶圓 上之各個圖形區中的凸起結構的頂部的臨界尺寸,步 驟⑴係量測該預測晶圓上之各個圖形區中的凸起結構 的頂部的臨界尺寸。 8. 如請求項1所述之方法,其中步驟(c)係量測各該晶圓 上之各個圖形區中的凸起結構的底部的臨界尺寸;步 驟(f)係量測該預測晶圓上之各個圖形區中的凸起結構 的底部的臨界尺寸。 9. 如請求項1所述之方法,其中步驟(c)係量測各該晶圓 上之各個圖形區中的凸起結構的頂部及底部的臨界尺 寸;步驟⑴係量測該預測晶圓上之各個圖形區中的凸 起結構的頂部及底部的臨界尺寸。 10. 如請求項1所述之方法,另包含步驟(0):依據步驟⑴ 所判斷出之該複數個製程參數的設定值與一組標準設 定值,調整該複數個製程參數的設定值。 11. 如請求項10所述之方法,另包含步驟(p):依據步驟(0) 調整後的該複數個製程參數的設定值,經由該光罩對 19 1294141 一晶圓進行曝光。 12.如請求項1所述之方法,其中步驟(c)係為藉由一散射臨 界尺寸量測法量測各該晶圓上之各個圖形區的一臨界 尺寸。 13. 如請求項1所述之方法,其中步驟(f)係為藉由一散射臨 界尺寸量測法量測該預測晶圓上的各個圖形區的一臨 界尺寸。 14. 一種判斷半導體曝光條件的方法,包含有: (a) 提供一具有複數個圖形區之光罩,各該圖形區具有 複數個線條,該複數個圖形區之線條間距係為相異; (b) 依據複數組設定值相異的製程參數經由該光罩對複 數個晶圓曝光,以於各該晶圓上形成複數個線條間 距相異之圖形區, (c) 量測各該晶圓的該複數個圖形區,並據以產生該晶 圓的該複數個圖形區的一組頻譜圖, (d) 經由該光罩對一預測晶圓曝光,以於該預測晶圓上 形成複數個線條間距相異之圖形區; (e) 量測該預測晶圓的該複數個圖形區,並據以產生該 預測晶圓之該複數個圖形區的一組頻譜圖; (f) 由步驟(c)所產生之該複數組頻譜圖中,找出一組頻 20 1294141 譜圖,其係最近似於步驟(e)所產生之該組頻譜圖; 以及 (g)依據步驟⑴所找出之該組頻譜圖,判斷當該預測晶 圓進行曝光時所使用之該複數個製程參數的設定 值。 15. 如請求項14所述之方法,另包含步驟(h):依據步驟(g) 所判斷出之該複數個製程參數的設定值與一組標準設 定值,調整該複數個製程參數的設定值。 16. 如請求項15所述之方法,另包含步驟⑴:依據步驟(h) 調整後產生之該複數個製程參數的設定值,經由該光 罩對一晶圓進行曝光。 17. 如請求項14所述之方法,其中步驟(c)係為藉由一散射 臨界尺寸量測法量測各該晶圓的該複數個圖形區,並據 以產生該晶圓的該複數個圖形區的該複數個頻譜圖。 18. 如請求項14所述之方法,其中步驟(e)係為藉由一散射 臨界尺寸量測法量測該預測晶圓的該複數個圖形區,並 據以產生該預測晶圓之該複數個圖形區的該複數個頻 譜圖。 21^ 1294141 X. Patent application scope: h - a method for judging semiconductor exposure conditions, comprising: (8) providing - a photomask having a plurality of graphics regions, each of the graphics regions having a plurality of lines, and a line spacing of the plurality of _-shaped regions (b) exposing a plurality of wafers through the mask according to the process parameters of the complex array 5, so as to form a plurality of pattern regions having different line spacings on each of the wafers; _ (4) Measure the -critical dimension of each graphics area on each of the wafers; (4) establish a corresponding relationship between the line spacing of the plurality of graphics areas on the plurality of wafers and the corresponding complex array of multiple critical dimensions, each of which The line spacing of the plurality of graphics areas on the circle is associated with a plurality of corresponding critical dimension systems. (e) exposing a predicted wafer through the mask to form a plurality of the predicted wafers. a pattern area having different line spacings; (f) measuring a critical dimension of each of the pattern areas on the predicted wafer; (g) establishing a line spacing of the plurality of pattern areas on the predicted wafer and corresponding a set of correspondences of a plurality of critical dimensions; (h) finding a set of correspondences corresponding to the complex array correspondence established by the step (d), which is most similar to the group corresponding to the step (g) And (in accordance with the group correspondence found in step (h), determining a setting value of the plurality of process parameters used when the predicted wafer is exposed. 17 1294141 2. As claimed in claim 1 The method further includes the step (1): establishing a binary equation corresponding to the line spacing and the critical dimension of the correspondence relationship of the group according to the correspondence relationship of the groups established in the step (d). 3. As described in claim 2 The method, wherein the step (h) is the plurality of binary equations established by the step (1), and finding a binary equation which most closely matches the set correspondence corresponding to the step (g). The method of claim 2, further comprising the step (k): establishing a binary equation corresponding to the line spacing and the critical dimension of the correspondence of the group according to the set correspondence corresponding to the step (g). The method of claim 4, wherein Step (h) is to find a binary equation from the plurality of binary equations established by the step (1), which is most consistent with the binary equation established in the step (k). The method further comprises the following steps: (1) generating a proximity contour error mark curve according to the difference between each of the binary equation and the standard binary equation established in the step (1); (m) establishing according to the step (k) A difference between the binary equation and the standard binary equation produces a proximity contour error signature curve; and (n) a plurality of adjacent contour error signature curves generated by the step (1) to find an adjacent contour error marker curve, It is the most consistent with the adjacent contour error mark curve generated by the step (m) of 18 1294141. 7. The method of claim 1, wherein the step (c) measures a critical dimension of a top portion of the raised structure in each of the pattern regions on the wafer, and the step (1) measures the predicted wafer. The critical dimension of the top of the raised structure in each graphics area. 8. The method of claim 1, wherein the step (c) measures a critical dimension of a bottom portion of the raised structure in each of the pattern regions on the wafer; and the step (f) measures the predicted wafer The critical dimension of the bottom of the raised structure in each of the graphics regions. 9. The method of claim 1, wherein the step (c) measures the critical dimensions of the top and bottom of the raised structures in each of the pattern regions on the wafer; and the step (1) measures the predicted wafer. The critical dimensions of the top and bottom of the raised structure in each of the graphics regions. 10. The method of claim 1, further comprising the step (0): adjusting the set value of the plurality of process parameters according to the set value of the plurality of process parameters determined by the step (1) and a set of standard set values. 11. The method of claim 10, further comprising the step (p): exposing a wafer to the 19 1294141 via the mask according to the set value of the plurality of process parameters adjusted in step (0). 12. The method of claim 1 wherein step (c) is to measure a critical dimension of each of the pattern regions on each of the wafers by a scattering critical dimension measurement. 13. The method of claim 1, wherein the step (f) is to measure a critical dimension of each of the graphics regions on the predicted wafer by a scattering critical dimension measurement. 14. A method for determining a semiconductor exposure condition, comprising: (a) providing a mask having a plurality of pattern regions, each of the pattern regions having a plurality of lines, wherein the line spacing of the plurality of pattern regions is different; b) exposing a plurality of wafers through the mask according to process parameters having different set values of the complex array, so as to form a plurality of pattern regions having different line spacings on the wafer, and (c) measuring each of the wafers The plurality of graphics regions, and a set of spectrograms of the plurality of graphics regions of the wafer are generated, (d) exposing a predicted wafer through the mask to form a plurality of the plurality of graphics regions on the prediction wafer a pattern area having different line spacings; (e) measuring the plurality of pattern areas of the predicted wafer, and generating a set of spectrum patterns of the plurality of pattern areas of the predicted wafer; (f) by step ( c) in the generated complex array spectrogram, find a set of frequency 20 1294141 spectra, which is closest to the set of spectrograms generated in step (e); and (g) find out according to step (1) The set of spectrograms to determine when the predicted wafer is exposed The plurality of process parameter setpoint. 15. The method of claim 14, further comprising the step (h): adjusting the setting of the plurality of process parameters according to the set value of the plurality of process parameters determined by the step (g) and a set of standard set values. value. 16. The method of claim 15, further comprising the step (1): exposing a wafer via the reticle according to the set value of the plurality of process parameters generated after the step (h) is adjusted. 17. The method of claim 14, wherein the step (c) is to measure the plurality of graphics regions of each of the wafers by a scattering critical dimension measurement, and thereby generating the plurality of the wafers The plurality of spectrograms of the graphics area. 18. The method of claim 14, wherein the step (e) is to measure the plurality of graphics regions of the predicted wafer by a scattering critical dimension measurement, and thereby generating the predicted wafer. The plurality of spectrograms of the plurality of graphics regions. twenty one
TW95109327A 2006-03-17 2006-03-17 Method for detecting semiconductor manufacturing conditions TWI294141B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW95109327A TWI294141B (en) 2006-03-17 2006-03-17 Method for detecting semiconductor manufacturing conditions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW95109327A TWI294141B (en) 2006-03-17 2006-03-17 Method for detecting semiconductor manufacturing conditions

Publications (2)

Publication Number Publication Date
TW200737295A TW200737295A (en) 2007-10-01
TWI294141B true TWI294141B (en) 2008-03-01

Family

ID=45068071

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95109327A TWI294141B (en) 2006-03-17 2006-03-17 Method for detecting semiconductor manufacturing conditions

Country Status (1)

Country Link
TW (1) TWI294141B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI453394B (en) * 2012-08-20 2014-09-21

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5412528B2 (en) 2008-12-30 2014-02-12 エーエスエムエル ネザーランズ ビー.ブイ. Inspection method, inspection system, substrate, and mask
KR101257453B1 (en) 2009-05-12 2013-04-23 에이에스엠엘 네델란즈 비.브이. Inspection method for lithography
TWI488245B (en) * 2009-05-19 2015-06-11 United Microelectronics Corp Method for inspecting photoresist pattern
US10121709B2 (en) * 2017-01-24 2018-11-06 Lam Research Corporation Virtual metrology systems and methods for using feedforward critical dimension data to predict other critical dimensions of a wafer
CN112038249B (en) * 2020-08-27 2022-08-09 上海华力集成电路制造有限公司 Method for detecting abnormal process of photoetching process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI453394B (en) * 2012-08-20 2014-09-21

Also Published As

Publication number Publication date
TW200737295A (en) 2007-10-01

Similar Documents

Publication Publication Date Title
US11067904B2 (en) System for combined imaging and scatterometry metrology
JP3854539B2 (en) Method and apparatus for measuring size and three-dimensional shape of fine pattern of semiconductor wafer
US10612916B2 (en) Measurement of multiple patterning parameters
US10732516B2 (en) Process robust overlay metrology based on optical scatterometry
JP6305399B2 (en) Overlay target for instrument-like scatterometry
KR102317060B1 (en) Methods and apparatus for patterned wafer characterization
US10030965B2 (en) Model-based hot spot monitoring
KR101257954B1 (en) Scatterometry method with characteristic signatures matching
KR102515228B1 (en) Apparatus, techniques, and target designs for measuring semiconductor parameters
US10352876B2 (en) Signal response metrology for scatterometry based overlay measurements
US10151986B2 (en) Signal response metrology based on measurements of proxy structures
CN106796105B (en) Metrology of multiple patterning processes
TWI671835B (en) Metrology test structure design and measurement scheme for measuring in patterned structures
TWI294141B (en) Method for detecting semiconductor manufacturing conditions
IL140179A (en) Method and system for measuring in patterned structures
KR20060061240A (en) Method for designing an overlay mark
US7553678B2 (en) Method for detecting semiconductor manufacturing conditions
CN100535759C (en) Method of determining semiconductor technological condition
US20090116040A1 (en) Method of Deriving an Iso-Dense Bias Using a Hybrid Grating Layer
US7639370B2 (en) Apparatus for deriving an iso-dense bias
JP2012018097A (en) Pattern measurement method and pattern measurement device
JP2013231648A (en) Pattern measurement method
KR20080006946A (en) Method for detecting overlay of semiconductor memory device