TWI293831B - Two stage power conversion circuit - Google Patents

Description

FIELD OF THE INVENTION The present invention relates to power conversion circuits, such as secondary power conversion circuits for network applications and applications. . C OFF ^ 负 负 拂 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明As bandwidth requirements increase, the quality of service (Q〇S) requirements continue to improve by 10, which makes it better to ensure the integrity of the data and maximize the system's boot time. In order to achieve this project, intelligent routing management is often used. For example, in a packet distribution route, the data stream is reorganized into small data packets, each data packet is routed through the final destination of the individual data path, and the final destination packet is reassembled into the original data stream. This type of routing can only be achieved through complex deep packet processing, which requires NPUs & ASICs that are accelerating and growing in power. The increased demand for data processing affects the internal hardware design, especially for the internal hardware design of the power distribution field is not surprising. The reason is that the standard size of the communication board remains relatively constant, and since future designs require more processors 20 to be added to the board, the power distribution system must be implemented in a shrinking space. At the same time, the increase in the number of components invariably results in an increase in power consumption. In order to fit the power supply into a small space and meet ever-increasing power requirements, the power distribution design must be optimized to ensure power efficiency. Design a more efficient power supply to reduce power dissipation and thus reduce heat generation. The power architecture adopted by the 7th-day network and communication system received 48 volts from the Magic AC/DC rectification group. The volt input is the name input 'but multiple systems can accept a range of power rounds in both the ends of the name input. For example, the universal telecommunications voltage is 36Vin to 75Vin, and the ETSI (European Telecommunications Standard Input) voltage is in the range of % volts to (6) volts. Other systems are operating in the adjusted 48 volt bus +/_1〇% range. Regardless of the power distribution method used, the input voltage must be distributed in the most energy efficient and cost effective way. In order to meet these needs, the secondary power conversion becomes a new standard for built-in power transmission. A plurality of conventional split power converters 105a, ..., 105n-1 (% as "building blocks") are used to supply a plurality of low voltage loads to a board (e.g., a computer motherboard, as shown in Fig. 1). The lower current peripheral output is powered by the intermediate power generated by the PQL ιιι.η refueling "building blocks". It then attempts to increase the simplicity and resiliency of the built-in power distribution design. The fully regulated converter is used to generate the intermediate bus voltage, which is then converted to the point-of-load voltage through the point-of-load power converter (P0LS). For example, in one scheme (not shown), the ·48νίη name is input to the material 1 (four) and is converted into a 3.3 volt medium-flow voltage. This intermediate bus voltage is directly supplied to most of the load on the board that requires power, while the load that does not require power is received by a sink converter. In order to achieve maximum output efficiency and minimum cost for either of the two secondary schemes, each power conversion stage must be carefully optimized. However, the output efficiency of these programs is usually low. SUMMARY OF THE INVENTION - The object of the present invention is to overcome the shortcomings of the conventional secondary power distribution scheme, which provides a cost-effective and space efficient power distribution 5 design that utilizes fewer components while meeting multiple Today's applications use ever-increasing power demands to overcome the shortcomings of conventional technology. In order to achieve this, embodiments of the present invention take advantage of the fact that individual converters do not require precise control of the intermediate bus voltage when using a tightly tuned POL converter. Instead, an effective performance can be achieved by operating the open circuit of the converter 10 in an unregulated manner. By processing the individual DC busbar converter open loops in an unregulated manner using a 50% duty cycle, the circuit design that controls the control required for such power conversion becomes extremely simple and highly efficient because the open loop design does not require tradition A compact closed-loop 15-way control circuit and overvoltage protection circuit that closely adjusts the t-force conversion design. Such a control circuit can be implemented in a small integrated space in a small integrated circuit. Power conversion performance is achieved with minimum voltage and current stress, allowing for more efficient power MOSFETs with lower figure of merit (FOMs). In addition, a fixed 50% duty cycle allows for improved reliability through a simple and highly efficient self-driven secondary synchronous rectification circuit while minimizing the need for input filtering and output filtering. To control the simple and novel open loop control scheme presented here. Two example integrated circuit controllers are proposed, one for a half bridge converter and the other for a full bridge converter. An example half-bridge converter according to the present invention can be used to convert a nominal input power supply to a specified range, for example, 60-160 7

Further, the range of I watts can be converted by the full-bridge converter according to the present invention, for example, in the range of 120-160 watts. Due to the fixed 50% duty cycle, the output voltage is proportional to the nominal input voltage by a factor of K. In the case of the half bridge converter according to the present invention, K is for example equal to 1/2 divided by the transformer turns ratio. 5 In the case of a full bridge converter according to the invention, K is for example equal to 1 divided by the transformer turns ratio. Therefore, full bridge topology provides greater flexibility in terms of choice of output voltage. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing a conventional secondary power conversion architecture. 10 Figure 2 is a block diagram showing the basic secondary power conversion architecture in accordance with the present invention. Figure 3 is a block diagram showing a first example power conversion architecture in accordance with the present invention. Fig. 4 is a diagram showing an exemplary electric power conversion circuit of a power module mounted on a board according to the present invention. Fig. 5 is a line diagram showing the neutral time of the half bridge driver 1C in accordance with the present invention. Fig. 6 is a block diagram of the half bridge driver 1C of Fig. 4. Figure 7 is an illustration of the front and rear of an exemplary power conversion panel in accordance with the present invention. Figure 8 is a line graph showing power conversion efficiency versus output load current. Fig. 9 is a diagram showing another example of a power conversion circuit of a power module mounted on a board according to the present invention. Figure 10 is a line graph showing the snoring waveform. .. -...-.. ..." 1293831 The 11th u-members do not use two methods for assembling the half-bridge driver of Figure 4 to operate in a self-oscillating mode or a synchronous mode. [Embodiment] DETAILED DESCRIPTION OF THE INVENTION In accordance with an embodiment of the present invention, as shown in FIG. 2, a name of -48 volts is converted into a 12 volt intermediate busbar package 205 through a single converter 21G and then the intermediate busbar voltage is 2 〇. 5 is converted into various load point voltages through individual 215a, ..... 215n. Referring now to Figure 3, there is shown a first example of a half bridge 2 stage 1 〇 power conversion according to the present invention. Architecture 3GG. Power Conversion Architecture · Single, unregulated, power-on-board power module (BMp) 3〇5 for shut-off loop operation. BMP 305 can be operated to convert the nominal input voltage to 32 中间 to intermediate bus voltage 325. The intermediate bus voltage 325 is then fed to respective load point (p〇L) switching states 31〇a, 310b, ..., 31〇n, which convert the intermediate bus voltage 325 into i5 other load point voltages 330a, 330b , ..., 33〇n is used to supply power to each load on the board (not shown). Refer to Figure 4 now. The example half bridge shown in the BMp power module 3〇5 for Fig. 3 is converted into a circuit 405. The half bridge converter circuit 4〇5 includes an open loop inverting circuit 410, a primary bias circuit 43〇, two The secondary rectification and filtering 20 wave circuit 425 and the secondary bias circuit 420. The primary open circuit inverting circuit 410 includes terminals (cs), (CT), (G), (LO), (Vb), (HO) , (Vs) and (Vcc) primary half-bridge controller IC 415. Diode D1 is connected between Vdd and controller IC 415 terminal (乂13)' pen resistor R1 is connected to Vdd and controller 1 [415 terminals (() D); :Ef3K3T Ί it it/li 2:Ϊ4"Ί ' r,ί i 14 ϊ 5

Capacitor is connected between Vdd and terminal (CS) and (G) of controller IC 415; capacitor C2 is connected to controller 1 (: terminal between 415 (CT) and ground potential' can also be connected to controller Terminals (〇8) and (〇) of the ^415; capacitors 〇3 are connected between the terminals (Vb) and (Vs) of the controller 1C 415; and the terminals (vcc) are connected to the Vdd. Circuit 41〇 also includes power MOSFETs M1, M2 (eg, two-legged 6603 30 volt η·channel DirectFET)

The MOSFET S' brake drive voltage is clamped to a bias voltage, for example, 75 volts, and is coupled to the node N1 of the half-bridge assembly state, between the 48 volt input voltage 320 and the ground potential. The node N1 is also connected to the terminal 10 (Vs) of the controller 1 (:; 415. The gates of the MOSFETs M1 and M2 are respectively connected to the terminals (H〇) and (L〇). The capacitors C5 and C6 and the capacitor C4 are connected in series. The parallel-connected half-bridge MOSFETs M1, M2 are between the 48 volt nominal input voltage 320 and the ground potential. The primary wiring II is connected between the node N2 and the terminal (Vs) of the controller 1C 415. 15 MOSFET selection is to satisfy the electrical efficiency and Thermal efficiency requirements and maintenance

The overall footprint is of critical importance and must be maintained with a minimum number of components. The power MOSFETs Ml, M2 include next-generation MOSFET technology that can be combined into a half-bridge configuration to operate with the half-bridge controller IC 415. The DirectFET package can also be used to virtually eliminate package resistance while allowing a lower overall ON state resistance of 20. In addition, because the DirectFET technology is packaged in plastic, the DirectFET MOSFETS is extremely effective when using top-side cooling.

The primary bias circuit 430 includes a dual FET package 435 (eg, IRF7380 η-channel FETs) including primary bias MOSFETs M3, M4; resistors R2, R3 are coupled in parallel between the 48 volt nominal input voltage 320 and the MOSFET 10 0 M3; The resistor R4 is connected between the input voltage of 32 volts and the MOSFET M4; the Zener diodes D4 and D5s connected in series are connected between the resistor R4 and the ground potential; and the diode D3 is connected between the nodes N3 and Vdd. The one-pole D2 is connected to the MOSFET M4, and the primary bias wiring 12 is connected between the diode D2 and the ground potential. In this way, the primary end bias is obtained via the start of the linear regulator and then the primary end bias is obtained from the steady state transformer. The primary rectification and filtering circuit 425 includes a secondary wiring 13 which is magnetically coupled to the primary wiring n of the open loop inverting circuit 410. The secondary wiring 13 is connected between the MOSFETs Μ5 and Μ6, and is coupled to the node Ν4. The resistive state R5 and the capacitor C7 are connected in parallel with each other to lighten the diode D6, and the diode D6 is connected in parallel to the source terminal and the drain terminal of the MOSFET M5. Similarly, the resistor R6 and the capacitor C8 are coupled in parallel with the diode D7, and the diode D7 is coupled in parallel with the source terminal and the 汲 terminal of the MOSFET Μ6. The gate nodes of Μ5 and Μ6 are individually connected to the node Ν4 via resistors R7 and R8. The inductor coil 14 is coupled to the center tap node Ν5; the capacitors C9, CIO, and C11 are connected in parallel between the inductor coil 14 and the node N4. The secondary rectification and filtering circuit 425 is also provided with two secondary MOSFETs S M7, M8. The gates of the MOSFETs M7 and M8 are connected to each other. The source nodes of MOSFETS M7 and M8 are respectively connected to the gate nodes of MOSFETS M5 and M6, and the 汲 nodes of MOSFETS M7 and M8 are respectively connected to the 汲 nodes of MOSFETS M5 and M6. The secondary MOSFETs M7, M8 can be implemented, for example, using the IRF6603 DirectFET MOSFETs as a self-driven synchronous rectification topology. _831; " '2.. Oi" ^ The one-person bias circuit 420 includes a secondary bias wiring I5 that is magnetically coupled to the primary bias wiring 12 of the human bias circuit 43A. The diodes D8 and D9 are connected in series between the node N4 and the node N6, the capacitor C12 is connected to the node N7, the bias wiring 15 is connected between the capacitor c12 and the node N4, and the resistor R8 is connected in series with the adder. The diode D10 is connected between the nodes N6 and N4 and the package C13 and the resistor R9 are connected in parallel between the node N4 and the gates of the MOSFETs Μ?, M8. In this manner, the secondary bias circuit 420 is designed to allow the output terminals of the two busbar converters to be connected in parallel, operating separately from different nominal input voltages. Thus, even when one of the two busbar converters fails, the secondary biasing circuit 42〇 allows the half bridge converter circuit 405 to continue operating. Referring now to Figure 7, the front and back sides of an exemplary power board 7〇5 in accordance with the present invention are shown. The power board is on the 1/8 converter BMP profile and can deliver 150 watts to an output voltage of 8 volts over 96% efficiency. This efficiency is 3 to 5% more efficient and 15 50% smaller than the well-regulated power converter mounted on the board. In order to reduce the power consumption of the printed circuit board (PCB), the power board 7〇5 is composed of a multi-layer PCB board, for example, an 8-layer PCB board. The top and bottom layers, for example, contain 2 ounces of copper and the inner 6 layers contain, for example, 4 ounces of copper. The power board 7〇5 also includes a transformer having a flat PQ core that provides isolation of the voltage converter between the primary open loop inverting circuit 410 and the secondary rectifying and filtering circuit 425. The core of the transformer can be selected according to the maximum input voltage and frequency. FR3 materials can be used for low frequency loss at high frequencies. The extremely small air gap of the transformer can be set to reduce the open time of the primary MOSFETs Μ1, M2 during optical loading. A small 160 ηΗ output inductor with a gas PM 1 house meter can be used to limit the output and ripple current ripple to less than 4 amps. 12 The Half-Bridge Controller IC 415 is operative to provide high-side and low-side drive signals to the primary driver MOSFETS Ml, M2 with a 50% duty cycle and a minimum of external components. The gate drive capability of the half-bridge controller IC 415 is optimized to directly drive the next-generation power MOSFETs Ml, M2 without any additional drivers or buffers. Even though the example circuit of Figure 4 is implemented using the VW's nominal input voltage, the high-end nominal input voltage of 32 〇 can be as high as, for example, 1 volt. This architecture therefore allows for a wide range of nominal input voltage ranges for telecommunications, networking, and computing applications, such as 24 volts to 48 volts. In addition, the primary terminal bias can further optimize circuit performance in, for example, 1 (M 5 volt range). The difference in pulse width between the high-side drive signal and the low-end drive signal must be less than a predetermined threshold, such as less than 25 nanoseconds. In order to prevent the imbalance of magnetic flux, magnetic flux imbalance may be a problem in some applications. The switching frequency and neutral time between the high-end drive signal and the low-end drive signal can be adjusted for different applications by adjusting the resistor R1 value and capacitor. The value changes. The switching frequency is determined by the following equation: s 2RjC2 The external resistor R1 and the capacitor €2 also determine the neutral time between the high-end drive signal and the low-end drive nickname. Referring now to Figure 5, a graph is shown. When the specific capacitance value of capacitor C2 is not specified, the relationship between the value of the resistor and the neutral time. The neutral time must be longer than the primary end ]5]?]£1^]^1, M2. In order to prevent the shoot trough current, the off-time of the primary power MOSFET can be estimated by the following formula:

T〇ff - !δ where Qgd is the opening of the M0SFET to the 汲 charge (that is, the "Miller" charge guangqing. For the threshold voltage and (4) the driver current. In the neutral time, two *M0SFETS M7, The body diode guide 5 [the mouth must be set as short as possible to obtain the maximum efficiency of the same time.] The same % still provides enough time for the primary end M〇SFETS]v^, M2 can deteriorate Under the operating conditions, the circuit is broken. Now, according to Figure 6 of the tea photo, the example of the half-bridge controller ic 4ΐ5 φ of Figure 4 is shown. The whole system (four) is still biased by the bias of the 6th position of the 6th position. (eg 1 ! to 5 volts) operation. The half-bridge controller includes the voltage under-lock (uVL〇) blocks 6〇5, 650 for Vcc and Vb respectively. The under-voltage lockout function ensures that all timing signals are guaranteed. Maintained within specifications. Oscillation benefit block 615 provides a simulated 555 signal S1 with a 5〇% duty cycle. The internal soft-start block 63〇 ensures signal illusion, illusion, and a 15 duty cycle progressively increased from 0 to 50%. In this way, it is convenient to inject electric power during starting, and the low-end drivers 655, 66〇 For example, the mqsfeTS 665, 670, 675, and 680 can provide, for example, 1 amp current to the high-side and low-side driver signals (HO), (LO). The half-bridge controller IC 415 also passes through the current sources 64〇, 645, and MOSFETS 690. 695 includes a current limiting function. 20 As mentioned above, the half bridge controller 1C 415 can be used to control an unregulated isolated DC busbar converter for open loop operation, for example, a 48 volt secondary built-in power distribution. The system uses a spent DC bus converter. The half-bridge control state 1C 415 is optimized for performance, simplification and cost. The whole control is 14 1293831 ;.;84Γ2; 〇''4^ J ·, —— now Mai Zhao Figure 9 shows an example full bridge converted to the circuit 9〇〇 for the BMp power module 3〇5 of Fig. 3. The full bridge converter circuit 9〇〇 includes an open loop inverting circuit 910, a primary bias current The circuit 915 and the secondary rectification and filtering 5 wave circuit 425. The primary open circuit inverting circuit 91A includes a primary bridge controller Ic 905 having terminals (CS), (D), (CT), (Gl), (LOl) ), (Vcc), (VB1), (HOI), (VS1), (G2), (L02), (VS2), (H 02) and (VB2). The diode D11 is connected between the Vcc and the terminal (VB1) of the controller 圯905; the two-pole 10 body D12 is connected to the Vcc and the controller 1 (: 9〇5 terminal (VB2) The resistor R1 is connected between Vdd and the terminal (CT) of the controller 1<:: 9〇5; the capacitor a is connected between the terminal (G1) and (G) of the Vdd and the controller ic 905; the capacitor C2 It is connected between the terminal (CT) of the controller ic 905 and the ground potential. Capacitor C15 is connected between terminals (VM) and (VS1) of controller iC 9〇5; terminal (Vcc) 15 is connected to Vcc; capacitors C17 and C18 are connected in parallel to 48 volts of input voltage 320 and ground potential. The capacitor ci6 is connected between the terminals (VS2) and (VB2) of the controller 1C 905. An open loop inverting circuit 905 also includes power MOSFETs M9, M10, MU, M12 (eg four IRF6603 30 volts n_channel DirectFEir power MOSFETS) 〇20 MOSFETS M9, M10 and Μη, M12 in the full bridge configuration state are connected to each other' The junctions are respectively connected to nodes Ν9, Ν10 and between the 48 volt nominal input voltage 320* and the ground potential. The node Ν9 is also connected to the terminal (VS1) of the controller 1C 905 and the node Ν10 is also connected to the terminal of the controller 1 (: 905 (VS2). The gates of the MOSFETs Μ9'Μ10, Μ11, Μ12 are respectively connected to the terminals (H〇 l), (L01), 15 1293831, n〇4 j (H02), (L02). Primary wiring 17 is connected between nodes N9 and N10

The primary bias circuit 915 includes primary bias MOSFETs M15, M16; the resistors R16 and R17 are connected in parallel between the 48 volt nominal input voltage 320 and the MOSFET S M15; the resistor R18 is connected in parallel to the 48 volt nominal 5 mesh input voltage 320. Between the MOSFETs M4 and the series connection, the Zener diodes D13 and D14 are connected between the resistor R18 and the ground potential; the diode D15 is connected to the MOSFETS M16; the sub-bias wiring 19 is connected to the diode D15 and Between the ground potentials; the resistor R14 and the capacitor C22 are connected in parallel between the terminal (CS) of the controller 1C 905 and the ground potential; the resistors R15 and R13 are connected in series 10 to the terminal of the node Nil at the controller IC 905 ( Between CS) and ground potential; resistor R19 is connected between terminals (CS) and (rm) of controller IC 905; diodes D16 and D17 connected in series are connected between node Nil and ground potential; The diodes D18 and D19 are connected between the node Nil and the ground potential; and the coil 110 is connected between the diodes Di6 and D17 and the D18 and 15D19 connected in series.

The secondary rectification and filtering circuit 920 includes a secondary wiring ill that is magnetically coupled to the primary winding Γ7 of the primary open loop inverting circuit 910. The secondary wiring in is connected between the MOSFETs M17 and M18, and the MOSFETs M17 and M18 are coupled to each other at the node N12. The gates 20 of the MOSFETs M17 and M18 are connected to the node N12 via resistors R11 and R10, respectively. The inductance measuring coil 18 is coupled to the center tap node N13, and the capacitors C19, C20, and C21 are connected in parallel between the inductor coil 18 and the node N12. The secondary rectification and filtering circuit 425 is also provided with two secondary MOSFETs S13, M14. The gate nodes of the MOSFETs 1^13 and 1^14 are connected to each other. The diode 〇20 and the capacitor (: 23 16 Η - the 丨 are connected in parallel between the gates of the MOSFETs Μ13 and Μ14 and the node N12. The resistor R12 is connected to the gates and coils 18 of the MOSFETs M13 and M14. The source nodes of MOSFETS M13 and M14 are respectively connected to the gates of MOSFETS M17 and M18; and the node nodes of MOSFETS M13 and M14 are respectively connected to the 汲 nodes of MOSFETS M17 and M18.

The secondary MOSFETs M13, M14 can be implemented, for example, using the IRF6603 DirectFET MOSFETs as a self-driven synchronous rectification topology. The full bridge controller and driver 1C 905 is similar to the half bridge controller 415 of Figure 4, but with an improved current limiting function and elastic soft start capability. The current limiting function has a hiccup mode in which the snoring period can be controlled by an external capacitor. The primary current is sensed using a current transformer. The current transformer has a south resistance ratio, such as a resistance ratio of 15 0 to 1. The sensed AC current information is rectified and then provided as an input signal to the current sense pin (CS) of the driver IC 905 after RC filtering. Since the controller 1C 905 is designed as a full bridge circuit, four gate drive signals for MOSFETS M9, M10, Mil, and M12 are provided, respectively. Each branch controller is alternately turned on with a 50% duty cycle. The difference in the conduction period between the two branches must be less than, for example, 25 nanoseconds to prevent the imbalance of the magnetic flux. The turn-on and turn-off timing difference between the two MOSFETs must also be less than 25 nanoseconds. Referring now to Figure 10, there is shown a line graph showing the output voltage waveform of the snoring mode with a current limit of 21 amps, a current load setting of 22 amps, and a nominal input voltage of volts. As shown in Fig. ίο, control cry 1 (:;:9〇5 once attempting to turn on the converter at a predetermined time. For example, the predetermined time can be, for example, via the value of 黎魏 31 94 g: 04 Ί > - the cargo adjustment capacitor C14 Set to, for example, 5 milliseconds 10 15 20

The Half Bridge Controller 1C 415 and the Full Bridge Controller IC 9〇5 are designed to allow external synchronization to be easily achieved across the SAR frequency range. In order to achieve this, the timing resistor R1 must be removed, and the timing capacitor C2 is coupled between the Ic 415, 905 and the external synchronization source, as shown in FIG. In the self-oscillating mode, the timing capacitor is charged by an external timing resistor. When the (CT) terminal voltage of the ic 415, 905 is higher than a predetermined threshold, for example, the half-day of the supply voltage Vcc or Vdd, the internal drive of the controller ICs 415, 9〇5 starts to discharge the timer f. After the voltage of the terminal ((3) is lower than a predetermined threshold, such as the power supply voltage 乂 "or one-fifth of this, the controller = 405, 905 can be used to cancel the internal capacitor, and the discharge of the timing capacitor C2 is suspended, thus flowing through The current of the resistor R1 starts to charge the capacitor C2 again.

In the synchronous operation mode, the external capacitor C2 engages the rising edge of the external synchronization source to the (CT) terminal. When the voltage of the terminal (CT) is above a predetermined threshold, such as half of the ic supply voltage, the internal driving of the controller IC 415, 9〇5 begins to cry at the terminal (ct) discharge voltage. #为料(CT) The voltage system is lower than the = limit value, for example, 1C 415, 905, the power supply voltage is five-points, IC, power and electricity. When negative is applied, the internal diode resets the voltage at the terminal (CT) and maintains the electrical (four) volts across the external ~ container C2. When the electrical layer across the external timing capacitor (4) reaches 〇, the capacitor is prepared for a secret-external positive pulse. In (5) modulo 'vacuum solar phase only terminal (the impedance of (7) is determined, and the capacitance of the # chronograph capacitor C2 is determined. 1 Therefore, the limit is the most self-vibrating mode, and the chronograph resistor R1 cannot be too low 18 'y4. r .2 — high frequency of operation. Usually the timing resistor R1 must be higher than the predetermined value, for example, 2 kilo ohms. The lower the resistance value of the resistor R1, the higher the collection current of the internal discharge driver of the Belle 1C 415, 905. In the mode, the timing resistor R1 is removed, so that a higher operating frequency can be achieved. The maximum operating frequency of the synchronous mode is determined by the power dissipation caused by driving the external primary MOSFETS. I: Simple illustration of the figure 3 A block diagram showing a conventional secondary power conversion architecture. Figure 2 is a block diagram showing basic secondary power conversion in accordance with the present invention.

Architecture. 10 is a block diagram showing a first example power conversion architecture in accordance with the present invention. Figure 4 is a diagram showing an example power conversion circuit for a power module mounted on a board in accordance with the present invention. Figure 5 is a line diagram showing the neutral time of the half bridge driver 1C in accordance with the present invention. Fig. 6 is a block diagram of the half bridge driver 1C of Fig. 4.

Figure 7 is an illustration of the front and rear of an exemplary power conversion panel in accordance with the present invention. Figure 8 is a line graph showing the power conversion efficiency relative to the output load. Fig. 9 is a diagram showing another example of a power conversion circuit of a power module mounted on a board according to the present invention. Figure 10 is a line graph showing the snoring waveform. Figure 11 shows two methods for the half-bridge driver 1C group of Figure 4 19 〇 4. 2. 〇 4 < 曰 _ self-resonance mode or synchronous mode operation [the main component symbol of the figure Table 105a-n···Power converters 〇an, 215a-n··load point power converters 205, 325... intermediate bus voltage 210··· converter 300...half bridge secondary power conversion architecture 305 ...the power module 310a-n installed on the board...the load point converter 320...the name input voltage 330a-n··the point voltage 405···the half bridge converter circuit 410,910----open Loop inverting circuit 415···half bridge controller iC 420...secondary bias circuit

425...Secondary rectification and filtering circuit 430, 915...primary bias circuit 435···double FET package 605, 650. "UVLO block 610...biasing block 615...oscillator block 630···internal soft start Blocks 640, 645... Current source 655... High-end driver 660... Low-end driver 665-680·--MOSFETS 705... Power board 900... Full-bridge converter circuit 905----Second full bridge controller 1C

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Claims (1)

1293831 Pickup, patent application scope: L A power conversion circuit comprising: an unregulated isolated power module mounted on the board, operable to convert the nominal input voltage into an intermediate bus voltage, the isolated The power module mounted on the board can be controlled in an open loop; and a plurality of closely regulated load point converters are operable to convert the intermediate bus voltage into individual load point voltages and supply power to a plurality of individual loads . 2. The power conversion circuit of claim 1, wherein the power module mounted on the board comprises a primary open loop inverting circuit, a primary bias circuit, a secondary synchronous rectification and filtering circuit, and a Secondary bias circuits are magnetically coupled to each other, and the synchronous rectification and filtering circuit can generate the intermediate bus voltage. 3. The power conversion circuit of claim 2, wherein the primary open loop inverter circuit comprises a half bridge controller 1C and a pair of MOSFETs connected in a half bridge assembly state, the controller 1C being operable to 50 The % duty cycle alternately controls the pair of MOSFETs. 4. The power conversion circuit of claim 3, wherein the _ times open loop inverter circuit comprises a timing resistor and a timing capacitor, and a neutral time of the controller 1C and a switching frequency are according to the timing The value of the resistor and timing capacitor is adjusted. 5. The power conversion circuit of claim 4, wherein the switching frequency is determined by the following equation bl/QRA), where fs is the switching frequency, Ri is the value of the timing resistor 21 1293831, and c2 is the value of the timing capacitor. . 6. The power conversion circuit of claim 3, wherein the pair of MOSFETs comprises DirectFETs. 7. The power conversion circuit of claim 3, wherein the half bridge controller 1C is operable in at least two modes, one of which is a self-oscillating mode and the other of which is a synchronous mode. 8. The power conversion circuit of claim 2, wherein the primary open loop inverter circuit comprises a full bridge controller 1C and two pairs of MOSFETs connected in a full bridge configuration state, the controller 1C being operable to 50 The two pairs of MOSFETs are alternately controlled by the % 10 duty cycle. 9. The power conversion circuit of claim 8, wherein the one open loop inverting circuit comprises a timing resistor and a timing capacitor, and one of the full bridge controller 1C has a neutral time and a switching frequency according to the The value of the timing resistor and the timing capacitor is adjusted. 15 10. The power conversion circuit of claim 9 wherein the switching frequency is determined by the following equation: fs=l/(2RiC2), where fs is the switching frequency, Ri is the tenth time resistor value, and C2 is The value of the timing capacitor. 11. The power conversion circuit of claim 8, wherein the two pairs of 20 MOSFETs comprise DirectFETs 〇 12. The power conversion circuit of claim 8 wherein the full bridge controller 1C can operate in at least two modes One of the modes is a self-oscillating mode, and the other mode is a synchronous mode. 13. A half-bridge controller 1C for a power conversion circuit, comprising a power module mounted on a board by 22 1293831, which is operable on the board: the power of the board: v_ is replaced by An intermediate busbar voltage; the two sets of tightly-tuned can be controlled by the in-service loop; and the plurality of tightly-converted, point-to-turn converters that are operable to supply the intermediate busbar voltage bridge control point voltages to a plurality of Individual load, the half i: circuit 'which can generate a bias voltage county to operate the half bridge control insufficient house lock circuit, which is operable to monitor the power supply pin of the half bridge controller 10 IC; a vibrator The circuit can provide a timing signal with a _% guard cycle; a soft start circuit ensures that the duty cycle of the timing signal is gradually increased from 〇 to 5G% duty cycle 俾 during the start-up period to facilitate the thirsty current; The driver and the low-side driver provide a driving signal to control a m〇sFETs that are connected to each other for a half-bridge configuration state. The half-bridge controller 1C alternately controls the MOSFETs with a 50% duty cycle. 20 14. The half-bridge controller ic of claim 13 wherein the MOSFETS comprises a pair of DirectFETs. 15. A power conversion circuit comprising: an unregulated isolated power module mounted on a board operable to convert a target input voltage into an intermediate bus voltage, the 23 1293831, And the power module on the board can be open loop control, and the power module installed on the board that is not isolated for one week includes half bridge control $ic 'the half bridge control (4) includes - bias circuit , which can generate a bias voltage to operate the half-bridge controller ic, and the insufficient voltage lockout circuit is operable to monitor the half-bridge controller 1 (the power supply pin of the power supply), which can be provided with 5G%oi cycle time ##, a soft start circuit, 俾 ensure that the duty cycle of the timing signal is progressively transferred to 50% duty cycle, easy to sink current during start-up, and the rear drive and low-end driver, MOSFETProvide MOSFET driver 10 to control a MOSFETS that is connected to each other for the half-bridge configuration state. The half-bridge controller IC alternately controls the MOSFETS with a 5〇% duty cycle; and a plurality of closely-regulated negatives. A load point converter operable to convert the intermediate bus voltage into individual load point voltages and to supply a plurality of individual loads. 16 A power conversion circuit according to claim 15 wherein the device is mounted on the board. The power module includes a primary open loop inverting circuit, a primary biasing circuit, a secondary rectifying and filtering circuit, and a secondary biasing circuit, the primary open loop inverting circuit is magnetically coupled to the second 20 times rectification and chopper circuit, the primary bias circuit is magnetically coupled to the secondary bias circuit, and the secondary rectification and filtering circuit can generate the intermediate bus voltage. 17· The power conversion circuit of the item, wherein the one-time open loop inverting circuit comprises a timing resistor and a timing capacitor 24 1293831, and one of the controller ic neutral time and a switching frequency can be based on the timing resistor and the timing capacitor 18. The power conversion circuit of claim 17, wherein the switching frequency is determined by the following equation: 5 6=1/(21(^), where fs is the switching frequency Rate, & is the value of the timing resistor and C2 is the value of the timing capacitor. 19. The power conversion circuit of claim 16 wherein the pair of MOSFETs comprises DirectFETs. 20. Power conversion as in claim 16 The circuit, wherein the half bridge controller 1C can operate in at least two modes, one of which is a self-oscillating mode and the other of which is a synchronous mode. 25 1293831 /! j )r -r. / Μ Please.Is,11 substance ο 21 41- Γ ΐ 鼹 丄§ G 5 20 , 215a Open X2l5b 215η 1293831 ‘Boom/Supplement 2/10 酦ε kneeιητ—ε 12细1 柒, designated representative figure: (1) The representative representative figure of this case is: (3) Figure (2) The representative symbol of the representative figure is a simple description: 300···Half Bridge Level Power conversion architecture 305... Power module 310a-n installed on the board. Point-of-load converter 320...Name input voltage 325···Intermediate bus voltage 330a-n···Load point voltage捌, if there is a chemical formula in this case When revealing the chemical formula that best shows the characteristics of the invention: