TWI293178B - Signal line structure being used on flat display panel and flat display panel - Google Patents

Description

!293178 The equivalent resistance values are substantially equal. The first output terminal and the second output end are respectively configured to output a first signal and a number 'flat display panel, including: a substrate according to the purpose of the present invention, and further, a flat display panel is provided by a signal output device The driven 'signal wheel out of the assembly has the first output and the second output': the signal and a signal line group check the main 丄... ---- one ~, / into the current deep group. The denier region is formed on the substrate. The pixel area has a first receiving end and a second receiving end, and the first receiving end and the second receiving end are respectively configured to receive the first signal and the first signal. The signal line group is electrically connected to the signal output device and the pixel area. The signal line group includes: a first main signal line and a: main signal line. The first main signal line is formed of a first metal material. The third main signal line is formed by the first __ metal material. The first auxiliary signal line is formed by the second metal material and electrically connected to the first main signal line to form a first path. The second auxiliary signal line is formed by the second metal material and electrically connected to the second main signal line to form a second path. The overall equivalent resistance value of the first path is substantially equal to the overall equivalent resistance value of the second path. The above described objects, features, and advantages of the present invention will become more apparent and understood from the following description. Referring to FIG. 2A and FIG. 2B , FIG. 2A is a schematic diagram of a signal line group used in a flat display panel according to a first embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along line 2A of FIG. 2A. 2Β, the section view. The flat display panel 2 is driven by a signal output device 204 (data driver or gate driver). 1293178 The flat display panel 200 is, for example, a liquid crystal display panel, and includes: a substrate 2, a pixel area 206, and a signal line group 208. The signal line group 208 includes a plurality of - and auxiliary signal lines. Please refer to... The main signal line is formed by the first gold material, which is arranged in parallel on the substrate 2〇2, and the auxiliary signal line is formed by the second metal material 212, which is substantially parallel to the main signal line. Configuration. The signal output device _ is electrically connected to the first metal material 210, and the signal output device 2〇4 has a first output terminal 2〇4a and a second output terminal 2〇4b, and the first output terminal 2〇牦 and the second output terminal 2 The servants are each used to output the first signal S1 and the second signal S2. The pixel region 2〇6 is formed on the earth plate 210. The pixel region 206 has a first receiving end 206a and a second receiving end 206b. The receiving end 206a and the second receiving end 206b are, for example, one end of a scanning line or a data line. The first receiving end 206a and the second receiving end 206b are configured to respectively receive the first signal S1 and the second signal S2 output by the first output end 204a and the second output end 204b, and the first output end 2〇4a and the second end The output terminal 2 is the output pin of the driving chip of the liquid crystal display panel. The pixels of the pixel area 206 are driven by the first message 5 Tiger S1 and the second signal § 2. As shown in Fig. 2A, the signal line group 208 includes a plurality of main signal lines and auxiliary signal lines. The two main signal lines and two auxiliary signal lines will be taken as an example to illustrate the present invention. The signal line group 208 includes: a first main signal line 208a, a second main signal line 208b, a first auxiliary signal line 222, a second auxiliary signal line 226, two first through holes 223a and 223b, and two second Through holes 22乜 and 224b. The first main signal line 2〇8a· and the second main signal line 208b are formed by the first metal material 210. The first main message 5 is connected to the first output terminal 2〇4a and the first receiving terminal 2〇6a, and the second main signal-line 208b is connected to the second output terminal 2〇41) and the second receiving terminal 206b. The first main signal line 208a, the first auxiliary signal line 222 and the first through holes 223 & 223 and 223b are electrically connected to form a first path. The second main signal line 208b, the second auxiliary signal line 226 and the second penetration holes 224a and 224b are electrically connected to form a second path. The lengths of the first main signal line 9 1293178 208a and the second main signal line 208b are not equal. The first auxiliary signal line 222 and the second auxiliary signal line 226 are formed by the second metal material 212. The first through-holes 223a and 223b are disposed on the first main signal line 208a for electrically connecting the first main signal line 208a and the first auxiliary signal line 222. The two second through holes 224a and 224b are disposed on the second main signal line 208b for electrically connecting the second main signal line 208b and the second auxiliary signal line 226. The equivalent resistance values of the two first penetration holes 223a and 223b and the first auxiliary signal line 222 are not equal to the equivalent resistance values of the two second penetration holes 224a and 224b and the second auxiliary signal line 226. The distance between the two first penetration holes 223a and 223b is not equal to the distance between the two second penetration holes 224a and 224b. The first main signal line 208a, the second main signal line 208b, the first auxiliary signal line 222, and the second auxiliary signal line 226 are metal wires. Please refer to FIG. 2C, which shows an equivalent circuit diagram of a part of the signal line group in FIG. 2A. Rla is a resistance value between the first output terminal 204a and the first penetration hole 223a, and R2a is a resistance value between the second output terminal 204b and the second penetration hole 224a. Rib is the resistance value of the first main signal line 208a between the first penetration holes 223a, 223b, and R2b is the resistance value of the second main signal line 208b between the second penetration holes 224a, 224b. Rlc is a resistance value between the first through hole 223b to the first receiving end 206a, and R2c is a resistance value between the second through hole 224b to the second receiving end 206b. Rid is the resistance value of the first penetration hole 223a, Rle is the resistance value of the first penetration hole 223b, R2d is the resistance value of the second penetration hole 224a, and R2e is the resistance of the second penetration hole 224b. value. Rif is the resistance value between the first auxiliary signal line 222 between the first penetration hole 223a and the first penetration hole 223b, and R2f is the second auxiliary signal line 226 located at the second penetration hole 224a and the second penetration hole. The resistance between 224b. Rib is connected in parallel with Rid, Rif and Rle and is connected in series with Rla and Rlc. R2b is connected in parallel with R2d, R2f and R2e and in series with R2a and R2c. In the first embodiment, the length of the first main signal line 208a is greater than the second main signal line 208b, and the distance between the first penetration holes 223a and 223b is greater than the distance between the second penetration holes 224a and 224b. The effective resistance length of the first auxiliary signal line 222 is greater than the length of the second auxiliary signal line 226. By adjusting the length of the first auxiliary signal line 222 and the length of the second auxiliary signal line 226, the first main signal line 208a, the two first through holes 223a and 223b, and the first auxiliary signal line 222 can be integrated. The effective resistance value (first path) is substantially equal to the overall equivalent resistance value of the second main signal line 208b, the two second penetration holes 224a and 224b, and the second auxiliary signal line 226 (second path). As shown in the following formula 1. Thus, when the first signal S1 is transmitted through the first main signal line 208a and the first auxiliary signal line 222, and the second signal S2 is transmitted through the second main signal line 208b and the second auxiliary signal line 226, the first signal S1 It has substantially the same signal delay as the second signal S2. In this way, the image quality of the display panel will be effectively improved. In this embodiment, the first path may be formed only by the first main signal line and the first auxiliary signal line. The second main signal line and the second auxiliary signal line form a second path, and the equivalent resistance values of the first path and the second path are substantially changed by changing resistance values of the first auxiliary signal line and the second auxiliary signal line equal.

Rla+Rlb(Rld+Rle+Rlf)/(Rlb+Rld+Rle+Rlf)+Rlc= R2a+R2b(R2d+R2e+R2f)/(R2b+R2d+R2e+R2f)+R2c (Formula 1) For the second embodiment, please refer to FIG. 3A, which illustrates a schematic diagram of a signal line group used in a flat display panel according to a second embodiment. The signal line group 308 includes: a first main signal line 308a, a second main signal line 308b, a first auxiliary signal line 322 having a first line segment 371a and a second line segment 371b, and a third line segment 371c and a fourth line segment 37Id. The second auxiliary signal line 326, the two first penetration holes 323a and 323b and the two second penetration holes 324a and 324b. In this embodiment, the first path is formed by the first main signal line 308a, and the first line segment 371a and the second line segment 371b are electrically connected to the two first through holes 323a and 323b. The second path is formed by the second main signal line 308b, the third line segment 11 1293178 371c, and the fourth line segment 371d being electrically connected to the two second through holes 324a and 324b. The second embodiment is different from the first embodiment in that, as shown in FIG. 3A, the distance between the two first penetration holes 323a and 323b of the second embodiment is smaller than that of the two second penetration holes 324a and 324b. The first through holes 323a and 323b and the second through holes 324a and 324b are respectively disposed at an intermediate portion between the first main signal line 308a and the second main signal line 308b. That is, the two first through holes 323a and 323b are disposed between the two ends of the first main signal line 308a, and the two second through holes 324a and 324b are disposed at the two ends of the second main signal line 308b. The distance between the two first penetration holes 323a and 323b is smaller than the distance between the two second penetration holes 324a and 324b. The first auxiliary signal line 322 has a first line segment 371a and a second line segment 371b. The second auxiliary signal line 326 has a third line segment 371c and a fourth line segment 371d. One end of the first line segment 371a and the second line segment 371b are electrically connected to the first output end 304a and the first receiving end 306a, respectively, and the other ends of the first line segment 371a and the second line segment 371b are respectively separated from the first one. The through holes 323a and 323b are electrically connected. One end of the third line segment 371c and the fourth line segment 371d are electrically connected to the second output end 304b and the second receiving end 306b, respectively, and the third line segment 371c and the fourth line segment 371d are respectively connected. One end is electrically connected to the two second penetration holes 324a and 324b, respectively. The difference between the length of the first main signal line 308a and the first auxiliary signal line 322 is smaller than the length difference between the second main signal line 308b and the second auxiliary signal line 326. Please refer to both Figures 3A and 3B. Fig. 3B is a cross-sectional view taken along line 3B-3B' of Fig. 3A. As shown in Fig. 3B, the substrate 302 has a first metal material 310 forming a main signal line, and the first metal material 310 is provided with a second metal material 312 forming an auxiliary signal line. The first metal material 310 and the second metal material 312 are electrically connected by two first through holes 323a and 323b. Please refer to FIG. 3C, and FIG. 3C shows an equivalent circuit diagram of a part of the signal line group in FIG. 3A. In FIG. 3C, Rla is the resistance between the first output terminal 304a and the first through hole 323a in the first main signal line 308a, and 12 1293178 R2a is the output of the second main signal line 308b. Know the resistance between the 304b and the second penetration hole 324a. Rib is the resistance value between the first main signal line 308a between the first penetration holes 323a and 323b, and R2b is the resistance value between the second main signal line 308b and the second penetration holes 324a and 324b. Rlc is a resistance value between the first through hole 323b and the first receiving end 306a of the first main signal line 308a, and R2c is a resistance between the second through hole 324b and the second receiving end 306b of the second main signal line 308b. value. Rid is the resistance value of the first auxiliary signal line 322 from the first output end 304a to the first through hole 323a. R2d is the resistance value of the second auxiliary signal line 326 from the second output end 304b to the second through hole 324a. Rle and Rif are resistance values of the first penetration holes 323a and 323b, respectively. R2e and R2f are resistance values of the second penetration holes 324a and 324b, respectively. Rig is the resistance value of the first auxiliary signal line 322 from the first through hole 323b to the first receiving end 306a, and R2g is the resistance of the second auxiliary signal line 326 from the second through hole 324b to the second receiving end 306b. value. As shown in Fig. 3C, R1a is connected in parallel with Rid and Rle, Rlc is connected in parallel with Rif and Rig, and is connected in series with Rib. R2a is connected in parallel with R2d and R2e, and R2c is connected in parallel with R2f and R2g and in series with R2b. By adjusting the lengths of the two line segments of the first auxiliary signal line 322 and adjusting the lengths of the two line segments of the second auxiliary signal line 326, the first main signal line 3 0 8 a and the two first through holes 323a can be made. And an overall equivalent resistance value of the 323b and the first auxiliary signal line 322 (first path), and the second main signal line 308b, the two second penetration holes 324a and 324b, and the second auxiliary signal line 326 (second path) The overall equivalent resistance values are substantially equal, as shown in Equation 2 below:

Rla(Rld+Rle)/(Rla+Rld+Rle)+Rlc(Rlf+Rlg)/(Rlc+Rlf+Rlg)+R lb= R2a(R2d+R2e)/(R2a+R2d+R2e)+R2c( R2f+R2g)/(R2c+R2f+R2g)+R 2b (Formula 2) 13 1293178 Second Embodiment Please refer to FIG. 4A and FIG. 4B simultaneously, and FIG. 4A illustrates the use of the third embodiment in the plane. A schematic diagram of the signal line group of the display panel. Fig. 4B is a cross-sectional view taken along line 4B-4B of Fig. 4A. Different from the first embodiment, the third embodiment further includes a first indium tin oxide (ITO) signal line 414a and a second indium tin oxide signal line 414b, which are respectively disposed on the first main The signal line 408a is above the two first penetration holes and the second main signal line 4〇8b is above the two second penetration holes. The first indium tin oxide signal line 414a and the second indium tin oxide signal line 414b are respectively passed through the two first through holes 423a, 423b and the two second through holes 424a and 424b and the first main signal line 408a. The first auxiliary signal line 422 and the second main signal line 408b and the second auxiliary signal line 426 are electrically connected. That is, the first path of the embodiment includes a first main signal line 408a, a first auxiliary signal line 422, two first through holes 423a and 423b, and a first indium tin oxide signal line 414a. The second path includes a second main signal line 408b, a second auxiliary signal line 426, two second through holes 424a and 424b, and a second indium tin oxide signal line 414b. The first main signal line 408a, the two first through holes 423a and 423b, the first auxiliary signal line 422 and the first indium tin oxide signal line 414a have an overall equivalent resistance value (first path), and the second main The overall equivalent resistance values of the signal line 408b, the two second penetration holes 424a and 424b, the second auxiliary signal line 426 and the second indium tin oxide signal line 414b (second path) are substantially equal. As shown in FIG. 4B, the first indium tin oxide signal line 414a is disposed above the first metal material 410 forming the main signal line and the second metal material 412 forming the auxiliary signal line, and passes through the first through hole 423a. And 423b are electrically connected to the first metal material 410 / and the second metal material 412. Fourth Embodiment Referring to Figure 4C, there is shown a diagram of a portion of the signal 14 1293178 of the fourth embodiment of the present invention. Different from the second embodiment, in this embodiment, the first metal material 310 in the second embodiment may be disposed with an indium tin oxide signal line (Ιτ〇: signal line) 420 between the two through holes, and may also be The equivalent resistance values mentioned in the above embodiments are the same. The planar m-display panel disclosed in the above embodiment of the present invention, in the signal line group, although the resistance values of the first main signal line and the second main signal line are different, but the first auxiliary signal line and the second part are configured a through hole in the first main signal line and the second auxiliary signal line and the second second through hole on the second main signal line, so that the first main signal line, the first auxiliary signal line and the two first wearing The overall equivalent resistance value of the through hole (first path) is the same as the equivalent electric resistance value of the second main signal line, the second auxiliary signal line, and the two second penetration holes (second path). In the process, no additional changes can be made to solve the problem of poor imaging due to different signal delays, and the competitiveness of the flat display panel is improved. In view of the above, the present invention has been described above in terms of a preferred embodiment, and is not intended to limit the invention, and various modifications may be made without departing from the spirit and scope of the invention. And the refinement, and therefore the protection of the present invention is defined by the scope of the patent application. [Simple Description of the Drawing] Fig. 1 is a schematic view showing the connection of a wafer and a pixel region. 2A is a schematic diagram showing a signal line group used in a flat display panel according to a first embodiment of the present invention. Fig. 2B is a cross-sectional view taken along line 2B_2B of Fig. 2A. Figure 2C shows an equivalent circuit diagram of a partial signal line group. FIG. 3A is a schematic diagram showing the signal line group used in the flat display panel of the second embodiment. 3B is a cross-sectional view taken along line 3B-3B of FIG. 3A. Figure 3C shows an equivalent circuit diagram of a portion of the signal line group of Figure 3A. 15 1293178 FIG. 4A is a schematic diagram showing the signal line group used in the flat display panel of the third embodiment. Fig. 4B is a cross-sectional view taken along line 4B-4B' of Fig. 4A. FIG. 4C is a schematic diagram showing a portion of the signal line group of the fourth embodiment. [Description of Main Component Symbols] 101: Wafers 101a, 101b, 101c, 101d: Pin 102: Alizarin Regions 102a, 102b, 102c, 102d · Receiving End 103: Metal Wires 103a, 103b, 103c, 103d: Line 200: Flat display panel 202: substrate 204, 304: signal output device 206, 306 · pixel region 208, 308 · signal line group 210, 310: first metal material 212, 312: second metal material 204a, 304a: An output terminal 204b, 304b: a second output terminal 51: a first signal 52: a second signal 206: a halogen region 206a, 306a: a first receiving end 206b, 306b: a second receiving end 1293178 208a, 308a, 408a: A main signal line 208b, 3 08b, 408b: a second main signal line 222, 322, 422 · a first auxiliary signal line 223a, 223b, 323a, 323b, 423a, 423b: a first through hole 224a, 224b, 324a , 324b, 424a, 424b · second penetration holes 226, 326, 426: second auxiliary signal line 371a · first line segment 371b: second line segment 371c: third line segment 371d · · fourth line segment 414a: Indium tin oxide signal line 414b: second indium tin oxide signal line 420: indium tin oxide signal line

Rla, R2a, Rib, R2b, Rlc, R2c, Rid, R2d, Rle R2e, Rif, R2f, Rig, R2g: resistance value

Claims (1)

1293178 Oxidation Ming Ixi Signal Continued ^ ^ #τ /» Deep /, brother - emulsified indium tin signal line, respectively, is placed on the first main signal line and the second main signal line. < 5 · The signal line structure described in the sf patent _ 4, in the middle of the 'indium: indium tin oxide signal line by the two [penetrating holes and the first - main signal line connection 'To form the first path, and the second indium tin oxide signal line is electrically connected to the second main signal line by the two second through holes, two paths. 6. The signal line structure of claim 2, wherein the first auxiliary line has a first line segment and a second line segment, and the first line segment is the second line segment - The end systems are electrically connected to the two first through holes respectively to form the first = diameter, and the second auxiliary signal line has a third line segment and a fourth line segment, the third line segment and the fourth line segment The end portions are electrically connected to the two second penetration holes respectively to form the second path. The 钤+strong type flat display panel is driven by a signal output device, and the signal has a -first output terminal and a second output terminal, and the first output terminal and the == output terminal are respectively used. Outputting the H number and the second signal, the plane display surface includes: a substrate; a mountain-pixel region formed on the substrate, the pixel region having a first connection end and a second reception end The first receiving end and the second receiving-signal line group are connected to the signal output device and the pixel. The signal line group includes: a package connection 19 1293178 a first main signal line is a first metal material Formed by: the second main signal line is formed by the first metal material; the first auxiliary signal line is formed by the second metal material, and is electrically connected to the main signal line to form the first path And the second and second second auxiliary signal lines are formed by the second metal material and electrically connected to the first main squall line to form a second path; the person in the 'the first path' (four) effect The resistance wire resistance values are substantially equal. The flat display panel of the seventh aspect of the invention, wherein the length of the first main signal line and the second main signal line are not equal. The flat display panel of claim 7, wherein the two-wire system is connected to the first output end and the first receiving end, and the first main branch line is connected to the second output. And the second receiving end. The flat display panel of the ninth aspect of the invention, wherein the system is connected to the first main signal line by at least two first through holes and the first main line, the line lightning? The first auxiliary signal line is electrically connected to the second main winding line by at least two second penetration holes. V 兮-H Please refer to the flat display panel described in the scope of claim 1G, wherein the equivalent resistance values of the II first hole and the first auxiliary signal line, and the two second teeth f and the second auxiliary signal The equivalent resistance values of the lines are not equal. 12. The flat (four) display panel according to item 1G, wherein the length of the first main signal line of 20 1293178 ° is greater than the length of the second main signal line, and the two first through holes The distance between the two second penetration holes is greater than the length of the first auxiliary signal line is greater than the length of the second auxiliary signal line. The flat display panel of claim 12, wherein the length of the first auxiliary signal line is smaller than the first main signal line, and the length of the second auxiliary signal line is smaller than the second main signal The first main signal line, the second main signal line, the first auxiliary signal line, and the second auxiliary signal line have substantially the same width. The flat display panel of claim 10, wherein the Λ line group further includes a first indium tin oxide signal line and a second indium tin oxide lanthanum line respectively disposed in the first A main signal line and the second main signal line. The flat display panel of claim 14, wherein the first emulsified indium tin signal line is electrically connected to the first main signal line by the two first through holes. Forming the _th path, and the second indium tin oxide signal line is electrically connected to the second main signal line by the two second through holes to form the jin. 16 The flat display panel of the item, wherein the first auxiliary signal line has a g, a first line segment and a second line segment, the second auxiliary signal number " line segment and - fourth line segment, the first line segment and the One of the second line segments is electrically connected to the first output end of the first output end, and the first line of the first line segment is electrically connected to the (four) four lines of the seventh through hole; The second end of the fourth line segment and the other end of the fourth line segment are electrically connected to the 21 1293178 second penetration holes respectively. 7) If the flat display panel described in claim 16 is small, the length of the main message is greater than the length of the third line. The distance between the teeth is smaller than the two. The distance between the penetrating holes. twenty two