1289878 九、發明說明： 【發明之領域】 本發明係提供一種主動光學接近修正法(aggressive 〇ptical proximity correction)，尤指一種避免直線末端緊縮效應的光學接近 修正法。 【背景說明】 為了在半導體晶片上形成一設計的積體電路(integrated circuits)，目前的半導體製程均是先製作一光罩並在光罩上形成一 0又汁的圖案，然後再藉由一微影製程來將光罩上 的圖案以一定的比例轉移(transfer)到半導體晶片表面的光阻層 上，進而將積體電路的佈局(layout)圖案順利地轉移到半導體晶片 上。因此微影製程幾可說是半導體製程中最重要的一個步驟。 然而當電路之元件尺寸日益縮小，在經過微影製程之後，晶 片表面的電路圖案與原始光罩圖案之間的差異也隨之增大，尤其 疋光學接近效應(optical proximity effect)造成之轉角圓形化(comer rounding)以及直線末端緊縮(lineendsh〇rtening)等等，是典型可以 觀察到的現象。 為了避免光學接近效應造成晶片上的圖案與光罩圖案不一 致，目前解決的方法多是利用電腦輔助設計(c〇mputer aided design， CAD)來對光罩圖案進行一光學接近修正(〇ρ—ι 以 1289878 —η，QpQ ’叫除移接奴應，缝·齡正過的光罩 圖案進灯圖案轉移此外，為因應製程線寬不斷縮小的要求，現 今的趨勢，係於該光罩圖案於晶片表面中形成之後，再對圖案化. 光p s進行d韻刻製程(咖etchi啤卿^)，俾使製程的線 寬能繼續縮減至曝光極限之下，以達成更小面積容财更多元件 的目的。 請參考圖―，圖—騎知之光學接近修正之翁流程圖。如 圖一所示’習知利用電腦輔助設計(computer aided design，⑽)進| 行之光學接近修正’是先利用一輸入裝置將光罩圖案之原始佈局 圖(ongmal layout)輸入至_之記憶體中，然後輸入光罩條件設定 值(illuminationconditions)等操作參數’以進行一光學程式計算， 模擬光罩圖案在晶片表面所形成的晶片圖案佈局圖。之後將模擬 出的晶片圖案佈局_儲存的光罩_佈局圖進行崎，當二者 圖案相符合時，亦即二者圖案之比對結果合於一容許誤差 (tolerance)時’即利用一輸出裝置將光罩圖案佈局圖輸出，並形成籲 於-透明光罩之上。若是二者_不符合，則針對比對出的不符 合部份進行鮮®案佈局圖之修改’再娜正後之光罩圖案佈局 圖作為-原始佈局圖儲存於記憶體中，並依照上述步驟重新進行 整個流程的運算迴路(calcu論nloop) ’朗晶片圖案佈局圖與修 正後之光罩圖案佈局圖的比對結果相符合。 請參考圖二及圖三，圖二及圖三是以一直線圖案為例，一原 6 1289878 始佈局圖案、該佈局圖案依序經過光阻曝光顯影(afterdevd〇pmem inspection，ADI)以及進行一修整蝕刻製程形成之晶片圖案佈局圖 之示意圖。圖二為在未經過光學接近修正的情形下，一原始佈局 圖案10以及原始佈局圖案1〇依序經過一光阻曝光顯影(^^沉 development inspection，ADI)13以及進行一修整蝕刻製程15形成之 晶片圖案佈局圖14、16之示意圖。其中原始佈局圖案1〇由於在顯 影製程13中受到光學接近效應的影響，以及後續之修整蝕刻製程 15造成之直線末端縮減效應，因此最後形成之晶片圖案佈局圖14 與原始佈局圖案10有明顯差異。圖三為利用光學接近修正後，一 佈局圖案16以及佈局圖案16依序經過一光阻曝光顯影(after development inspection，ADI)13以及進行一修整蝕刻製程15形成之 晶片圖案佈局圖18、2〇之示意圖。其巾佈局_16為圖二中之原 始佈局圖案10經過光學修正之結果，因此經過微影13與修整侧 製程15形成之晶片圖案佈局圖20與原始佈局圖案1〇差異較小。 然而，由於習知對光罩圖案進行之光學接近修正，主要是以 消除光學接近效應為目的，並未考慮該修整蝕刻製程造成之直線 末端縮減的現象，因此原始佈局圖案與實際形成之晶片圖案佈局 圖仍有相當的差異，進而產钱焦(defocus)與曝光容忍度㈣瞻e latitude，EL)降低的問題，不但使得光罩圖案嚴重失真，同時亦有 可月b因為要避免該直線末端縮減的現象而缺乏足夠的製程空間 (process window)。這種情形尤其在最小線寬縮減至〇13微米以下 時，最為明顯。 1289878 【發明概述】 因此，本發明之主要目的即在於避免該修整餘刻製程造成之直 線末端緊縮的效應，以解決絲與曝光容忍度降低等之問題，並 同日守改善製程空間(process window)。 本發明係提供一種利用電腦輔助設計以修改一光罩圖案 (photomaskpattem)的方法，該光罩圖案係用來製作一光罩，以轉 移至-半導體晶片表面之光阻層上，形成一預定之原始圖案。本 發明方法是先依據i定之絲接近效應(Qptie effect) 進行-第-修正’再依據―預定之直線末端緊縮效雜此㈣ shortening effect)進行-第二修正。本發明可避免後續在對該原始 圖案進行-修整侧製程(trim d_ etehing p_s机賴該原始 圖案的線寬時，發生該直線末端緊縮效應。 由於本發明是顧兩次修正程絲修改光罩圖案，以改善微影 製程中之光學接近效應，以及後續修整蝕刻製程造成之直線末端 緊縮效應所引__失真以及其所帶來的失減曝光容忍度的 降低等之問題。 【發明的詳細說明】 本發明係為-種利用電腦輔助設計(c〇mputer如_， CAD)修改一光罩圖案(photo mask pattern)之主動光學接近修正 法’該光罩圖案制來製作-光罩，而該光糊侧於—微影製 1289878 私中’用來使-半導體晶片之―預定區域表面之光阻層形成—預 定之原始圖形。 本發明之主動光學接近修正法是先依據_預定之光學接近效 應(optic proximity effect)以對光罩圖案進行一第一修正，以降低該 光罩圖案自-鮮齡至—半導體晶絲糾所可能纽的光學 接近效應。然後依據-修紐職程可能造成之直線末端緊縮效 應，利用-包含-多階方程式之修正程式以對該光罩圖案進行第 二修正。其中該光罩圖案於晶片表面之光阻層中形成後，另對該 图案化之光阻層進行一修整敍亥4製程⑻爪d〇wn etching卩咖㈣， 俾使·始圖案之最小線寬，能縮減至約αΐ3微米以下。 清參閱圖四’圖四為本發明之主動光學接近修正法之運算流 程圖。如圖四所示’本發明係細用—輸人裝置將光罩圖案之原 始佈局圖(original layout)輸入至電腦之記憶體中，然後輸入光罩條 件設定值(illuminationconditions)等操作參數，以進行一光學程式 计异。此光學程式計算係用來避免該光罩圖案在進行曝光的過程 中’發生過度曝光(overexp〇se)或是曝光不足(underexj_等之導 致解析度減_SGlutiGnlGSS)的現象，進而避免轉移至光阻層中之 原始圖形產生如轉肖圓形化效應(eQmer咖邊^他叫等的光學 接近效應。接著再將—健侧製紅㈣參數輸人，以進行一 直線末端_效應的程式計算。其中，祕整綱製程之操作參 數可由習知-般半導體製財發生的直線末端緊縮效师此㈤ 1289878 shortening effect)結果逆推計算得之，故在此不多加費述。 成的=圖次之程式計算結果，再模擬在晶片表面形 將模擬出的晶片圖_局圖與錯存的 案佈局圖進行比對，當二者圖案相符合時，亦即二者圖案 罩圖案佈局圖輸出。若是二者圖案不符合，則針對比對出的不符 2份物縣_佈局社錢，修錢之光補雜局圖作 為-原始佈局_存於記鐘中，並依虹述步驟鑛進行整個 流程的運算迴路㈣culationloop) ’直到晶片圖案佈局圖與修正後 之光罩圖案佈局圖的輯結果婦合，並將該光罩圖案佈局圖輪 出為止。 凊參考圖五’圖五係以圖二中之直線圖案為例，一佈局圖案 30以及佈局_3序㈣—細曝轴影(金^丨啊伽、 mspection，趨)31以及進行一修整餘刻製程％形成之晶片圖案佈 局圖32、34之示意圖。其中佈局圖案3()為圖二中之原始佈局圖案 1〇經過經過本發明之主動絲修正雜正之絲。細三所示利 用習知光學接近修正得狀晶片圖案佈局圖_較之下，利用本 毛明之主動光學修正法形成之晶片_佈局圖％，與原始佈局圖 案10較為相近。 综合上述說明’本發明是利用兩次修正程式來修改光罩圖 1289878 案 造以改善微影製程中之光學接近效應，以及後續修整餘刻製程 "、之直線末端緊縮效應所引触圖形失真，與 與曝光容忍度的降低之問題。的失焦 相較於習知技術，本發料僅考劇—光學近接效應，亦考 卜直線末端緊縮效應，所以在對圖案化之光阻層進行一修整 Μ製沾縮段製程線寬時，可以有效聽習知光學接近修 所無法解決之該鱗末端緊縮效應。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。 【圖式簡單說明】 圖一為習知之光學接近修正之運算流程圖。 圖二為在未_光學接近修正的情形下，—縣佈局圖案、 該原始佈局圖案依序經過光阻曝光顯影以及進行一修整侧 製程形成之晶片圖案佈局圖之示意圖。 圖三為利用絲接近修正後，—佈局_、該佈局圖案依序 經過光阻曝光㈣彡以及進行—修整侧製程形成之晶片圖案 佈局圖之示意圖。 圖四為本發明之主動光學接近修正法之運算流程圖。 圖五為利用本發明之主動光學接近修正後，一佈局圖案、該 佈局圖案依序經過光轉光顯影以及進行—修整烟製程形 11 1289878 成之晶片圖案佈局圖之示意圖。 【圖示的詳細說明】 10 原始佈局圖案 16、30佈局圖案 13、31顯影製程 15、33修整蝕刻製程 12、14、18、20、32、34 晶片圖案佈局圖1289878 IX. INSTRUCTIONS: [Field of the Invention] The present invention provides an aggressive 〇ptical proximity correction, and more particularly to an optical proximity correction method that avoids a linear end tightening effect. BACKGROUND OF THE INVENTION In order to form a designed integrated circuit on a semiconductor wafer, the current semiconductor process is to first fabricate a photomask and form a pattern of etched on the reticle, and then use a The lithography process transfers the pattern on the reticle to the photoresist layer on the surface of the semiconductor wafer at a certain ratio, thereby smoothly transferring the layout pattern of the integrated circuit to the semiconductor wafer. Therefore, the lithography process is one of the most important steps in the semiconductor process. However, as the component size of the circuit is shrinking, the difference between the circuit pattern on the surface of the wafer and the original mask pattern increases after the lithography process, especially the angular round caused by the optical proximity effect. Comer rounding and lineendsh〇rtening are typical observations. In order to avoid the optical proximity effect caused by the pattern on the wafer and the reticle pattern are inconsistent, the current solution is mostly to use computer-aided design (c〇mputer aided design, CAD) to perform an optical proximity correction on the reticle pattern (〇ρ—ι In 1289878-η, QpQ 'called the transfer slave, the slit pattern is transferred to the lamp pattern. In addition, in response to the requirement that the process line width is continuously reduced, the current trend is based on the mask pattern. After the surface of the wafer is formed, the patterning of the light ps is performed, and the line width of the process can be further reduced to the exposure limit to achieve a smaller area and more wealth. The purpose of the component. Please refer to the figure, the figure - the optical path of the Chi-Chi optical proximity correction. As shown in Figure 1, 'computer aided design (computer aided design, (10)) into the optical proximity correction is the first Input an original layout of the reticle pattern into the memory of _ using an input device, and then input operation parameters such as illuminating condition settings to perform an optical Calculate the pattern of the wafer pattern formed on the surface of the wafer by simulating the pattern of the reticle pattern. The simulated pattern of the wafer pattern _ stored in the pattern _ layout is then carried out, when the two patterns match, that is, the two patterns When the comparison result is combined with a tolerance, the reticle pattern layout is outputted by an output device and formed on the transparent mask. If the two _ do not match, the comparison is performed. The non-conformity part of the fresh® case layout modification [re-Nana's reticle pattern layout as the original layout is stored in the memory, and according to the above steps to re-run the entire process of the circuit (calcu on the nloop The comparison between the layout of the rough chip pattern and the corrected mask pattern layout is shown in Fig. 2 and Fig. 3, and Fig. 2 and Fig. 3 are examples of the straight line pattern, an original 6 1289878 layout pattern. The layout pattern is sequentially subjected to photoresist exposure development (afterdevd〇pmem inspection, ADI) and a wafer pattern layout diagram formed by performing a trimming etching process. FIG. In the case of near correction, an original layout pattern 10 and an original layout pattern 1 are sequentially subjected to a photoresist exposure development (ADI) 13 and a wafer pattern layout diagram 14 formed by performing a trim etching process 15 . Figure 16 is a schematic diagram of the original layout pattern 1 〇 due to the optical proximity effect in the development process 13 and the linear end reduction effect caused by the subsequent trim etching process 15, so that the finally formed wafer pattern layout 14 and the original layout pattern 10 has significant differences. FIG. 3 is a wafer pattern layout diagram 18, 2 in which a layout pattern 16 and a layout pattern 16 are sequentially subjected to an after development inspection (ADI) 13 and a trim etching process 15 after optical proximity correction. Schematic diagram. The towel layout_16 is the result of optical correction of the original layout pattern 10 in Fig. 2, so that the difference between the wafer pattern layout 20 formed by the lithography 13 and the trimming side process 15 and the original layout pattern 1 is small. However, due to the optical proximity correction of the mask pattern, the optical proximity effect is mainly eliminated, and the linear end reduction caused by the trim etching process is not considered. Therefore, the original layout pattern and the actually formed wafer pattern are The layout map still has considerable differences, and the problem of defocus and exposure tolerance (4) e latitude, EL) is reduced, which not only makes the mask pattern seriously distorted, but also has the possibility of avoiding the end of the line. The phenomenon of shrinking and lacking sufficient process window. This is especially the case when the minimum line width is reduced to less than 微米13 microns. 1289878 SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to avoid the effect of the straight end end tightening caused by the trimming process, to solve the problem of the silk and the exposure tolerance reduction, and to improve the process window. . The present invention provides a method for modifying a photomask pattern using a computer-aided design for fabricating a mask for transfer to a photoresist layer on the surface of a semiconductor wafer to form a predetermined Original pattern. The method of the present invention first performs a -first correction according to the Qptie effect, and then performs a second correction according to the "predetermined straight end effect". The invention can avoid the subsequent tightening effect of the straight end when the trimming side process of the original pattern is performed (trim d_ etehing p_s depends on the line width of the original pattern. Since the invention is to modify the mask by two correction lines The pattern is used to improve the optical proximity effect in the lithography process, as well as the problem of the distortion caused by the linear end tightening effect caused by the subsequent trimming etching process and the reduction of the exposure tolerance caused by the loss. Description: The present invention is an active optical proximity correction method for modifying a photo mask pattern using a computer-aided design (c〇mputer such as _, CAD) to create a reticle. The photo paste side is formed in the lithography system 1289878 to form a predetermined photoresist pattern on the surface of the predetermined area of the semiconductor wafer. The active optical proximity correction method of the present invention is based on the predetermined optical An optic proximity effect to perform a first correction to the reticle pattern to reduce the optical proximity of the reticle pattern from the age of the smear to the semiconductor filament Then, according to the linear end tightening effect that may be caused by the repair process, the correction of the reticle pattern is performed by using a correction program including a multi-order equation, wherein the reticle pattern is on the photoresist layer on the surface of the wafer. After the formation, the patterned photoresist layer is further trimmed by a process of (8) claws, and the minimum line width of the pattern can be reduced to less than about ΐ3 μm. Figure 4 'Figure 4 is the flow chart of the active optical proximity correction method of the present invention. As shown in Figure 4, 'the invention is used in detail—the input device inputs the original layout of the mask pattern to the computer. In the memory, input operating parameters such as mask condition setting values (illumination conditions) are used to perform an optical program calculation. This optical program calculation is used to prevent the reticle pattern from being overexposed during exposure (overexp 〇se) or underexposed (underexj_ et al. caused the resolution to decrease _SGlutiGnlGSS), thereby avoiding the original pattern generated in the photoresist layer to produce a circular effect (eQme) r coffee side ^ he called the optical proximity effect. Then, the health-side red (four) parameter is input to perform the calculation of the end-of-line effect. Among them, the operating parameters of the secret process can be learned by conventional semiconductors. The end of the straight line at the end of the production of money (5) 1289878 shortening effect) The result is calculated backwards, so there is no more to mention here. The calculation result of the == map program, then simulate the wafer on the surface of the wafer. The map_the map is compared with the staggered layout map. When the two patterns match, the two pattern cover layouts are output. If the two patterns do not match, then for the comparison of the two parts of the county _ layout of the money, the repair of the light to make up the miscellaneous map as the original layout _ in the memory, and according to the rainbow The calculation circuit of the flow (4) culationloop) 'until the result of the layout of the wafer pattern layout and the corrected reticle pattern layout diagram, and the reticle pattern layout diagram is rotated.凊 Refer to Figure 5' Figure 5 for the line pattern in Figure 2 as an example, a layout pattern 30 and layout _3 sequence (four) - fine exposure axis shadow (gold 丨 丨 gamma, mspection, trend) 31 and a repair A schematic diagram of the wafer pattern layouts 32, 34 formed by the engraving process %. Wherein the layout pattern 3() is the original layout pattern in FIG. 2, and the magnetic wire is modified by the active yarn of the present invention. As shown in the third, the conventional wafer is used to approximate the modified wafer pattern layout. In contrast, the wafer_layout pattern % formed by the active optical correction method of the present invention is similar to the original layout pattern 10. Based on the above description, the present invention utilizes two correction programs to modify the reticle pattern 1289878 to improve the optical proximity effect in the lithography process, and the subsequent trimming process " , with the problem of reduced exposure tolerance. Compared with the prior art, the present invention only examines the optical proximity effect and also the linear end tightening effect. Therefore, when the patterned photoresist layer is trimmed and the shrinkage process line width is It can effectively listen to the effect of the optical close to the end of the scale that can not be solved by the repair. The above is only the preferred embodiment of the present invention, and all changes and modifications made in accordance with the scope of the present invention should be covered by the present invention. [Simple Description of the Drawings] Figure 1 is a flow chart of the conventional optical proximity correction. Figure 2 is a schematic diagram of a wafer pattern layout in which the county layout pattern, the original layout pattern is sequentially subjected to photoresist exposure development, and a trimming process is performed in the absence of optical proximity correction. Fig. 3 is a schematic diagram of a wafer pattern layout pattern formed by using the wire proximity correction, the layout pattern, the layout pattern sequentially passing through the photoresist exposure (four), and the trimming side process. FIG. 4 is a flow chart of the operation of the active optical proximity correction method of the present invention. FIG. 5 is a schematic diagram of a layout pattern of a wafer pattern formed by sequentially performing photo-rotation development and performing a process of trimming the tobacco process 11 11289878 by using the active optical proximity correction of the present invention. [Detailed illustration of the illustration] 10 Original layout pattern 16, 30 layout pattern 13, 31 development process 15, 33 trimming etching process 12, 14, 18, 20, 32, 34 wafer pattern layout
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