TWI287862B - Semiconductor package - Google Patents

Abstract

A semiconductor package includes a transparent substrate, and at least a chip. In this case, a circuit layer is formed on one surface of the transparent substrate, wherein the circuit layer includes a circuit for electrical inter-connection and a plurality of electrical pads for electrically connecting to outward. In part of the circuit for electrical inter-connection, a plurality of first bumps is formed. A second bump is formed on each of the electrical pads. The chip has a chip electrical pad and is mounted on the transparent substrate in flip-chip type. The chip electrical pad, which directly contacts or indirectly contacts by an anisotropic conductive film, electrically connects to the first bumps in the circuit for electrical inter-connection.

Description

j No. 91119467, >year and month 1287862

V. DESCRIPTION OF THE INVENTION (1) [Field of the Invention] A semiconductor package, particularly a semiconductor package of a transparent substrate. When the electronic system is increasingly powerful, and its body is thin and short, Feng Yi I# s Μ 装 装 , , , , , 追求 追求 + + + + + + + + + + + + Intensive, recently, a wide range of packaging technologies such as flip chip, stacked crystal (stacked, the most packaged (chlp Scale Package), etc.), which has the advantages of small size and good performance, has become extremely popular before S Value

In the above various packaging technologies, the common point is that the substrate system on which the 曰曰 is mounted is mostly a resin substrate (for example, a BT substrate or a F ΐ Λ is a ceramic substrate. Generally, the substrates can provide ί 与 ^ and line spacing (pitch), or electric pad (pad) size and electrical connection most =: above 30 # m. And in order to find a smaller line width and electrical pad, there is also Using semiconductor manufacturing technology to produce germanium substrates, near::: substrate materials. The industry is actively reducing the substrate: Second, its main original (four) can shrink the substrate size and new process and install t. Jane, even if the semiconductor wafer τ The use of the most to make it smaller, but due to the line width of the substrate and the electrical mat of the most bran-like semiconductor wafer, the size of the electrical mat can not be effectively reduced / limited: two right more precise circuit board can solve The above problem j, when the extremely precise substrate is used right, there is a problem that the cost increases.

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What kind of substrate is the tube, which is opaque and has an eight-way point, that is, τ, J, and a side, which is quite disadvantageous when it is not necessary to use optical characteristics. Wenliang or has 1287862. V. INSTRUCTION (2) In addition, it is quite disadvantageous to use optical characteristics when it is necessary to use such substrates. How to provide a substrate with a light transmissive, low-cost line width and an electric connection pad, and a substrate that is extremely inexpensive and has a very high line width and electrical connection. [Summary of the invention] The board and the clock have the above problems, and the present invention mainly focuses on the development of the technology. The basis for the day-to-day planting is that the object of the present invention is to provide an optical characteristic, easy inspection, and a small volume J, low cost, and a semiconductor package. " *Good frequency characteristics and high reliability: And 'the characteristics of the present invention are based on a transparent substrate'", (4) the substrate can be used as a "tablet", ί::i In order to achieve the above object, the present invention provides a semi-conducting h' ί ί = 布 设有 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '曰曰曰μ系', and there are -f-chips, which are in direct contact with the 凸2 bumps in the internal electrical connection circuit or indirectly via an anisotropic conductive paste. The wafer is placed on the glass substrate while being contacted. In the semiconductor package of the present invention, since the transparent substrate may be a glass-earth plate, the thermal expansion coefficient of the upper glass substrate and the coffin of the wafer is similar, because ΙΗ1 I is broken...... ..........------

Case No. 91119467 1287862 V. Description of the Invention (3) The inner and the spacing between the transparent substrate and the wafer can be formed into a wafer-level path: the size and spacing of the circuit layers on the substrate: can be :::,, The size and spacing of the lines of the transmissive layer can also be different. The size of the wafer on the circuit board on the substrate can also be relatively $, ^, so it is placed on the transparent substrate, which is a glass substrate, and the transparent substrate can be used. High frequency characteristics. The phenomenon of glass reduction is therefore similar to a good coefficient of thermal expansion, so that the limbs of the conductors and the positive conductors can be formed in advance, and the bumps in the BGA package technology can be similar. Pin function. In addition, since the effect ^ ', the change / the unit cost of the high-grain substrate is far more than that of the glass substrate, and the glass is low-cost, X, because of the cheapness of the internal substrate, it can be used for the falling of the film. Bumps (the second part is formed with a crystal-forming bump, and the ancient part can be stepped down and lowered). Therefore, it is not necessary to form a shape on each wafer in advance. [Detailed Description of Preferred Embodiments]丨~ Example of semiconductor sealing. ·, 5, according to one of the preferred embodiments of the present invention, FIG. 1A, FIG. 1, only one y body package 1 includes a transparent W, the other half of the preferred embodiment of the present invention The guide substrate 1 1 and at least one wafer 1 2 . Case No. 91119467 This is the first year 丨 3 \ 丨 1 786 1287862 Revision 5, the invention description (4) at least one surface of the transparent substrate 1 1 is provided with a circuit layer 110 The circuit layer 1 10 is provided with a plurality of electrical pads 11 2 for interconnecting the circuit ln for internal electrical connection (electri cal inter-(3) nnecti on). The internal electrical connection circuit 丨丨丨The middle portion is partially formed with a plurality of first bumps 11 3 , and the electrical interconnect pads 2 are divided into A second bump 11 4 is formed. In the embodiment of the invention, the transparent substrate can be a glass substrate, and the minimum line width provided on the glass substrate can reach 3#m by using current manufacturing technology, or even The first bump 11 3 may be a gold bump or a solder bump 3 (for example, a solder bump) (as shown in FIG. 3); and, the second The bump 114 may be a gold bump, or a copper bump, or a solder bump, as shown in FIG. 2 to FIG. 5. The wafer 12 is in a flip chip bonding manner and the inner gate m The first bumps 113 are electrically connected to form the wafer; the transparent substrate 11. In the embodiment of the present invention, the plurality of first bumps are formed by the portions of the internal electrical connection circuit 111. The arrangement of 3 corresponds to the wafer electrical pad 1 2 1 (shown in FIG. 丨B) on the wafer 12, so that the wafer electrical pad 1 2 1 of the wafer 12 can be matched with the first The bumps 3j 3 are electrically connected to each other, so that the wafer 12 can be placed on the transparent substrate 11. As described above, the wafer 12 is flip-chip bonded (fUp - The bonding is electrically connected to the first bump in the internal electrical connection circuit ln, as shown in FIG. 1A or FIG. 2, the flip-chip bonding method may be a conductive conductive adhesive (ACFM51 as mutual The material is further attached to the transparent substrate 11 by the wafer 12 (or, die, die). Further, as shown in Fig. B, when the cymbal film 12 is mounted on the transparent substrate 11, it is attached to the transparent substrate.胃上的胃曰曰曰曰'

1^· Page 9 1278862 A ^ ^ - - Case No. 91919467 slightly hair 'month - 11 曰 _ repair; f 5, invention description (5) = a plurality of _ bumps 113 are formed on the part of the connection circuit ill ( Typically, it is a gold bump) and then electrically connected to the wafer 12 via conductive particles 1511 (typically gold balls) in an anisotropic conductive paste (ACF). In the flip chip bonding method, in addition to the ACF, the solder bumps may be used for flip chip bonding, as shown by =3, on the transparent substrate u, the internal electrical connection circuit U1, the first bump 1 13 may also be a solder bump 1 13' (generally a solder ball). Of course, in addition to the above methods, there are other flip-chip bonding methods, which are omitted here. In addition, as shown in FIG. 4, in the embodiment of the present invention, when the wafer 12 is electrically connected to the first bumps on the internal electrical connection circuit hi, the transparent substrate may be The internal electrical connection circuit 丨丨1 is provided with at least one passive component 13 or, as shown in FIG. 5, at least one active component 14 is provided, so that the IC designer designs a powerful circuit system, or Convenient product testing. Of course, as shown in FIG. 6 and FIG. 7, at least one passive component 13 and at least one active component 14 are simultaneously disposed on the internal electrical connection circuit 11 of the transparent substrate 11. As described above, in the semiconductor package of the present embodiment, since the transparent substrate 11 can be a glass substrate, and the thermal expansion coefficient of the glass substrate and the substrate of the wafer is similar, the inside of the transparent substrate 11 is electrically connected to the wafer cassette 2. The size and spacing of the electrical connection circuits can be formed to the size and pain of the wafer level. > The spacing of the circuit layers on the transparent substrate 11 can be relatively small. The spacing can also be relatively reduced. 1 1 area, and the size and spacing of the internal electrical connection circuit can be reduced. Therefore, the electrical connection pads 1 2 1 of the wafer 12 wafer can also be relatively reduced, so the size of the wafer i 2 is -

Page 10 MM 911194R7 b \\ .Λ, 月___日 1287862 Revision V. Description of invention (6)

Can also be reduced by 0. In addition, by the two i Xiu Ming I can provide extremely ancient dip board 1 1 ' especially glass substrate, 俜 electric image with r high frequency signal due to parasitic capacitance and; glass substrate thermal expansion coefficient and half = high Frequency characteristics. Further, it is possible to avoid the stomach which is reduced in reliability due to the coefficient of thermal expansion of the multi-wafer package. η swell, number is different

The second pad is formed in advance on the pad 112. The two-dimensional arrangement effect of the bumps in the silicon technology is in other words, in other words, the south outer pin function: in addition, the transparent substrate π may be a glass substrate. However, the unit cost of the glass substrate is much lower than that of the US soil to reduce the cost 'and' because of the internal electrical connection. The partial structure of the circuit ui and the first bump 113 for the electrical connection are not required. The bumps are formed on the 12, so that the cost can be further reduced. In addition, it is worth mentioning that, since the transparent substrate 11 is transparent, when the wafer j 2 is pasted on the transparent substrate 11, or the transparent substrate is adhered to a circuit substrate by surface adhesion technology (SMT) ( PCB, PWB), can easily use its transparent characteristics for defect inspection, which can greatly improve the yield and reliability of the product, which is not achieved by general packaging technology (such as BGA package), because the general package The substrate is opaque.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the present invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a cross-sectional side view of a semiconductor package in accordance with a preferred embodiment of the present invention, wherein the wafer is adhered to a transparent substrate by ACf. Figure 1B is a partial enlarged view of the dotted line indicated in Figure 1A. 2 is a side elevational view of a semiconductor package in accordance with a preferred embodiment of the present invention, wherein the second bump is a solder bump. Figure 3 is a side elevational view of a semiconductor package in accordance with a preferred embodiment of the present invention / wherein the first bump is a solder bump. Figure 4 is a side elevational view of a preferred embodiment of the present invention, wherein the inner Qiu Xue is further divided into sections by the soil. ^Electrical connection circuit is provided with a passive element. Fig. 5 is a side view of the present invention, wherein the internal thunder is also a further assembly of the semiconductor package. Inside. The circuit for electrical connection is provided - the earth moving month a. The modified sectional view is a view of one of the present inventions, wherein the internal active circuit of the semiconductor package of the internal electrical circuit is connected to the circuit. At the same time, there is a _4 side view moving element and an active element. FIG. 7 is a side view of the present invention, wherein the internal component of the semiconductor package and the active element are connected to the circuit. At the same time, there is a section [illustration of the symbol] I semiconductor package II transparent substrate 苐 12 pages 1287862 case number 91 Π 9467 \ 曰 曰 correction diagram simple description 110 circuit layer 111 internal electrical connection circuit 112 electrical pad 113 first convex Block (welding bump, gold bump) 113, solder bump (first bump) 114 second bump (solder bump, gold bump 114' solder bump (second bump), 12 wafer 121 wafer Electrical pads 13 Passive components 14 Active components 151 Anisotropic conductive adhesive 1511 Conductive particles❶

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Claims (1)

Case No. 9WfUR7 Shuangshou 1878862 Correction VI, _ patent scope 1, a semiconductor package, including a glass substrate, one surface of which is provided with at least one circuit layer, the circuit layer is provided as an internal electrical connection The circuit and the external electrical connection are provided with a plurality of electrical pads, wherein the internal electrical connection circuit is partially formed with a plurality of first bumps, wherein the electrical interconnects are respectively formed with a second bump; and at least a wafer having a wafer electrical pad, which is in direct contact with the first bumps in the internal electrical connection circuit or via an anisotropic conductive paste in a flip chip bonding manner The wafer is placed on the glass substrate by indirect contact and electrical connection. 2. The semiconductor package of claim 1, wherein the first bumps are solder bumps. 3. The semiconductor package of claim 1, wherein the first bump is a gold bump. The semiconductor package of claim 1, wherein the second bumps are solder bumps. 5. The semiconductor package of claim 1, wherein the second bumps are gold bumps. 6. The semiconductor package of claim 1, wherein the first 1287862 \ §__ Amendment - _ Case No. 91119467 /, Shen Qing patent range A bump copper bump. 7. The semiconductor package of the first aspect of the patent application, wherein the transparent substrate is further provided with at least a passive component, the passive component being electrically connected to the internal electrical connection circuit of the transparent substrate. 3. The semiconductor package of the active-L is further provided on the substrate, wherein the transparent transparent substrate has two internal electrical connections, and the active component is electrically connected to the circuit. 1287862 Case No. 91119467 1V 'Monthly I丨 Correction Page 16 1287862 Case No. 91119467 0^Year January If amended Page 4