TWI287266B - Seal ring structures, semiconductor wafers and methods for reducing die saw induced stresses - Google Patents

Abstract

A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. A bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A plug is formed on the plug sublevel in substantial alignment with the bridge, wherein the plug has a width substantially the same as that of the bridge. Semiconductor wafers and methods for reducing die saw induced stresses are also provided.

Description

1287266: Patent Specification No. 94131293 Revision Date: 96丄3 • Nine, Invention: Technical Field of the Invention The present invention relates to the design of a semiconductor integrated circuit chip, and in particular to a dense seal A sealing ring structure having a physical strength that is strong enough to limit and resist, and to prevent advancement of cracks at the corners and edges of the integrated circuit chip. [Prior Art] The integrated circuit chip is fabricated on a circular single crystal wafer in accordance with a rectangular array type. Most of the wafers are formed by Shi Xi. The wafer can be segmented by scribing, breaking (four), stress cracking (s) or the most commonly done (sawing). The alignment is aligned to the selected crystal axis such that separation of the wafers can be performed in a sequential and predetermined manner. However, this separation procedure inevitably causes unintentional stress cracks. (4) ^ The situation occurs most at the corner of the intersection of the two vertical dividing lines close to the integrated circuit chip. • Advancing as the crystal axis. Since the crystal grain is mostly adapted to the wafer, the above-mentioned unconventional cracks often start perpendicular to the edge of the wafer. The tip of the 2 marks is used to make the amount of breaking. In any material, this two: ==:: 然:: This crack _ such machine, called (four) from other structures. When the wafer is made of metal, ceramic or plastic packaging material, more stress is formed. - But cracks begin to form, and two: _ ^ can lead to cracks. d. The same is true for the wafer to be separated by any means to separate small cracks in the integrated circuit, especially near the corners. The scoop of the package /', white may form a micro-natural nature from its edge, and the crack will continue to pile up. Such as =I cover may also cause the formation of cracks. Living in it is destroyed. Therefore, it is usually in the core circuit system 'body power, the crack of the core circuit advancement may be built on the same day as the core circuit and its 0503-A31117TWF1/shawn chang 1287266

:帛94131293 Patent Specification Amendment 々正(4)Q '舒^ has a secret ring with a knot. The seal is mainly intended to limit any cracks in the internal nuclear circuit. In addition, the sealing ring can also avoid the infiltration of moisture, such as the inclusion of damage or the spread of the dyeable material. As the current generation technology of integrated circuit chips continues to shrink, the distribution and degree of intrinsic stress increase, and the problem of this crack is: ,,,,,,,,, Shape, it is convenient to make crystals along the bottom circuit, and the sealing surface of the multilayer dielectric layer and the metal pattern is required. ▲ Each new generation axis needs a new dense touch design and manufacturing method. In this way, the seal ring is more complicated and critical. , α — in today's multi-layer: under-metal assembly _, through (four) bribery double-dip method to create a poor seal structure. Each metallization layer consists of two sub-layers (sublevel is dirty. The lower sub-layer is set to listen to the nucleus. The circuit area is formed by inserting a plug hole formed by rhyme. The upper part is the upper part. It is formed by filling the bridge into the opening of the groove, and is interspersed with the metal conductive or semi-conducting structure underneath. In this way, the whole county structure is not enough to resist cracks. The intrusion, and in particular, is at the fragile plug sublayer. Therefore, the plug in the conventional seal ring structure needs to be preferably designed to more restrict and block the edge from the integrated circuit chip. SUMMARY OF THE INVENTION In view of the above, it is a primary object of the present invention to provide a seal ring structure suitable for use in a core circuit region of an integrated circuit chip. In the present invention - an embodiment, the seal ring structure includes. a metallized film layer having a bridged sublayer and a plug sublayer; a bridge located in the bridging sublayer between a peripheral edge of the integrated circuit chip and the core circuit section; And - a plug, located at the plug Internally and substantially aligned with the bridge, the plug has a width that is substantially the same as the width of the bridge. 〃 μ In another embodiment of the invention, a seal ring structure is provided for use in the core of the gated wafer Circuit area, including: Beiyibao 0503-Α31117TWFl/shawn chang 6 !287266 - Amendment No. 94131293 - Amendment date: 96.1.3. - Group _ or multiple (four) ring lines, located in the integrated body Circuit day and day #—the corner-corner core circuit area-corner interval; and—the second group—or multiple seal ring lines, bits=the integrated circuit chip-edge and one of the core circuit areas An interval, wherein each of the seal ring lines comprises a metallized film layer, comprising: a bridge sublayer and an interstitial sublayer; and a substrate disposed in a peripheral edge of the integrated circuit chip The core electric I has a predetermined position; and at least the __plug is located in the plug sublayer, and the at least-inserted wire has a width greater than 5〇% of the width of the bridge. In addition, the present invention further implements In the example, a half-wafer is provided. Including: including - a semiconductor substrate; at least - a main dragon, located within the semiconductor substrate: and a circuit 'located in the active - to reduce the shear stress of the structure, to cut the active region, along the active region; At least one sealing ring structure surrounding the wire region; and at least a shallow trench spacer located in the semiconductor between the (four) ring structure and the m-channel, wherein the sealing ring structure may be the aforementioned sealing ring structure. In addition, in another embodiment of the present invention, there is provided a method for reducing stress caused by cutting, for use in a main body of a substrate----------------------------- Step: forming a seal ring structure surrounding the active region; and laterally removing a portion of the semiconductor to form a shallow trench barrier in the semiconductor substrate between the seal ring structure and the scribe line. Among them, the seal ring structure can be applied to the aforementioned seal ring structure. The above and other objects, features, and advantages of the present invention will become more apparent and understood from The sealing ring structure, which has (4) the material county has a metallization layer, can preferably limit the advancement of the miscellaneous crack. The sealing ring structure is interposed between the center of the two-core circuit and the edge of the integrated circuit chip and has a thick structure. This structure is 堆叠5〇3.A31117TWFl/shawn chang 7 1287266. 帛94131293 Patent Specification Revision This is the stack formed by the upper bridge and the lower bridge. It can provide the impedance of bribery to crackers. m and strength • The stress at the edge of the self-frequency circuit chip of the county can be encountered. (4) Such a fault can be caused by the enlargement of the crack in the portion of the wafer in Fig. 1A. At the time of wafer loading, it may be that the inner person 2 is produced in an initial microcrack 102. This splits into and across the wafer and the photovoltaic layer 104. When the crack of the advancement encounters a metal wire such as one of the copper wires 1〇6, the crack may be laterally advanced along the side of the wire, such as a stress crack, and it may be pushed straight through the wire. Such as cracks 110. At the self-stress crack (10), the initial microcrack 1〇2 can be piled up in its original direction, such as crack 112. This will result in more stress cracks and cracks. Figure 1B shows a partially enlarged section 114 of a wafer including an initial microcrack 116. Even if the initial microcrack 116 does not advance to the metal wire ι8, the stress concentrated at the tip of the propelling crack will form a sag at the side of the metal wire 118. Χ Figure 1C shows a partially enlarged section m of a wafer including an initial microcrack 124. Even if the initial microcrack 124 does not advance to the metal wire (3), the stress concentrated at the sharp tip of the thrust crack will form a direct crack (3) beside the metal wire m. ▲When such a crack pushes it to the core circuit of the integrated circuit chip, the circuit function is such that the sealing ring between the edge of the wafer and the domain core circuit area is the standard protection wire. This seal ring typically includes a metal structure that can be fabricated simultaneously with standard metal structures in the core circuit. • When the component size is gradually reduced, a mosaic or dual damascene structure is usually used to make the seal %. Full planarization techniques such as chemical mechanical polishing and etch back provide flat performance and shallow scalarity for successful lithography at each metal layer. Within the normal structure of the job, each metallization layer is a two-layer structure. The sublayer (suWevel) located below is formed by interposing a metal plug and a barrier layer in the via hole formed by etching in the first dielectric layer. The lower sublayer is a second 0503-A31117TWF1/shawn chang 8 1287266, the revised specification of the patent specification 94131293, date of revision: 96.1.3) covered by the electric layer. In the embodiment, the lower sublayer is covered by the __stop layer and the second layer. And the second dielectric layer is formed on the second dielectric layer. In the example, the trench is formed in a sub-layer having a second dielectric layer and a side stop layer. = The trench is filled with a metal formed by any technique to form a second pass of the metal.

By grinding to the dielectric layer to remove excess metal, only the metal that fills the trench is left. The metal in the trench forms a bridge between the plugs and is connected to a portion of the metal wire that straddles it. The order of trench etch and via etch can be reversed to allow for a single product. The metal used may include materials such as |lu, tungsten or copper. Fig. 2 shows a conventional inlaid structure as a seal ring which is susceptible to microcrack damage as shown in Fig. The profile shows a complete stack of multiple layers of metal delamination. The wafer edge in the vertical direction is formed when the wafer is fabricated or divided. The area 204 illustrates a metallization structure for the core circuit. In each metal layer, the interpolated sub-layer 208 is formed with six commissions 206, and each bridge sub-layer 212 is formed with a _bridge ^ 210. . Region 216 illustrates a metallization structure for the seal ring. In each metal layer 214, two plugs 218 are formed in the plug sub-layer 208, and a bridge 220 is formed in each of the bridge sub-layers 212. The plug 218 in the plug sub-layer 208 is isolated by the dielectric structure 222. Each of the metallization layers within the metallization of the seal ring can include more than two plugs in the plug sublayer and one of the bridges in each of the bridge sublayers. More than two plugs in the plug sublayer are isolated by a dielectric layer. The metallization of the seal ring may also include more than one bridge in the bridging sub-layer of each metal layer. The metal layer 214 for the core region 204 and the seal ring 216 is comprised of a plug sub-layer 208 and a bridge sub-layer 212. In the seal ring, the insert 218 in the plug sub-layer 2〇8 is subject to propulsion damage that may be caused by micro-cracks. In the plug sublayer, the plug 218 is most likely to be damaged by the advancing microcracks. The width 218 of the plug is narrower and relatively narrower than the width of the dielectric layer. The width of the plug 218 is narrower than the width of the bridge 220 in the bridging sub-layer 212 within the seal ring. Since the dielectric layer has a lower impedance capability for advancing microcracks, it exhibits very little adhesion strength to the bridge 22() of the upper and lower metal layers. Since 0503-A31117TWFl/shawn chang 9 1287266: Amendment No. 94131293 Patent Revision Date: 96.1.3 Therefore, the impedance of the plug sublayer 208 for crack intrusion is relatively low. • The embodiment of the present invention provides a reliable seal ring structure. When the plug in the plug-in sub-layer expands to a width that is substantially similar to the width of the dielectric structure in the sub-layer of the plug, a sealing ring having a physical strength can be produced. Therefore, the total width of the plug in the plug sub-layer extends to the junction, which is close to the bridge width of the bridge sub-rib. Level 3 relates to various embodiments of the invention, wherein like reference numerals designate like structural elements. The second figure shows a section 322 of the stacking of the entire multilayer metallization structure, which includes a seal ring 324 having a strong physical strength. The vertical wafer edge 3〇2 is formed during wafer fabrication or dicing. The area 3〇4 illustrates a metallization structure for the core circuit, in which six plugs 306 are formed in each of the metal layers 3U, and a bridge is formed in each of the bridge sublayers 312. 31〇. The seal ring structure 324 having a firm physical strength is illustrated as having three plugs 326 formed in the plug sub-layer gauge of each metal layer, and a bridge 32〇 formed in each of the bridge sub-layers 312. The plug-in is isolated by the dielectric structure 328. The width of the plug 326 is generally similar to the width of the dielectric structure. Thus, the total width of the plug 326 in the plug 08 has more than 50 〇/〇 of the width of the bridge 320 in the bridge sub-layer 312. Preferably, in another embodiment, as shown in the third embodiment, the total width of the plugs 326 in the plug sub-layer 308 is substantially the same width in the bridging sub-layer 312 within the bridge 32 φ φ. Depending on the design of the helium seal, the number of plugs in the plug sublayer may be the same or different from the number of bridges in the bridge sublayer. As shown in Fig. 3, among the respective metal layers, three insertions 326 correspond to a bridge 320. Another embodiment is shown in Fig. 3B, in which one of the plugs 326 in the plug sublayer 308 corresponds to a bridge 320 located in the bridging sublayer 312. The number of bridges and plugs can vary depending on the width of the plug to optimize seal ring strength for the advancement of the crack. In another embodiment, the hard seal ring structure of the physical strength may comprise more than one metallization region, as shown in FIG. 3C, wherein the two metallization regions 322-1 and 322-2 constitute a stronger one. Sealing ring structure. In another consistent embodiment, the metallized structure of the physically rigid seal ring can form more than one bridge within the bridging sublayer to exhibit a relatively strong seal ring structure. 0503-A31117TWFl/shawn chang 10 1287266 Revision date: 96.1.3: Revision of the patent specification No. 94131293 This month || The demonstration process of the ring closure will be described below. The tributary layer 314 applied to the core, the circuit outline, and the sealed U 可 can be simultaneously turned on. The trenches of the young 3-6 and the trenches of the lower bridge 326 are formed at the same time. The metal material is then formed in the via hole and the lower trench. The bridge 326 below the plug sub-layer 3G8 is generally aligned with the bridge 32G located within the bridging sub-layer 312. In the embodiment, an etch stop layer can be formed in the bridge sub-layer 312 and the lower intervening sub-layer 308 (not shown in Figure 8).

Dielectric structure 328 can include a low-k dielectric material that typically has a dielectric constant of less than % 3.0. The Wei dielectric constant dielectric material may be a material containing nitrogen, containing or containing oxygen. Low '|Electric recording; I electrical material can also be - hole material or - doped material, such as the replacement of Shishi glass; 丨 electric t structure can be by chemical vapor deposition, low pressure chemical gas Deposition, electrical reinforced chemical IU mesh deposition, high density plasma and spin coating procedures. The barrier layer below, the upper barrier layer and the side stop system can be used for money, carbon, 9, oxygen or a combination thereof. The barrier layer below, the upper transfer layer, and the stop layer can be formed by chemical deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma or spin coating procedures. The plug-in human plug has a visibility greater than 〇·4 μm and preferably between 〇.4 and 12 μm. In the embodiment, the width of the plug is between 0.4 and 4 microns. In another embodiment, the width of the plug is between μ and micro when the inner side of the area 304 core circuit area is formed as a via hole filled by the plug 3〇6, and is filled in by the lower layer bridge 326. The lower layer trenches are also formed in the sealing structure 324 at the same time, but the process openings are different. Regardless of whether the dry or wet side is used, the _ rate will vary depending on how much exposed areas are exposed in each opening, and will also vary depending on the process tolerance of the pattern density in the adjacent area. This caused the lack of reading of reactants for the side anti-ship. In other words, the side rate is a letter of bribe density that can continue the width of the metal and then saturate. Then, as the width of the metal reaches a predetermined value, the curve decreases. Since the width of the inspection 306 and the bridge 326 of the lower layer are different, For example, if the process of returning to the moment and the machine is correct, it is necessary to _ touch the flattening table of the cultivating. 0503-Α31117TWF 1/shawn chang 11 1287266 Revision date: 96.1.3 Amendment to the patent specification No. 94131293 Production. In order to reconcile the difference in width between the plug 3 () 6 and the lower bridge 326, a number of different paste preparation schemes have been introduced for such patterns. In the chemical mechanical polishing process, the dummy pattern can be selectively set by the density of the fine pattern to avoid the upper groove gold light and part of the plug, which also contributes to the pattern density. Adjustment. Thus, in procedures such as etchback and chemical mechanical polishing, the aforementioned seal ring structure 326 which is like the inner and lower layers is suitable for the plug-in test 3〇6 in the core circuit.

The stacking of the metallized film layer composed of the bridge 32 () of the sealing ring structure 324 on the lower layer bridge 难 is difficult to understand. The surface area of the structure is relatively good == the adjacent film layer has better adhesion. . The multi-layer = ^ sheet metallization stack structure provides a stronger resistance to crack intrusion. The seal ring structure 324 shown in the same space as the third shot has a m (four) shape as compared with the second figure. The conventional seal ring structure is thick. The display shown in field 216 can thus be avoided and contributes to improved greening. Wei Laiyi lacks people to the core, the track and the integrated circuit.

In the 4A picture of Mingshen, the right ring of the seal ring is added to the four lines with straight edges, and the line is 10 microns. Regional technique _ Designed for different corners of the line. The line side is flat:: road, ===, diagonal 2::ring:: 2 width is:, the edge line and the horizontal side, the turn 2 is said to have a vertical straight line damage display The double angle ^ at the corner is - the long diagonal. And the two are long diagonal. Line 420 Bay u can not be located at the corner Please refer to Figure 4C, seal ^ ~ corner - her double long diagonal. All the metal lines of the clothes are Sichuan micron. Displayed in area 422 〇503-A31117TWFl/shawnchang 12 1287266 Revision No. 94131293

Four plus people have straight edge lines, I 96.U edge lines and horizontal edge scales. ^ H —« Straight edge guard ring, which has a shorter diagonal corner. It touches the corner and is separated by a double protection. The weight is accompanied by a right loop. Line 426 is composed of corners - eight: f has 1 obscured corner segment. Line 428 constitutes a bit = knife division %, which is parallel to the other double as the isolation ring of the corner to form a single seal ring, which is heavy. The double line of line 430. The corner is set at the other side as the isolation ring of the corner. The link is the 4D map of the Ming dynasty, the extension of the area 422 -^

The design has four different corners with different metal line widths, knives # straight straight edge lines and junctions - in the case, the lines parallel to the diagonal line have a triangular path and another diagonal line at their corners. Recording changes "1 A, 聿 1 line edge green is 4 microns wide" line 436 is 6 microns wide, line 438 is 8 micro wide, and the line is 1 〇 micron wide. The first ~ milk map shows ^ 隹The more and the thicker the number, the more powerful it is. In addition, the side of the pure pass ^ two, & domain, so its _f to be stronger than the thief ring depends on the advancement of revenue. Therefore, The layout design with more protection loop lines or thicker protection y is the preferred embodiment of (4). In addition, the insertion of corners

A preferred embodiment of the invention is also disclosed in which the inner car is formed with a plurality of wider widths at the horizontal and vertical edges. # In addition, the following figure 5A and the first drawing diagram are used to show the sealing ring structure of the present invention on the process of the conductor wafer, and the fifth drawing of the towel is cut or divided in the Japanese yen. A variety of component designs are applied in sequence to reduce wafer profile conditions caused by dicing the wafer, while Figure 5B shows the top view of the wafer region as in Figure 5A. Referring to Figure 5A, a cross-sectional view of a wafer is shown. Here, the component &amp; used is the seal ring 5〇2 and the shallow trench spacer 5〇6. Sealing rings 5〇2 are formed on and/or surrounded by a metal layer constituting a stacked structure 504 which constitutes the main circuit of the active region. The 4-ring 502 has a width equal to or greater than 1 〇 micrometer. The shallow groove spacer 5〇6 is set at 〇5〇3.A31li7TWF1/shawnchang 13 1287266 The first 293 patent specification is amended. The date of revision: the stack of coffee, 、, σ, 5 〇 4, the base 5〇8 Inside. The shallow trench spacers are filled with a dielectric material such as a dioxide dioxide. The depth of the shallow trench isolation 506 is preferably no greater than 3 mm. In addition, more than one shallow trench spacer may be employed for the purpose of achieving the upper speed. The area outside the seal ring 5 may be any area not surrounded by the seal ring 5〇2. The other element used to reduce damage due to wafer dicing is the isolation trench 选择性, which is selectively slid down the area outside the stack structure and passes through the surface of the substrate 5〇8. The process of forming the shallow trench spacer 5G6 includes the side of the (four) bottom. Shallow trench isolation 506 is typically formed by the formation of a buried oxide trench in the German substrate. The shallow trench spacers in this embodiment serve as a barrier to wafer dicing that may pass through the bottom and reach the circuit area as a result of wafer cutting or rupture. Based on this _ ' shallow trench spacer 5 〇 6 must be formed outside the sealing ring 5 〇 2 and the main circuit area. The 裱5〇2 is used to block contaminants into the wafer circuit including the conductive and non-conductive materials. The seal ring 502 can be continuous and has a narrow contact f around the active area of the wafer. (that is, around the stack structure 5〇4). The scribe lines in the structure (not shown in Figure 5A) are usually wrapped around the entire wafer. The surface does not include any wire circuits. Contaminants may leak laterally to the immediate vicinity of the oxygen barrier: layer: thus the seal ring 502 surrounding the stack 504 may block any membrane layer of oxygen ===::£::=type_. Familiar with this; the circuit enjoys the time, Qing Ru, such as 0503-A311l7TWFl/shawn chang 14 1287266, the patent specification of 9411293 is revised. ^ Amendment date · · 96 1 3 The metal layer in the ring 502 is also · · Structure, the system is made up of - chest ice, and also includes a pollution barrier knot, 9... hood, slave cover - not directly exposed to the top surface or wafer including the stack structure The surface, the surface of the shallow trench spacer 506. The design of the protective cover is 4 = with extensions such as knives as an obstacle to any wafer cut surface to avoid moving ions to reach the next to the Sebow Road. It is worth noting that the protection of the downward coverage is outside:: Cover:::=: Structure = slice r. Since the cutting path does not contain any _ lines, . The mask will cause the self-cutting or separating procedure ', —— -«, ^rr;;;r〇r«: to avoid all the movement through the material interface of the broken substrate. <', effective, ==== The bottom surface of the crack induced by the cutting or separation process of the Cong wafer. The clear trench 5 is formed on the surface of the surface to the stress of the circuit in the structure 504. Similar to the shallow trench isolation guard ring 102 and the main circuit area, the trench 510 is also placed in the selective element, and the barrier 5H is used as its final cut guide structure. Since the use of the sealing ring 5〇2 and the groove 51〇 for the use of the two-piece dicing substrate 108 surface is blocked by the shallow trench spacer 5〇6, the stress applied to the scribe line does not affect the stack structure. 5〇4. ,. "V-knife is applied to the process. It can reduce the process of cracking in the circuit or additional process: the system: the private method can be achieved by the organic platform, without using Figure 5B to show the first 5A block 518 shows where the core circuit is located, complex = § _ - top view case 516. Where the area is wide, it also shows the 婧 纟 纟 纟 〇 〇 第 第 第 area in Figure 5A The core circuit in 518 is surrounded by a seal. Seal ring 502 = and stack ° 5 〇 3. A31117TWFl / shawn chang 1287266 ' Patent No. 94131293 amendments • Metal layers, interlayer contacts and layers The electrical layer has (four) degrees of repair H6.1.3 to prevent the contaminants from reaching the core circuit in the area 518. If the mouth is not wide, it only occupies a small part of the width of the scribe line. In order to protect the wafer from the degree - the crack advances through the 矽In the case of the base, #胃,日日°丨] hope to cause _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Stress, optionally - to the outer edge of the seal ring 5〇2 to cut矽 5 ^ between the base of the raft to form the isolation trench 51 外. The outer edge of the 卩 虽然 本 本 四 四 四 四 四 魏 魏 魏 魏 魏 魏 , , , , , , , , , , , , , , , , , , , , , , , , Within the spirit and scope, # can be used for various ^ = retouching, so the scope of protection of the present invention is defined by the appended patent application. [Simplified Schematic Description] Figures 1A to 1C show the self-integrated circuit chip. The edge enters the crack of its inner region; Figure 2 illustrates a cross-sectional view of a conventional seal ring structure; ί Figure 3C is a system, column diagram to show that in accordance with various embodiments of the present invention The sealing ring structure of the multi-layer metallization layer; 4A~ still does not show the layout design of the sealing ring according to different embodiments of the present invention, and FIG. 5A shows that the wafer is not in accordance with another embodiment of the present invention. The profile of the CM〇s process using a variety of component designs to reduce damage caused by the die cutting or splitting process / Figure 5B shows the top view of the wafer area as in Figure 5A. 106~ copper wire; 110, 112~ crack; 128~ direct crack; [main component symbol description] 102, 116, 124~ microcrack; 108~ stress crack; 118~ metal wire; 0503-A31117TWFl/shawn chang 16 1287266 Date: 96·1·3 Patent No. 94131293 modifies the 202 to the edge of the wafer; 204, 216, 304, 324 to the area on the wafer; 206, 218~ plug; 212, 312~ bridge sublayer; 208, 308~ plug sublayer; 210, 220, 310, 320~ bridge; 222, 328~ dielectric structure; 214, 314~ metallization layer; 200, 322, 322-1, 322-2~ multi-layer metal stack Sectional condition; 324~seal ring structure; 326~plug-in, lower-layer bridge; 404, 406, 408, 410, 414, 416, 418, 420, 424, 426, 428, 430, 434, 436, 438, 440 ~ line; 402, 412, 422, 432 ~ corner area; 500 ~ wafer profile 502 ~ seal ring; 506 ~ shallow trench spacer; 510 ~ isolation trench; 514 ~ barrier; 518 ~ core circuit Area, 504~stacked structure; 508~矽 substrate; 512~substrate contact; 516~crystal Depending on the case; 520~ scribe.

0503-Α31117TWFl/shawn chang 17

Claims (1)

1287266 Amendment date: 96·1·3 Revision No. 94131293 Patent Specification: Patent scope: 1. A seal ring structure suitable for protecting a core circuit area of an integrated circuit chip, including: a metallization layer, The utility model has a bridge sublayer and a plug sublayer; a bridge located in the bridging sublayer between a peripheral edge of the integrated circuit chip and a predetermined position of the core circuit section; and a plug The plug sub-layer is substantially aligned with the bridge, wherein the plug has a width that is substantially the same as one of the widths of the bridge. 2. The seal ring structure of claim 1, wherein the plug has a width that is substantially greater than a width of a plug formed in the core circuit region. 3. If the seal ring structure of the special fiber stalk is applied, the width of the towel plug is between 0.4 and 12 microns. The seal ring structure as described in the application of the special fiber, wherein the width of the plug is between 4 and 4 microns. 5. The seal ring structure of claim 1, wherein the plug has a width of between 4 and 1 micron. 6. The seal ring structure of claim i, wherein the metallization layer comprises a dielectric material. 7. The seal ring structure of claim 6, wherein the dielectric material has a dielectric constant of less than 3.0. 8. The seal ring structure of claim 6, wherein the dielectric material is a nitrogen-containing material. A. The sealing ring structure of claim 6, wherein the dielectric material is an oxygen-containing material. The melon is applied for a special profit Μ 6 Lai Shu seal ring structure, which is the person carbon material.十二. 3 η. As claimed in the patent «The sealing ring structure of the sixth item, further includes a _ _ barrier layer, 0503-A31117TWFl / shawn chang 18 1287266: Patent Specification No. 94131293 is located in the dielectric material Below. t 正正·························································································· (4) The touch-transfer layer comprises 15. The seal ring structure as described in the item [i] of the patent application, further comprising a material covering the dielectric material.卩平材一含=糊卿(四)献(四)结构, the towel barrier layer comprises the dense structure as described in claim 15 of the patent application, wherein the second barrier comprises a carbonaceous material. θ ^ material = the sealing ring structure described in the first application of the patent scope, wherein the bridge is composed of a copper-containing instrument, a ring-sealing structure, a core circuit region including a metal a layer having a bridge sublayer and a plug sublayer; a bridge located in the bridging sublayer at a predetermined position of one of the peripheral circuit core circuits of the integrated circuit chip; and at least two plugs, Located within the plug sublayer and isolated by at least one dielectric structure, wherein the plugs have a greater overall width than one of the dielectric structures. 20. The seal ring structure of claim 19, wherein the plugs have a width that is substantially greater than a width of a plug formed in the core circuit region. Further, 2L is the seal ring structure as described in claim 19, wherein the plugs have a width of 0.4 to 12 μm. 0503-Α31117TWFl/shawn chang 19 1287266: Patent specification No. 94131293 modifies this revision period: 96.1.3 Yu 〇. = The sealing ring structure described in item 19 of the patent scope, wherein the widths of the insertions are between 〇 The sealing ring structure of claim 19, wherein the width of the insertion is 24. The dielectric material having a sealing ring electrical constant of less than 3.0 as described in claim 19 of the patent application. The electrical structure comprises a sealing ring structure according to claim 24, wherein the dielectric material comprises an oxygen-containing material, a briquettes, a fine material, and a material comprising a 27. The application is generally (four) 24 trees. The dense carbonaceous material described. The H-age fabric comprises a 28. The seal ring structure as described in claim 19 is located below the dielectric structure. A barrier layer, as described in claim 28, a nitrogen-containing material. , 肀 The younger one barrier layer contains 30. The sealed 兮 an oxygen-containing material as described in claim 28 of the patent application. It is said that the middle of the eight-story barrier layer contains 3L of dense tree-carbonaceous material as described in claim 28 of the patent application.八中五海弟—The barrier layer comprises 32. The sealing ring structure material as described in claim W of the patent application covers the dielectric material. The second barrier material 33. The sealing material described in item 32 of the patent application produces a nitrogen-containing material. And, the second barrier layer comprises: 34. The sealing ring-oxygenated material as described in claim 32 of the patent application. /, the middle and second barrier layers include 20 0503-A31117TWFl/shawn chang 1287266: Patent No. 94131293, the amendment date is: 96 丄 3 / 35. The sealing ring structure described in claim 19, wherein The bridge is made of a steel-containing material. 36. The seal ring structure of claim 19, further comprising a second bridge, located on the bridge sublayer. * 37. The seal ring structure of claim 19, further comprising a second seal ring structure interposed between a peripheral edge of the integrated circuit chip and the core circuit section. 38. A sealing ring structure suitable for protecting a core circuit area of an integrated circuit chip, comprising: a metallization layer having a bridge sublayer and a plug sublayer; a bridge located at the bridge a layer is disposed between a peripheral edge of the integrated circuit chip and a predetermined position of the core circuit section; and at least two plugs are located in the plug sublayer, wherein a total width of the at least two plugs is greater than the bridge The width is 50% or more. 39. The sealing structure of claim 38, wherein the width of the interpolation is substantially greater than the width of the plug formed in the core circuit region. 40. The seal ring structure of claim 38, wherein the width of the inserts is between 0.4 and 12 microns. 41. The seal ring structure of claim 38, wherein the plugs have a width of between 4 and 4 microns. 42. The loop structure of claim 38, wherein the plugs have a width of between 0.4 and 1 micron. 43. The seal ring structure of claim 38, further comprising a dielectric structure having a dielectric material having a dielectric constant of less than 3.0. 44. The sealing ring, body, and structure of claim 43, wherein the dielectric material comprises a nitrogen-containing material. For example, the seal ring structure described in the scope of the patent application, wherein the dielectric material comprises a 0503-A31117TWFl/shawn chang 21 1287266 w. Revision date: 96·1·3 46. As described in 憎·范_3, carbon-containing materials. /, the electrical material contains a '47 tree, please pay attention to 43. It is located below the dielectric structure. Further, the first layer is blocked, and the sealing ring described in claim 43 of the patent application is covered on the dielectric material.冓 冓 further includes a second barrier layer, 49 · a kind of sealing ring structure, suitable for protecting the advancement of a crack, the sealing ring structure comprises: - a group- or a plurality of seal ring lines located in the corner region of the core circuit region; and ..., the corners of the body circuit chip and - the second group - or a plurality of seal ring lines of the core circuit region - an edge interval, the edge of the bulk circuit chip, and the method comprising: each of the back seal lines comprises a metallized film layer, a bridged sublayer and a plug sublayer; - a bridge, a bit bridge One of the predetermined positions of the core circuit section; and a peripheral edge of the integrated circuit chip and the at least - plug, located in the plug sublayer, the width of the object is more than 50%. The total width of the plug is greater than the bridge. If the application for full-time _ 49 scales, the seal ring line includes at least two seal ring lines. , 'where the first group - or more 51 · as claimed in claim 49, the sealing ring circuit includes at least one sealing ring circuit. The mountain U 冓, wherein the second group - or more 52 · The seal ring line as described in the patent application scope includes a non-electrical connection to the first *, clothing, and structure, wherein one of the first group or one of the excess male and the sealing ring is a sealing ring. Line. $,, or 夕一弟一谂封环线的 remaining 0503-A31117TWFl/shawn chang 22 !287266 Patent No. 94131293 Revision Amendment Date: 96.1.3 53. As described in claim 49 a seal ring structure, wherein the first set of one or more seal ring lines comprises a seal ring line non-electrically coupled to one or more of the second set of seal rings. 54. - A semiconductor wafer, including A structure for reducing stress caused by dicing, comprising: a semiconductor substrate; at least one active region, located within the semiconductor substrate; and one or more circuits located within the active region; and a scribe line for cutting the active region Set along the active zone; a seal ring structure surrounding the active region; and at least one shallow trench spacer located in the semiconductor substrate between the seal ring structure and the scribe line. 55. The semiconductor crystal according to claim 54 The semiconductor wafer of claim 54 wherein the sealing ring structure has a width greater than about 10 microns. The semiconductor wafer of claim 54, wherein the active region is a film stack structure, the film stack structure comprising one or more conductive film layers formed by a plurality of via contacts The semiconductor wafer is provided between the one or more conductive film layers. The semiconductor wafer of claim 54, wherein the sealing ring structure is bonded to the semiconductor substrate via one or more The semiconductor wafer of claim 54, wherein the shallow trench spacer is a trench filled with at least one dielectric material. The semiconductor wafer of claim 54 wherein the shallow trench spacer has a depth of at least 3000 angstroms. /, 61. The semiconductor wafer of claim 100, further comprising an isolation Groove, set 0503-A31117TWFl/shawn chang 23 1287266 Amendment date: 96.1.3 wherein the isolation groove is set to be modified by the patent specification No. 94131293 placed on the base between the seal ring structure and the cutting path. The semiconductor wafer according to claim 61 is above the shallow trench spacer. - 63. A semiconductor wafer comprising: a structure for reducing stress caused by cutting, comprising: a semiconductor substrate; at least one An active region, located in the semiconductor substrate; and one or more circuits located in the active region; a cutting channel for cutting the active region disposed along the active region; at least one sealing ring structure surrounding the active region; At least one shallow trench spacer located within the semiconductor substrate between the seal ring structure and the scribe line; and &lt; an isolation trench disposed on the seal ring structure The scribe lines between the position above the semiconductor substrate shallow trench isolation. - The earth - wherein the seal ring structure has 64. The semiconductor wafer of claim 63, which is about one width greater than 10 microns. Or one of the seal ring structures - wherein the shallow turn spacer is the shallow trench spacer 66. The semiconductor wafer of claim 63 is filled with a trench of at least one dielectric material. 67. The semiconductor wafer of claim 63, having a depth of at least 3,000 angstroms. 68. A method for reducing the influence of stress caused by cutting, which is suitable for the active region of the semiconductor-electrical riding along the "--------------------------------------------------------------------------- And etching to remove a portion of the semiconductor substrate for reading between the sealing ring structure and the cutting pass. 〇 503. A31117TWFl/shawn chang 1287266 Revision date: 96·1·3 Patent No. 94131293 modifies the semiconductor A shallow trench spacer is formed in the substrate. 69. The method of reducing the influence of stress caused by cutting according to claim 68 of the patent application, comprising the step of forming a _ 麟 槽 槽 on the base of the quaternary ring structure. 70. A method of reducing the effect of stress caused by cutting as described in claim 68 of the patent application, wherein the 铪 ring structure has a width greater than about one 〇 micron. The method of reducing the effect of stress caused by cutting as described in claim 68, wherein the seal ring structure is grounded via one or more contacts bonded to the semiconductor substrate. 72. A method of reducing the effects of stress caused by cutting as described in claim 68, wherein the shallow trench spacer is a trench filled with at least one dielectric material. The method of reducing the effect of stress caused by cutting as described in claim 68, wherein the shallow trench spacer has a depth of at least 3,000 angstroms. /,in 0503-A31117TWFl/shawn chang 25 '1287266 w : Amendment of Patent Specification No. 94131293 Revision Date: 96.1.3, VII. Designation of Representative Representatives: ^ (1) The representative representative of this case is: Figure 3A. (b) A brief description of the symbol of the representative figure: 304, 324~ area on the wafer; 308~ plug sublayer; 312~ bridge sublayer; 310~ bridge; ^ 314~ metallization; 322~ Stacked structure of metallization layer; 326~ plug; 328~ dielectric structure. 8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: 0503-A31117TWFl/shawn chang 4