Ϊ286378 九、發明說明： 【發明所屬之技術領域】 本發明係有關於積體電路設計，尤其是指_種#恭 放電（electrostatic discharge，ESD)防護電路，.、、希笔 放電防護電路之佈局中，具有可選择性排列之 體區域以調整靜電放電防護電路之寄生電容。 ％曰曰 【先前技術】 在積體電路（integrated circuit, ic)設叶中 一、 (metal-oxide-semiconductor，MOS)電晶體之 p 二氧卞 鴂交屆円心μ —广 之間極氧化層 4谷易囚X到兩壓而損壞。一般常用的積體 二 二:伏特或以下’而普通的靜電放電雷I 就间4千、甚至數萬伏特。即使靜電引起的電流不二， 但如此咼的靜電電壓具有足以毁 t 、 此，如何在靜電雷 毛日日妝之此力。因 。何糸矛貝成具破壞力之黑恭殿义 電荷放電’成為電路料者所關心的課f 4靜電 熱防護電路通f設計在烊墊(bond pad)上。焊 墊為積體電路與外部電路、供應 耸之相技幸1 地線、褕入訊號 、 处。增設的靜電放電防護電路必須不影塑原右 電路的運作，也就是說，靜電放電防 、二:土身至接地點、其他電路或接合墊，此 正常操作之1C核心。t+ y ϋ/、/、 十Μ 電路離對一個操作中的積體電路 2::應電_接到vcc接合塾、地線_物接 口⑥人訊料接到-個或多個輪人接合墊、由核心 0503-A30819TWF/Scarlett 5 1286378 電路產生的輸出訊號耦接到其他接合墊。對一個獨立 ♦ 的、未與任何其他電路耦接的積體電路來說，所有的接 合墊都視為浮接，或位於一個未知的電位。 靜電放電可能發生在任何接合墊上。舉例來說，若 有人接觸到積體電路的接合墊，則被接觸到的接合墊即 接收到人體帶的靜電。此靜電與在乾燥天氣下走過地 毯，再接觸接地的金屬物品所放出的靜電是相同的。對 一個未與任何其他電路耦接的積體電路來說，靜電放電 _ 就像施加一個電源在一個到多個接合塾上’而其他的接 合墊則保持浮接或是接地。由於其他接合墊仍保持接 地，所以當靜電發生在任一的接合墊上時，靜電放電防 護電路的動作與ic於正常操作模式下之操作不同。當靜 電發生時，靜電放電防護電路會迅速的導通，使得靜電 電荷可以被導入地線，也使核心電路免於被靜電電荷破 壞。 因此，一個靜電放電防護電路具有兩種狀態：一種 是正常操作模式，一種是靜電防護模式。當積體電路操 作於正常操作模式時，靜電放電防護電路阻擋了電流流 經其本身，因此對積體電路來說有如不存在一般，避免 - 影響核心電路的運作’而在靜電防護板式下時’靜電放 電防護電路就將靜電放電電流引入地線’以免核心電路 %r 遭到破壞。 習知的四層PNPN裝置，或稱矽控整流器(silicon controlled rectifier，SCR)，為靜電放電防護電路中最有效 0503-A30819TWF/Scarlett 6 1286378 的靜電放電防護元件之一。一個矽控整流器有兩種操作 模式：一種是栓鎖（latch-up)模式，一種是阻隔（blocking) 模式。在阻隔模式中，矽控整流器阻擋電流流入其中， 使得靜電放電防護電路的存在不影響核心電路的運作。 當有一個足夠大的再生電流（regeneraticm current)流入矽 控整流器時，矽控整流器就操作在栓鎖模式。這使得一 個大電流流經矽控整流器，使得靜電放電電流流入時積 體電路時，藉由矽控整流器引開，以避免核心電路遭到 破壞。 增加N型金氧半（NMOS)電晶體的數目可以降低栓 鎖模式中矽控整流器的觸發電壓。然而，NMOS電晶體 的尺寸必須經過精岔計异。若NMOS電晶體的尺寸夠 大，就容易觸發矽控整流器，但是若NM〇s電晶體的尺 寸太小，則無法降低矽控整流器的觸發電壓。由於越大 的NMOS電晶體具有較大之寄生電容，因此，寄生電容 越大，則越容易觸發矽控整流器。 故’本發明之目的為提供—個由矽控整流器構成的 靜電放電防護電路，藉由調H急^傳來降低石夕控整 流器的觸發電壓，以及早啟動靜電放電防護功能。 【發明内容】 本發明提出一可調整寄生電容之靜電放電防護電 路。在本發明之一實施例中，靜電放電防護電路包括= 一矽控整流斋及一金氧半電晶體。矽控整流器耦接在電 0503-A30819TWF/Scarlett 1286378 路接合塾及地線之間^用以在靜電放電發生時，引開由 電路接合墊流入的靜電放電電流。金氧半電晶體具有與 矽控整流器共用之源極，耦接於電路接合墊及地線之 間，用以在靜電放電發生時，降低矽控整流器之觸發電 壓。矽控整流器具有一第一二極體，其與一第二二極體 反向串聯，且上述第一、第二二極體耦接於上述電路接 合墊與上述金氧半電晶體之源極之間，以執行雙載子接 面電晶體之功能，在一靜電放電防護電路之佈局中，用 _ 以放置第一及第二二極體之第一區域位於至少兩個分開 且用來放置金氧半電晶體的第二區域之間。 為使本發明之上述目的、特徵和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 第1A、1B圖分別顯示依據本發明實施例所述之靜電 放電防護電路之剖面圖100及電路圖102。該靜電放電防 護電路包括一閘極接地的NMOS電晶體106、一低電容 的矽控整流器，其中上述矽控整流器包括一第一二極體 ； 108及一第二二極體109,且矽控整流器與NMOS電晶體 106共用一個源極114 〇 參考第ΙΑ、1B圖。在電路圖102中，NMOS電晶體 106具有耦接至電路接合墊112之汲極110，源極114及 耦接至地線或VSS之閘極116。電路接合墊112更耦接 0503-A30819TWF/Scarlett 8 !286378 至一核心電路（未纟會出）’而靜電放電防護電路係用來避免 核心電路遭到靜電放電破壞。第一二極體108與第二< 極體109串聯，且第一二極體108與第二二極體1〇9為 、反向電性連接。在第1A圖中之剖面圖100可看出，第、 二極體之〆端輛接到電路接合藝112，第二二極缝 109之一端耦接到地線。第一二極體1〇8是由P型接觸窗 (contact) 128及P型接觸窗128所位於的N型外 (N-well)132所構成。第二二極體1〇9是由N型井132及 N型井I32所位於的P型基底（substrate)所構成。石夕控楚 流器的一部分就是由第一和第二二極體108、1〇9構成的 雙载子接面電晶體（bipolar transistor) 136组成。一第三〜 極體118和一第四二極體12〇分別耦接於電路接合墊u) 和地線之間、VDD和地線之間，用以使靜電放電防護電 路達到更佳的效能。 剖面圖1〇〇中顯示等效寄生矽控整流器與NM〇s電 晶體、接合墊之連接關係。NM〇s電晶體1〇6的汲極11〇 和源極114 * N型南摻雜（N+ d〇ped)濃度區域組成。源 + 114同也向（iateral)寄生雙載子接面電晶體 而/及極1 0 P型接觸窗128和N型接觸窗13〇都 耦接到電路接合墊112。斗冰^ 此外，N型接觸窗124耦接到操 作電壓獅。P型接觸窗128形成於N型井132之内。 j P型基底和=11 〇接面形成的pN接面構成第三二極 體118，0 L底和，型接猶124的捿轉成第四 0503-A30819TWF/Scarlett 9 1286378 二極體12G°N型井出内有-等效㈣ 於N型井132内的横向寄生pNp型雙载電阻134。位 亦構成石夕控整流器的一部分。當橫向寄面電晶體136 接面電晶體136之射極輕接到p型接觸=型雙載子 到N型接觸窗13Ό，而集極耦'接到橫 ^’基極轉接 接面電晶體122。橫向寄生ρ型雙載子Ν型雙载子 之集極亦透過一基底電阻138及第四二極:面電晶體136 型接觸窗124。橫向寄生ΡΝρ型雙載子^12〇耦接到Ν 和橫向寄生Ν型雙戴子接面電晶體122構，電晶體136 流器。石夕控整流器轉接到NM〇s電晶體义了一石夕控整 第1A、1B圖所顯示的靜電放電防護^源極114。 模式’-種為正常操作模式，—種為靜％ :兩種工作 正常操作模式下，VDD和vss會赛接於供應 晶片得以運作，而電路接合墊112的電聲^宅堅，使侍 vss之間變化。由於NM〇s電晶體1〇6之門:? 得NMOS電晶體106處於關閉狀態（cm_〇ff),型 ==t138使雙載子接面€晶體在正常操作二式 下保持關閉狀恶，使電路接合墊112之電壓可以不受^ 電放電防護電路影響。當操作在靜電模式下時，自電= 接合墊112進入的電壓會遠遠大於VDD和vss之電壓， 此時NMOS電晶體1〇6讓矽控整流電路啟動。在靜 電防護電路中，搭配良好設計的^皿〇3電晶體，矽控整 流器會先工作於栓鎖〈丨atch，up)狀態下，如此可以將避免 靜電放電電流流至核心電路。, 0503-.A30819TWF/Scarlett Ϊ286378 為了要更有效的保護核心電路，矽控整流器的觸發 電壓越低越能及早防止靜電放電電流流入核心電路。如 上所述，靜電放電防護電路中越高的寄生電容會使矽控 整流器的觸發電壓越高。使寄生電容增加的主因之一為N 型井132和P型基底的PN接面。此接面的面積與NMOS 電晶體106的尺寸有關，也就是說，NMOS電晶體106 的尺寸越小，PN接面的面積就越小，進而降低寄生電容 值。 一般來說，如第1A、1B圖所示的靜電放電防護電路 之佈局都免不了要設計小尺寸的NMOS電晶體。在傳統 的佈局中，NMOS電晶體放置的地方與第一二極體108 和第二二極體109是分開來的，再由一長導線耦接NMOS 電晶體和二極體區。若此長導線之等效電阻非均勻分 布，則流經此長導線之電流會因位置不同而改變。如此 可能會導致矽控整流器在栓鎖前導通NMOS電晶體。故 .提高傳統NMOS電晶體之體積以避免電流不均勻的問 題。然而，如此一來又使寄生電容變大，進而提高矽控 整流器之觸發電壓。 第1C圖顯示依據本發明實施例所述之靜電放電防 護電路之佈局圖142。佈局圖142顯示靜電放電防護電路 之元件的設置位置。舉例來說，第1A圖中的NMOS電 晶體106設置在電晶體區144處。狹長型的SCR二極體 區146約置於兩個電;晶;體區、1.44之腐，SC 内放置第一和第二二極禮108、109。附加二極體區148 0503-A3 0819TWF/Scarlett 11 1286378 • 位於SCR二極體區146之末端，第三二極體118係設置 於附加二極體區148内。一防護環（guard ring) 150以及一 笔子冤集防護環（electron collecting guard ring) 152 包圍 整個佈局。防護環150耦接到基底，用以偏壓防護環ι5〇 對N型井的接面。電子蒐集防護環152 _接到供應電壓 VCC用以擴大空乏區，提高蒐集的效率。 母一個電晶體區144包含有複數電晶體，其作用如 第1B圖中的NM0S電晶體106。電晶體區144的大小大 致相门使件母一個電晶體區可等效於一個s電曰 體106。這些電晶體區144可以排的較靠近scr二二二 146J1，以縮短耦接此二區的導線長度，同時也克服了習 知佈π之電流不平均的問題。也因此，可以藉由增加 NM〇S電晶體106的數目，以減小NM0S電晶體1〇6的 尺寸’進而減小寄生電容和矽控整流器的觸發電壓。另 、方面，龟晶體區144的數量增加的話，則可增加寄生 φ 包谷和矽控整流器的觸發電壓。由於NM0S電晶體的實 際尺寸直接的影響到寄生電容值，因此必須透過仔細計 异來決定NM0S電晶體的大小。在本發明的實施例中， 放置有數個電晶體的電晶體區144之寬度為(到彻微 米（μιη)，其中每一個電晶體的寬度為2到8〇微米。 在本發明的另一實施例中，佈局圖142的長寬為49 微米乘以22微米。每一個電晶體區144包括有8個分開 的電晶體，每一個電晶體的览度為L5微米，長度為 微米。因此，每一電晶.體區144的長寬為平 0503-A30819TWF/Scarlett 12 1286378 方微米。在佈局圖142中共有15個電晶體區144，故一 共有120個電晶體，電晶體區面積共佔I]。平 方微米。每兩個SCR:極體區146為一區段（sect〇r)形成 在電晶體區144之間，共有五個區段，佔平方微米 的面積。SCR二極體區146内放置的為PN接面二極體 108和NP接面二極體109,而附加二極體區148(2M2平 方微米）等效於第1A圖中的PN接面二極體us。 第2圖頦示一更詳細的佈局圖15心可以更進一步看 出第ic圖所示之矽控整流器，包括有2個電晶體區144、 一個SCR二極體區146。佈局圖154顯示NMOS電晶體 如何與矽控整流器整合在一起。區域156和158代表第 1C圖中的兩個電晶體區144，而區段160代表1C圖中一 個SCR二極體區區段146。每一塊區域156和158都包 含另8個為一組的NMOS電晶體。NMOS電晶體之源極/ 汲極之標號為164，閘極之標號為162。在區域156、158 的每一個電晶體之寬度為1.5微来，長度為〇·22微米。 佈局圖154中共有16個電晶體，所佔面積為ι·5*.22*16 平方微米。區段160之尺寸為1 ·3*5平方微米，並包括一 ΡΝ接面二極體D1，以構成矽控整流器。 表一列舉出依據本發明之實施例中，觸發電壓與尺 寸大小之關係。Ϊ286378 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to the design of an integrated circuit, in particular to an electrostatic discharge (ESD) protection circuit, and a layout of a discharge protection circuit. The body region is selectively arranged to adjust the parasitic capacitance of the ESD protection circuit. %曰曰[Prior Art] In the integrated circuit (ic), the metal-oxide-semiconductor (MOS) transistor is p-dioxide. Layer 4 Valley is easy to prison X to two pressure and damaged. Commonly used integrated body two two: volts or less 'and the ordinary electrostatic discharge mine I is 4,000 or even tens of thousands of volts. Even if the current caused by static electricity is not the same, the electrostatic voltage so smashed is enough to ruin t, this, how to apply this force on the static day. Because. He Yumao became a destructive black Gong Dianyi charge discharge 'become a circuit material concern class 4 4 electrostatic heat protection circuit through f design on the bond pad. The pad is an integrated circuit and an external circuit, and the supply is good. 1 ground wire, input signal, and place. The added ESD protection circuit must not affect the operation of the original right circuit, that is, the ESD protection, 2: earth to ground, other circuits or bond pads, the 1C core for normal operation. t+ y ϋ /, /, 十Μ The circuit is separated from the integrated circuit in one operation 2:: should be connected to the vcc junction, the ground wire _ object interface 6 people receive the connection to one or more wheel people The pad, the output signal generated by the core 0503-A30819TWF/Scarlett 5 1286378 circuit is coupled to other bond pads. For an integrated circuit that is not coupled to any other circuit, all of the pads are considered floating or at an unknown potential. Electrostatic discharge can occur on any bond pad. For example, if someone touches the bond pad of the integrated circuit, the contact pad that is touched receives the static electricity from the body band. This static electricity is the same as the static electricity emitted by the metal objects that pass through the carpet in dry weather and then come into contact with the ground. For an integrated circuit that is not coupled to any other circuit, the electrostatic discharge _ is like applying a power supply to one or more of the pads, while the other pads remain floating or grounded. Since the other bonding pads remain grounded, the action of the electrostatic discharge protection circuit is different from the operation of the ic in the normal operation mode when static electricity is generated on any of the bonding pads. When static electricity occurs, the ESD protection circuit is quickly turned on, so that the electrostatic charge can be introduced into the ground and the core circuit is protected from electrostatic charge damage. Therefore, an ESD protection circuit has two states: one is the normal operation mode and the other is the ESD protection mode. When the integrated circuit is operated in the normal operation mode, the electrostatic discharge protection circuit blocks the current from flowing through itself, so that it does not exist for the integrated circuit, avoiding - affecting the operation of the core circuit' while under the electrostatic protection plate type 'The ESD protection circuit will introduce the ESD current into the ground wire' to prevent the core circuit %r from being damaged. A conventional four-layer PNPN device, or silicon controlled rectifier (SCR), is one of the most effective ESD protection components of the EDM protection circuit 0503-A30819TWF/Scarlett 6 1286378. A 矽 controlled rectifier has two modes of operation: one is a latch-up mode and the other is a blocking mode. In the blocking mode, the voltage controlled rectifier blocks the flow of current into it, so that the presence of the electrostatic discharge protection circuit does not affect the operation of the core circuit. The controlled rectifier operates in the latch mode when a sufficiently large regenerative current flows into the pilot rectifier. This causes a large current to flow through the pilot rectifier, so that when the electrostatic discharge current flows into the integrated circuit, the rectifier is turned on to prevent the core circuit from being damaged. Increasing the number of N-type MOS transistors reduces the trigger voltage of the 整流 controlled rectifier in latch mode. However, the size of the NMOS transistor must be carefully measured. If the size of the NMOS transistor is large enough, it is easy to trigger the step-controlled rectifier, but if the size of the NM〇s transistor is too small, the trigger voltage of the step-controlled rectifier cannot be lowered. Since the larger NMOS transistor has a larger parasitic capacitance, the larger the parasitic capacitance, the easier it is to trigger the pilot rectifier. Therefore, the object of the present invention is to provide an electrostatic discharge protection circuit composed of a controlled rectifier, which can reduce the trigger voltage of the Shi Xi control rectifier and activate the electrostatic discharge protection function by adjusting the H emergency transmission. SUMMARY OF THE INVENTION The present invention provides an electrostatic discharge protection circuit that can adjust parasitic capacitance. In an embodiment of the invention, the ESD protection circuit includes a voltage controlled rectifier and a MOS transistor. The voltage-controlled rectifier is coupled between the power supply 0503-A30819TWF/Scarlett 1286378 and the ground wire to draw an electrostatic discharge current flowing from the circuit bonding pad when electrostatic discharge occurs. The MOS transistor has a source shared with the 矽-controlled rectifier and is coupled between the circuit bond pad and the ground line to reduce the trigger voltage of the 矽-controlled rectifier when an electrostatic discharge occurs. The step-controlled rectifier has a first diode connected in reverse series with a second diode, and the first and second diodes are coupled to the circuit pad and the source of the MOS transistor Between the two functions of performing the bi-carrier junction transistor, in the layout of the ESD protection circuit, the first region of the first and second diodes is placed at least two separate and used for placement Between the second regions of the gold oxide semi-transistor. The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] Figs. 1A and 1B are a cross-sectional view 100 and a circuit diagram 102, respectively, showing an electrostatic discharge protection circuit according to an embodiment of the present invention. The ESD protection circuit includes a gate-grounded NMOS transistor 106 and a low-capacitance 矽-controlled rectifier, wherein the 矽-controlled rectifier includes a first diode; 108 and a second diode 109, and is controlled The rectifier shares a source 114 with the NMOS transistor 106. Referring to Figures 1 and 1B. In circuit diagram 102, NMOS transistor 106 has a drain 110 coupled to circuit bond pad 112, a source 114 and a gate 116 coupled to ground or VSS. The circuit bond pad 112 is further coupled to 0503-A30819TWF/Scarlett 8 !286378 to a core circuit (not shown) and the ESD protection circuit is used to protect the core circuit from electrostatic discharge damage. The first diode 108 is connected in series with the second < pole body 109, and the first diode 108 and the second diode 1 are electrically connected in reverse. As can be seen in the cross-sectional view 100 of FIG. 1A, the ends of the second and second poles are connected to the circuit junction 112, and one end of the second pole slot 109 is coupled to the ground. The first diode 1 8 is composed of a P-type contact 128 and a N-well 132 in which the P-type contact window 128 is located. The second diode 1〇9 is composed of a P-type substrate in which the N-type well 132 and the N-type well I32 are located. A part of the Shixi control device is composed of a bipolar transistor 136 composed of first and second diodes 108 and 1〇9. A third body 112 and a fourth diode 12 are respectively coupled between the circuit bond pad u) and the ground, between the VDD and the ground, to achieve better performance of the ESD protection circuit. . Section 1〇〇 shows the connection between the equivalent parasitic 矽-controlled rectifier and the NM〇s transistor and bond pad. The NM〇s transistor has a drain of 11〇6 and a source 114*N-doped (N+ d〇ped) concentration region. The source + 114 is also coupled to the circuit bond pad 112 to the (iateral) parasitic bipolar junction transistor and/or the pole 10 P-type contact window 128 and the N-type contact window 13A. Bucket Ice ^ In addition, the N-type contact window 124 is coupled to the operating voltage lion. P-type contact window 128 is formed within N-well 132. The p-type junction formed by the j-P substrate and the =11 junction surface constitutes the third diode 118, the bottom of the 0 L and the junction of the junction 124 is converted into the fourth 0503-A30819TWF/Scarlett 9 1286378 diode 12G° The N-type well has an equi-parasitic pNp type double-load resistor 134 in the N-type well 132. It also forms part of the Shi Xi Control Rectifier. When the emitter of the lateral transfer transistor 136 junction transistor 136 is lightly connected to the p-type contact = type bi-carrier to the N-type contact window 13 Ό, and the collector coupling 'connected to the horizontal ^ ' base adapter junction Crystal 122. The collector of the lateral parasitic p-type bi-carrier 双 type bi-carrier also passes through a substrate resistor 138 and a fourth diode: a surface transistor 136 type contact window 124. The lateral parasitic ΡΝp-type bi-carrier ^12〇 is coupled to the Ν and lateral parasitic 双 type double-fader junction transistor 122, and the transistor 136. The Shi Xi control rectifier is transferred to the NM〇s transistor for a stone control. The electrostatic discharge protection ^ source 114 shown in Fig. 1A and Fig. 1B. Mode '- kind of normal operation mode, - kind of static %: two working normal operation modes, VDD and vss will be connected to the supply chip to operate, and the electric circuit of the circuit bonding pad 112 is strong, so the waits vss Change between. Since the gate of the NM〇s transistor is 1〇6: the NMOS transistor 106 is in the off state (cm_〇ff), the type==t138 causes the double carrier interface to remain closed in the normal operation mode. The voltage of the circuit bond pad 112 can be prevented from being affected by the electric discharge protection circuit. When operating in electrostatic mode, the self-power = bond pad 112 enters a voltage much greater than the voltages of VDD and vss, at which point the NMOS transistor 1〇6 causes the pilot rectifier circuit to start. In the static protection circuit, with a well-designed ^ 〇 3 transistor, the 整 control rectifier will work in the 丨atch, up state, so that the electrostatic discharge current can be prevented from flowing to the core circuit. , 0503-.A30819TWF/Scarlett Ϊ286378 In order to protect the core circuit more effectively, the lower the trigger voltage of the rectifier rectifier, the earlier the electrostatic discharge current can be prevented from flowing into the core circuit. As mentioned above, the higher the parasitic capacitance in the ESD protection circuit, the higher the trigger voltage of the 矽controlled rectifier. One of the main causes of increasing parasitic capacitance is the N-well 132 and the PN junction of the P-type substrate. The area of this junction is related to the size of the NMOS transistor 106. That is, the smaller the size of the NMOS transistor 106, the smaller the area of the PN junction, thereby reducing the parasitic capacitance. In general, the layout of the ESD protection circuit as shown in Figs. 1A and 1B necessitates the design of a small-sized NMOS transistor. In a conventional layout, the NMOS transistor is placed separately from the first diode 108 and the second diode 109, and a long wire is coupled to the NMOS transistor and the diode region. If the equivalent resistance of the long wire is unevenly distributed, the current flowing through the long wire will vary depending on the position. This may cause the pilot rectifier to turn on the NMOS transistor before latching. Therefore, the volume of the conventional NMOS transistor is increased to avoid current unevenness. However, this in turn increases the parasitic capacitance, which in turn increases the trigger voltage of the step-controlled rectifier. Fig. 1C shows a layout 142 of an electrostatic discharge protection circuit in accordance with an embodiment of the present invention. Layout 142 shows the location of the components of the ESD protection circuit. For example, the NMOS transistor 106 in Fig. 1A is disposed at the transistor region 144. The elongated SCR diode region 146 is placed approximately two electrodes; crystal; body region, 1.44 rot, and first and second diodes 108, 109 are placed in the SC. Additional Dipole Region 148 0503-A3 0819TWF/Scarlett 11 1286378 • Located at the end of the SCR diode region 146, the third diode 118 is disposed within the additional diode region 148. A guard ring 150 and an electron collecting guard ring 152 surround the entire layout. A guard ring 150 is coupled to the base for biasing the guard ring ι5 接 to the junction of the N-well. The electronic collection guard ring 152 _ is connected to the supply voltage VCC to expand the depletion zone and improve the efficiency of collection. The parent transistor region 144 includes a plurality of transistors that function as the NMOS transistor 106 in FIG. 1B. The size of the transistor region 144 is such that a phase gate allows a transistor region to be equivalent to an s-electrode body 106. These transistor regions 144 can be arranged closer to the scr 222 261J1 to shorten the length of the wires coupled to the two regions while also overcoming the problem of current π current averaging. Therefore, the parasitic capacitance and the trigger voltage of the pilot rectifier can be reduced by increasing the number of NM〇S transistors 106 to reduce the size of the NMOS transistor 1〇6. On the other hand, if the number of turtle crystal regions 144 is increased, the trigger voltage of the parasitic φ-valve and the controlled rectifier can be increased. Since the actual size of the NM0S transistor directly affects the parasitic capacitance value, the size of the NM0S transistor must be determined by careful measurement. In an embodiment of the invention, the width of the transistor region 144 in which the plurality of transistors are placed is (to the nearest micron), wherein each transistor has a width of 2 to 8 Å. In another embodiment of the invention In the example, the width and width of the layout 142 are 49 microns by 22 microns. Each of the transistor regions 144 includes eight separate transistors, each having a viewing angle of L5 microns and a length of microns. Therefore, each The length and width of the body region 144 are flat 0503-A30819TWF/Scarlett 12 1286378 square micrometer. There are 15 transistor regions 144 in the layout diagram 142, so there are 120 transistors in total, and the area of the transistor region accounts for I. Square micron. Every two SCR: polar body region 146 is a segment (sect〇r) formed between the transistor regions 144, having a total of five segments, occupying an area of square micrometers. SCR diode region 146 The PN junction diode 108 and the NP junction diode 109 are placed inside, and the additional diode region 148 (2M2 square micron) is equivalent to the PN junction diode us in Figure 1A. The figure shows a more detailed layout diagram. The heart can further see the 矽 control rectifier shown in Figure ic, including 2 A transistor region 144, an SCR diode region 146. Layout 154 shows how the NMOS transistor is integrated with the 矽-controlled rectifier. Regions 156 and 158 represent the two transistor regions 144 in Figure 1C, while the segments 160 represents an SCR diode region section 146 in the 1C diagram. Each of the regions 156 and 158 includes another eight NMOS transistors. The source/drain of the NMOS transistor is numbered 164, and the gate is The number is 162. The width of each transistor in the regions 156, 158 is 1.5 micrometers and the length is 〇 22 micrometers. There are 16 transistors in the layout diagram 154, occupying an area of ι·5*.22*16 Square micron. Section 160 has a size of 1 · 3 * 5 square microns and includes a junction diode D1 to form a controlled rectifier. Table 1 lists trigger voltages and dimensions in accordance with an embodiment of the present invention. The relationship between size.
NMOS(3*36Mm) NMOS(4*36|nm) NMOS(5*36Mm) ㈩ vs.VSS HBM 325KV 4.5KV 5.75KV IT2 1.93 A 2.53A 3· 14 人 (+)vs. DD HBM 5.5KV 7KV 7.75KV IT2 2.8A 3·68Α 4.55A 0503-Α30819TWF/Scarlett 13 1286378 表一:依據本發明之實施例之觸發電壓與尺寸大小之關係表 上述之結果係根據人體模型（human body model， HMB)對不同尺寸的NMOS電晶體之靜電放電效應測 試。靜電放電測試係對不同大小的NMOS電晶體之靜電 放電防護電路測試其對正/負電壓的反應。共測試了三種 不同的靜電放電防護電晶體，分別為108微米、144微米 以及180微米。表一之數字代表可以驅動該電路之最高 _ 的電壓和没極電流。表一亦顯示出越小的NMOS電晶體 越可以降低觸發電壓。 本發明藉由以多個、較小的電晶體面積，來降低寄 生電容值以及觸發電壓，可以有效降低啟動矽控整流器 所需的啟動電壓（流），也使靜電放電防護電路可以及早開 啟，使核心電路免於靜電破壞。低寄生電容使靜電放電 防護電路適用於高頻方面的應用，如射頻方面的應用。 _ 本發明所提出之矽控整流器有效降低高頻應用中的寄生 電容值。 本發明雖以較佳實施例揭露如上，然其並非用以限 定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可做些許的更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。 0503-A3 0819TWF/Scarlett 14 1286378 【圖式簡單說明】 第1A圖顯示依據本發明之實施例之靜電放電防護電 路之剖面圖。 第1B圖顯示依據本發明之實施例之靜電放電防護電 路圖。 第1C圖顯示依據本發明之實施例之靜電放電防護電 路之佈局圖。 第2圖顯示依據本發明之實施例佈局之部分放大圖。 【主要元件符號說明】 108〜第一二極體； 110〜汲極； 114〜源極； 118〜第三二極體； 124、130〜N型接觸窗； 134〜N型井電阻； 138〜基底電阻； 14 8〜附加二極體區， 152〜電子蒐集防護環； 160〜二極體區區段； 162〜閘極； VSS〜地線,。 106〜NMOS電晶體； 109〜第二二極體； 112〜電路接合墊； 116〜閘極； 120〜第四二極體；NMOS (3*36Mm) NMOS (4*36|nm) NMOS (5*36Mm) (10) vs.VSS HBM 325KV 4.5KV 5.75KV IT2 1.93 A 2.53A 3· 14 people (+) vs. DD HBM 5.5KV 7KV 7.75 KV IT2 2.8A 3·68Α 4.55A 0503-Α30819TWF/Scarlett 13 1286378 Table 1: Relationship between trigger voltage and size according to an embodiment of the present invention The above results are different according to a human body model (HMB) Electrostatic discharge effect test of a sized NMOS transistor. The ESD test tests the response of positive and negative voltages to electrostatic discharge protection circuits of NMOS transistors of different sizes. Three different ESD protection transistors were tested, 108 microns, 144 microns, and 180 microns, respectively. The numbers in Table 1 represent the highest _ voltage and immersion current that can drive the circuit. Table 1 also shows that the smaller the NMOS transistor, the lower the trigger voltage. By reducing the parasitic capacitance value and the trigger voltage by using a plurality of smaller transistor areas, the invention can effectively reduce the startup voltage (flow) required to start the step-controlled rectifier, and also enable the electrostatic discharge protection circuit to be turned on earlier. Protect the core circuit from electrostatic damage. The low parasitic capacitance makes the ESD protection circuit suitable for high frequency applications such as RF applications. The proposed step-controlled rectifier of the present invention effectively reduces the parasitic capacitance value in high frequency applications. The present invention has been described above by way of a preferred embodiment, and is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. 0503-A3 0819TWF/Scarlett 14 1286378 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a cross-sectional view showing an electrostatic discharge protection circuit according to an embodiment of the present invention. Fig. 1B shows an electrostatic discharge protection circuit diagram in accordance with an embodiment of the present invention. Fig. 1C is a view showing the layout of an electrostatic discharge protection circuit in accordance with an embodiment of the present invention. Figure 2 shows a partial enlarged view of the layout in accordance with an embodiment of the present invention. [Main component symbol description] 108~first diode; 110~dip; 114~source; 118~third diode; 124,130~N type contact window; 134~N type well resistance; 138~ Substrate resistance; 14 8~ additional diode region, 152~ electron collection guard ring; 160~ diode region segment; 162~ gate; VSS~ ground line. 106 to NMOS transistor; 109 to second diode; 112 to circuit bonding pad; 116 to gate; 120 to fourth diode;
122〜寄生雙載子接面電晶體 126、128〜P型接觸窗； 132〜N型井； 136〜雙載子接面電晶體； 144、146〜SCR二極體區； 150〜防護環； 156、158〜電晶體區； 164〜源極/没極； VDD〜操作電壓； 0503-A30819TWF/Scarlett 15122~ parasitic bipolar junction transistor 126, 128~P type contact window; 132~N type well; 136~double carrier junction transistor; 144, 146~SCR diode region; 150~ guard ring; 156, 158 ~ transistor area; 164 ~ source / no pole; VDD ~ operating voltage; 0503-A30819TWF/Scarlett 15