TWI286320B - The weak programming method of a non-volatile memory - Google Patents

Abstract

A weak programming method of a non-volatile memory. A first voltage is applied to a substrate during a first duration, while a control-gate voltage, such as the fourth voltage, is applied to the gate, such that the leakage of the bit line is reduced and electron-hole pairs are generated. In the second duration, a second voltage is applied to the substrate, and a third voltage is applied to the gate to enhance the capability of injecting electrons into the floating gate of the non-volatile memory. Therefore, the distribution of the threshold voltage is more concentrated. The second voltage has a polarity the same as that of the first voltage, while the polarity of the third voltage is opposite to that of the second voltage.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a weak stylized method, and more particularly to a non-volatile memory (Non-Vo). 1 at i ie Memory) weak stylized method. / Previous technology

Flash Memory is an electrical erasable programmable read-only memory (EEPR0M) that has the advantages of being writable, erasable, and capable of saving data after power-off. It is a personal computer and A memory component widely used in electronic devices. In addition, the flash memory is a non-volatile memory (NVM), which has the advantages of small volume, low access speed, and low power consumption. Flash memory is erased by Block by Block when erasing Erasing, but it is often used in the commonly used Fowler-Nordheim channel erasing method. Erasing' results in a wide distribution of the threshold voltage and a larger leakage current of the bit line of the flash memory.

In a conventional flash memory, a tunneling oxide layer is separated from a floating gate by a tunneling oxide layer, and a control gate is disposed on the floating gate. The two gates are separated by an Inter-gate Dielectric Layer. The flash memory is a stacked gate flash memory, and the floating gate and the control gate are doped. The polycrystalline germanium is fabricated, and the source region and the nonpolar region are disposed on both sides of the substrate. ^ When the flash memory is in the process of writing data, the source is

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1286320 Case No. 92113288 V. INSTRUCTIONS (2) The substrate is grounded and an appropriate voltage is applied to the control gate and the drain to inject electrons into the floating gate. When reading the data in the flash memory, an appropriate working voltage is applied to the control gate, and the charged state of the floating gate affects the on/off of the lower channel, and the channel The opening/closing is the basis for interpreting the data value “0” or “丨”. In addition, when the flash memory is erased, the relative potential of the substrate, the germanium (source) region or the control gate is increased, and the tunneling effect is used to pass electrons through the floating gate. The oxide layer is discharged to the substrate (ie, Substrate Erase) or Drain (Source) Side Erase, or is discharged through the gate dielectric layer into the control gate. In the operation of writing to the flash memory, channel Hot Electron injection (CHEN mode is used to program the flash memory) to write data to the flash memory. In the body, when data is erased in the flash memory, electrons are pulled out from the floating gate through the tunneling oxide layer into the channel in a Fowler Nordheiro tunneling mode.

"When the data is erased in the FN tunneling mode, the number of electrons pulled out from the floating gate is not easily controlled, so it is easy to generate too many electrons pulled out from the floating gate, so that floating The gate is positively charged, causing the phenomenon of 〇ver - E rase, and the distribution of the threshold voltage of the flash memory is widened and the drain current is generated by the bit line. If the erasing is too severe, the channel will not be turned on without the voltage of the control gate, resulting in erroneous data. Therefore, it is customary to use additional Soft Program and erase erase confirmation (0ver-Erase).

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1286320 92113288 V. Inventive Note (3) V erify ) to remedy the over-erasing problem of flash memory, the increase of 4 erasing time and the increase of the hardware circuit area will result in the invention. Therefore, the present invention proposes a non-volatile (Weak Program) method for correcting the weak program phenomenon of the non-volatile body and reducing the erasing time to improve the erasing degree of the non-volatile memory. . S & the reliability of the memory is to achieve the weak programming of the gate and the substrate, the first voltage, and the control, on the substrate. Wherein the polarity of the first first voltage is in the first region to reduce the non-volatile leakage current, resulting in a non-volatile electron-hole pair. The second region is applied with a third voltage plus ' to increase the injection target. Other methods: weak-range braking plus the opposite of the voltage, memory weak memory, the non-volatile memory flickering method is to apply a fourth voltage to the control electrode in the first zone; Apply

Eight people, in the first voltage of two voltages, and the power applied to the control gate is the same as the polarity of the first voltage T u 'the third voltage and the first voltage applied to the substrate are negative, the leakage current of the bit line, Avoiding the low efficiency of bit line tying, and at the junction electric field at the junction of the first region of the first interval, a second 'applied to the substrate and the control gate' is generated to control the gate and the substrate. The vertical electric field between the two increases the number of the floating gate of the non-volatile memory. 4 The present invention is the first when the non-volatile memory has been erased.

1286320 Case No. 92113288 Amendment 、 V, invention description (4) First 'apply a negative voltage on the substrate (P-type well area), and apply a fourth voltage on the control gate 'Second' to maintain the previous on the substrate (P-type well area) A negative voltage is applied and a positive voltage is applied to the control gate. The above steps will generate an electron-hole pair in the non-volatile memory junction with the drain region, and then increase the vertical electric field in the non-volatile memory when a positive voltage is applied to the control gate. The strength, so that the electrons have enough energy to pass through the oxide layer into the floating gate. The above and other objects, features, and advantages of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; It is not intended to be a profile of a flash memory in a non-volatile memory. In FIG. 1, the flash memory includes a substrate 1 ο 隧, a tunneling oxide layer 1 〇 2, a floating gate layer 丨〇 4, an inter-gate dielectric layer 丨〇 6, a control gate layer 1 0 8 , The source region 1 1 〇 and the drain region 1 丨 2 . Substrate 1 0 0 ' As is known to those skilled in the art, the substrate 丨〇 can be a ruthenium material. A well region is disposed in the substrate 100. The control gate 108 is disposed on the substrate 100. The floating gate 104 is disposed between the control gate 102 and the substrate 1 ,, wherein 'the material of the control gate 1 〇 8 and the floating gate 1 〇 4 can be doped as known to those skilled in the art. Polycrystalline germanium. The gate dielectric layer 106 is disposed between the control gate 108 and the floating gate 1〇4, and the material of the gate dielectric layer 1〇6, if cooked, the artist may know that it may be an oxidized oxide eve. / nitrided / oxidized;: The material of the layer 106 can also be oxidized ... oxidized stone Xi Xi layer special. The tunneling oxide layer 108 is disposed on the oceanic gate 1〇4 and the substrate 1

1286320 Case No. 92113288 Noon, Friday, Amendment V. Invention Description (5) The material of the tunneling oxide layer 108 is known to those skilled in the art and may be oxidized stone. Source area 1 1 0 and bungee area! 2 is disposed in the substrate 1 0 0 on both sides of the floating gate 1 〇 4 . As can be seen by those skilled in the art, the flash memory can be n-plastic channel flash memory and p-type channel flash memory. In the n_channel flash memory, the modes of writing data and erasing data include: (1) Injecting electrons into the floating gate 1 in the drain region 112 by the channel hot electron injection (CHEI) mode 1 〇 4 Medium (write data), and pull the electrons out (source data) from the source region. (2) Using the F N tunneling mode, electrons are injected into the floating gate 丨〇 4 (writing data) in the channel region, and the electrons are pulled out from the drain region in the Fn tunneling mode to remove the data). V徕 (3) uses F N tunneling mode to inject electrons into the floating gate in the channel region (write data), and divide the data from the channel region in FN tunneling mode). % τ &lt; ® V socks, using channel hot electron injection (CHEI) mode, will be injected into the floating gate 1〇4 in the drain region 112 (write data), and pull the electrons from the channel region by FN Out (erasing data) Calling in the p_-type channel flash memory, the data-writing mode includes: Ding, and removing the Becky (1) Using the channel hot electron injection (CHEI) mode in the 汲The pole region 112 is placed in the gate 104 (writing data), and the electrons are pulled out from the channel region in the FN follow-up mode (erasing data). Jun (2) Using the valence band-guideband tunneling effect caused by the channel thermal electrons 1286320 - Case No. 92113288__年月日日 Revision__ V. Invention description (6) (Band-to-Band tunneling induced Hot Electron Injection, referred to as BB HE) mode, injects electrons into the floating gate 1 0 4 (write data) in the drain region 11 and pulls out the electrons from the channel region in F n tunneling mode (erasing data). Next, please refer to FIG. 2A, FIG. 2B and FIG. 2C, respectively, which respectively illustrate the operation diagram of the weak stylized method of the flash memory in the non-volatile memory of the preferred embodiment of the present invention, wherein This includes stylizing this flash memory and correcting the flash erase over erase operation in a weakly stylized way. b When the flash memory is programmed, a voltage of, for example, 9 volts to 12 volts is applied to the control gate 1 0 8 . §, a voltage vd of, for example, 5 volts to 7 volts is applied to the drain 丨12 such that the voltage of the source 11 例如 is, for example, 〇 volt and the substrate 1 Ρ (Ρ well region) voltage is 〇 volt. Under such a voltage condition, a large channel current (〇·25 mA/memory cell to 1 mA/memory cell) is generated, in which the electron system moves from the source 11 terminal to the drain 112 end, The 〉 and pole 112 ends are accelerated by a high-channel electric field to generate hot electrons, and the kinetic energy is sufficient to overcome the energy barrier of the tunneling oxide layer ,2, and a high positive voltage is applied to the control electrode 108 to make the hot electrons The tip of the drain 12 is injected into the ocean gate 104 as shown in FIG. 2A. After the stylization, due to the net negative charge on the floating drain 1 〇 4, the 1 / voltage (VT) of the non-volatile memory will rise. These electrons stay in the floating gate 丨〇 4 for a period of time (for example, at room temperature, the residence time is about ten years), and they are erased unless they are forbearing. In the second diagram, we use the FN erase operation mode to apply a fourth voltage of, for example, 0 volts to the control gate, applying, for example, to the substrate 100.

Case No. 92113288 1286320 曰Λ_3 V—Inventive Note (7) __ is a positive voltage of 20 volts, and the source region 1 1 0 and the xenon state pull the electrons out of the floating gate 104 to the pass For the floating situation, it is impossible to control the number of electrons pulled out, resulting in over-wiping ^ 'and because of the positive charge in our gate 1 0 4 . So that floating in Figure 2C, in order to remedy the erase, applying an electric demon, for example, about 2 volts on the substrate 10 我们, we first apply a fourth voltage, for example, 〇 'The two-gate gate 1 10 0 is grounded, the drain region 1 1 2 is applied, for example, 4 to 5 volts ^ and the source region will generate an electron hole in the junction of the drain region 1 i 2, :, this = leakage current, then, on the control interpole 108: plus and '= ΐί: the voltage around, while the substrate 100 still applies negative 2; especially I, this ^ 2 〇 grounded 'the non-polar region 112 is 4 to The electrical memory of the volts of about 5 volts J = the positive voltage of the ' 使得 使得 使得 使得 使得 使得 使得 非 非 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 This 篁 passes through the tunneling oxide layer 1 0 2 into the floating in the test "V X. Flash memory. In the best example, the flash memory is η-type channel, please continue to match your picture. The green one is the third picture, the fourth picture, the fourth picture and the 4th flash memory. In the non-volatile memory of the preferred embodiment, the non-volatile, voltage-operated operation timing diagram and the preferred embodiment of the present invention respectively contain the threshold voltage distribution map of the flash memory in the memory. The threshold voltage distribution diagram after the threshold 畲$ erasing and the weak distribution map of the present invention are outside the range from time t 0 to 11

1286320 -SS_92113288 V. Description of invention (8) Remediation zone, the range of t1 to t2 is the following remediation zone.昤捃Ϊ4二Γ A voltage distribution map has been generated for the flash memory in non-volatile memory, in which the critical voltage distribution includes the outer 3, and the remediation area. Therefore, in Figure 3, the outer line of tl to tl ^ we apply a voltage of about 2 volts on the substrate, control the closed pole to apply 0 volts, and the source region is grounded, and the drain region applies a voltage of about 4 to 5 volts. As a result, not only the leakage current of the bit line is reduced, but also the polymerization point of the threshold voltage is shifted to the right (as depicted in FIG. 4B). Then, in the following compensation region of t1 to t2 in Fig. 3, we apply a voltage of about 0.5 volts to about 5 volts on the control gate, while the substrate still applies a voltage of minus 2 volts, and the source region is grounded. The voltage in the drain region of about 4 to 5 volts enhances the amount of electrons injected into the floating gate, and the junction point 300 of the threshold voltage continues to move to the right (as depicted in Figure 4C). Therefore, it can be seen from Fig. 4A, Fig. 4B and Fig. 4c that the distribution of the threshold voltage is made closer after the weakly programmed flash memory. In summary, the weak stylized method of the flash memory in the non-volatile memory of the present invention has the following advantages: (1) The weak stylized method of the flash memory in the non-volatile memory of the present invention can It is simply controlled by the voltage of the control gate to obtain a narrower erase threshold voltage distribution. (2) The weak stylized method of flash memory in the non-volatile memory of the present invention 'supplied by the application of a negative voltage on the substrate, the degree of injection of the thermoelectric hole into the S i 0 2 /S i interface can be reduced, and the non-improvement can be improved. Volatile memory cell reliability 0

10175twfl.ptc Page 16 1286320 _ Case No. 92113288_年月日日 Revision _ V. Invention Description (9) (3) The weak stylized method of flash memory in the non-volatile memory of the present invention, after erasing The remedy and power consumption can be reduced after the operation of erasing the threshold voltage is tighter. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10175twfl.ptc Page 17 1286320 _ Case No. 92113288_± Schematic description of the monthly correction Figure 1 shows a cross-sectional view of a flash memory in a non-volatile memory, and Figure 2A shows the invention. An operational diagram of a weakly programmed method of flash memory in a non-volatile memory of a preferred embodiment; FIG. 2B is a diagram showing a weak program of a flash memory in a non-volatile memory of a preferred embodiment of the present invention FIG. 2C is a diagram showing the operation of the weak program method of the flash memory in the non-volatile memory of the preferred embodiment of the present invention; FIG. 3 is a view showing a preferred embodiment of the present invention; A weakly programmed operating voltage timing diagram of flash memory in non-volatile memory;

4A through 4C are diagrams showing the threshold voltage distribution of the flash memory in the non-volatile memory of the preferred embodiment of the present invention. The figure does not indicate: 100 base 102 tunneling oxide layer 104 floating gate 106 gate dielectric layer 108 control gate 110 source region 112 thorium region 300 polymerization point

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Claims (1)

1286320 Amendment VI. Applying for a patent year, 弱IΓ, a weak stylized method for non-volatile memory, the non-volatile step ν includes a control gate and a substrate, the method comprising the following steps in a first interval Applying a first voltage to the substrate and applying a fourth voltage to the control gate; and applying a second voltage to the substrate in the first interval and applying a third voltage to the batch gate The second voltage is the same as the polarity of the first voltage, the third thermal polarity phase... The second interval is operated by is 41 ί I, the non-volatile matter described in the first item of the patent scope The weak step of the sexual memory: including the step of the first interval, and then the program 3, ί Γ the non-volatile memory of the non-volatile memory described in the first item of the range For the Π-type channel flash memory 化/化m: the weak 非 of the non-volatile memory described in the first item of the range i ί ? ΐ , the first interval, when the substrate is a p-type substrate, πίίϊί The first voltage is a negative voltage to reduce the non-volatile enthalpy Recover the leakage current of the 7-turn line. Early praise 5 · The non-swinging method described in item 4 of the patent application scope, wherein the first voltage includes a negative 2 volts and the weakness of the hidden body 6 · If the patent application scope is not the same as the wave # ^ ^ ^ Stylized method, where the second voltage includes a negative 2 volts and a weak body 10175twfl.ptc Page 19 1286320 _ Case No. 92113288_年月日日 Revision _ 6. Patent application scope 7. The weakly stylized method of non-volatile memory according to claim 1, wherein the third voltage Includes from about 0.5 volts to about 1.5 volts. 8. The weakly stylized method of non-volatile memory according to claim 1, wherein the fourth voltage comprises about 0 volts. 9. A method of modifying a non-volatile memory over-wiping, the non-volatile memory comprising at least a control gate and a substrate, the method comprising the steps of: erasing the non-volatile memory; in a first interval, Applying a first voltage to the substrate, and applying a fourth voltage to the control gate; and | applying a second voltage to the substrate in a second interval, and applying a third voltage to the control gate; The second voltage is the same polarity as the first voltage, the third voltage is opposite to the second voltage, and the second interval is operated by hot electron injection. 1 . The method for modifying the non-volatile memory over-erasing according to claim 9 of the patent application, further comprising the step of performing the first interval first, and then performing the step of the second interval. Π A method for correcting non-volatile memory over-wiping as described in claim 9 wherein the non-volatile memory is erased by Fowler-Nordheim tunneling to generate a plurality of electrons from the non-volatile memory. One of the volatile memories is pulled out inside the floating gate. 1 2 · Non-volatile memory excess as described in claim 9 10175twfl.ptc Page 20 1286320 Case No. 92113288 修正 Amendment VI. Patent application scope Correction method for erasing, which is non-memory. 1 3 . The correction method of the ninth erasing of the patent application scope, wherein the first time, the leakage of the bit line of the first volatile memory applied to the substrate is 1 4 . The method of correction, wherein the method of modifying the ninth erasing of the patent application scope, wherein the first method is the modification method of the ninth application of the patent scope, wherein the first and the third. 1 7 . The correction method of the ninth erasing of the patent application scope, wherein the first volatile memory is an interval of non-volatile memory of the n_channel flashing term, when the substrate is a P-type substrate voltage It is a negative voltage to reduce this non-current. The non-volatile memory of the three items described above has a negative voltage of about 2 volts. The non-volatile memory excess voltage described in the item includes a negative voltage of about 2 volts. The non-volatile memory excess described in the above three voltages includes a non-volatile memory excess of 0.5 volts to 1.5 volts. The four voltages include about 0 volts. 10175twf1.ptc Page 21 1286320 MM 921132«« 年月曰修四, Chinese invention summary (invention name: weak stylized method of non-volatile memory) Fang Jiaxiao system set two polarization P control floating type In the middle of the pole, the pressure-stroke brakes and the weak electric power in the body, recall the second control of the pressure. First, and the electricity production is dense, and the second is tight and the square pressure, the first wave is the pressure current plus the non-electrical type, the electric energy is applied to the three-way first leakage, and the weakly added base is applied. In the voltage homologous element, the boundary between the power-on phase and the base is recorded in the small area to reduce the polarity, and the second voltage is used to make the electricity and the pressure area in the third place. A type of second pressure addition. The first is the electric and the anti-system 4; the extreme pole phase method is the first pair of gates, (1), the representative figure of the case is: ____2 A____ diagram (2), the representative figure of the representative figure is simple symbol Description: 1〇2: tunneling oxide layer, 1 0 4 : floating gate, 1 〇 6 · gate dielectric layer, 1 〇 8 · · control gate, 1 1 0 : source region, 1 1 A. The weak programming method of a non-volatile memory. A weak programming method of a non-volatile memory. A weak programming method of a non-volatile memory. A first voltage is applied to a substrate during a first duration , a control-gate voltage, such as the fourth voltage, is applied to the gate, such that the leakage of the bit line is reduced and e 1 ectron-ho 1e pairs are generated. In the second duration, a second voltage is Applied to the substrate, and a third voltage is applied 10175twfl.ptc Page 5 1286320 Case No. 92113288 Year Month Correction 10175twfl.ptc Page 7