CN106326780B - A kind of phy chip fingerprint generation method and system - Google Patents
A kind of phy chip fingerprint generation method and system Download PDFInfo
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- CN106326780B CN106326780B CN201610695830.XA CN201610695830A CN106326780B CN 106326780 B CN106326780 B CN 106326780B CN 201610695830 A CN201610695830 A CN 201610695830A CN 106326780 B CN106326780 B CN 106326780B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
Abstract
The invention discloses a kind of phy chip fingerprint generation methods, comprising: generates the first operation signal and the address of phy chip storage array；Storage array was carried out the weak programming operation of erasing or crossed to program weak erasing operation according to the first operation signal and address；Read operation is carried out to storage array, judges whether the threshold value distribution of cells of memory arrays meets preset value, if so, the fingerprint for completing storage array generates；If it is not, then: generating the second operation signal of phy chip storage array；Storage array was carried out the weak programming operation of erasing or crossed to program weak erasing operation according to the second operation signal and address, until judging that the threshold value distribution of cells of memory arrays meets preset value when carrying out read operation to storage array.The present invention can be improved the reliability of phy chip.The invention also discloses a kind of phy chip fingerprints to generate system.
Description
Technical field
The present invention relates to chip encryption technical field more particularly to a kind of phy chip fingerprint generation method and systems.
Background technique
With the development of information-based industry, more and more electronic products enter the public visual field and become live it is necessary
Product.The information security of electronic product already becomes the significant challenge faced at present.And the core as electronic product
Part --- IC chip becomes the most important thing of security protection research.
The principle of physical security chip is that certain safeguard procedures are arranged in the chips, even if attacking so that chip is stolen
The person of hitting can not also obtain the confidential information contained inside it.Common physical protection method includes: that metal is arranged in the chips
Protective layer, passivation layer are used vulnerable to the material of strong acid caustic corrosion and the sequence for upsetting some circuit modules of chip interior etc..
But these physical protection methods only increase the difficulty that attacker steals chip data to a certain extent,
It increases attacker and attacks the cost that chip information is paid, can not fundamentally prevent attacker to the robber of chip data
It takes.
Summary of the invention
The present invention provides a kind of phy chip fingerprint generation methods, can be improved the reliability of phy chip.
The present invention provides a kind of phy chip fingerprint generation methods, comprising:
Generate the first operation signal and the address of phy chip storage array；
The storage array was carried out the weak programming operation of erasing or crossed to program according to first operation signal and address
Weak erasing operation；
Read operation is carried out to the storage array, it is default to judge whether the threshold value distribution of the cells of memory arrays meets
Value, if so, the fingerprint for completing the storage array generates；If it is not, then:
Generate the second operation signal of the phy chip storage array；
The storage array was carried out the weak programming operation of erasing or crossed to program according to second operation signal and address
Weak erasing operation, until judging that the threshold value distribution of the cells of memory arrays is full when carrying out read operation to the storage array
Sufficient preset value.
Preferably, described that the storage array is carried out weak programming or crossed to program according to first operation signal and address
Operation includes:
Generate element address, programming value and the programming duration of phy chip storage array to be programmed；
Element address according to the storage array to be programmed generates a programming source line voltage and a programmed word line
Voltage；
By the source line and wordline of programmed source line voltage and programmed word line voltage-drop loading to the storage array to be programmed；
Program current is generated according to the programming value；
The storage array to be programmed is programmed in the programming duration by the program current.
Preferably, described that erasing or weak erasing were carried out to the storage array according to first operation signal and address
Include:
Generate element address and the erasing duration of phy chip storage array to be erased；
Element address according to the storage array to be erased generates an erasing word line voltage；
The erasing word line voltage is loaded into the wordline of the storage array to be erased；
According to the erasing duration, the storage array to be erased is wiped in the erasing duration.
Preferably, described to include: to storage array progress read operation
Generate element address and the read operation signal of phy chip storage array to be read；
Element address according to the storage array to be read generates a reading word line voltage；
The reading word line voltage is loaded into the wordline of the storage array to be read；
The size of current of the storage array to be read is flowed through according to the read operation signal detection, and according to the electricity
It flows size and exports read operation result.
A kind of phy chip fingerprint generation system, comprising:
Generation unit, for generating the first operation signal and the address of phy chip storage array；
Operating unit, for carrying out the weak programming of erasing to the storage array according to first operation signal and address
It operates or crosses and program weak erasing operation；
Read operation unit judges the threshold of the cells of memory arrays for carrying out read operation to the storage array
Whether Distribution value meets preset value, when the threshold value for judging the cells of memory arrays, which is distributed, meets preset value, deposits described in completion
The fingerprint for storing up array generates；
When the threshold value for judging the cells of memory arrays, which is distributed, is unsatisfactory for preset value, the generation unit is also used to generate
Second operation signal of the phy chip storage array；
The operating unit is also used to carry out erasing to the storage array according to second operation signal and address
Weak programming operation programs weak erasing operation excessively, until the read operation unit carries out read operation to the storage array
When, judge that the threshold value distribution of the cells of memory arrays meets preset value.
Preferably, the operating unit includes:
Logic control circuit, for generate the element address of phy chip storage array to be programmed, programming value and
Program duration；
Adjustable high-tension circuit, for the control based on the logic control circuit, according to the storage array to be programmed
Element address generate a programming source line voltage and a programmed word line voltage；
Row decoding circuit, for selecting the programming source line voltage and programmed word line voltage, by programmed source line
The source line and wordline of voltage and programmed word line voltage-drop loading to the storage array to be programmed；
Program current generation circuit is programmed for being generated by the logic control circuit according to the control of the programming value
Electric current；
Array decoding circuit, for being connected with the program current generation circuit；
The logic control circuit is also used to through the program current in the programming duration to described to be programmed
Storage array is programmed.
Preferably, the operating unit includes:
The logic control circuit is also used to generate element address and the wiping of phy chip storage array to be erased
Except duration；
The adjustable high-tension circuit, is also used to the control based on the logic control circuit, deposits according to described to be erased
The element address for storing up array generates an erasing word line voltage；
The row decoding circuit is also used to by selecting the erasing word line voltage being loaded into the storage to be erased
The wordline of array；
The logic control circuit is also used to according to the erasing duration, to described to be erased in the erasing duration
Storage array wiped.
Preferably, the read operation unit includes:
The logic control circuit is also used to generate element address and the reading of phy chip storage array to be read
Operation signal；
The adjustable high-tension circuit, is also used to the control based on the logic control circuit, deposits according to described to be read
The element address for storing up array generates a reading word line voltage；
The row decoding circuit is also used to by selecting the reading word line voltage being loaded into the storage to be read
The wordline of array；
Array decoding circuit, for being connected with sense amplifier；
The sense amplifier, for flowing through the electricity of the storage array to be read according to the read operation signal detection
Size is flowed, and exports read operation result according to the size of current.
Preferably, the system also includes:
Voltage and current reference circuit, with the adjustable high-tension circuit, sense amplifier and program current generation circuit phase
Even, for providing the reference voltage value and current value unrelated with temperature change.
Preferably, the adjustable high-tension circuit include: charge pump circuit, voltage sampling circuit, it is adjustable relatively potential circuit,
Comparator, clock generation circuit, timing circuit and charge pump clock circuit；Wherein:
The timing circuit is connected with the logic control circuit and clock generation circuit respectively；
The charge pump clock circuit is connected with clock generation circuit, charge pump circuit and comparator respectively；
The adjustable relatively potential circuit is connected with the logic control circuit and comparator respectively；
The voltage sampling circuit is connected with the charge pump circuit and comparator.
By above scheme it is found that a kind of phy chip fingerprint generation method provided by the invention, passes through generation phy chip
The operation signal of storage array and address carried out the weak programming operation of erasing or mistake to storage array according to operation signal and address
Weak erasing operation is programmed, until the threshold value distribution of cells of memory arrays meets default when carrying out read operation to storage array
Value, the fingerprint for completing storage array generate.Weak erasing operation is programmed by crossing to wipe weak programming operation or cross, can be generated more
Stable and more random key data, improves the reliability of phy chip.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of basic flash cell disclosed by the invention；
Fig. 2 is a kind of flow chart of phy chip fingerprint generation method disclosed by the embodiments of the present invention；
Fig. 3 is the threshold value distribution that mistake disclosed by the invention wipes storage array after weak programming operation；
Fig. 4 is the threshold value distribution that mistake disclosed by the invention programs storage array after weak erasing operation；
Fig. 5 carries out the weak method flow diagram programmed or cross programming operation to storage array to be disclosed by the invention；
Fig. 6 is the method flow diagram disclosed by the invention that erasing or weak erasing operation were carried out to storage array；
Fig. 7 is the method flow diagram disclosed by the invention that read operation is carried out to storage array；
Fig. 8 is the structural schematic diagram that a kind of phy chip fingerprint disclosed by the embodiments of the present invention generates system；
Fig. 9 is the structural schematic diagram that another phy chip fingerprint disclosed by the embodiments of the present invention generates system；
Figure 10 is the structural schematic diagram of adjustable high-tension circuit disclosed by the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1, being the structure of basic flash cell disclosed by the invention, flash cell is being programmed and is being wiped
The mechanism removed is thermoelectron injection and F-N tunnelling respectively.By to flash cell different port wordline WL, bit line BL and source line SL
Apply specific voltage, electric current, due to the effect of above two mechanism, electrons are across insulating medium layer (usually Si-
SiO2 potential barrier), in channel and floating gate (Floating Gate), the floating gate and control gate (Control Gate) of storage unit
Between flowed.When being programmed, electronics enters floating gate from cell channel, improves the threshold voltage of storage unit；When
When being wiped, electronics tunnelling from floating gate enters control gate, since electronics is reduced on floating gate, the threshold voltage of storage unit
It decreases.
Due to the fluctuation of manufacturing process, the dielectric bed boundary of each storage unit, there are differences for source and drain doping concentration
Different, thus in the case where identical programming is with erased conditions, there is differences for the efficiency of different its electron transfer of storage unit, this leads
A storage unit threshold voltage not instead of single value after causing programming or erasing, has certain distribution.Previous programming
It is all to be adjusted to storage unit threshold value to reading outside distinguishable window with erasing, i.e. formation " strong flash cell " is read
When can differentiate the data of flash memory cell by distinguishing the firing current of storage unit.
For same flash memory cell, when applying different programmings with erasing operation condition, the programming of flash cell and
Erasing speed is different.Different flash cells due to technique fluctuation, even if programming with erasing operation during use
Identical operation, there is also apparent differences for the programming of different flash memory cells and efficiency of erasing.For array, pass through
After program/erase operation, the threshold value of a unit not instead of value, a distribution.The threshold value of part of unit is programmed
It is excessively high, or wipe too low, programming/mistake erasing is referred to as crossed, it is more higher than common program/erase to cross programming/mistake erasing requirement
Voltage and longer time.So that flash memory cell is become " phy chip fingerprint key storage unit ", wiping need to be carried out
Except-it is weak programming or cross programming-two steps of weak erasing operate.
As shown in Fig. 2, for a kind of phy chip fingerprint generation method disclosed in the embodiment of the present invention one, comprising:
S101, the first operation signal for generating phy chip storage array and address；
When needing to generate the fingerprint of phy chip, the first operation signal and ground of phy chip storage array are firstly generated
Location, the address correspond to the element address of storage array to be processed.
S102, the weak programming operation of erasing or mistake were carried out to the storage array according to first operation signal and address
Program weak erasing operation；
The weak programming operation of erasing was carried out to storage array according to the first operation signal of generation and address or was programmed excessively weak
Erasing operation.It is specifically described for crossing erasing-weak programming operation, erasing operation was being carried out to flash memory storage array
Afterwards, the threshold value of flash memory storage array can be made to be distributed and tend to be unified, be lower state.In weak programming, general storage unit
Channel in have a biggish electric current, electronics is accelerated in channels and has part to enter floating gate, changes the threshold value of unit.In threshold
After value is enhanced, the electric current in channel becomes smaller, and the electronics for being able to enter floating gate also accordingly tails off, that is, the efficiency programmed reduces,
And over time, efficiency is lower in the backward.The process of weak programming can be divided into several stages, to different unit point
Not Tiao Zheng wordline and bit line voltage, make flash memory cell all in array enter " phy chip fingerprint key storage
Unit " threshold interval.Shown in Fig. 3 is after carrying out erasing, and the threshold value of storage array is unified for Vth0, then to each unit
Weak programming is carried out, is distributed VthN by the random threshold value that statistics obtains entire storage array.Shown in Fig. 4 was the weak wiping of programming-
Except the threshold value distribution of storage array after operation.
S103, read operation is carried out to the storage array, judges whether the threshold value distribution of the cells of memory arrays is full
Sufficient preset value, if so, S106 is executed, if it is not, then executing S104:
After carrying out the weak programming operation of erasing to storage array or programming weak erasing operation excessively, storage array is read
It operates, is judged after mistake wipes weak programming operation or programs weak erasing operation excessively out, the threshold value distribution of cells of memory arrays is
It is no to meet preset value.
S104, the second operation signal for generating the phy chip storage array；
When the threshold value for judging cells of memory arrays, which is distributed, is unsatisfactory for preset value, changed again the weak programming operation of erasing or
It crosses and programs weak erasing operation condition, that is, generate the second operation signal.
S105, the weak programming operation of erasing or mistake were carried out to the storage array according to second operation signal and address
Weak erasing operation is programmed, until judging the threshold value point of the cells of memory arrays when carrying out read operation to the storage array
Cloth meets preset value；
According to the operating condition after change, i.e. the second operation signal re-started the weak programming operation of erasing to storage array
Or cross and program weak erasing operation, until judging the threshold of the cells of memory arrays when carrying out read operation to the storage array
Distribution value meets preset value.
S106, the fingerprint for completing the storage array generate.
In conclusion operation signal and address by generating phy chip storage array, according to operation signal and address
Storage array was carried out the weak programming operation of erasing or crossed to program weak erasing operation, until carrying out read operation to storage array
When, the threshold value distribution of cells of memory arrays meets preset value, and the fingerprint for completing storage array generates.Weak programming behaviour is wiped by crossing
Make or cross to program weak erasing operation, more stable and more random key data can be generated, improve the reliable of phy chip
Property.
As shown in figure 5, carrying out the weak one of which for programming or crossing programming operation in fact to storage array to be disclosed by the invention
Existing mode, comprising the following steps:
S501, the element address for generating phy chip storage array to be programmed, programming value and programming duration；
Storage array is rearranged by many flash cells, carrys out tissue with sector, can be to therein in programming process
Certain sectors are programmed.Therefore, when multiple storage array is programmed, the list of phy chip storage array to be programmed is generated
First address, meanwhile, generate the time span of programming value (0 or 1) and programming.
S502, element address one programming source line voltage of generation according to the storage array to be programmed and a programming
Word line voltage；
S503, the source line and word of source line voltage and programmed word line voltage-drop loading to the storage array to be programmed will be programmed
Line；
S504, program current is generated according to the programming value；
S505, the storage array to be programmed is programmed in the programming duration by the program current.
As shown in fig. 6, real for the one of which disclosed by the invention for carrying out erasing or weak erasing operation to storage array
Existing mode, comprising the following steps:
S601, the element address for generating phy chip storage array to be erased and erasing duration；
S602, one erasing word line voltage of element address generation according to the storage array to be erased；
S603, the wordline that the erasing word line voltage is loaded into the storage array to be erased；
S604, according to the erasing duration, the storage array to be erased is wiped in the erasing duration.
As shown in fig. 7, for one of implementation disclosed by the invention for carrying out read operation to storage array, including
Following steps:
S701, the element address for generating phy chip storage array to be read and read operation signal；
S702, one reading word line voltage of element address generation according to the storage array to be read；
S703, the wordline that the reading word line voltage is loaded into the storage array to be read；
S704, the size of current that the storage array to be read is flowed through according to the read operation signal detection, and foundation
The size of current exports read operation result.
As shown in figure 8, for a kind of structural schematic diagram of phy chip fingerprint generation system disclosed by the embodiments of the present invention, packet
It includes:
Generation unit 801, for generating the first operation signal and the address of phy chip storage array；
When needing to generate the fingerprint of phy chip, the first operation signal and ground of phy chip storage array are firstly generated
Location, the address correspond to the element address of storage array to be processed.
Operating unit 802, it is weak for carrying out erasing to the storage array according to first operation signal and address
Programming operation programs weak erasing operation excessively, and the fingerprint for completing the storage array generates；
The weak programming operation of erasing was carried out to storage array according to the first operation signal of generation and address or was programmed excessively weak
Erasing operation.It is specifically described for crossing erasing-weak programming operation, erasing operation was being carried out to flash memory storage array
Afterwards, the threshold value of flash memory storage array can be made to be distributed and tend to be unified, be lower state.In weak programming, general storage unit
Channel in have a biggish electric current, electronics is accelerated in channels and has part to enter floating gate, changes the threshold value of unit.In threshold
After value is enhanced, the electric current in channel becomes smaller, and the electronics for being able to enter floating gate also accordingly tails off, that is, the efficiency programmed reduces,
And over time, efficiency is lower in the backward.The process of weak programming can be divided into several stages, to different unit point
Not Tiao Zheng wordline and bit line voltage, make flash memory cell all in array enter " phy chip fingerprint key storage
Unit " threshold interval.Shown in Fig. 3 is after carrying out erasing, and the threshold value of storage array is unified for Vth0, then to each unit
Weak programming is carried out, is distributed VthN by the random threshold value that statistics obtains entire storage array.Shown in Fig. 4 was the weak wiping of programming-
Except the threshold value distribution of storage array after operation.
Read operation unit 803 judges the cells of memory arrays for carrying out read operation to the storage array
Whether threshold value distribution meets preset value；
After carrying out the weak programming operation of erasing to storage array or programming weak erasing operation excessively, storage array is read
It operates, is judged after mistake wipes weak programming operation or programs weak erasing operation excessively out, the threshold value distribution of cells of memory arrays is
It is no to meet preset value.
Generation unit 801 is also used to generate when the threshold value distribution for judging the cells of memory arrays is unsatisfactory for preset value
Second operation signal of the phy chip storage array；
When the threshold value for judging cells of memory arrays, which is distributed, is unsatisfactory for preset value, changed again the weak programming operation of erasing or
It crosses and programs weak erasing operation condition, that is, generate the second operation signal.
The operating unit 802 is also used to carry out the storage array according to second operation signal and address
It wipes weak programming operation or crosses and program weak erasing operation, until being deposited described in judgement when carrying out read operation to the storage array
The threshold value distribution of storage array element meets preset value；
According to the operating condition after change, i.e. the second operation signal re-started the weak programming operation of erasing to storage array
Or cross and program weak erasing operation, until judging the threshold of the cells of memory arrays when carrying out read operation to the storage array
Distribution value meets preset value, and the fingerprint for completing storage array generates.
In conclusion operation signal and address by generating phy chip storage array, according to operation signal and address
Storage array was carried out the weak programming operation of erasing or crossed to program weak erasing operation, until carrying out read operation to storage array
When, the threshold value distribution of cells of memory arrays meets preset value, and the fingerprint for completing storage array generates.Weak programming behaviour is wiped by crossing
Make or cross to program weak erasing operation, more stable and more random key data can be generated, improve the reliable of phy chip
Property.
As shown in figure 9, for a kind of structural schematic diagram of phy chip fingerprint generation system disclosed by the invention, comprising:
Logic control circuit 901, for generating element address, the programming value of phy chip storage array to be programmed
With programming duration；
Adjustable high-tension circuit 902, for the control based on the logic control circuit, according to the storage battle array to be programmed
The element address of column generates a programming source line voltage and a programmed word line voltage；
Row decoding circuit 903, for selecting the programming source line voltage and programmed word line voltage, by programmed source
The source line and wordline of line voltage and programmed word line voltage-drop loading to the storage array to be programmed；
Program current generation circuit 904, for being generated by the logic control circuit according to the control of the programming value
Program current；
Array decoding circuit 905, for being connected with the program current generation circuit；
Logic control circuit 901 is also used to through the program current in the programming duration to described to be programmed
Storage array is programmed；
Logic control circuit 901 is also used to generate element address and the wiping of phy chip storage array to be erased
Except duration；
Adjustable high-tension circuit 902, is also used to the control based on the logic control circuit, according to the storage to be erased
The element address of array generates an erasing word line voltage；
Row decoding circuit 903 is also used to by selecting the erasing word line voltage being loaded into the storage to be erased
The wordline of array；
Logic control circuit 901 is also used to according to the erasing duration, to described to be erased in the erasing duration
Storage array is wiped；
Logic control circuit 901 is also used to generate element address and the reading of phy chip storage array to be read
Operation signal；
Adjustable high-tension circuit 902, is also used to the control based on the logic control circuit, according to the storage to be read
The element address of array generates a reading word line voltage；
Row decoding circuit 903 is also used to by selecting the reading word line voltage being loaded into the storage to be read
The wordline of array；
Array decoding circuit 905, for being connected with sense amplifier 906；
Sense amplifier 906, for flowing through the electricity of the storage array to be read according to the read operation signal detection
Size is flowed, and exports read operation result according to the size of current；
Voltage and current reference circuit 907, with the adjustable high-tension circuit, sense amplifier and program current generation circuit
It is connected, for providing the reference voltage value and current value unrelated with temperature change.
The working principle of above-described embodiment are as follows: voltage and current reference circuit can be provided to other circuits and temperature change
Unrelated accurate voltage and current value, other circuits then by the way that reference voltage and electric current are replicated or adjusted, have come
It is controlled at accurate voltage or current.
Storage array is rearranged by many flash cells, carrys out tissue with sector.In erase process, it can wipe a few
A sector, can also be with simultaneously erased all sectors.Operation address is exported ranks decoding circuit, storage array by control logic circuit
It is connected with ranks decoding circuit, selected cell or sector can be performed corresponding read-write and wipe operation.
General flash cell write-in voltage is higher than 5V, and erasing needs negative pressure.Circuit external supply voltage is often unsatisfactory for
The requirement of high pressure and often only single supply power supply.Since " phy chip fingerprint key storage unit " needed erasing-weak
Programming-weak erasing needs are crossed in programming, therefore contain adjustable voltage circuit in entire circuit, to complete different operation mould
Boosting and negative-pressure operation under formula, and the operating time can also be by the regulation of electrical circuit.
Specifically, as shown in Figure 10, for adjustable high-tension circuit by charge pump circuit 1001, voltage sampling circuit 1002 is adjustable
Comparison voltage circuit 1003, comparator 1004, clock generation circuit 1005, timing circuit 1006 and charge pump clock circuit 1007
Composition, is controlled by logic control circuit.When to carry out erasing or programming operation, logic control circuit sends control letter
Number, notice timing circuit can start to work；Timing circuit, which sends total clock circuit switching signal, generates clock generation circuit
Clock, this clock not only feed back to timing circuit and carry out timing, be also inputted in charge pump clock circuit, generate charge pump electricity
The clock that road needs；Charge pump circuit can be converted to supply voltage VDD high pressure, but its need of work provides charge pump clock；
Voltage sampling circuit samples the output high pressure of charge pump circuit, and usual sampled voltage and output high pressure are at certain ratio
Example, and the input voltage range of comparator need to be met；The adjustable potential circuit that compares is according to the control of logic control circuit, with base
Quasi- voltage is radix, adjusts the voltage of another input terminal of comparator；Comparator is compared sampled voltage with comparison voltage,
When sampled voltage is higher than comparison voltage, shutdown charge pump clock (but total clock is still working, and timing is not interrupted), charge pump electricity
After road stops working, input high tension voltage decline, when sampled voltage is lower than comparison voltage, charge pump clock is opened, charge pump
It works on, input high pressure rises, therefore can stablize near a voltage；When the clock periodicity of timing circuit statistics reaches
When number scheduled to logic control circuit, total clock cut-off signals are issued, one-time programming or erasing operation terminate.
The effect of sensitive amplifier circuit is the memory cell current size according to reading, exports corresponding logical value.It compiles
Electric current needed for journey circuit generation circuit generates programming according to reference current.
Logic control circuit can operation according to input and address, entire circuit is controlled: including address point
Row decoding and array decoding circuit are not given；Sense amplifier work is controlled in read operation；In programming or erasing, control can
The duration of volt circuit adjustment output voltage size and voltage is turned up.
Specifically, when being programmed operation, when inputting the value (0 or 1) and programming for the element address, programming to be programmed
Between length, logic control circuit controls adjustable high-tension circuit and generates a programming source line voltage and a programmed word line voltage, this
Two voltages are loaded on the source line (SL) and wordline (WL) of unit to be programmed respectively by the selection of line decoder.Column decoding
Device is connected unit to be programmed with program current generation circuit, and logic control circuit can be controlled according to the value (0 or 1) of programming
Program current generation circuit processed generates corresponding program current.Programming operation, programming time are completed after one section of programming time
It is controlled by control logic.
When carrying out erasing operation, inputs the sevtor address to be wiped or entire array and wipe corresponding signal, logic
Control circuit controls one erasing word line voltage of adjustable booster circuit generation and is loaded into be erased by the selection of line decoder
Sector location wordline (WL) on, erasing operation is completed after one section of erasing time, erasing operation is continued by input signal
Time determines.
When carrying out read operation, the element address to be read and the corresponding signal of read operation, logic control circuit control are inputted
Adjustable high-tension circuit generates a reading word line voltage and is loaded into cell word lines to be read by the selection of line decoder
(WL) on.Column decoder is connected unit to be read with sense amplifier, and sense amplifier flows through reading unit according to detection
Size of current output read operation result.
If function described in the present embodiment method is realized in the form of SFU software functional unit and as independent product pin
It sells or in use, can store in a storage medium readable by a compute device.Based on this understanding, the embodiment of the present invention
The part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products, this is soft
Part product is stored in a storage medium, including some instructions are used so that calculating equipment (it can be personal computer,
Server, mobile computing device or network equipment etc.) execute all or part of step of each embodiment the method for the present invention
Suddenly.And storage medium above-mentioned includes: USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), deposits at random
The various media that can store program code such as access to memory (RAM, Random Access Memory), magnetic or disk.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with it is other
The difference of embodiment, same or similar part may refer to each other between each embodiment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of phy chip fingerprint generation method characterized by comprising
Generate the first operation signal and the address of phy chip storage array；
The storage array was carried out the weak programming operation of erasing or crossed to program weak wiping according to first operation signal and address
Except operation；
Read operation is carried out to the storage array, it is default to judge whether the voltage threshold distribution of the cells of memory arrays meets
Value, if so, the fingerprint for completing the storage array generates；If it is not, then:
Generate the second operation signal of the phy chip storage array；
The storage array was carried out the weak programming operation of erasing or crossed to program weak wiping according to second operation signal and address
Except operation, until judging that the voltage threshold distribution of the cells of memory arrays is full when carrying out read operation to the storage array
Sufficient preset value.
2. the method according to claim 1, wherein it is described according to first operation signal and address to described
Storage array carries out weak programming or crosses programming operation
Generate element address, programming value and the programming duration of phy chip storage array to be programmed；
Element address according to the storage array to be programmed generates a programming source line voltage and a programmed word line voltage；
By the source line and wordline of programmed source line voltage and programmed word line voltage-drop loading to the storage array to be programmed；
Program current is generated according to the programming value；
The storage array to be programmed is programmed in the programming duration by the program current.
3. according to the method described in claim 2, it is characterized in that, it is described according to first operation signal and address to described
Storage array carried out erasing or weak erasing operation includes:
Generate element address and the erasing duration of phy chip storage array to be erased；
Element address according to the storage array to be erased generates an erasing word line voltage；
The erasing word line voltage is loaded into the wordline of the storage array to be erased；
According to the erasing duration, the storage array to be erased is wiped in the erasing duration.
4. according to the method described in claim 3, it is characterized in that, described include: to storage array progress read operation
Generate element address and the read operation signal of phy chip storage array to be read；
Element address according to the storage array to be read generates a reading word line voltage；
The reading word line voltage is loaded into the wordline of the storage array to be read；
The size of current of the storage array to be read is flowed through according to the read operation signal detection, and big according to the electric current
Small output read operation result.
5. a kind of phy chip fingerprint generates system characterized by comprising
Generation unit, for generating the first operation signal and the address of phy chip storage array；
Operating unit, for carrying out the weak programming operation of erasing to the storage array according to first operation signal and address
Or it crosses and programs weak erasing operation；
Read operation unit judges the voltage threshold of the cells of memory arrays for carrying out read operation to the storage array
Whether Distribution value meets preset value, when the voltage threshold for judging the cells of memory arrays, which is distributed, meets preset value, completes institute
The fingerprint for stating storage array generates；
When the voltage threshold for judging the cells of memory arrays, which is distributed, is unsatisfactory for preset value, the generation unit is also used to generate
Second operation signal of the phy chip storage array；
The operating unit is also used to carry out the weak volume of erasing to the storage array according to second operation signal and address
Journey, which is operated or crossed, programs weak erasing operation, until sentencing when the read operation unit carries out read operation to the storage array
The voltage threshold distribution for the cells of memory arrays of breaking meets preset value.
6. system according to claim 5, which is characterized in that the operating unit includes:
Logic control circuit, for generating element address, programming value and the programming of phy chip storage array to be programmed
Duration；
Adjustable high-tension circuit, the list for the control based on the logic control circuit, according to the storage array to be programmed
First address generates a programming source line voltage and a programmed word line voltage；
Row decoding circuit, for selecting the programming source line voltage and programmed word line voltage, by programmed source line voltage
With the source line and wordline of programmed word line voltage-drop loading to the storage array to be programmed；
Program current generation circuit, for generating programming electricity according to the control of the programming value by the logic control circuit
Stream；
Array decoding circuit, for being connected with the program current generation circuit；
The logic control circuit is also used to through the program current in the programming duration to the storage to be programmed
Array is programmed.
7. system according to claim 6, which is characterized in that the operating unit includes:
The logic control circuit, when being also used to generate element address and the erasing of phy chip storage array to be erased
It is long；
The adjustable high-tension circuit, is also used to the control based on the logic control circuit, according to the storage battle array to be erased
The element address of column generates an erasing word line voltage；
The row decoding circuit is also used to by selecting the erasing word line voltage being loaded into the storage array to be erased
Wordline；
The logic control circuit is also used to deposit described to be erased in the erasing duration according to the erasing duration
Storage array is wiped.
8. system according to claim 7, which is characterized in that the read operation unit includes:
The logic control circuit is also used to generate element address and the read operation of phy chip storage array to be read
Signal；
The adjustable high-tension circuit, is also used to the control based on the logic control circuit, according to the storage battle array to be read
The element address of column generates a reading word line voltage；
The row decoding circuit is also used to by selecting the reading word line voltage being loaded into the storage array to be read
Wordline；
Array decoding circuit, for being connected with sense amplifier；
The sense amplifier, the electric current for flowing through the storage array to be read according to the read operation signal detection are big
It is small, and read operation result is exported according to the size of current.
9. system according to claim 8, which is characterized in that further include:
Voltage and current reference circuit is connected with the adjustable high-tension circuit, sense amplifier and program current generation circuit, uses
In the offer reference voltage value and current value unrelated with temperature change.
10. system according to claim 9, which is characterized in that the adjustable high-tension circuit includes: charge pump circuit, electricity
Press sample circuit, adjustable relatively potential circuit, comparator, clock generation circuit, timing circuit and charge pump clock circuit；Its
In:
The timing circuit is connected with the logic control circuit and clock generation circuit respectively；
The charge pump clock circuit is connected with clock generation circuit, charge pump circuit and comparator respectively；
The adjustable relatively potential circuit is connected with the logic control circuit and comparator respectively；
The voltage sampling circuit is connected with the charge pump circuit and comparator.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1063372A (en) * | 1992-01-08 | 1992-08-05 | 程宗有 | Optic erasable read only memory encrypted chip and encryption method thereof |
| TW200426845A (en) * | 2003-05-16 | 2004-12-01 | Winbond Electronics Corp | The weak programming method of a non-volatile memory |
| CN101213614A (en) * | 2005-03-31 | 2008-07-02 | 桑迪士克股份有限公司 | Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells |
| CN100479064C (en) * | 2004-09-30 | 2009-04-15 | 株式会社东芝 | Nonvolatile semiconductor memory device and data erasing method thereof |
| CN102428520A (en) * | 2009-04-09 | 2012-04-25 | 桑迪士克技术有限公司 | Two pass erase for non-volatile storage |
| CN103778374A (en) * | 2014-02-19 | 2014-05-07 | 邹候文 | Trusted terminal, double-channel card, anti-cloning chip, chip fingerprint and channel attack resistance method |
| US9098694B1 (en) * | 2011-07-06 | 2015-08-04 | Marvell International Ltd. | Clone-resistant logic |
-
2016
- 2016-08-18 CN CN201610695830.XA patent/CN106326780B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1063372A (en) * | 1992-01-08 | 1992-08-05 | 程宗有 | Optic erasable read only memory encrypted chip and encryption method thereof |
| TW200426845A (en) * | 2003-05-16 | 2004-12-01 | Winbond Electronics Corp | The weak programming method of a non-volatile memory |
| CN100479064C (en) * | 2004-09-30 | 2009-04-15 | 株式会社东芝 | Nonvolatile semiconductor memory device and data erasing method thereof |
| CN101213614A (en) * | 2005-03-31 | 2008-07-02 | 桑迪士克股份有限公司 | Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells |
| CN102428520A (en) * | 2009-04-09 | 2012-04-25 | 桑迪士克技术有限公司 | Two pass erase for non-volatile storage |
| US9098694B1 (en) * | 2011-07-06 | 2015-08-04 | Marvell International Ltd. | Clone-resistant logic |
| CN103778374A (en) * | 2014-02-19 | 2014-05-07 | 邹候文 | Trusted terminal, double-channel card, anti-cloning chip, chip fingerprint and channel attack resistance method |
Non-Patent Citations (2)
| Title |
|---|
| 基于智能卡芯片指纹的身份认证方案设计;高雪峰，等;《微型电脑应用》;20080901;第24卷(第6期);第20-22页 |
| 芯片指纹提取技术的安全应用;李辉，等;《2010通信理论与技术新发展--第十五届全国青年通信学术会议论文集（上册）》;20101231;第54-58页 |
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