TWI285942B - Capacitor with nano-composite dielectric structure and method for fabricating the same - Google Patents

Capacitor with nano-composite dielectric structure and method for fabricating the same Download PDF

Info

Publication number
TWI285942B
TWI285942B TW094146965A TW94146965A TWI285942B TW I285942 B TWI285942 B TW I285942B TW 094146965 A TW094146965 A TW 094146965A TW 94146965 A TW94146965 A TW 94146965A TW I285942 B TWI285942 B TW I285942B
Authority
TW
Taiwan
Prior art keywords
layer
dielectric
nanocomposite
dielectric layer
source
Prior art date
Application number
TW094146965A
Other languages
Chinese (zh)
Other versions
TW200638514A (en
Inventor
Deok-Sin Kil
Kwon Hong
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200638514A publication Critical patent/TW200638514A/en
Application granted granted Critical
Publication of TWI285942B publication Critical patent/TWI285942B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • AHUMAN NECESSITIES
    • A47FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47GHOUSEHOLD OR TABLE EQUIPMENT
    • A47G9/00Bed-covers; Counterpanes; Travelling rugs; Sleeping rugs; Sleeping bags; Pillows
    • A47G9/10Pillows
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • C23C16/405Oxides of refractory metals or yttrium
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • C23C16/45527Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • C23C16/45531Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations specially adapted for making ternary or higher compositions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02192Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02194Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Metallurgy (AREA)
  • Nanotechnology (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • Otolaryngology (AREA)
  • Pulmonology (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Inorganic Insulating Materials (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

A capacitor with a nano-composite dielectric structure and a method for fabricating the same are provided. The capacitor includes: a lower electrode; a nano-composite dielectric structure; and an upper electrode. The nano-composite dielectric structure is obtained by mixing an HfO2 layer and a dielectric layer having a dielectric constant equal to or greater than that of the HfO2 layer in the form of a nano-composition. The dielectric layer includes a material selected from a group consisting of ZrO2, La2O3 and Ta2O5, each having a dielectric constant in a range of approximately 25 to approximately 30 and a band gap energy level ranging from approximately 4.3 to approximately 7.8.

Description

1285942 、 , ( 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種半導體裝置及一種製造該半導體裝置 之方法,更特別地,關於一種具有奈米複合材料介電結構 之電容器及一種製造該電容器之方法。 【先前技術】 因爲藉由在半導體技術中之微小化製造方法 (m i c r ο n i z a t i ο η)而加速記憶體產品的大型整合,所以已快速 > 地縮小單位單元之大小及可達成低操作電壓。然而,即使 已減少單元之大小,但是用以操作一記憶體裝置所需之電 容應該大於25 pF/每一單元,以防止軟錯誤(soft error)事件 及縮短更新時間。因此,即使已實施一具有大的表面積之 半球型電極表面的三維儲存節點,但是已使一使用氮化矽 層(ShN4)之用於一動態隨機存取記憶體(DRAM)的NO電容 器之高度亦持續地增加。該氮化矽層通常係使用二氯矽甲 院(dicholorosilane,DCS)來形成。 | 因爲確保獲得一具有25 6M以上之DRAM所需之充分位 準的電容之NO電容器的限制,所以使用高介電常數K之 介電材料或三維儲存節點(例如:圓柱或凹型儲存節點)以克 服該電容限制。高介電常數 K材料之範例爲氧化鉬 (Ta2〇5)、氧化錦(AhCh)及氧化給(Hf〇2)。 然而,Ta2Ch具有一不良漏電流特性。雖然介電常數値爲 9之Al2〇3具有一良好漏電流特性,仍然因低介電常數値而 限制所期望位準之電容的獲得。Hf〇2因具有高介電常數而 能獲得該電容;然而,Hf〇2具有低強度之潰崩電壓。因此’ 1285942 久 * j *BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a capacitor having a nanocomposite dielectric structure and a A method of manufacturing the capacitor. [Prior Art] Since the large-scale integration of a memory product is accelerated by a miniaturization manufacturing method (micr ο nizati ο η) in semiconductor technology, the size of a unit cell has been rapidly reduced and A low operating voltage can be achieved. However, even if the cell size has been reduced, the capacitance required to operate a memory device should be greater than 25 pF per cell to prevent soft error events and reduce update time. Therefore, even if a three-dimensional storage node having a large surface area of the hemispherical electrode surface has been implemented, the height of the NO capacitor for a dynamic random access memory (DRAM) using a tantalum nitride layer (ShN4) has been made. It is also continuously increasing. The tantalum nitride layer is usually made of dicholorosilane (DCS). Forming. | Using a dielectric material with a high dielectric constant K or a three-dimensional storage node (eg, a cylindrical or concave storage node) because it ensures the limitation of a NO capacitor with a sufficient level of capacitance required for a DRAM of 25 6M or more. To overcome this capacitance limitation, examples of high dielectric constant K materials are molybdenum oxide (Ta2〇5), bismuth oxide (AhCh), and oxidation (Hf〇2). However, Ta2Ch has a poor leakage current characteristic. Al2〇3 with an electric constant 値 of 9 has a good leakage current characteristic, and still obtains a capacitance of a desired level due to a low dielectric constant 。. Hf〇2 can obtain the capacitance because of having a high dielectric constant; , Hf〇2 has a low-intensity collapse voltage. Therefore ' 1285942 long * j *

Hf〇2易於電震,因而減少該電容器之耐久性。 因此,已提供一包括Hf〇2及Al2〇3之堆疊結構(亦即’雙 介電結構)。 第1圖係顯示一具有一 Hf〇2/Al2〇3之傳統介電結構的電 容器之剖面圖。 一介電結構1 2形成於一下電極1 1與一上電極1 3之間且 具有一雙介電結構,其中該雙介電結構係藉由堆疊一 Al2〇3 層12A及一 HfCb層12B所獲得。 | 因爲Al2〇3具有低介電常數,所以Ah〇3係以奈米複合之 形式製造於次-8 0 n m裝置中以減少漏電流。因爲即使當薄 薄地形成Al2〇3時,Al2〇3亦可獲得預定位準之漏電流,所 以可在高達80nm裝置中完成良好電性特性及大量生量。然 而,因爲在一 DRAM中之一凹型電容器需要一已具有較大 程度之減小的有效氧化物厚度,所以通常很難將Al2〇3應 用至該凹型電容器。 因此,目前已使用一介電結構(包括:以一預定比率混合 ,之Hf〇2與Al2〇3的複合)(亦即,以Hf〇2_Al2〇3之奈米複合 所形成的介電結構)做爲一以凹型結構所形成之電容器的 介電層。以下’將此介電結構稱爲"HfAlO奈米複合材料介 電層"。儘管有此優點,該HfAlO奈米複合材料介電層具有 13至15範圍之低介電常數。 第2圖係顯示包括AhCh、Hf〇2及奈米複合材料HfA1〇 之傳統介電材料的介電常數値之曲線圖。 如所示,Hf〇2及Al2〇3分別具有25及9之介電常數。另 一方面,一 HfAlO奈米複合材料介電層其中Hf〇2及幻⑴3 1285942 ( « 係以奈米複合物形態混合著,具有從n至1 5範圍之介電 常數’其中H fO2及Al2〇3係以奈米複合之方式來混合。特 別地,在該HfA10奈米複合材料介電層中之Hf對Αι的混 合比大約爲1 : 1。 因爲該H fA 10奈米複合材料介電層具有比町〇2低之介電 常數’所以該HfA10奈米複合材料介電層之Hf〇2可以具有 減少之介電常數値。結果’很難確保在次_ 8 〇 n m裝置中可 獲得具有預定高介電常數之H fA 10奈米複合材料介電層。 • 因爲該H fA 10奈米複合材料介電層包括介電常數有大約 爲9之Ah〇3,所以該HfAlO奈米複合材料介電層具有比該 Hf〇2介電層更低之介電常數。因而,通常需要使用一種可 應用至所有形態(包括凹型)之電容器的介電層且可獲得良 好漏電流特性及幾乎相同於HfCh之介電常數的高介電常 數値。 【發明內容】 因此,本發明之一目的在於提供一種具有一奈米複合材 φ 料介電結構之電容器及一種用以製造該電容器之方法,其 中該奈米複合材料介電結構具有良好漏電流特性,可應用 至不同型態之電容器及可獲得高介電常數値。 依據本發明之一觀點,係提供一種電容器之介電結構, • 該介電結構包括:一氧化給(Hf〇2)層,以及一以具有幾乎相 . 同於該Hf〇2層之介電常數的材料爲主之介電層,其中該介 電結構包括一奈米複合材料介電結構,該奈米複合材料介 電結構係藉由以奈米複合之形式,混合該Hf〇2層與該介電 層而獲得。 1285942 < , 依據本發明之另一觀點,係提供一種用以製造一電 之介電結構的方法,該方法包括:形成一奈米複合材 層電,係藉由依據一原子層沉積(ALD)方法,經由重複 施分別爲Y次及Y次之氧化給(Hf〇2)沉積週期與介電 積週期,以奈米複合之方式,混合一氧化給(Hf〇2)層 介電層而成;以及實施退火處理,以緻密化該奈米 材料介電結構。 依據本發明之又另一觀點,係提供一種電容器,該 • 器包括:一下電極;一奈米複合材料介電結構,其形成 下電極上且包括一氧化給(HfCh)層及一具有幾乎相同 HfCh層之介電常數的介電層,其中該Hf〇2層及該介電 以奈米複合之形式來混合;以及一上電極,形成於該奈 合材料介電結構上。 依據本發明之另外觀點,係提供一種製造一電容器 法’該方法包括:形成一下電極;形成一奈米複合材料 結構’係在該下電極上,實施一原子層沉積(ALD)方 φ 得’其中該奈米複合材料介電結構係藉由,以奈米複 形式’混合一氧化給(Hf〇2)層及一具有幾乎相同於該 之介電常數的介電層所獲得;實施退火處理,以緻密 該奈米複合材料介電結構;以及形成一上電極於該已 - 奈米複合材料介電結構上。 . 從下面較佳實施例之描述並配合所附圖式將更加了 發明之上述及其它目的及特徵。 【實施方式】 將配合所附圖式,以詳細說明依據本發明之示範性 容器 料介 地實 層沉 與一 複合 電容 於該 於該 層係 米複 之方 介電 法而 合之 Hf〇2 化對 退火 解本 實施 1285942 *· 、 ^ 例的一具有一奈米複合材料介電結構之電容器及一用以製 造該電容器之方法。 本發明之示範性實施例提示一介電結構,其具有和Al2〇3 _永好之漏電流特性’可確保約大於2 〇的高介電常數(接 近H f〇2之介電吊數)及可應用至各種型態之電容器。這些 優點允g午將該介電層應用至具有約小於7〇ηιη之尺寸的高 度整合型半導體裝置。 桌3圖係描述依據本發明之一特定實施例的一奈米複合 • 材料介電結構之示意圖。依據本發明之特定實施例,該奈 米複合材料介電結構不是一具有第一介電層及一第二介電 層之簡單堆疊結構,而是一種以奈米複合之形式,混合該 第一介電層及該第二介電層之結構。 如所示,該奈米複合材料介電結構包括一具有第一原子 之第一介電層Ml〇,及一具有第二原子M2之第二介電層 m2〇,其中該第一介電層Μι0及該第二介電層m2〇係以奈 米複合之形式混合。該奈米複合材料介電結構不是只有該 鲁 第一介電層ΜιΟ及該第二介電層m2〇之組合特性,而是具 有一 mw2◦奈米複合介電材料之特性,其中該ΜιΜ2〇奈米 複合介電材料,係一包括第一原子Ml及第二原子M2之以 氧化物爲主的材料。 M1M2O奈米複合介電結構之第一原子^及第二原子 • M2’係選自可提供大於HfAlO奈米複合材料介電層之常數 的原子中選擇出來。亦即,該MlM2〇奈米複合介電層之介 電常數至少約大於20。例如:該第一原子Μι包括Hf,及該 第二原子M2包括一選自銷(Zr)、鑭(La)及鉅(Ta)所組成之群 1285942 f' * 的材料。因而,該MiM2〇奈米複合材料介電層可以是 HfZr〇、HfLaO或iifTaO之一層,以及這些奈米複合材料介 電層具有大於該HfAlO奈米複合材料介電層之約13-15範 圍的介電常數。 下面表1顯示依介電材料型態而定之介電常數、帶隙能 量値及傳導帶補償(CB〇)値。 表1 介電材料 介電常數 帶隙能量(Eg,eV) 對Si之CB〇(eV) SiCb 3.9 8.9 3.5 S13N4 7 5.1 2.4 AI2O3 9 8.7 2.8 Y2O3 15 5.6 2.3 Zr〇2 25 7.8 1.4 Hf〇2 25 5.7 1.5 Ta2〇5 26 4.5 0.3 La2〇3 30 4.3 2.3 T1O2 80 3.5 0.0Hf〇2 is susceptible to electrical shock, thus reducing the durability of the capacitor. Therefore, a stacked structure including Hf 〇 2 and Al 2 〇 3 (i.e., 'dual dielectric structure') has been provided. Fig. 1 is a cross-sectional view showing a capacitor having a conventional dielectric structure of Hf 〇 2 / Al 2 〇 3. A dielectric structure 12 is formed between the lower electrode 1 1 and an upper electrode 13 and has a double dielectric structure, wherein the double dielectric structure is formed by stacking an Al 2 〇 3 layer 12A and an Hf Cb layer 12 B obtain. Since Al2〇3 has a low dielectric constant, Ah3 is fabricated in a nano-8 0 m device in the form of a nanocomposite to reduce leakage current. Since Al2〇3 can obtain a predetermined level of leakage current even when Al2〇3 is formed thinly, good electrical characteristics and a large amount of production can be achieved in a device of up to 80 nm. However, since a concave capacitor in a DRAM requires an effective oxide thickness which has been reduced to a large extent, it is generally difficult to apply Al2?3 to the concave capacitor. Therefore, a dielectric structure (including: a mixture of Hf〇2 and Al2〇3 mixed at a predetermined ratio) (that is, a dielectric structure formed by nanocomposite of Hf〇2_Al2〇3) has been used. As a dielectric layer of a capacitor formed by a concave structure. The following dielectric structure is referred to as "HfAlO nanocomposite dielectric layer". Despite this advantage, the HfAlO nanocomposite dielectric layer has a low dielectric constant in the range of 13 to 15. Fig. 2 is a graph showing the dielectric constant 値 of a conventional dielectric material including AhCh, Hf〇2, and nano composite material HfA1〇. As shown, Hf〇2 and Al2〇3 have dielectric constants of 25 and 9, respectively. On the other hand, a HfAlO nanocomposite dielectric layer in which Hf〇2 and illusion (1)3 1285942 (“ is mixed in a nanocomposite form with a dielectric constant ranging from n to 15′′ where H fO2 and Al2 The 〇3 series is mixed in a nanocomposite manner. In particular, the mixing ratio of Hf to Αι in the dielectric layer of the HfA10 nanocomposite is about 1:1. Because the HfA 10 nanocomposite dielectric is dielectric The layer has a lower dielectric constant than the 〇2, so the Hf 〇 2 of the HfA10 nanocomposite dielectric layer can have a reduced dielectric constant 値. The result 'it is difficult to ensure that it is available in the next _ 8 〇 nm device H FA 10 nanocomposite dielectric layer having a predetermined high dielectric constant. • Since the H fA 10 nanocomposite dielectric layer includes Ah 〇 3 having a dielectric constant of about 9, the HfAlO nanocomposite The material dielectric layer has a lower dielectric constant than the Hf 〇 2 dielectric layer. Therefore, it is generally required to use a dielectric layer that can be applied to all forms (including concave) capacitors and obtain good leakage current characteristics and almost A high dielectric constant 相同 similar to the dielectric constant of HfCh. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a capacitor having a dielectric structure of a nanocomposite material and a method for fabricating the capacitor, wherein the nanocomposite dielectric structure has good leakage current The characteristics can be applied to different types of capacitors and obtain a high dielectric constant 値. According to one aspect of the present invention, a dielectric structure of a capacitor is provided, and the dielectric structure includes: a oxidized (Hf 〇 2) a layer, and a dielectric layer mainly composed of a material having a dielectric constant substantially identical to the Hf〇2 layer, wherein the dielectric structure comprises a nano composite dielectric structure, the nano composite material The electrical structure is obtained by mixing the Hf〇2 layer with the dielectric layer in the form of a nanocomposite. 1285942 < According to another aspect of the present invention, a dielectric structure for manufacturing an electricity is provided. The method comprises the steps of: forming a layer of nano-composite layer by means of an atomic layer deposition (ALD) method, by repeatedly applying a Y-time and Y-order oxidation (Hf〇2) deposition period and Dielectric a product cycle in which a dielectric layer of (Hf〇2) layer is mixed by oxidation, and an annealing treatment is performed to densify the dielectric structure of the nano material. According to another aspect of the present invention, Providing a capacitor comprising: a lower electrode; a nanocomposite dielectric structure formed on the lower electrode and comprising an oxidized (HfCh) layer and a dielectric constant having substantially the same HfCh layer An electrical layer, wherein the Hf〇2 layer and the dielectric are mixed in a nanocomposite form; and an upper electrode formed on the dielectric material dielectric structure. According to another aspect of the present invention, a manufacturing Capacitor method 'This method includes: forming a lower electrode; forming a nanocomposite structure 'on the lower electrode, performing an atomic layer deposition (ALD) square φ to obtain 'the nanocomposite dielectric structure by And obtained in a nanocomposite form of a mixed-oxidation (Hf〇2) layer and a dielectric layer having substantially the same dielectric constant; an annealing treatment is performed to densely bond the nano composite dielectric structure And forming an upper electrode on the already - the nano composite dielectric structure. The above and other objects and features of the present invention will become more apparent from the description of the preferred embodiments illustrated herein. [Embodiment] The exemplary container material according to the present invention will be described in detail with reference to the Hf〇2 of the exemplary container material layer and a composite capacitor in the layered dielectric method. A pair of capacitors having a dielectric structure of a nanocomposite and a method for fabricating the same are disclosed. An exemplary embodiment of the present invention suggests a dielectric structure having a high dielectric constant (approximately a dielectric hang of Hf 〇 2) with an Al2 〇 3 _ permanent leakage current characteristic 'to ensure greater than about 2 ) And can be applied to various types of capacitors. These advantages allow the dielectric layer to be applied to a highly integrated semiconductor device having a size of less than about 7 nm. Table 3 is a schematic illustration of a nanocomposite material dielectric structure in accordance with a particular embodiment of the present invention. According to a particular embodiment of the invention, the nanocomposite dielectric structure is not a simple stacked structure having a first dielectric layer and a second dielectric layer, but a hybrid in the form of a nanocomposite. The structure of the dielectric layer and the second dielectric layer. As shown, the nanocomposite dielectric structure includes a first dielectric layer M1〇 having a first atom, and a second dielectric layer m2〇 having a second atom M2, wherein the first dielectric layer Μι0 and the second dielectric layer m2 are mixed in the form of a nanocomposite. The nano composite dielectric structure is not only a combination of the first dielectric layer ΜιΟ and the second dielectric layer m2〇, but has the characteristics of a mw2 nanocomposite dielectric material, wherein the ΜιΜ2〇 The nano composite dielectric material is an oxide-based material including a first atom M1 and a second atom M2. The first atom and the second atom of the M1M2O nanocomposite dielectric structure are selected from atoms which provide a constant greater than the dielectric layer of the HfAlO nanocomposite. That is, the MlM2 nanocomposite dielectric layer has a dielectric constant of at least about 20. For example, the first atom Μι includes Hf, and the second atom M2 includes a material selected from the group consisting of pins (Zr), lanthanum (La), and giant (Ta) 1285942 f'*. Thus, the MiM2 nanocomposite dielectric layer can be a layer of HfZr(R), HfLaO or iifTaO, and the nanocomposite dielectric layers have a size greater than about 13-15 of the HfAlO nanocomposite dielectric layer. Dielectric constant. Table 1 below shows the dielectric constant, bandgap energy 値, and conduction band compensation (CB〇)値 depending on the type of dielectric material. Table 1 Dielectric Properties of Dielectric Materials Band Gap Energy (Eg, eV) CB〇(eV) for Si SiCb 3.9 8.9 3.5 S13N4 7 5.1 2.4 AI2O3 9 8.7 2.8 Y2O3 15 5.6 2.3 Zr〇2 25 7.8 1.4 Hf〇2 25 5.7 1.5 Ta2〇5 26 4.5 0.3 La2〇3 30 4.3 2.3 T1O2 80 3.5 0.0

在表1中,’對Si之CBCT係一表示擷取電子困難度之指 標。該CBO値越低,該漏電流特性越好。同樣地,當該帶 隙能量較高時,該漏電流特性會較好。如果該介電層在室 溫時具有一非晶質結構,則在傳導路徑方面係有利的’藉 以導致漏電流位準之減少。然而,該介電層應該具有一結 晶結構,以便具有高介電常數。亦即,該介電常數及該非 晶質狀態具有一取捨關係(trade-off relationship)。 如表1所示,因爲S i 0 2、S i 3 N 4、A12〇3及Y 2〇3具有約小 於20之介電常數,所以這些介電材料很難獲得一高度整合 -10- 1285942 { * t 1 半導體裝置之一電容器所需位準之電容。因爲Zr〇2、Hf〇2、 Ta2〇5、La2Ch及Ti〇2具有約大於20之介電常數,所以這些 介電常數允許獲得所需之電容。然而,當單獨或組合使用 後者所提之介電材料時,會限制介電特性之喪失、漏電流 特性之降低及可應用電容器結構。 因此,在本發明之示範性實施例中提議使用一非晶質奈 米複合材料介電層,其可獲得高度整合半導體裝置之電容 器所需的高位準電容及可應用至各種電容器結構而不會喪 φ 失介電特性及漏電流特性。 根據表1,該奈米複合材料介電層可以是HfZrO、HfLaO 及HfTaO奈米複合材料介電層中之一。這些奈米複合材料 介電層具有高於一 HfAlO奈米複合材料介電層之介電常 數。上述HfZrO、HfLaO及HfTaO之奈米複合材料介電層 共同包括Hf以及藉由以奈米複合之形式將Zr〇2、La2〇3及 Ta2〇5與HfCh混合所獲得。Hf〇2、Zr〇2、La2Ch及Ta2〇5之 介電常數大約分別爲25、25、30及26。因此,上述奈米複 φ 合材料介電層具有至少大約高於20之介電常數而沒有減 少Hf〇2之介電常數。相較下,一 HfAlO奈米複合材料介電 層係以奈米複合之形式藉由將具有約20之介電常數的 H f〇2與具有約9之介電常數的a h 0 3混合所獲得。因此, - 該HfAlO奈米複合材料介電層具有低於Hf〇2之介電常數, ^ 藉以促使Hf〇2之介電常數的減少。 如表1所示’將具有約80之高介電常數的Ti〇2與Hf〇2 混合以形成一奈米複合材料介電層。然而,Ti〇2具有低於 其它介電材料之帶隙能量(Eg)。因此,使用Ti〇2以形成一 -11- 1285942 κ * I k 奈米複合材料介電層,幾乎不可能獲得次_70nm裝置通常 所需之約小於1 〇 A的有效氧化物厚度,以及此限制導致電 容器之電氣特性的降低。 包括第一原子M!之第一介電層及包括第二原子M2 之第一介電層M2〇係經由使用一原子層沉積(ald)方法所 形成,以便該Μ 1 Μ 2 0奈米複合材料介電層不是以一堆疊結 構而是以一混合該第一介電層Μ^Ο及該第二介電層μ2〇之 結構來形成。 | 以下’將描述依據本發明之示範性實施例的用以沉積示 範性奈米複合材料介電層(例如:HfZrO、HfLaO及HfTaO奈 米複合材料介電層)之方法以及這些奈米複合材料介電層 的結構。 第4圖係描述一用以依據本發明之第一實施例以相關氣 體之連續供應沉積一 HfZrO奈米複合材料介電層的ALD方 法之曲線圖。 依據該ALD方法,將一來源氣體供應至一反應室中以促 | 使在一基板表面上以化學方式吸收一單層之氣體來源分 子。將該等物理吸吸來源分子清除至該反應室之外面。然 後,將一反應氣體供應至上述單層之來源分子。因爲在該 反應氣體與該等來源分子間發生化學反應,所以沉積一預 定原子層。將該未反應之反應氣體清除至該反應室之外 面。這些連續操作構成該ALD方法之一單位週期。 該ALD方法利用一表面反應機制,其允許形成一穩定且 均勻之薄層。因爲以連續次序分別供應及清除該來源氣體 及該反應氣體’所以該ALD方法可比一化學氣相沉積(CVD) :S〕 -12- 1285942 … · , 1 方法更有效地防止一氣相反應所造成之粒子的產生。 用以沉積該HfZrO奈米複合材料介電層之ALD方法的上 述單位週期如下:[(Hf源/清除/氧化劑暴露/清除)y(Zr源/清 除/氧化劑暴露/清除)z ]n。以下,將此單位週期稱爲第一單 位週期。 該Hf源係一用以供應該Hf源以便產生Hf〇2之脈衝’以 及該Zr源係一用以供應該h源以便產生Ζι*〇2之脈衝。下 標符號'ζ'及Υ分別表示(Hf源/清除/氧化劑暴露/清除) | 週期之次數、(Zr源/清除/氧化劑暴露/清除)週期之次數及 決定該HfZrO介電層之厚度的週期之次數。 在該第一單位週期之更詳細細節中,將(Hf源/清除/氧化 劑暴露/清除)週期稱爲一 Hf〇2沉積週期,其包括··供應該 Hf源;清除該物理吸收Hf源;暴露該Hf源至一氧化劑;及清 除該未反應Hf源及氧化劑,以及使該Hf〇2沉積週期重複y 次。將(Z r源/清除/氧化劑暴露/清除)週期稱爲一 Z r 0 2沉積 週期,其包括:供應該Zr源;清除該未反應Zr源;暴露該Zr | 源至一氧化劑;及清除該未反應Z r源及氧化劑。使該Z r〇2 沉積週期重複z次。藉由使該Hf〇2沉積週期及該Zr〇2沉積 週期分別重複y及z次,以沉積具有預定厚度之一 Hf〇2層 及一 ZrCh層。使一包含該HfCh沉積週期及該Zr〇2沉積週 期之組合沉積週期重複η次以決定該HfZrO奈米複合材料 介電層之整個厚度。 有關於第4圖,以下將描述一個依據本發明之第一實施 例的HfZrO奈米複合材料介電層之範例。 應該注意到將(Hf/N2/〇3/N2)之單位週期稱爲一 HfCh沉積 1285942 / ' . * 週期及重複y次。在此,Hf、N2、及〇3分別爲一 Hf源、 一清除氣體及一氧化氣體。亦應該注意到將(Zr/N2/〇3/N2) 之單位週期稱爲一' Zr〇2iii積週期及重複z次。在此,Zr、 N2、及〇3分別爲一 Zr源、一清除氣體及一氧化氣體。在 維持約0· 1托耳至約10托耳之壓力及約100。^至約450°C 之基板溫度的反應室中實施該Hf〇2沉積週期及該Zr〇2沉 積週期。 至於該Hf〇2沉積週期,使選自由HfCl4、Hf(N〇3)4、 φ Hf(NCH2C2H5)4及Hf(OC2H〇4所組之群的Hf源在一蒸發器 中蒸發。然後,將該Hf源供應至該維持在上述條件下的反 應室中約0.1秒至約3秒,以便在該基板上吸收該Hf源。 將該N 2氣體供應至該反應室中約〇. 1秒至約5秒以清除該 未反應Hf源至該反應室之外面。將該〇3氣體供應至該反 應室中約0.1秒至約3秒,以便在該吸收Hf源與該〇3氣體 間引起反應,藉以形成一 Hf〇2層。將該N2氣體再次供應 至該反應室約0.1秒至約5秒以清除該未反應Ch氣體及該 φ 反應之副產物。 使該Hf〇2沉積週期重複y次以沉積約1A至約5A之預 定厚度的Hf02層。除該03氣體之外,還可使用H20蒸氣 做爲該氧化劑。同樣地,除上述N 2氣體之外,還可使用像 . 氬(Ar)之惰性氣體做爲清除氣體。 至於該 Zr〇2沉積週期,將做爲該 Zr 源之 Zf(N(CH3)(C2H5))4(TEMAZ)供應至該維持在上述條件下之 反應室中約0.1秒至約3秒,以便在該基板上吸收該 TEMAZ 〇將該N2氣體供應至該反應室中約〇.1秒至約5秒 -14-In Table 1, 'the CBCT system for Si represents an indicator of the difficulty of electron extraction. The lower the CBO, the better the leakage current characteristics. Similarly, when the band gap energy is high, the leakage current characteristic is better. If the dielectric layer has an amorphous structure at room temperature, it is advantageous in terms of conduction path, thereby causing a decrease in leakage current level. However, the dielectric layer should have a crystalline structure to have a high dielectric constant. That is, the dielectric constant and the amorphous state have a trade-off relationship. As shown in Table 1, since S i 0 2, S i 3 N 4, A12〇3, and Y 2〇3 have a dielectric constant of less than about 20, it is difficult to obtain a highly integrated -10- 1285942 for these dielectric materials. { * t 1 Capacitance of the required level of a capacitor in a semiconductor device. Since Zr 〇 2, Hf 〇 2, Ta 2 〇 5, La 2 Ch and Ti 〇 2 have dielectric constants greater than about 20, these dielectric constants allow the desired capacitance to be obtained. However, when the dielectric material of the latter is used alone or in combination, loss of dielectric characteristics, reduction in leakage current characteristics, and application of a capacitor structure are limited. Accordingly, it is proposed in an exemplary embodiment of the invention to use an amorphous nanocomposite dielectric layer that achieves the high level capacitance required for highly integrated semiconductor device capacitors and can be applied to various capacitor structures without Loss of dielectric properties and leakage current characteristics. According to Table 1, the nanocomposite dielectric layer can be one of the dielectric layers of HfZrO, HfLaO, and HfTaO nanocomposites. These nanocomposite dielectric layers have a dielectric constant higher than that of a HfAlO nanocomposite dielectric layer. The dielectric layers of the above-mentioned HfZrO, HfLaO and HfTaO nanocomposites collectively include Hf and are obtained by mixing Zr〇2, La2〇3 and Ta2〇5 with HfCh in the form of nanocomposite. The dielectric constants of Hf 〇 2, Zr 〇 2, La 2 Ch and Ta 2 〇 5 are approximately 25, 25, 30 and 26, respectively. Therefore, the above dielectric layer of the nanocomposite material has a dielectric constant of at least about 20 without reducing the dielectric constant of Hf 〇 2 . In contrast, a HfAlO nanocomposite dielectric layer is obtained in a nanocomposite form by mixing Hf〇2 having a dielectric constant of about 20 with ah03 having a dielectric constant of about 9. . Therefore, the dielectric layer of the HfAlO nanocomposite has a dielectric constant lower than Hf〇2, thereby promoting a decrease in the dielectric constant of Hf〇2. As shown in Table 1, Ti 2 having a high dielectric constant of about 80 was mixed with Hf 〇 2 to form a nanocomposite dielectric layer. However, Ti〇2 has a lower band gap energy (Eg) than other dielectric materials. Therefore, using Ti〇2 to form a dielectric layer of -11-1285942 κ*I k nanocomposite, it is almost impossible to obtain an effective oxide thickness of less than about 1 〇A, which is usually required for a sub-70 nm device, and Limitations result in a reduction in the electrical characteristics of the capacitor. The first dielectric layer including the first atom M! and the first dielectric layer M2 including the second atom M2 are formed by using an atomic layer deposition (ald) method so that the Μ 1 Μ 20 nm composite The material dielectric layer is formed not in a stacked structure but in a structure in which the first dielectric layer and the second dielectric layer μ2 are mixed. The following describes a method for depositing an exemplary nanocomposite dielectric layer (eg, HfZrO, HfLaO, and HfTaO nanocomposite dielectric layers) and these nanocomposites in accordance with an exemplary embodiment of the present invention. The structure of the dielectric layer. Figure 4 is a graph depicting an ALD method for depositing a HfZrO nanocomposite dielectric layer in a continuous supply of associated gases in accordance with a first embodiment of the present invention. According to the ALD method, a source gas is supplied to a reaction chamber to chemically absorb a single layer of gas source molecules on the surface of a substrate. The physical absorption source molecules are removed to the outside of the reaction chamber. Then, a reactive gas is supplied to the source molecules of the above single layer. Since a chemical reaction occurs between the reaction gas and the molecules of the source, a predetermined atomic layer is deposited. The unreacted reaction gas is purged to the outside of the reaction chamber. These continuous operations constitute one unit period of the ALD method. The ALD process utilizes a surface reaction mechanism that allows for the formation of a stable and uniform thin layer. Since the source gas and the reaction gas are separately supplied and removed in a sequential order, the ALD method can be more effectively prevented by a gas phase reaction than a chemical vapor deposition (CVD):S]-12-1285942 ... The production of particles. The above unit period of the ALD method for depositing the dielectric layer of the HfZrO nanocomposite is as follows: [(Hf source/clearing/oxidizing agent exposure/clearing) y (Zr source/clearing/oxidizing agent exposure/clearing) z]n. Hereinafter, this unit period is referred to as a first unit period. The Hf source is used to supply the Hf source to generate a pulse of Hf 〇 2 and the Zr source is used to supply the h source to generate a pulse of Ζι*〇2. The subscript symbols 'ζ' and Υ indicate (Hf source/clear/oxidant exposure/clearance), the number of cycles, the number of (Zr source/clear/oxidant exposure/clearing) cycles, and the thickness of the HfZrO dielectric layer. The number of cycles. In more detail of the first unit period, the (Hf source/clearing/oxidant exposure/clearing) period is referred to as an Hf〇2 deposition period, which includes supplying the Hf source; clearing the physical absorption Hf source; Exposing the Hf source to an oxidant; and removing the unreacted Hf source and the oxidant, and repeating the Hf〇2 deposition cycle y times. The (Z r source/clear/oxidant exposure/clearing) cycle is referred to as a Zr 0 2 deposition cycle, which includes: supplying the Zr source; removing the unreacted Zr source; exposing the Zr | source to an oxidant; The unreacted Zr source and the oxidant. The Z r 〇 2 deposition cycle was repeated z times. The Hf 2 layer and a ZrCh layer having a predetermined thickness are deposited by repeating the Hf 〇 2 deposition period and the Zr 〇 2 deposition period by y and z times, respectively. A combined deposition cycle comprising the HfCh deposition cycle and the Zr〇2 deposition cycle is repeated n times to determine the overall thickness of the HfZrO nanocomposite dielectric layer. Regarding Fig. 4, an example of a dielectric layer of a HfZrO nanocomposite according to a first embodiment of the present invention will be described below. It should be noted that the unit period of (Hf/N2/〇3/N2) is referred to as an HfCh deposition 1285942 / '. * Cycle and repetition y times. Here, Hf, N2, and 〇3 are each an Hf source, a purge gas, and a oxidizing gas. It should also be noted that the unit period of (Zr/N2/〇3/N2) is referred to as a 'Zr〇2iii product period and is repeated z times. Here, Zr, N2, and 〇3 are respectively a Zr source, a purge gas, and an oxidizing gas. Maintain a pressure of about 0. 1 Torr to about 10 Torr and about 100. The Hf〇2 deposition cycle and the Zr〇2 deposition cycle are carried out in a reaction chamber to a substrate temperature of about 450 °C. As for the Hf〇2 deposition cycle, an Hf source selected from the group consisting of HfCl4, Hf(N〇3)4, φHf(NCH2C2H5)4, and Hf(OC2H〇4 is evaporated in an evaporator. Then, The Hf source is supplied to the reaction chamber maintained under the above conditions for about 0.1 second to about 3 seconds to absorb the Hf source on the substrate. The N 2 gas is supplied to the reaction chamber for about 1 second to The unreacted Hf source is purged to the outside of the reaction chamber for about 5 seconds. The helium 3 gas is supplied to the reaction chamber for about 0.1 second to about 3 seconds to cause a reaction between the absorbed Hf source and the helium 3 gas. And forming an Hf〇2 layer. The N2 gas is again supplied to the reaction chamber for about 0.1 second to about 5 seconds to remove the unreacted Ch gas and the by-product of the φ reaction. The Hf〇2 deposition cycle is repeated y Next, a layer of HfO 2 having a predetermined thickness of about 1 A to about 5 A is deposited. In addition to the 03 gas, H20 vapor may be used as the oxidizing agent. Similarly, in addition to the above N 2 gas, an image such as argon may be used. The inert gas of Ar) is used as the purge gas. As for the Zr〇2 deposition cycle, Zf(N(CH3)(C2H5))4(TEMAZ) supply of the Zr source will be used. The reaction chamber is maintained under the above conditions for about 0.1 seconds to about 3 seconds, in order to absorb the TEMAZ square on the substrate the N2 gas is supplied to the reaction chamber for about seconds to about 5 seconds 〇.1 -14-

V S 1285942 , 1 以清除該未反應TEMAZ至該反應室之外面。然後,將該 〇3氣體供應至該反應室中約0 · 1秒至約3秒以在該吸收 TEMAZ與該〇3氣體間引起反應,以更沉積一 Zr〇2層。藉 由供應該N 2氣體至該反應室中約〇. 1秒至約5秒以將該未 反應〇3氣體及副產物清除至該反應室之外面。 使該Ζι:〇2沉積週期重複z次以沉積約1 A至約5A之預定 厚度的 Zr02層。除上述 TEMAZ之外,還可使用 Zr(N(C2H5)2)4(TDEAZ)。同樣地,除該〇3氣體之外,還可 φ 使用H20蒸氣做爲該氧化劑,以及除該N2氣體之外,還 可使用像氬之惰性氣體做爲該清除氣體。 第5圖係描述依據本發明之第一實施例所沉積的HfZrO 奈米複合材料介電層之結構的圖式。 如所述,該HfZrO奈米複合材料介電層不是以一具有該 Hf〇2層及該Zr〇2層之堆疊結構而是一以奈米複合之形式混 合該Hf〇2層及該ZrCh層的特定結構所形成。 因爲使用該ALD方法來沉積該Hf〇2層及該Zr〇2層,所 ^ 以獲得上面奈米複合結構。特別地,控制以,y,表示之H f〇2 沉積週期的次數及以’z1表示之Zr〇2沉積週期的次數以沉積 約1人至約5 A厚之HfCh層及Zr〇2層的每一層。當不連續 地沉積該Hf〇2層及該Zr〇2層之每一層時,可獲得此厚度。 - 如果該厚度大於約5 A,則連續地沉積該Hf〇2層及該Zr〇2 _ 層,進而導致一堆疊結構。 獲得該HfZrO奈米複合材料介電層需具有一些條件。首 先,該HfCh層及該ZrCh層之厚度應該在約1 a至約5 A範 圍內。如以上所述’如果該厚度大於約5 A,則以個別特 -15- 1285942 ^ * I > 性連續地沉積該Hf〇2層及該Zr〇2層之每一層,以及因而, 可能導致該堆疊結構或甚至導致特性之降低。 第二,應該設定該Hf〇2沉積週期之次數(亦即,,y,)及該 ZrCh沉積週期之次數(亦即,·ζ·)至約1〇次以下以形成一奈 米複合材料結構。亦即,· y ·對· ζ ·之比率係在約1 :丨〇至約丨〇 : ! 之間。 如果該Hf〇2沉積週期及該ZrCh沉積週期中之每一週期 的次數少於約1 〇次,則以奈米複合之形式混合該H f〇 2層 • 及該Zr〇2層,進而導致該HfZrO奈米複合材料介電層,其 中該HfZrO奈米複合材料介電層不是該HfCh層且不是該 Z r〇2層。同樣地,如果將· y ·對’ z ’之比率設定在約丨:1 〇與約 10:1之間,則該HfCh層及該Zr〇2層之每一層具有約1 A 至約5 A之厚度。 藉由在上述條件下實施之ALD方法所獲得的HfZrO奈米 複合材料介電層具有下面幾個特性:增加之結晶溫度及耐 熱特性以及改良之介電特性。特別地,該介電特性之改善 φ 可由下面事實來證明:測量到該HfZrO奈米複合材料介電層 之介電常數有約25的數値。 第6圖係顯示依據本發明之第一實施例所製成的HfZr〇 奈米複合材料介電層與其它介電材料間之介電常數的比較 . 結果之圖式。 • 如所示’ Hf〇2與Zr〇2之介電常數約爲25。該HfZrO奈 米複合材料介電層具有約2 5之介電常數。此結果表示該 HfZrO奈米複合材料介電層具有一幾乎相同於价〇2之介電 常數。因此’可獲得該HfZrO奈米複合材料介電層而不會 1285942 h < I 1 損害到Hf〇2之介電常數。結果’該HfZr0奈米複合材料介 電層具有良好之漏電流特性。 在該HfZrO奈米複合材料介電層之沉積後,實施—退火 處理以改善在該HfZrO奈米複合材料介電層內所包含之有 機材料及緻密化該HfZrO奈米複合材料介電層。該退火處 理係特別在一 03環境中約300°C至約5〇〇。〇下實施約30 秒至約1 2 0秒。 第7圖係描述一用以依據本發明之第二實施例以相關氣 φ 體之連續供應沉積一 H fLaO奈米複合材料介電層的ALD方 法之曲線圖。 用以沉積該HfLaO奈米複合材料介電層之ALD方法的一 單元週期如下:[(Hf源/清除/氧化劑暴露/清除)y(La源/清除/ 氧化劑暴露/清除)ζ] η。將此單位週期稱爲第二單位週期。 該Hf源係一用以供應該Hf源以便產生Hf〇2之脈衝,以 及該La源係一用以供應該La源以便產生La2〇3之脈衝。 下標符號及Y分別表示(Hf源/清除/氧化劑暴露/清 ^ 除)週期之次數、(La源/清除/氧化劑暴露/清除)週期之次數 及決定該HfLaO介電層之厚度的週期之次數。 在該第二單位週期之更詳細細節中,將(Hf源/清除/氧化 劑暴露/清除)週期稱爲一 Hf〇2沉積週期,其包括:供應該 . Hf源;清除該物理吸收Hf源;暴露該Hf源至一氧化劑;及清 除該未反應Hf源及氧化劑,以及使該Hf〇2沉積週期重複y 次。將(La源/清除/氧化劑暴露/清除)週期稱爲一 La2〇3沉 積週期,其包括:供應該La源;清除該未反應La源;暴露該 La源至一氧化劑;及清除該未反應La源及氧化劑。使該 Ϊ285942V S 1285942, 1 to remove the unreacted TEMAZ to the outside of the reaction chamber. Then, the helium 3 gas is supplied to the reaction chamber for about 0.1 second to about 3 seconds to cause a reaction between the absorption TEMAZ and the helium 3 gas to further deposit a layer of Zr〇2. The unreacted helium 3 gas and by-products are purged to the outside of the reaction chamber by supplying the N 2 gas to the reaction chamber for about 1 second to about 5 seconds. The Ζ::2 deposition cycle is repeated z times to deposit a ZrO 2 layer of a predetermined thickness of about 1 A to about 5 Å. In addition to the above TEMAZ, Zr(N(C2H5)2)4 (TDEAZ) can also be used. Similarly, in addition to the ruthenium 3 gas, H20 vapor may be used as the oxidant, and in addition to the N2 gas, an inert gas such as argon may be used as the purge gas. Fig. 5 is a view showing the structure of a dielectric layer of a HfZrO nanocomposite deposited in accordance with a first embodiment of the present invention. As described, the HfZrO nanocomposite dielectric layer does not have a stacked structure having the Hf〇2 layer and the Zr〇2 layer, but a Hf〇2 layer and the ZrCh layer in a nanocomposite form. The specific structure is formed. Since the ALD method is used to deposit the Hf〇2 layer and the Zr〇2 layer, the upper nanocomposite structure is obtained. Specifically, the number of H f 〇 2 deposition cycles represented by y, and the number of Zr 〇 2 deposition cycles indicated by 'z1 are controlled to deposit a HfCh layer and a Zr 〇 2 layer of about 1 to about 5 A thick. Each layer. This thickness is obtained when the Hf〇2 layer and each of the Zr〇2 layers are deposited discontinuously. - If the thickness is greater than about 5 A, the Hf〇2 layer and the Zr〇2_ layer are successively deposited, resulting in a stacked structure. There are some conditions for obtaining the HfZrO nanocomposite dielectric layer. First, the thickness of the HfCh layer and the ZrCh layer should be in the range of about 1 a to about 5 A. As described above, 'if the thickness is greater than about 5 A, the Hf〇2 layer and each of the Zr〇2 layers are successively deposited in a specific degree of -15-1285942 ^*I > and thus, may result in This stacked structure may even result in a reduction in characteristics. Second, the number of times of the Hf〇2 deposition cycle (ie, y,) and the number of times of the ZrCh deposition cycle (ie, ζ·) should be set to less than about 1〇 to form a nanocomposite structure. . That is, the ratio of y · 对 · ζ · is between about 1: 丨〇 to about 丨〇 : ! If the number of the Hf〇2 deposition period and each of the ZrCh deposition periods is less than about 1 〇, the H f〇2 layer and the Zr〇2 layer are mixed in the form of a nanocomposite, thereby causing The HfZrO nanocomposite dielectric layer, wherein the HfZrO nanocomposite dielectric layer is not the HfCh layer and is not the Zr〇2 layer. Similarly, if the ratio of y · to ' z ' is set between about 1:1 〇 and about 10:1, then each of the HfCh layer and the Zr〇2 layer has about 1 A to about 5 A. The thickness. The HfZrO nanocomposite dielectric layer obtained by the ALD method carried out under the above conditions has the following characteristics: increased crystallization temperature and heat resistance characteristics, and improved dielectric properties. In particular, the improvement in dielectric properties φ can be demonstrated by the fact that the dielectric constant of the HfZrO nanocomposite dielectric layer is measured to have a number 约 of about 25. Figure 6 is a graph showing the comparison of the dielectric constant between the dielectric layer of the HfZr(R) nanocomposite and other dielectric materials produced in accordance with the first embodiment of the present invention. • The dielectric constants of 'Hf〇2 and Zr〇2 as shown are approximately 25. The HfZrO nanocomposite dielectric layer has a dielectric constant of about 25. This result indicates that the HfZrO nanocomposite dielectric layer has a dielectric constant which is almost the same as the valence 〇2. Therefore, the dielectric layer of the HfZrO nanocomposite can be obtained without 1285942 h < I 1 impairing the dielectric constant of Hf 〇 2 . As a result, the HfZr0 nanocomposite dielectric layer has good leakage current characteristics. After deposition of the dielectric layer of the HfZrO nanocomposite, an annealing treatment is performed to improve the organic material contained in the dielectric layer of the HfZrO nanocomposite and to densify the dielectric layer of the HfZrO nanocomposite. The annealing process is particularly from about 300 ° C to about 5 Torr in a 03 environment. The armpit is implemented for about 30 seconds to about 120 seconds. Figure 7 is a graph showing an ALD method for depositing a HfLaO nanocomposite dielectric layer in a continuous supply of associated gas φ bodies in accordance with a second embodiment of the present invention. The unit period of the ALD method for depositing the dielectric layer of the HfLaO nanocomposite is as follows: [(Hf source/clearing/oxidant exposure/clearing) y (La source/clearing/oxidant exposure/clearing) ζ] η. This unit period is referred to as a second unit period. The Hf source is used to supply the Hf source to generate a pulse of Hf 〇 2, and the La source is used to supply the La source to generate a pulse of La 〇 3 . The subscript symbol and Y indicate the number of cycles (Hf source/clearing/oxidizing agent exposure/clearing), the number of (La source/clearing/oxidizing agent exposure/clearing) cycles, and the period determining the thickness of the HfLaO dielectric layer, respectively. frequency. In more detail of the second unit period, the (Hf source/clear/oxidant exposure/clearing) period is referred to as an Hf〇2 deposition period, which includes: supplying the Hf source; clearing the physical absorption Hf source; Exposing the Hf source to an oxidant; and removing the unreacted Hf source and the oxidant, and repeating the Hf〇2 deposition cycle y times. The (La source/clear/oxidant exposure/clearing) cycle is referred to as a La2〇3 deposition cycle, which includes: supplying the La source; removing the unreacted La source; exposing the La source to an oxidant; and removing the unreacted La source and oxidant. Make the Ϊ285942

La2〇3沉積週期重複z次。藉由使該Hf〇2沉積週期及該La2〇3 沉積週期分別重複y及z次,以沉積具有預定厚度之一 Hf〇2 層及一 La2〇3層。使一包含該HfCh沉積週期及該La2〇3沉 積週期之組合沉積週期重複η次以決定該HfLaO奈米複合 材料介電層之整個厚度。 有關於第7圖,以下將描述一個依據本發明之第二實施 例沉積該HfLaO奈米複合材料介電層的範例。 應該注意到將(Hf/N2/〇3/N2)之單位週期稱爲一 Hf〇2沉積 > 週期及重複y次。在此單位週期中,Hf、N2、及〇3分別爲 一 Hf源、一清除氣體及一氧化氣體。亦應該注意到將 (La/N2/〇3/N2)之單位週期稱爲一 La2Ch沉積週期及重複z 次。在此單位週期中,La、N2、及〇3分別爲一 La源、一 清除氣體及一氧化氣體。在維持約0.1托耳至約1 0托耳之 壓力及約100°C至約450°C之基板溫度的反應室中實施該 Hf〇2沉積週期及該La2〇3沉積週期。 至於該 Hf〇2沉積週期,使選自由 HfCl4、Hf(N〇3)4、 p Hf(NCH2C2H5)4及Hf(〇C2H5)4所組之群的Hf源在一蒸發器 中蒸發。然後,將該Hf源供應至該維持在上述條件下的反 應室中約0 · 1秒至約3秒,以便在該基板上吸收該Hf源。 將該N2氣體供應至該反應室中約〇. 1秒至約5秒以清除該 未反應H f源至該反應室之外面。將該〇 3氣體供應至該反 應室中約0 · 1秒至約3秒,以便在該吸收H f源與該⑴氣體 間引起反應,藉以形成一 Hf〇2層。將該Nf2氣體再次供應 至該反應室中約0· 1秒至約5秒以清除該未反應〇3氣體及 該反應之副產物。 18- 1285942 4 * 使該HfCh沉積週期重複y次以沉積約1 A至約5A之預 定厚度的1^02層。除該03氣體之外,還可使用H20蒸氣 做爲該氧化劑。同樣地,除上述N2氣體之外,還可使用像 氬(A〇之惰性氣體做爲清除氣體。 至於該LuCh沉積週期,將做爲該La源之La(TMHD)3供 應至該維持在上述條件下之反應室中約0.1秒至約3秒, 以便在該基板上吸收該La(TMHD)3。將該N2氣體供應至該 反應室中約0.1秒至約5秒以清除該未反應La(TMHD)3至 > 該反應室之外面。然後,將該〇3氣體供應至該反應室中約 0.1秒至約3秒以在該吸收La(TMHD)3與該〇3氣體間引起 反應,以更沉積一 La2〇3層。藉由供應該N2氣體至該反應 室中約0.1秒至約5秒以將該未反應〇3氣體及副產物清除 至該反應室之外面。 使上面La2〇3沉積週期重複z次以沉積約1A至約5A之 預定厚度的LazCh層。除上述La(TMHD)3之外,還可使用 La(iPrCp)3 > La(TMHD)3 tetraglyme、La(TMHD)3 tetraen 或 I La(TMHD)3diglyme。同樣地,除該03氣體之外,還可使 用H20蒸氣做爲該氧化劑,以及除該n2氣體之外,還可 使用像氬之惰性氣體做爲該清除氣體。 第8圖係描述依據本發明之第二實施例所沉積的HfLaO 奈米複合材料介電層之結構的圖式。 如所述,該HfLaO奈米複合材料介電層不是以一具有該 Hf〇2層及該La2Ch層之堆疊結構而是一以奈米複合之形式 混合該Hf〇2層及該La2〇3層的特定結構所形成。 用以沉積該Hf〇2層及該La2〇3層之ALD方法允許獲得上 -19- 1285942 I 4 . 1 面奈米複合結構。特別地’控制以Y表示之Hf〇2沉積週期 的次數及以Y表示之La2〇3沉積週期的次數以沉積約1 A 至約5A厚之HfCh層及La2〇3層的每一層。當不連續地沉 積該Hf〇2層及該La2〇3層之每一層時,可獲得此厚度。如 果該厚度大於約5A ’則連續地沉積該HfCh層及該La2Ch 層,進而導致一堆疊結構。 獲得該HfZrO奈米複合材料介電層需具有一些條件。首 先,上述HfCh沉積週期所沉積之HfCh層及上述La2〇‘3沉積 | 週期所沉積的La2〇3層之厚度應該在約1 A至約5 A範圍 內。如以上所述,如果該厚度大於約5 A,則以個別特性 連續地沉積該HfCh層及該La2〇3層之每一層,以及因而, 可能導致該堆疊結構或甚至導致特性之降低。 第二,應該設定該Hf〇2沉積週期之次數(亦即,彳·)及該 La2Ch沉積週期之次數(亦即,·ζ·)至約1〇次以下以具有一 奈米複合材料結構。亦即,1 y ·對· ζ ·之比率係在約1 : 1 〇至約 1 0 :1之間。 | 如果該則〇2及La2Ch沉積週期中之每一週期的次數少於 約10次,則以奈米複合之形式混合該Hf〇2層及該La2〇3 層’進而導致該HfLaO奈米複合材料介電層,其中該HfLaO 奈米複合材料介電層不是該Hf〇2層且不是該La2Ch層。同 樣地’如果將,y,對,z,之比率設定在約1:1〇與約之間, 則可沉積具有約i A至約5 A之預定厚度的HfCh層及La2Ch 層之每一層。 藉由在上述條件下實施之ALD方法所獲得的HfLaO奈米 複合材料介電層具有下面幾個特性:增加之結晶溫度及耐 -20- 1285942 * » ^ I t 熱特性以及改良之介電特性。特別地,該介電特性之改善 可由下面事貫來§登明:該HfLaO奈米複合材料介電層之介 電常數係在約2 5至約3 0範圍內。此高介電常數係由下面 事實所造成:Hf〇2層及La2〇3之介電常數分別約爲25及30。 在該HfLaO奈米複合材料介電層之沉積後,實施一退火 處理以除去在該HfLaO奈米複合材料介電層內所包含之有 機材料及緻密化該H fL a 0奈米複合材料介電層。該退火處 理係特別在一 03環境中約30(TC至約500°C下實施約30 | 秒至約1 2 0秒。 第9圖係描述一用以依據本發明之第三實施例以相關氣 體之連續供應沉積一 HfTa◦奈米複合材料介電層的ALD方 法之曲線圖。 用以沉積該HfTaO奈米複合材料介電層之ALD方法的一 單元週期如下:[(Hf源/清除/氧化劑暴露/清除)y(Ta源/清除/ 氧化劑暴露/清除)z]n。以下,將此單位週期稱爲第三單位 週期。 | 該H f源係一*用以供應該H f源以便產生H f 0 2之脈衝,以 及該Ta源係一用以供應該Ta源以便產生Ta2〇5之脈衝。 下標符號、’、及Y分別表示(Hf源/清除/氧化劑暴露/清 除)週期之次數、(Ta源/清除/氧化劑暴露/清除)週期之次數 及決定該HfTaO介電層之厚度的週期之次數。 在該第三單位週期之更詳細細節中,將(Hf源/清除/氧化 劑暴露/清除)週期稱爲一 Hf02沉積週期,其包括:供應該 Hf源;清除該物理吸收Hf源;暴露該Hf源至一氧化劑;及清 除該未反應Hf源及氧化劑,以及使該Hf〇2沉積週期重複y -21- 1285942The La2〇3 deposition cycle was repeated z times. The Hf〇2 layer and the La2〇3 layer having a predetermined thickness are deposited by repeating the Hf〇2 deposition period and the La2〇3 deposition period by y and z times, respectively. A combined deposition period comprising the HfCh deposition period and the La2〇3 deposition period is repeated n times to determine the entire thickness of the HfLaO nanocomposite dielectric layer. Regarding Fig. 7, an example of depositing a dielectric layer of the HfLaO nanocomposite in accordance with a second embodiment of the present invention will be described below. It should be noted that the unit period of (Hf/N2/〇3/N2) is referred to as a Hf〇2 deposition > cycle and repetition y times. In this unit cycle, Hf, N2, and 〇3 are respectively an Hf source, a purge gas, and a oxidizing gas. It should also be noted that the unit period of (La/N2/〇3/N2) is referred to as a La2Ch deposition period and repeated z times. In this unit period, La, N2, and 〇3 are a La source, a purge gas, and an oxidizing gas, respectively. The Hf〇2 deposition cycle and the La2〇3 deposition cycle are carried out in a reaction chamber maintained at a pressure of from about 0.1 Torr to about 10 Torr and a substrate temperature of from about 100 °C to about 450 °C. As for the Hf〇2 deposition cycle, an Hf source selected from the group consisting of HfCl4, Hf(N〇3)4, pHf(NCH2C2H5)4, and Hf(〇C2H5)4 was evaporated in an evaporator. Then, the Hf source is supplied to the reaction chamber maintained under the above conditions for about 0.1 second to about 3 seconds to absorb the Hf source on the substrate. The N2 gas is supplied to the reaction chamber for about 1 second to about 5 seconds to purge the unreacted Hf source to the outside of the reaction chamber. The helium gas is supplied to the reaction chamber for about 0. 1 second to about 3 seconds to cause a reaction between the source of the absorbed Hf and the gas of the (1), thereby forming a layer of Hf?. The Nf2 gas is again supplied to the reaction chamber for about 0.1 second to about 5 seconds to remove the unreacted helium 3 gas and by-products of the reaction. 18- 1285942 4 * The HfCh deposition cycle is repeated y times to deposit a layer of 1 02 of a predetermined thickness of about 1 A to about 5 Å. In addition to the 03 gas, H20 vapor can also be used as the oxidizing agent. Similarly, in addition to the above N2 gas, an inert gas such as argon (A 〇 as a purge gas may be used. As for the LuCh deposition cycle, La (TMHD) 3 as the La source is supplied to the maintenance. The reaction chamber is conditioned for about 0.1 second to about 3 seconds to absorb the La(TMHD)3 on the substrate. The N2 gas is supplied to the reaction chamber for about 0.1 second to about 5 seconds to remove the unreacted La. (TMHD) 3 to > outside the reaction chamber. Then, the helium 3 gas is supplied into the reaction chamber for about 0.1 second to about 3 seconds to cause a reaction between the absorbed La(TMHD) 3 and the helium 3 gas. To deposit a layer of La2〇3. The N2 gas is supplied to the reaction chamber for about 0.1 second to about 5 seconds to remove the unreacted helium 3 gas and by-products to the outside of the reaction chamber. The 〇3 deposition cycle is repeated z times to deposit a LazCh layer of a predetermined thickness of about 1 A to about 5 A. In addition to the above La(TMHD)3, La(iPrCp)3 > La(TMHD)3 tetraglyme, La ( TMHD) 3 tetraen or I La(TMHD) 3diglyme. Similarly, in addition to the 03 gas, H20 vapor can be used as the oxidant, and in addition to the n2 gas In addition, an inert gas such as argon may be used as the purge gas. Fig. 8 is a view showing the structure of a dielectric layer of a HfLaO nanocomposite deposited in accordance with a second embodiment of the present invention. The HfLaO nanocomposite dielectric layer is not a composite structure having the Hf〇2 layer and the La2Ch layer, but a specific structure of the Hf〇2 layer and the La2〇3 layer in a nanocomposite form. The ALD method for depositing the Hf〇2 layer and the La2〇3 layer allows obtaining the upper -19-1285942 I4.1 nanocomposite structure. Specifically, 'controls the Hf〇2 deposition period represented by Y The number of times and the number of La2〇3 deposition cycles denoted by Y to deposit each layer of HfCh layer and La2〇3 layer of about 1 A to about 5 A thick. When the Hf〇2 layer and the La2〇3 layer are discontinuously deposited The thickness is obtained for each of the layers. If the thickness is greater than about 5 A', the HfCh layer and the La2Ch layer are successively deposited, resulting in a stacked structure. The HfZrO nanocomposite dielectric layer is required to have some conditions. First, the HfCh layer deposited in the above HfCh deposition cycle and the above La2〇'3 The thickness of the La2〇3 layer deposited in the cycle should be in the range of about 1 A to about 5 A. As described above, if the thickness is greater than about 5 A, the HfCh layer and the La2 are successively deposited with individual characteristics.层 3 layers of each layer, and thus, may cause the stack structure or even cause a decrease in characteristics. Second, the number of times of the Hf 〇 2 deposition cycle (ie, 彳·) and the number of times of the La 2Ch deposition cycle ( That is, ζ·) to less than about 1 以 to have a nanocomposite structure. That is, the ratio of 1 y · · · ζ is between about 1: 1 〇 and about 10: 1. If the number of each of the 〇2 and La2Ch deposition cycles is less than about 10, the Hf〇2 layer and the La2〇3 layer are mixed in the form of a nanocomposite to cause the HfLaO nanocomposite. a material dielectric layer, wherein the HfLaO nanocomposite dielectric layer is not the Hf〇2 layer and is not the La2Ch layer. Similarly, if the ratio of y, y, z is set to be between about 1:1 Å and about, each of the HfCh layer and the La2Ch layer having a predetermined thickness of about i A to about 5 A may be deposited. The dielectric layer of the HfLaO nanocomposite obtained by the ALD method carried out under the above conditions has the following characteristics: increased crystallization temperature and resistance to -20-1285942 * » ^ I t thermal characteristics and improved dielectric properties . In particular, the improvement in dielectric properties can be ascertained by the fact that the dielectric constant of the HfLaO nanocomposite dielectric layer is in the range of from about 25 to about 30. This high dielectric constant is caused by the fact that the dielectric constants of Hf〇2 and La2〇3 are about 25 and 30, respectively. After the deposition of the dielectric layer of the HfLaO nanocomposite, an annealing treatment is performed to remove the organic material contained in the dielectric layer of the HfLaO nanocomposite and densify the dielectric of the HfL a nano composite Floor. The annealing treatment is carried out at about 30 (TC to about 500 ° C for about 30 sec to about 1200 sec in a 03 environment. Figure 9 is a diagram for describing a third embodiment in accordance with the present invention. A graph of the ALD method for depositing a dielectric layer of a HfTa nano-composite composite material by continuous supply of gas. The unit period of the ALD method for depositing the dielectric layer of the HfTaO nanocomposite is as follows: [(Hf source/clear/ Oxidant exposure/clearing) y (Ta source/clearing/oxidizing agent exposure/clearing) z]n. Hereinafter, this unit period is referred to as a third unit period. | The Hf source is a * for supplying the Hf source so that A pulse of H f 0 2 is generated, and the Ta source is used to supply the Ta source to generate a pulse of Ta 2 〇 5. The subscript symbols, ', and Y respectively represent (Hf source/clear/oxidant exposure/clear) cycles The number of times, the number of (Ta source/clearing/oxidizing agent exposure/clearing) cycles, and the number of cycles determining the thickness of the HfTaO dielectric layer. In more detail of the third unit cycle, (Hf source/clear/ The oxidant exposure/clearing cycle is referred to as an Hf02 deposition cycle, which includes: supplying the Hf ; Clear the source physical absorption Hf; Hf exposing the source to an oxidant; and clear of the Hf source and the unreacted oxidizing agent, and causing the deposition cycle is repeated Hf〇2 y -21- 1285942

It « 次。將(Ta源/清除/氧化劑暴露/清除)週期稱爲一 Ta2〇3沉 積週期’其包括:供應該Ta源V凊除該未反應Ta源;暴露該 Ta源至一氧化劑;及清除該未反應Ta源及氧化劑。使該 Ta2〇5沉積週期重複z次。藉由使該Hf〇2沉積週期及該Ta2〇5 沉積週期分別重複7及z次,以沉積具有預定厚度之一 HfCh 層及一 丁32〇5層。使一包含該Hf〇2沉積週期及該Ta2〇5沉 積週期之組合沉積週期重複η次以決定該HfTaO奈米複合 材料介電層之整個厚度。 有關於第9圖,以下將描述一個依據本發明之第三實施 例沉積該HfTaO奈米複合材料介電層的範例。 應該注意到將(Hf/N"〇3/N2)之單位週期稱爲一 HfCh沉積 週期及重複y次。在此單位週期中,Hf、N2、及Ch分別爲 一 Hf源、一清除氣體及一氧化氣體。亦應該注意到將 (Ta/N2/Ch/N2)之單位週期稱爲一 Ta2〇5沉積週期及重複z 次。在此單位週期中,Ta、N2、及〇3分別爲一 Ta源、一 清除氣體及一氧化氣體。在維持約〇. 1托耳至約1 0托耳之 壓力及約l〇〇°C至約450°C之基板溫度的反應室中實施該 Hf〇2沉積週期及該Ta2〇5沉積週期。 至於該HfCh沉積週期’使選自由 HfCh、Hf(NCh)4、 Hf(NCH2C2H5)4及Hf(OC2H〇4所組之群的Hf源在一蒸發器 中蒸發。然後,將該Hf源供應至該維持在上述條件下的反 應室中約0.1秒至約3秒’以便在該基板上吸收該Hf源。 將該N2氣體供應至該反應室中約〇 · 1秒至約5秒以清除該 未反應Hf源至該反應室之外面。將該〇3氣體供應至該反 應室中約0.1秒至約3秒’以便在該吸收Hf源與該〇3氣體 -22- 1285942 I * * . 4 間引起反應,藉以形成一 Hf〇2層。將該N2氣體再次供應 至該反應室中約0.1秒至約5秒以清除該未反應氣體及 該反應之副產物。 使該Hf〇2沉積週期重複y次以沉積約1A至約5A之預 定厚度的1^02層。除該03氣體之外,還可使用H2〇蒸氣 做爲該氧化劑。同樣地,除上述N2氣體之外,還可使用像 氬(Ar)之惰性氣體做爲清除氣體。 至於該Ta2Ch沉積週期,將做爲該Ta源之五氧化二鉅供 | 應至該維持在上述條件下之反應室中約0.1秒至約3秒, 以便在該基板上吸收該五氧化二鉬。將該%氣體供應至該 反應室中約0.1秒至約5秒以清除該未反應五氧化二鉬至 該反應室之外面。然後,將該〇3氣體供應至該反應室中約 0.1秒至約3秒以在該吸收五氧化二鉅與該〇 3氣體間引起 反應,以更沉積一 Ta2〇5層。藉由供應該N2氣體至該反應 室中約0· 1秒至約5秒以將該未反應〇3氣體及副產物清除 至該反應室之外面。 | 使上面Ta2〇5沉積週期重複z次以沉積約1A至約5 A之 預定厚度的Ta2〇5層。同樣地,除該〇3氣體之外,還可使 用HW蒸氣做爲該氧化劑,以及除該n2氣體之外,還可 使用像氬之惰性氣體做爲該清除氣體。 第10圖係描述依據本發明之第三實施例所沉積的HfTaO 奈米複合材料介電層之結構的圖式。 如所述,該HfTaO奈米複合材料介電層不是以一具有該 Hf〇2層及該Ta2〇5層之堆疊結構而是一以奈米複合之形式 混合該H f 〇 2層及該τ a 2 0 5層的特定結構所形成。It « times. The (Ta source/clearing/oxidant exposure/clearing) cycle is referred to as a Ta2〇3 deposition cycle 'which includes: supplying the Ta source V to remove the unreacted Ta source; exposing the Ta source to an oxidant; and clearing the Reacts Ta source and oxidant. The Ta2〇5 deposition cycle was repeated z times. The HfCh layer and the 32 Å layer having a predetermined thickness are deposited by repeating the Hf 〇 2 deposition period and the Ta 2 〇 5 deposition period, respectively, 7 and z times. A combined deposition period comprising the Hf〇2 deposition period and the Ta2〇5 deposition period is repeated n times to determine the entire thickness of the HfTaO nanocomposite dielectric layer. Regarding Fig. 9, an example of depositing a dielectric layer of the HfTaO nanocomposite in accordance with a third embodiment of the present invention will be described below. It should be noted that the unit period of (Hf/N"〇3/N2) is referred to as an HfCh deposition period and repeated y times. In this unit period, Hf, N2, and Ch are respectively an Hf source, a purge gas, and an oxidizing gas. It should also be noted that the unit period of (Ta/N2/Ch/N2) is referred to as a Ta2〇5 deposition period and is repeated z times. In this unit period, Ta, N2, and 〇3 are a Ta source, a purge gas, and an oxidizing gas, respectively. The Hf〇2 deposition cycle and the Ta2〇5 deposition cycle are carried out in a reaction chamber maintained at a pressure of from about 1 Torr to about 10 Torr and a substrate temperature of from about 10 °C to about 450 °C. As for the HfCh deposition period, the Hf source selected from the group consisting of HfCh, Hf(NCh)4, Hf(NCH2C2H5)4, and Hf(OC2H〇4 is evaporated in an evaporator. Then, the Hf source is supplied to Maintaining the reaction chamber under the above conditions for about 0.1 second to about 3 seconds to absorb the Hf source on the substrate. The N2 gas is supplied to the reaction chamber for about 1 second to about 5 seconds to clear the The unreacted Hf source is supplied to the outside of the reaction chamber. The helium 3 gas is supplied to the reaction chamber for about 0.1 second to about 3 seconds 'in order to absorb the Hf source and the helium 3 gas-22-1285942 I**. The reaction is initiated to form an Hf 2 layer. The N 2 gas is again supplied to the reaction chamber for about 0.1 second to about 5 seconds to remove the unreacted gas and by-products of the reaction. Repeating y times to deposit a layer of 1 0 to a predetermined thickness of about 1 A to about 5 A. In addition to the 03 gas, H 2 〇 vapor may be used as the oxidizing agent. Similarly, in addition to the above N 2 gas, it may be used. An inert gas such as argon (Ar) is used as a purge gas. As for the Ta2Ch deposition cycle, it will be used as the Ta-oxide bismuth supply. Up to about 0.1 second to about 3 seconds in the reaction chamber maintained under the above conditions to absorb the molybdenum pentoxide on the substrate. The % gas is supplied to the reaction chamber for about 0.1 second to about 5 seconds to remove The unreacted molybdenum pentoxide is applied to the outside of the reaction chamber. Then, the helium 3 gas is supplied to the reaction chamber for about 0.1 second to about 3 seconds to cause a reaction between the absorbed bismuth pentoxide and the ruthenium 3 gas. To deposit a further layer of Ta2〇5. The unreacted helium 3 gas and by-products are removed to the outside of the reaction chamber by supplying the N2 gas to the reaction chamber for about 0.1 second to about 5 seconds. The above Ta2〇5 deposition cycle is repeated z times to deposit a predetermined thickness of Ta2〇5 layer of about 1 A to about 5 A. Similarly, in addition to the 〇3 gas, HW vapor may be used as the oxidizing agent, and In addition to the n2 gas, an inert gas such as argon may be used as the purge gas. Fig. 10 is a view showing the structure of a dielectric layer of a HfTaO nanocomposite deposited in accordance with a third embodiment of the present invention. As described, the HfTaO nanocomposite dielectric layer does not have the Hf〇2 layer And the stacked structure of the Ta2〇5 layer is formed by mixing the Hf〇2 layer and the specific structure of the τa205 layer in the form of a nanocomposite.

:S -23- 1285942 用以沉積該HfCh層及該Ta2〇5層之ALD方法允許獲得上 面奈米複合結構。特別地,控制以γ表示之HfCh沉積週期 的次數及以’z1表示之Ta2〇5沉積週期的次數以沉積約1人 至約5 A厚之HfCh層及Ta2〇5層的每一層。當不連續地沉 積該HfCh層及該Ta2〇5層之每一層時,可獲得此厚度。如 果該厚度大於約5 A,則連續地沉積該H f 0 2層及該T a 2〇5 層,進而導致該堆疊結構。 獲得該HfTaO奈米複合材料介電層需具有一些條件。首 | 先,上述Hf〇2沉積週期所沉積之HfCh層及上述Ta2〇5沉積 週期所沉積的Ta2〇5層之厚度應該在約1 A至約5 A範圍 內。如以上所述,如果該厚度大於約5 A,則以個別特性 連續地沉積該Hf〇2層及該Ta2〇5層之每一層,以及因而, 可能導致該堆疊結構或甚至導致特性之降低。 第二,應該設定該HfCh沉積週期之次數(亦即,及該 Ta2〇5沉積週期之次數(亦即,·ζ·)至約丨〇次以下以具有一 奈米複合材料結構。亦即,1y·對·ζ·之比率係在約1:10至約 | 1 0 : 1之間。 如果該則〇2及Ta2〇5沉積週期中之每一週期的次數少於 約1 0次’則以奈米複合之形式混合該H f 0 2層及該T a 2〇5 層,進而導致該HfTa0奈米複合材料介電層,其中該HfTaO 奈米複合材料介電層不是該HfCh層且不是該Ta2〇5層。同 樣地’如果將· y ·對· z ·之比率設定在約1 :丨〇與約1 i之間, 則可沉積具有約1 A至約5A之預定厚度的Hf〇2層及Τυ〇5 層之每一層。 藉由在上述條件下實施之ALD方法所獲得的HfTa◦奈米 rs - 24· 1285942 看 ( I i 複合材料介電層具有下面幾個特性:增加之結晶溫度及耐 熱特性以及改良之介電特性。特別地,該介電特性之改善 可由下面事實來證明:該HfTa◦奈米複合材料介電層之介 電常數至少高於Hf〇2之介電常數。因爲Hf〇2層及Ta2〇5之 介電常數分別約爲25及26,所以造成此高介電常數。 在該HfTaO奈米複合材料介電層之沉積後,實施一退火 處理以除去在該HfTaO奈米複合材料介電層內所包含之有 機材料及緻密化該HfTaO奈米複合材料介電層。該退火處 φ 理係特別在一〇3環境中約300°C至約500°C下實施約30 秒至約1 2 0秒。 上述HfZrO、HfLaO、HfTaO奈米複合材料介電層之每一 層具有約25 A至約200 A的總厚度。 第1 1圖係描述依據本發明之另一示範性實施例的一具 有一奈米複合材料介電結構之電容器的剖面圖。舉例來 說’該奈米複合材料介電結構包括一 HfZrO奈米複合材料 介電層。 φ 如所述’該電容器包括:一下電極2 1 ;在該下電極2 1上所 形成之前述HfZrO奈米複合材料介電層22;以及在該HfZrO 奈米複合材料介電層22上所形成之一上電極23。該下電 極21及該上電極23係由一選自由摻雜有磷(P)或砷(As)之 - 複晶矽、氮化鈦(TiN)、釕(Ru)、氧化釕(Ru〇2)、鈾(Pt)、銥 _ (Ir)及氧化銥(Ir〇2)所組成之群的材料所形成。例如:該電容 器可以一矽-絕緣層-矽(S IS )結構來形成,其中該下電極2 1 及該上電極2 3係由複晶矽所形成。亦允許一金屬-絕緣層-矽(MIS)電容器結構或一金屬-絕緣層_金屬(MIM)電容器結 -25- 1285942 . ^ 構。對於該MIS電容器結構而言’該下電極2 1係由複晶矽 所形成及該上電極2 3係由金屬或氧化金屬所形成°對於該 ΜIM電容器結構而言’該下電極21及該上電極23係由金 屬或氧化金屬所形成。該下電極2 1可以一堆疊結構或以一 三維結構(例如:一凹型結構或一圓柱型結構)來形成。 如第4及5圖所述,在該下電極21與該上電極23間所 設置之HfZrO奈米複合材料介電層22係經由一 ALD方法 所形成。更特別地,重複地實施一 Hf〇2沉積週期及一 Zr〇2 | 沉積週期以獲得約25人至約200A之HfZrO奈米複合材料 介電層22。 該下電極21及該上電極23不是個別接觸一 H fO 2層及一 Zr〇2層,然而是同時接觸該Hf〇2層及該Zr〇2層(參考第5 圖)。亦即,該HfZrO奈米複合材料介電層22不是以一堆 疊結構(連續地使該H f 0 2層及該z r 0 2層彼此堆疊在一起) 所形成;取而代之,使該Hf〇2層及該ZrCh層以奈米複合之 形式來混合。 | 如以上所述,依據該ALD方法,可控制該單位週期之次 數以不連續地沉積該Hf〇2層及該ZrCh層,以便該HfZrO 奈米複合材料介電層2 2可具有一奈米複合材料結構。因爲 如同本發明之第一實施例沉積該HfZrO奈米複合材料介電 層22,所以將省略其詳細說明。 控制該Hf〇2沉積週期及該Zr〇2沉積週期之重複次數(例 如及Y)以沉積約^至約5人厚之Hf〇2層及Zr〇2層的 每一層’以便該HfZrO奈米複合材料介電層22之總厚度在 約25A至約200A之範圍內。例如:如第4及5圖所示,將 -26- 1285942 ft, t I i 、·對之比率設定在約i:i〇與約10:1間之範圍內。 如果該Hf〇2層及該Zr〇2層之每一層的厚度大於約5 A, 則連續地沉積該Hf〇2層及該Zr〇2層,進而導致一具有該 層及該Zr〇2層之堆疊結構。相較於前述HfZrO奈米複 合材料結構,該堆疊結構具有一降低之介電特性。 雖然未描述,但是如果該下電極2 1包括複晶矽,則因爲 在該下電極21上形成該H fZrO奈米複合材料介電層22期 間氧化該下電極2卜所以在一氨氣(NH3)環境中約800°C至 • 約1,000°C下實施一快速熱處理(RTP)約10秒至約120秒以 防止一原始氧化層(native oxide layer)之形成。該RTP之結 果形成一氮化矽層,以及此氮化矽層防止漏電流特性之變 差及介電常數之減少。 雖然第11圖描述應用該HfZrO奈米複合材料介電層做爲 該電容器之介電層的情況,但是亦可應用其它包括HfLaO 及HfTaO之奈米複合材料介電層。 依據本發明之示範性實施例,即使使用一薄奈米複合材 φ 料介電層,以奈米複合之形式所完成介電層可獲得漏電流 特性而不會減少介電常數。 本申請案包含有關於2005年4月30日在韓國專利局所 提出之韓國專利申請案第KR 2005 -003 65 29號的標的,在 - 此以提及方式倂入上述韓國專利申請案之整個內容。 , 雖然已描述有關於一些較佳實施例之本發明,但是熟習 該項技藝者將明顯了解到在不脫離下面申請專利範圍所界 定之本發明的精神及範圍內可實施各種變化及修飾。 【圖式簡單說明】:S -23- 1285942 The ALD method for depositing the HfCh layer and the Ta2〇5 layer allows obtaining an upper nanocomposite structure. Specifically, the number of HfCh deposition periods indicated by γ and the number of Ta2〇5 deposition periods indicated by 'z1 are controlled to deposit each layer of the HfCh layer and the Ta2〇5 layer of about 1 to about 5 A thick. This thickness is obtained when the HfCh layer and each of the Ta2〇5 layers are deposited discontinuously. If the thickness is greater than about 5 A, the H f 0 2 layer and the T a 2〇5 layer are continuously deposited, resulting in the stacked structure. There are some conditions for obtaining the HfTaO nanocomposite dielectric layer. First, the thickness of the HfCh layer deposited in the above Hf〇2 deposition cycle and the Ta2〇5 layer deposited in the above Ta2〇5 deposition cycle should be in the range of about 1 A to about 5 A. As described above, if the thickness is greater than about 5 A, each of the Hf 2 layer and the Ta 2 5 layer is successively deposited in an individual characteristic, and thus, may cause the stack structure or even cause a decrease in characteristics. Second, the number of times of the HfCh deposition cycle (i.e., the number of times of the Ta2〇5 deposition cycle (i.e., ζ·) should be set to about 丨〇 or less to have a nanocomposite structure. The ratio of 1y·对·ζ· is between about 1:10 and about |10: 1. If this is the case, the number of cycles in the deposition cycle of 〇2 and Ta2〇5 is less than about 10 times' Mixing the H f 0 2 layer and the T a 2〇5 layer in a nanocomposite form, thereby resulting in the HfTa0 nano composite dielectric layer, wherein the HfTaO nano composite dielectric layer is not the HfCh layer and is not The Ta2 〇 5 layer. Similarly, if the ratio of y · y · z · is set between about 1: 丨〇 and about 1 i, Hf 具有 having a predetermined thickness of about 1 A to about 5 A may be deposited. Each of the 2 and Τυ〇5 layers. The HfTa ◦ nanometer rs - 24· 1285942 obtained by the ALD method carried out under the above conditions (I i composite dielectric layer has the following characteristics: increased Crystallization temperature and heat resistance characteristics and improved dielectric properties. In particular, the improvement of the dielectric properties can be confirmed by the fact that the HfTa◦ The dielectric constant of the dielectric layer of the rice composite is at least higher than the dielectric constant of Hf 〇 2. Since the dielectric constants of the Hf 〇 2 layer and the Ta 2 〇 5 are about 25 and 26, respectively, this high dielectric constant is caused. After deposition of the dielectric layer of the HfTaO nanocomposite, an annealing treatment is performed to remove the organic material contained in the dielectric layer of the HfTaO nanocomposite and densify the dielectric layer of the HfTaO nanocomposite. The φ system is carried out in a range of about 300 ° C to about 500 ° C for about 30 seconds to about 120 seconds in a 〇 3 environment. Each of the above HfZrO, HfLaO, HfTaO nanocomposite dielectric layers has about A total thickness of 25 A to about 200 A. Figure 11 is a cross-sectional view showing a capacitor having a nanocomposite dielectric structure in accordance with another exemplary embodiment of the present invention. For example, the nanometer The composite dielectric structure comprises a dielectric layer of HfZrO nanocomposite. φ As described above, the capacitor comprises: a lower electrode 2 1 ; the aforementioned HfZrO nanocomposite dielectric layer 22 formed on the lower electrode 2 1 And on the HfZrO nanocomposite dielectric layer 22 An upper electrode 23. The lower electrode 21 and the upper electrode 23 are selected from the group consisting of - doped with phosphorus (P) or arsenic (As), titanium nitride (TiN), ruthenium (Ru), A material consisting of a group consisting of ruthenium oxide (Ru〇2), uranium (Pt), 铱_(Ir), and iridium oxide (Ir〇2). For example, the capacitor can be an insulating layer-矽 (S IS The structure is formed, wherein the lower electrode 2 1 and the upper electrode 23 are formed of a polysilicon. A metal-insulator-germanium (MIS) capacitor structure or a metal-insulator layer-metal (MIM) capacitor junction is also allowed. -25-1285942 . For the MIS capacitor structure, the lower electrode 2 1 is formed of a polysilicon and the upper electrode 23 is formed of a metal or an oxidized metal. For the ΜIM capacitor structure, the lower electrode 21 and the upper portion The electrode 23 is formed of a metal or an oxidized metal. The lower electrode 2 1 may be formed in a stacked structure or in a three-dimensional structure (for example, a concave structure or a cylindrical structure). As shown in Figs. 4 and 5, the HfZrO nanocomposite dielectric layer 22 disposed between the lower electrode 21 and the upper electrode 23 is formed by an ALD method. More specifically, an Hf 〇 2 deposition cycle and a Zr 〇 2 | deposition cycle are repeatedly performed to obtain a HfZrO nanocomposite dielectric layer 22 of from about 25 to about 200 Å. The lower electrode 21 and the upper electrode 23 are not individually in contact with an HfO 2 layer and a Zr〇2 layer, but are in contact with the Hf〇2 layer and the Zr〇2 layer at the same time (refer to FIG. 5). That is, the HfZrO nanocomposite dielectric layer 22 is not formed in a stacked structure (continuously stacking the H f 0 2 layer and the zr 0 2 layer on each other); instead, the Hf〇2 layer is formed And the ZrCh layer is mixed in the form of a nanocomposite. As described above, according to the ALD method, the number of unit periods can be controlled to discontinuously deposit the Hf〇2 layer and the ZrCh layer, so that the HfZrO nanocomposite dielectric layer 2 2 can have one nanometer. Composite structure. Since the HfZrO nanocomposite dielectric layer 22 is deposited as in the first embodiment of the present invention, a detailed description thereof will be omitted. Controlling the Hf〇2 deposition cycle and the number of repetitions of the Zr〇2 deposition cycle (for example, and Y) to deposit each layer of the Hf〇2 layer and the Zr〇2 layer of about 5 to about 5 people for the HfZrO nanometer. The total thickness of the composite dielectric layer 22 is in the range of from about 25A to about 200A. For example, as shown in Figures 4 and 5, the ratio of -26 - 1285942 ft, t I i , · is set to be in the range between about i: i 〇 and about 10: 1. If the thickness of each of the Hf〇2 layer and the Zr〇2 layer is greater than about 5 A, the Hf〇2 layer and the Zr〇2 layer are continuously deposited, thereby causing a layer having the layer and the Zr〇2 layer. Stack structure. The stacked structure has a reduced dielectric property compared to the aforementioned HfZrO nanocomposite structure. Although not described, if the lower electrode 21 includes a polysilicon, the lower electrode 2 is oxidized during the formation of the HfZrO nanocomposite dielectric layer 22 on the lower electrode 21, so that an ammonia gas (NH3) A rapid thermal processing (RTP) is performed in the environment at about 800 ° C to about 1,000 ° C for about 10 seconds to about 120 seconds to prevent the formation of a native oxide layer. The result of the RTP forms a tantalum nitride layer, and the tantalum nitride layer prevents deterioration of leakage current characteristics and reduction of dielectric constant. Although Fig. 11 depicts the application of the HfZrO nanocomposite dielectric layer as the dielectric layer of the capacitor, other nanocomposite dielectric layers including HfLaO and HfTaO may be applied. According to an exemplary embodiment of the present invention, even if a thin nanocomposite φ dielectric layer is used, the dielectric layer in the form of a nanocomposite can obtain leakage current characteristics without reducing the dielectric constant. The present application contains the subject matter of the Korean Patent Application No. KR 2005-003 65 29 filed on April 30, 2005 in the Korean Patent Office, the entire disclosure of which is incorporated herein by reference. content. While the invention has been described with respect to the preferred embodiments of the present invention, it will be apparent to those skilled in the art that various modifications and changes can be made without departing from the spirit and scope of the invention. [Simple description of the map]

-27- 1285942 * « t c 第i圖係顯示一具有一傳統介電結構之電容器的剖面 圖,其中該傳統介電結構包括一氧化給(Hf02)層及一氧化 鋁(Al2〇3)層; 第2圖係顯示包括Hf〇2、A12〇3及奈米複合材料HfA1〇 之傳統介電材料的介電常數之曲線圖; 第3圖係描述依據本發明之一特定實施例的一奈米複合 材料介電結構之槪念的圖式; 第4圖係描述一用以依據本發明之第一實施例沉積一 | HfZrO奈米複合材料介電層的原子層沉積(ALD)方法之曲 線圖; 弟5圖係描述依據本發明之第一實施例所獲得的HfZr〇 奈米複合材料介電層之結構的圖式; 第6 Η係顯示依據本發明之第一實施例所獲得的HfZr〇 材*料·介電層與其它介電材料之介電常數間的比較 結果之圖式; 第7 ffl係顯示〜用以依據本發明之第二實施例沉積一 | HfLaO奈米複合材料介電層的ald方法之曲線圖; 第8圖係描述依據本發明之第二實施例所獲得的HfLaO 奈米複合材料介電層之結構的圖式; 胃9 ®係顯示一用以依據本發明之第三實施例沉積一 HfTaO奈米複合材料介電層的ALD方法之曲線圖; 第10圖係描述依據本發明之第三實施例所獲得的HfTaO 奈米複合材料介電層之結構的圖式;以及 第1 1圖係顯示依據本發明之特定實施例的一具有一 HfZirO奈米複合材料介電層之電容器的結構之剖面圖。 -28- 1285942-27- 1285942 * « tc i is a cross-sectional view showing a capacitor having a conventional dielectric structure, wherein the conventional dielectric structure includes an oxidized (Hf02) layer and an aluminum oxide (Al 2 〇 3) layer; 2 is a graph showing the dielectric constant of a conventional dielectric material including Hf〇2, A12〇3, and nano composite material HfA1〇; FIG. 3 is a view showing a nanometer according to a specific embodiment of the present invention. A schematic diagram of a composite dielectric structure; FIG. 4 depicts a graph of an atomic layer deposition (ALD) method for depositing a dielectric layer of a HfZrO nanocomposite in accordance with a first embodiment of the present invention. Figure 5 is a diagram showing the structure of the dielectric layer of the HfZr〇 nanocomposite obtained in accordance with the first embodiment of the present invention; the sixth line shows the HfZr〇 obtained according to the first embodiment of the present invention. A pattern of comparison between the dielectric constant of the dielectric layer and the dielectric material and the dielectric material of the other dielectric materials; the 7th ffl shows that the dielectric layer is deposited in accordance with the second embodiment of the present invention | HfLaO nanocomposite dielectric The graph of the ald method of the layer; the figure 8 is based on the description of the hair A schematic diagram of the structure of the dielectric layer of the HfLaO nanocomposite obtained in the second embodiment; the stomach 9® shows an ALD for depositing a dielectric layer of a HfTaO nanocomposite according to the third embodiment of the present invention. FIG. 10 is a diagram depicting the structure of a dielectric layer of a HfTaO nanocomposite obtained in accordance with a third embodiment of the present invention; and FIG. 1 is a view showing a specific embodiment in accordance with the present invention. A cross-sectional view of the structure of a capacitor having a dielectric layer of a HfZirO nanocomposite. -28- 1285942

HfZrO奈米複合材料介電層之電容器的結構之剖面圖 主要兀件符號說明】 11 下電極 12 介電結構 12A A 1 2〇3層 12B Hf〇2層 13 上電極 21 下電極 22 HfZrO奈米複合材料介電層 23 上電極HfZrO nanocomposite dielectric layer capacitor structure cross-section diagram main element symbol description] 11 lower electrode 12 dielectric structure 12A A 1 2〇3 layer 12B Hf〇2 layer 13 upper electrode 21 lower electrode 22 HfZrO nano Composite dielectric layer 23 upper electrode

-29-29

Claims (1)

1285942 • , k 十、申請專利範圍: I—種電容器之介電結構,包括: —層氧化給(HfCh)層;以及 層介電層’主要爲具有等於或大於該Hf〇2層之介 電常數的材料,其中該介電結構包括一奈米複合材料介 電結構,該奈米複合材料介電結構係藉由,以奈米複合 之形式,混合該Hf〇2層與該介電層而得。 2.如申請專利範圍第丨項之介電結構,其中該介電層具有 • 介電常數範圍在約25至約3〇及帶隙能量位準範圍在約 4 · 3 至約 7.8。 3 ·如申請專利範圍第丨項之介電結構,其中該介電層包括 —選自Zr〇2、La2〇3及1^2〇5所組成之群的材料。 4 ·如申請專利範圍第丨項之介電結構,其中該奈米複合材 料介電結構係藉由,以奈米複合之形式,混合該Hf〇2 層與該介電層所獲得,每一層係經由原子層沉積(ald) 法所形成且每一沉積週期具有約丨A至約5人之厚度。 g 5·如申請專利範圍第4項之介電結構,其中該奈米複合材 料介電結構具有約2 5 A至約2 Ο Ο A之厚度。 6 · —種用以製造電容器之介電結構的方法,包括: 形成奈米複合材料介電層,係藉由原子層沉積(ALD) -法,重複地分別實施1y1次及次之氧化給(Hf〇2)沉積週 期與介電層沉積週期,以奈米複合之方式,混合氧化給 (Hf〇2)層與介電層;以及 實施退火處理’以緻密化該奈米複合材料介電結構。 7.如申請專利範圍第6項之方法,其中該Hf〇2沉積週期包 -30- 1285942 ί I 括: 吸收一給(Hf)源; 清除該Hf源之未反應部分; 供應氧化劑以誘發與該吸收Hf源之反應,以便沉積 Hf〇2層;以及 清除該氧化劑之未反應部分及該反應之副產物。 8.如申請專利範圍第7項之方法,其中該Hf〇2層沈積之實 施,係在約10(TC至約450°C之溫度範圍下及在約0.1 > 托耳(torr)至約10托耳(tori*)之壓力範圍下進行。 9 ·如申請專利範圍第7項之方法,其中該H f源之吸收包括: 蒸發該選自 HfCh、Hf(N〇3)4、Hf(NCH2C2H5)4 及 Hf(〇C2H5)4所組成之群的Hf源;以及 供應該蒸發H f源至一反應室中達約〇. 1秒至約3秒, 其中使該反應室維持在約0.1托耳至約1 0托耳之壓力 及約100°C至約45 0°C之基板溫度。 1 0 ·如申請專利範圍第7項之方法,其中該供應氧化劑,係 | 藉由供應Ch或H2〇蒸氣達約0.1秒至約3秒。 1 1 ·如申請專利範圍第7項之方法,其中該清除氧化劑之未 反應部分及該反應之副產物,係藉由使用氮氣(N2)或一 惰性氣體達約0.1秒至約5秒。 1 2 ·如申請專利範圍第6項之方法,其中該介電層包括選自 Zr〇2、La2〇3及Ta2〇5所組成之群其中之一的材料。 1 3 .如申請專利範圍第1 2項之方法,其中該介電層,係以 Zr〇2爲主之選擇材料,藉由使用一選自 Zr(N(CH3)(C2H5))4(TEMAZ)及 Zr(N(C2H5)2)4(TDEAZ)之 1285942 t 銷(Ζ〇源而形成的。 1 4.如申請專利範圍第丨2項之方法,其中該介電層,其以 La2〇3爲主之選擇材料,係藉由使用一選自La(TMHD)3、 La(iPrCp)3、La(TMHD)3tetraglyme、La(TMHD)3tetraen 及La(TMHD)3diglyme之鑭(La)源而形成。 1 5 ·如申請專利範圍第1 2項之方法,其中該介電層係以 Ta2〇5爲主之選擇材料,係藉由使用五氧化二鉅之鉬源 而形成。 | 1 6 ·如申請專利範圍第6項之方法,其中· y ’對Y之比率係 在約1 : 1 0與約1 0 : 1間之範圍內。 i 7.如申請專利範圍第6項之方法,其中該HfCh層及該介 電層係以奈米複合之形式,藉由重複地沉積Hf〇2層及 介電層每一沉積週期至約1 A至約5 A厚,以便該奈米 複合材料介電結構至具有約25人至約200A範圍之厚 度。 1 8 ·如申請專利範圍第6項之方法,其中該奈米複合材料介 > 電結構之退火係在約30(TC至約500°C下實施達約30 秒至約1 2 0秒。 1 9 . 一種電容器,包括: 一下電極; 一奈米複合材料介電結構,其形成於該下電極上且包 括一氧化給(Hf〇2)層及一具有等於或大於該Hf〇2層之 介電常數的介電層,其中該Hf〇2層及該介電層係以奈 米複合之形式來混合;以及 一上電極,其形成於該奈米複合材料介電結構上。 -32- 1285942 v l 20. 如申請專利範圍第19項之電容器,其中該Hf〇2層及該 介電層係經由原子層沉積(ALD)法所形成。 21. 如申請專利範圍第20項之電容器,其中該奈米複合材 料介電結構,係藉由以奈米複合之形式,重複地沉積該 HfCh層與該介電層而獲得,每一層具有約lA至約5入 之厚度。 22. 如申請專利範圍第19項之電容器,其中該奈米複合材 料介電結構,具有約25人至約200人範圍之厚度。 > 23.如申請專利範圍第19項之電容器,其中該介電層包括 一選自Zr〇2、La2Ch及Ta2〇5所組成之群的材料。 24. 如申請專利範圍第23項之電容器,進一步包括一層氮 化矽層,該氮化矽層形成於該下極極與該奈米複合材料 介電結構之間。 25. 如申請專利範圍第23項之電容器,其中該下電極及該 上電極包括一選自氮化鈦(TiN)、釕(Ru)、氧化釕 (RuCh)、鉑(Pt)、銥(Ir)、氧化銥(lr〇2)以及摻雜有磷(p) & 或砷(A s)之複晶矽所組成之群的材料。 26. —種用以製造電容器之方法,包括: 形成一下電極; 形成一奈米複合材料介電結構,係藉由原子層沉積 (ALD)法在該下電極上實施,其中該奈米複合材料介電 結構係藉由以奈米複合之形式,混合一層氧化給(Hf〇2) 層及一具有等於或大於該HfO2之介電常數的介電層所 獲得; 實施退火處理以緻密化該奈米複合材料介電結構;以 -33- 1285942 υ * • 教 及 形成一上電極於該已退火奈米複合材料介電結構上。 27. 如申請專利範圍第26項之方法’其中該以奈米複合之 形式所成之介電層結構,係藉由該ALD方法,包括一 用以沉積該Hf〇2層之Hf〇2沉積週期’及一用以沉積該 介電層之介電層沉積週期,分別實施V及1z,次該沈積 週期。 28. 如申請專利範圍第27項之方法,其中該HfCh沉積週期 > 包括: 吸收Hf源; 清除該Hf源之未反應部分; 供應氧化劑以誘發與該吸收Hf源之反應,以便沉積 Hf〇2層;以及 清除該氧化劑之未反應部分及該反應之副產物。 29. 如申請專利範圍第28項之方法,其中該Hf〇2沉積週期 係在約100°C至約450°C之溫度範圍下及在約〇.丨托耳 | 至約1 0托耳之壓力範圍下實施。 3 0 ·如申請專利範圍第2 8項之方法,其中該H f源之吸收包 括: 蒸發該選自由 HfCl4、Hf(N〇〇4、Hf(NCH2C2H5)4 及 Hf(〇C2H5)4所組之群的Hf源;以及 供應該蒸發Hf源至一反應室中約〇·丨秒至約3秒, 其中使該反應室維持在約0 · 1托耳至約1 〇托耳之壓力 及約100°C至約45 0°C之基板溫度。 3 1.如申請專利範圍第2 8項之方法,其中該氧化劑之供應 128.5942 係藉由供應〇3或H2〇蒸氣約01秒至約3秒。 32·如申請專利範圍第28項之方法,其中該清除氧化劑之 未反應部份及該反應之副產物,係藉由使用氮氣(M2)或 一惰性氣體約0 · 1秒至約5秒。 33·如申請專利範圍第27項之方法,其中藉由該介電層沉 積週期所形成之介電層,包括一選自Zr〇2、La2〇3及 T a 2 0 5所組成之群的材料。 3 4 ·如申g靑專利範圍第3 3項之方法,其中該以所選擇材料 , Zr〇2爲主之介電層,係藉由使用一選自 Zr(N(CH3)(C2H〇)4(TEMAZ)及 Zr(N(C2H5)2)4(TDEAZ)之 銷(Zr)源所形成。 3 5 ·如申請專利範圍第3 3項之方法’其中該以所選擇材料 La2〇3爲主之介電層,係藉由使用一選自La(TMHD)3、 La(iPrCp)3、La(TMHD)3tetraglyme、La(TMHD)3tetraen 及La(TMHD)3diglyme之鑭(La)源所形成。 36.如申請專利範圍第33項之方法,其中該以所選擇材料 p Ta2〇5爲主之介電層,係藉由使用五氧化二鉬之鉬源所 形成。 3 7 ·如申請專利範圍第2 7項之方法,其中· y'對· z ·之比率係 在約1 ·· 1 0與約1 0 : 1間之範圍內。 . 3 8·如申請專利範圍第26項之方法,其中該Hf〇2層及介電 層係藉由重複地沉積每一層每一沉積週期約1人至約5 A厚,以奈米複合之形式,來混合該HfCh層及該介電 層,以便該奈米複合材料介電結構具有約 25A至約 200A範圍之厚度。 -35- 12 物 42 ft 11 3 9 ·如申請專利範圍第2 6項之方法,其中在約該奈米複合 材料介電結構之退火係在3 00°C至約50CTC下實施約30 秒至約1 2 0秒。 4 0 ·如申請專利範圍第2 6項之方法,其中該下電極包括一 選自氮化鈦(TiN)、釕(Ru)、氧化釕(RuO〇、鉛(Pt)、銥 (1〇、氧化銥(Ir〇2)以及摻雜有磷(p)或砷(As)的複晶矽所 組成之群的材料。 4 1 ·如申請專利範圍第40項之方法,進一步包括一層氮化 | 矽層,該氮化矽層形成於該下極極與該奈米複合材料介 電結構之間。 42.如申請專利範圍第41項之方法,其中該氮化矽層係藉 由在一氨氣(NH3)環境中約800°C至約l,〇〇〇°C下,對該 下電極實施一快速熱處理(RTP)約10秒至約120秒。 vS1285942 • , k X. Patent application scope: I—The dielectric structure of a capacitor, including: —layer oxide (HfCh) layer; and layer dielectric layer 'mainly having dielectric equal to or greater than the Hf〇2 layer a constant material, wherein the dielectric structure comprises a nanocomposite dielectric structure, the nanocomposite dielectric structure is mixed with the dielectric layer by a nanocomposite form Got it. 2. The dielectric structure of claim 3, wherein the dielectric layer has a dielectric constant ranging from about 25 to about 3 Å and a band gap energy level ranging from about 4 · 3 to about 7.8. 3. The dielectric structure of claim 3, wherein the dielectric layer comprises a material selected from the group consisting of Zr〇2, La2〇3, and 1^2〇5. 4. The dielectric structure of claim 2, wherein the nanocomposite dielectric structure is obtained by mixing the Hf〇2 layer and the dielectric layer in the form of a nanocomposite, each layer It is formed by an atomic layer deposition (ALD) method and has a thickness of about 丨A to about 5 people per deposition period. g. The dielectric structure of claim 4, wherein the nanocomposite dielectric structure has a thickness of from about 25 A to about 2 Å Å. 6 - A method for fabricating a dielectric structure of a capacitor, comprising: forming a dielectric layer of a nanocomposite, by performing an atomic layer deposition (ALD)-method, repeatedly performing 1 y 1 and subsequent oxidation respectively ( Hf〇2) deposition period and dielectric layer deposition period, in a nanocomposite manner, mixed oxidation (Hf〇2) layer and dielectric layer; and annealing treatment to densify the nanocomposite dielectric structure . 7. The method of claim 6, wherein the Hf〇2 deposition period package -30-1285942 ί I comprises: absorbing a feed (Hf) source; removing an unreacted portion of the Hf source; supplying an oxidant to induce The reaction of absorbing the Hf source to deposit the Hf 2 layer; and removing the unreacted portion of the oxidant and by-products of the reaction. 8. The method of claim 7, wherein the Hf〇2 layer deposition is performed at a temperature ranging from about 10 (TC to about 450 ° C and at about 0.1 > torr to about The method of claim 7, wherein the absorption of the Hf source comprises: evaporating the selected from the group consisting of HfCh, Hf(N〇3)4, Hf ( a Hf source of the group consisting of NCH2C2H5)4 and Hf(〇C2H5)4; and supplying the source of the evaporated Hf to a reaction chamber for about 1 second to about 3 seconds, wherein the reaction chamber is maintained at about 0.1 Torr to a pressure of about 10 Torr and a substrate temperature of about 100 ° C to about 45 ° C. 1 0. The method of claim 7, wherein the oxidant is supplied by Ch or The H2 〇 vapor is from about 0.1 second to about 3 seconds. The method of claim 7, wherein the unreacted portion of the oxidizing agent and the by-product of the reaction are by using nitrogen (N2) or a The inert gas is from about 0.1 second to about 5 seconds. The method of claim 6, wherein the dielectric layer comprises a composition selected from the group consisting of Zr〇2, La2〇3, and Ta2〇5. The material of one of the groups. 1 3. The method of claim 12, wherein the dielectric layer is selected from the group consisting of Zr〇2, by using one selected from Zr (N(CH3) (C2H5)) 4 (TEMAZ) and Zr(N(C2H5)2)4 (TDEAZ) of 1,295,942 t pin (formed by the source of the product. 1 4. The method of claim 2, wherein The dielectric layer, which is selected from La2〇3, is selected from the group consisting of La(TMHD)3, La(iPrCp)3, La(TMHD)3tetraglyme, La(TMHD)3tetraen and La(TMHD). Formed by the source of 3 diglyme (La). 1 5 · The method of claim 12, wherein the dielectric layer is selected from the group consisting of Ta2〇5, which is obtained by using molybdenum pentoxide. Formed by the source. | 1 6 · As in the method of claim 6, wherein the ratio of y ' to Y is in the range of about 1:10 to about 10: 1. i 7. If applying for a patent The method of claim 6, wherein the HfCh layer and the dielectric layer are in a nanocomposite form by repeatedly depositing the Hf〇2 layer and the dielectric layer for each deposition period to about 1 A to about 5 A thick. In order to make the nano composite The dielectric structure has a thickness ranging from about 25 to about 200 A. The method of claim 6, wherein the nanocomposite dielectric > electrical structure is annealed at about 30 (TC to about 500) It is carried out at ° C for about 30 seconds to about 120 seconds. A capacitor comprising: a lower electrode; a nanocomposite dielectric structure formed on the lower electrode and comprising an oxidized (Hf 〇 2) layer and a layer equal to or greater than the Hf 〇 2 layer a dielectric constant dielectric layer, wherein the Hf〇2 layer and the dielectric layer are mixed in a nanocomposite form; and an upper electrode formed on the nanocomposite dielectric structure. 20. The capacitor of claim 19, wherein the Hf 2 layer and the dielectric layer are formed by an atomic layer deposition (ALD) method. 21. The capacitor of claim 20, wherein the nanocomposite dielectric structure is obtained by repeatedly depositing the HfCh layer and the dielectric layer in the form of a nanocomposite, each layer having about lA to about 5 thickness. 22. The capacitor of claim 19, wherein the nanocomposite dielectric structure has a thickness ranging from about 25 to about 200. The capacitor of claim 19, wherein the dielectric layer comprises a material selected from the group consisting of Zr〇2, La2Ch, and Ta2〇5. 24. The capacitor of claim 23, further comprising a layer of ruthenium nitride, the tantalum nitride layer being formed between the lower pole and the nanocomposite dielectric structure. 25. The capacitor of claim 23, wherein the lower electrode and the upper electrode comprise a titanium oxide (TiN), ruthenium (Ru), ruthenium oxide (RuCh), platinum (Pt), iridium (Ir) ), a material consisting of yttrium oxide (lr〇2) and a group of polycrystalline germanium doped with phosphorus (p) & or arsenic (A s). 26. A method for fabricating a capacitor, comprising: forming a lower electrode; forming a nanocomposite dielectric structure implemented on the lower electrode by atomic layer deposition (ALD), wherein the nanocomposite The dielectric structure is obtained by mixing a layer of oxidized (Hf〇2) layer and a dielectric layer having a dielectric constant equal to or greater than the HfO2 in the form of a nanocomposite; performing an annealing treatment to densify the naphthalene Rice composite dielectric structure; -33- 1285942 υ * • Teach and form an upper electrode on the dielectric structure of the annealed nanocomposite. 27. The method of claim 26, wherein the dielectric layer structure in the form of a nanocomposite comprises a deposition of Hf〇2 deposited on the Hf〇2 layer by the ALD method. The period 'and a dielectric layer deposition period for depositing the dielectric layer are respectively performed at V and 1 z, respectively, and the deposition period. 28. The method of claim 27, wherein the HfCh deposition cycle> comprises: absorbing an Hf source; removing an unreacted portion of the Hf source; supplying an oxidant to induce a reaction with the absorbing Hf source to deposit Hf〇 2 layers; and removing unreacted portions of the oxidant and by-products of the reaction. 29. The method of claim 28, wherein the Hf〇2 deposition cycle is at a temperature ranging from about 100 ° C to about 450 ° C and at about 〇 丨 Torr | to about 10 Torr Implemented under pressure. 3. The method of claim 28, wherein the absorption of the Hf source comprises: evaporating the group selected from the group consisting of HfCl4, Hf (N〇〇4, Hf(NCH2C2H5)4, and Hf(〇C2H5)4 a group of Hf sources; and supplying the evaporated Hf source to a reaction chamber for about 〇·丨 seconds to about 3 seconds, wherein the reaction chamber is maintained at a pressure of from about 0. 1 Torr to about 1 Torr. A substrate temperature of from 100 ° C to about 45 ° C. 3 1. The method of claim 28, wherein the supply of the oxidant 128.5942 is by supplying 〇3 or H2 〇 vapor for about 01 seconds to about 3 seconds. 32. The method of claim 28, wherein the unreacted portion of the scavenging oxidant and the by-product of the reaction are by using nitrogen (M2) or an inert gas for about 0.1 second to about 5 seconds. 33. The method of claim 27, wherein the dielectric layer formed by the dielectric layer deposition period comprises a group selected from the group consisting of Zr〇2, La2〇3, and T a 2 0 5 3 4 · The method of the third paragraph of the patent scope of the application, wherein the selected material, Zr〇2 is the dielectric layer, by using Formed from a source of Zr (N(CH3)(C2H〇)4 (TEMAZ) and Zr(N(C2H5)2)4 (TDEAZ) pin (Zr). 3 5 · As claimed in Article 3 3 Method 'The dielectric layer mainly composed of the selected material La2〇3 is obtained by using one selected from the group consisting of La(TMHD)3, La(iPrCp)3, La(TMHD)3tetraglyme, La(TMHD)3tetraen and La (TMHD) formed by the source of (3) of 3diglyme. 36. The method of claim 33, wherein the dielectric layer selected from the selected material p Ta2 〇 5 is used by using molybdenum pentoxide. The molybdenum source is formed. 3 7 · The method of claim 27, wherein the ratio of y 'to · z · is in the range of about 1 · · 1 0 and about 10 : 1 . The method of claim 26, wherein the Hf 2 layer and the dielectric layer are in the form of a nanocomposite by repeatedly depositing each layer for each deposition period of about 1 to about 5 A thick. And mixing the HfCh layer and the dielectric layer such that the nanocomposite dielectric structure has a thickness ranging from about 25 A to about 200 A. -35 - 12 of 42 ft 11 3 9 · as claimed in claim 26 Method, wherein The annealing of the dielectric structure of the nanocomposite is performed at 300 ° C to about 50 CTC for about 30 seconds to about 120 seconds. 4 0. The method of claim 26, wherein the lower electrode Including one selected from the group consisting of titanium nitride (TiN), ruthenium (Ru), ruthenium oxide (RuO〇, lead (Pt), ruthenium (1〇, iridium oxide (Ir〇2), and doped with phosphorus (p) or arsenic ( As) The material of the group consisting of polycrystalline germanium. 4 1 The method of claim 40, further comprising a layer of nitrided germanium, the tantalum nitride layer being formed between the lower pole and the nanocomposite dielectric structure. 42. The method of claim 41, wherein the tantalum nitride layer is applied to the lower electrode by an atmosphere of about 800 ° C to about 1 ° C in an ammonia (NH 3 ) environment. A rapid thermal process (RTP) is from about 10 seconds to about 120 seconds. vS -36--36-
TW094146965A 2005-04-30 2005-12-28 Capacitor with nano-composite dielectric structure and method for fabricating the same TWI285942B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050036529A KR100716652B1 (en) 2005-04-30 2005-04-30 Capacitor with nano-composite dielectric and method for manufacturing the same

Publications (2)

Publication Number Publication Date
TW200638514A TW200638514A (en) 2006-11-01
TWI285942B true TWI285942B (en) 2007-08-21

Family

ID=37085185

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094146965A TWI285942B (en) 2005-04-30 2005-12-28 Capacitor with nano-composite dielectric structure and method for fabricating the same

Country Status (5)

Country Link
JP (1) JP2006310754A (en)
KR (1) KR100716652B1 (en)
CN (1) CN100481461C (en)
DE (1) DE102005062964A1 (en)
TW (1) TWI285942B (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100805018B1 (en) * 2007-03-23 2008-02-20 주식회사 하이닉스반도체 Method of manufacturing in semiconductor device
KR20080093624A (en) 2007-04-17 2008-10-22 삼성전자주식회사 Multiple dielectric film for semiconductor device and method for fabricating the same
FI122009B (en) * 2007-06-08 2011-07-15 Teknologian Tutkimuskeskus Vtt Structures based on nanoparticles and process for their preparation
KR20150139628A (en) * 2007-09-14 2015-12-11 시그마 알드리치 컴퍼니 엘엘씨 Methods of preparing thin films by atomic layer deposition using hafnium and zirconium-based precursors
JP5221089B2 (en) * 2007-09-19 2013-06-26 東京エレクトロン株式会社 Film forming method, film forming apparatus, and storage medium
KR101451716B1 (en) 2008-08-11 2014-10-16 도쿄엘렉트론가부시키가이샤 Film forming method and film forming apparatus
US7820506B2 (en) * 2008-10-15 2010-10-26 Micron Technology, Inc. Capacitors, dielectric structures, and methods of forming dielectric structures
JP5693348B2 (en) 2010-05-28 2015-04-01 東京エレクトロン株式会社 Film forming method and film forming apparatus
JP5675458B2 (en) 2011-03-25 2015-02-25 東京エレクトロン株式会社 Film forming method, film forming apparatus, and storage medium
US8760845B2 (en) * 2012-02-10 2014-06-24 Nanya Technology Corp. Capacitor dielectric comprising silicon-doped zirconium oxide and capacitor using the same
KR101799146B1 (en) * 2012-04-05 2017-11-17 도쿄엘렉트론가부시키가이샤 Semiconductor device manufacturing method and substrate treatment system
JP6017361B2 (en) 2013-03-29 2016-10-26 東京エレクトロン株式会社 Film forming method and film forming apparatus
KR101632496B1 (en) * 2014-09-30 2016-06-21 서울대학교산학협력단 Energy storage capacitor, method of fabricating the same, and power electronics having the same
CN110098065A (en) * 2019-04-28 2019-08-06 复旦大学 A kind of double silicon wafer base solid state super capacitors and preparation method thereof
US20230326751A1 (en) * 2020-08-19 2023-10-12 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of metal oxide
TW202210653A (en) * 2020-09-07 2022-03-16 日商半導體能源研究所股份有限公司 Metal oxide film, semiconductor device, and manufacturing method therefor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420279B1 (en) * 2001-06-28 2002-07-16 Sharp Laboratories Of America, Inc. Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate
US6875678B2 (en) * 2002-09-10 2005-04-05 Samsung Electronics Co., Ltd. Post thermal treatment methods of forming high dielectric layers in integrated circuit devices
KR100555543B1 (en) * 2003-06-24 2006-03-03 삼성전자주식회사 Method for forming high dielectric layer by atomic layer deposition and method for manufacturing capacitor having the layer
KR20050002027A (en) * 2003-06-30 2005-01-07 주식회사 하이닉스반도체 Capacitor with double dielectric layer and method for fabricating the same
KR20050029427A (en) * 2003-09-22 2005-03-28 삼성전자주식회사 A fabrication method of a semiconductor capacitor having a diffusion-preventing layer

Also Published As

Publication number Publication date
CN1855500A (en) 2006-11-01
JP2006310754A (en) 2006-11-09
TW200638514A (en) 2006-11-01
KR100716652B1 (en) 2007-05-09
CN100481461C (en) 2009-04-22
KR20060113249A (en) 2006-11-02
DE102005062964A1 (en) 2006-11-02

Similar Documents

Publication Publication Date Title
TWI285942B (en) Capacitor with nano-composite dielectric structure and method for fabricating the same
TWI312196B (en) Capacitor with nano-composite dielectric layer and method for fabricating the same
TWI338331B (en) Method for forming tetragonal zirconium oxide layer and method for fabricating capacitor having the same
TWI322487B (en) Method for fabricating capacitor in semiconductor device
KR100555543B1 (en) Method for forming high dielectric layer by atomic layer deposition and method for manufacturing capacitor having the layer
CN1790674B (en) Capacitor with zirconium oxide and method for fabricating the same
US7888726B2 (en) Capacitor for semiconductor device
KR100640654B1 (en) Method of forming zro2 thin film using plasma enhanced atomic layer deposition and method of manufacturing capacitor of semiconductor memory device having the thin film
US8679939B2 (en) Manufacturable high-k DRAM MIM capacitor structure
US8092862B2 (en) Method for forming dielectric film and method for forming capacitor in semiconductor device using the same
TW200427858A (en) Atomic layer deposition of high k dielectric films
EP2434531B1 (en) Method for manufacturing of a metal-insulator-metal capacitor
JP2005159271A (en) Capacitor and its manufacturing method
US8828836B2 (en) Method for fabricating a DRAM capacitor
JP5883263B2 (en) Method for producing metal-insulator-metal capacitor used in semiconductor device
US20070099379A1 (en) Method of manufacturing a dielectric film in a capacitor
TW201212122A (en) A high-k dielectric material and methods of forming the high-k dielectric material
KR100968427B1 (en) Doped insulator in capacitor and method for fabrication of the same
US8563392B2 (en) Method of forming an ALD material
JP2001036045A (en) Capacitor of semiconductor memory device and manufacture thereof
KR101060740B1 (en) Capacitor comprising a dielectric film containing strontium and titanium and a method of manufacturing the same
KR101116166B1 (en) Capacitor for semiconductor device and method of fabricating the same
KR20110103534A (en) Methods of forming an dielectric layer structure, methods of manufacturing a capacitor using the same and capacitors
TW201044426A (en) Capacitor and process for manufacturing capacitor
KR100844956B1 (en) Capacitor with zrconium oxide and niobium oxide and method for manufacturing the same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees