TWI285841B - Branch target buffer, branch target buffer memory array, branch prediction unit and processor with a function of branch instruction predictions - Google Patents

Abstract

A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line gating value derived from branch history data related to the instruction. Additionally, a branch prediction unit and a processor incorporating the BTB are disclosed, along with methods for operating the BTB.

Description

I2858417p, doc function step or stage. Each processing phase completes its elemental operations in a single clock cycle. The non-pipelined (n〇n-Pipeiined) processor starts the processing of each instruction after the completion of the processing of each instruction. Unlike the non-pipelined processor, the pipeline is used in different processing stages of the pipeline. (5) Calling the secret instructions. The pipeline stage can be arbitrarily-designed by the designer but generally includes the following: the instruction acquisition phase, the ^decoding phase, the instruction execution phase, and the execution resolution phase. The fetch phase looks for a finger from anywhere where the instruction is currently stored (such as a primary memory or an instruction column)—v 一 one or more operations specified by the 日 日. (::=rr usually involves the execution of this instruction and generates a dual-use ΐ) 'Write----------------------------------------------------------------------------------------------------------------------------------------------------------------------- Step ^ goes to the next stage. Thus, in the first acquisition phase, the hardware register is obtained from the storage, and the solution is solved by y. In the relevant association, invite this to take a second instruction, and arrange it in the 'Ha's section, this instruction starts-execute operation 6 1285841 17007pif.doc such as: a logical, mathematical, address, Or the operation of the index), = the timer instruction decoder stage decodes the second instruction, and this refers to the acquisition - the third instruction. The pipeline operation is known to continue. Knife White # Again, in the 14-type mode, the overall processor of this processor is higher than the non-pipeline ___ county. The object's speed's ultra-quantitative architecture can simultaneously process and/or perform two or more executions (or - fresh eight = s, simultaneously and independently into the "". & 篁 (Scalar) system in each Only one non-St instruction can execute an instruction formed in a string of pipelines, or the instruction of this instruction is executed. The simultaneous execution of multiple instructions advances the performance of a processor. The work of the game has undoubtedly provided the performance benefits, as long as the beta, " sequence is held at 8 degrees, or can be deleted. But the unfortunate part of the touch paste contains (four) can be transferred to the _ order execution path "Orders, so-called, branch instructions, (including such as: jump, return, with 2 branch instructions, etc.), produce significant performance in the pipeline processor ^ unless a valid branch prediction can be implemented When a = pre/th (or erroneously predicted) branch instruction causes a departure from such an instruction 歹J, ie, the instruction sequence from the current pipeline in this processor = performance loss occurs. Loss occurred, current The sequence of pipe instructions must be thrown away, flushed, (fluShed), and a new sequence must be loaded into the pipeline. The flushing operation of the pipeline wastes a very large clock cycle and usually reduces processing. The execution speed of the device. 7 1285841 17007pif.doc ,: The method of evaluating the execution performance associated with a branch instruction is to predict the result of the branch instruction and insert a predicted instruction into the pipeline to directly follow the branch instruction. The latter. If ^ ' = implementation in 'this is related to the performance of the pipeline flushing, if the results of this branch instruction are incorrectly predicted, the traditional techniques and analysis have confirmed that many branches are correct. Predicted, this has - very high certainty - nearly 80% certainty for one-to-one applications. Therefore, the traditional types of several branch prediction mechanisms have been developed ^ one of the types of prediction mechanisms 'is The branch-target buffer is used to store a large number of data items, each of which is associated with a branch = so that the branch target buffer stores a lot of , ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The target address is over address), the ^ instruction opcode (〇pc〇de), branch history information, and other information can be used. In the processor that utilizes the - branch target buffer, this knife prediction mechanism monitors Each instruction that enters the pipeline. The address of the general command is monitored, and when the instruction address matches an entry of the second, the instruction is recognized as a branch instruction. From the relevant branch history information, The branch prediction mechanism determines whether the branch will be executed. The branch history information is generally determined by a state machine (state maehin^^, which monitors the branch instructions of each index in the branch target buffer and defines Information stored as branch history information, this resource 8 1285841 17007pif.doc relates to whether this branch was executed in the previous operation. When this branch history indicates that the branch is likely to be executed, one or more predicted instructions are inserted into the pipeline. By convention, the data entry for each branch target buffer includes the instruction opcode associated with the branch instruction, which is the arbitrage being evaluated for its branch history. This opcode can be inserted directly into this pipeline after it is properly indicated by this branch prediction mechanism. Similarly, the data entry for each ^ object buffer, including one, the destination address, is associated with the branch instruction being evaluated. In addition, after the appropriate mechanism is specified, the target appears to be output by the branch prediction unit as a tool address, and is used to obtain the processing of the branch instruction and its subsequent instructions in the sequence of instructions. This pipeline, 曰 ^ 1 7 , Lang in the execution phase of this point (four) let t stop /, there is a point in the court, the branch predicted that the gamma is the correct age of this branch, = 77. Execution of the device, intermittent continuous.] = This 3 theory: Fruit:: Not correctly predicted 'The pipeline is ί, first:: The order must be washed away. The double-digit command will be 9 1285841 17007pif.doc box, si = description - traditional branch target buffer 11 1, which is connected to the branch and associated hardware. Branch target buffer 'binary 解码 decode 23, - record array 4, and - sense amplifier

Shanghai namp hfier) 5. The address decoder 3 receives a binary address from an instruction fetch unit and selects the word line associated with the decoded instruction address. Word reading selection is routine, but it usually involves applying the force-character line voltage to the selected word line. The batch word line is stretched from the address decoder 3 to the memory array 4 in a column by column manner. The S memory array 4 includes a plurality of memory cells, each of which stores at least a data bit. The data items, each of which includes a plurality of (four) bits, are stored in a <and column by column, whereby - the selection of a particular word line, substantially access - the corresponding data item. The data entry includes at least a data field ‘which defines a branch address label and a further data field that defines a target address. The data items selected by one word line are conventionally output from the memory array 4 via the sense amplifier 5. From the sense amplifier 5, the branch address tag is passed to a tag compare register 6, which also receives the address of the instruction. The target address from a amplifying ^§ 5, along with an address associated with a non-branched instruction sequence (eg, a program count value (PC) + 4 of a 32-bit instruction word processor), It is communicated to the multiplexer 7. One of the two inputs of the multiplexer is selected and communicated to this instruction 4 column (shown here as a program multiplexer 8), this communication is through such an operation , that is, a logic gate 9 receives the result from the tag comparison register 6 and the logical walk/no take away from the branch prediction I28584107pifdoc. - The branch target buffer 11 in this system suffers from many disadvantages. Two-body it: In the remaining configuration, the branch target buffer is broken by each branch instruction access, regardless of the possible result of the instruction. Access to the knife target buffer, a READ drop For example, m melon involves a traditional reading of nm/, the word line from the address decoding series. €_takes electric energy to provide memory energy and ❿ 出° out of the shell material' where these memory cells and selected words The it line is associated with ',, 'L should be wasted'. Other traditional branch target buffers have been integrated into the design of this memory array. US Patent No. Νο· 574〇417 is an example. Here The branch target buffer of the present invention includes a consistent energy line that activates or closes the character spool H, which is associated with the memory array during the read operation. These word line drivers are activated or deactivated according to the status of the "take/take away" flag, which predicts whether a particular instruction is likely to be executed. For example, when a specific command, go/no take, the mark indicates one, and the strong does not take away, the shape of the second enable line transitions to a forbidden level, thereby making the memory line driver Lost ability. Unfortunately, this traditional approach saves power during branch target buffer access operations and also introduces significant overhead. That is, the branch prediction mechanism generates this signal, which requires not only time ^ resources, but pre-decode this instruction, and then determines its branch history data and take/take away status. Then, and if necessary, change the level of the two I2858iUc signals. As the speed of instruction execution and the depth of the instruction pipeline increase, the accuracy and speed of the branch become more and more important. Based on the understanding of this importance. 'Many traditional processors incorporate an extended pre-decoding scheme whereby all instructions are evaluated, branch instructions are identified, and branch history is looked up' or for branch instructions being evaluated and pre-decoded, This point, the calendar 5 information is dynamically calculated. Needless to say, this method of predicting the behavior of the instruction requires a lot of time and a lot of extra resources. Column, reason, extra delay and complexity, in - Branch prediction (4) 疋 undesired characteristics. However, 'this is exactly what many traditional methods provide. The problem of power consumption further makes the design win and lose. Not surprising _ Contemporary processors are all on the top, that is, they are characterized by strict computer and rehearsal for power consumption, such as mobile phones and personal digital assisted minimum thunder & some of the devices are ready-made examples, which integrate processors that prefer to consume the least amount of power. $型的述# This branch target buffer 11 is a high-reliance memory class: the illusion may store a lot of data items. Therefore, this branch has a memory _ and is suitable for a volatile £5M (v〇latlieme y) _ A lot of money is the secret of the electric y, some desire to make every access to this branch target buffer, means that this 12 branch 46088581 17007pif.doc target balancer a "read" operation of the memory array. Everyone agrees that the branch target buffer access is increasing, and some estimates are made about the memory array of this branch target buffer, read, Operation, accounting for 10% of the power consumption of traditional processors.

Obviously, it is necessary to implement a branch prediction mechanism in a better way in the emerging processor. Traditional methods require long, immediate evaluation of branch instructions, and/or slow search or calculation of branch history kinetic energy. In addition, the power consumption caused by the uninterrupted, but necessary, access to the memory array of the branch target buffer in Xu (f)f is completely wasted. . < SUMMARY OF THE INVENTION In the present invention - an embodiment provides a branch target buffer memory column comprising - word lines and - associated word line electrification circuits). The word read strobe circuit includes a body circuit, g word line strobe value. >, the memory of this memory array is better suited for storage and the character line phase = electrical selection circuit in addition to the storage of a word line strobe: 5 忆 体 电路 ' ' ' ' ' Tongluo = 4] In the example, the word line strobe circuit responds - the word ^ pressure is the applied word line and the character _ _ _ ^ this ^ can be used to save the item data ^ Thus the wait operation, its response in this branch 7:: two == can; yes - write this access operation or - read operation, = connect (four) - write signal, memory array. , ', the key involved in this word line 13 1285841 17007pif.doc ί 记 车 车 ' ' ' ' ' ' ' 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜 适宜The circuit includes a one-bit static-related specific example of the logic gate that receives the character and includes the value as its input, thereby generating a stored word line strobe including an m_, s generates a first burst output, the strobe logic $ is used as a gate, which receives the first logic output and writes the signal as its output - the second logic signal. Also provided is a memory array of the branch target buffer, which includes a factory circuit, which is turned over to the word line strobe value, and the word line strobe circuit further includes a strobe logic circuit. The receive-write signal and the word strobe value are input as input, thereby making it possible to access the data item during the write operation in the case of the write-reduction-positive identification. When the word line strobe value indicates a positive identification, it is known to allow conditional access to the data during the first reading operation: chrome tanning. Storing a data item and outputting a memory array of the target buffer in response to a read operation, which is suitable for including a word line circuit, which allows the write operation process to allow access This tribute entry, and in response to the word-meeting pass value stored in the word line gating circuit, makes the read operation too expensive, allowing conditional access to the negative item. In an example, the embodiment of the word line strobe circuit entry 0 I2858iW, 〇c memory array can be easily combined with the - branch target buffer: for example, 'another embodiment of the present invention, Provider = two, a branch target buffer of the memory array, the word line of the memory array is turned on. Each of the gated word lines is suitable for including a selection, and further includes a word line selection a pass circuit comprising a memory circuit with a strobe line strobe value, each word line having a gate ^^ having a word line portion of the strobe gate. The branch target buffer is usually and if decoded β , its receive-instruction, and respond to this instruction address some of the idle word lines - The branch target buffer is stopped and closed. It is suitable for reading from the selected (four) word line to receive the instruction address of the decoded H towel. (4) In the sub-invention, the sense amplifier includes such a line, in which the ν = sub-reading value transfer axis is in each of the memory circuits, and the gates are read, and the readout is amplified: the gate: the line' Passing a write signal to the respective word line strobe circuit associated with the ram read. - An embodiment of the branch target buffer, eight, including branch prediction logic, for: : ::::: This: The heart of this branch target buffer is suitable for the word line including the gate of the gate - each word line with a gate;: 1 =: 15

The I2858iU also includes a word line strobe circuit, and the word line strobe circuit includes a memory circuit that stores a word line strobe value, which is worth from the branch history data. In a related specific example, the branch history unit includes a state machine that determines the branch history data for the instruction in accordance with a previous branch execution history of an instruction. According to the present invention, another embodiment of the branch prediction unit includes a branch history unit for storing branch history data, and this embodiment further includes a branch target buffer including a plurality of word lines having gates. Each gated word line is accessed via a word line strobe circuit, wherein the branch target buffer outputs a data entry in response to receiving an instruction portion of the branch target buffer, the branch The target buffer also outputs a word line strobe value, which is worth from this branch history data. In accordance with the present invention, an embodiment of the branch prediction unit can be easily integrated into a processor. For example, the processor includes an instruction fetching unit for receiving an instruction and providing a corresponding instruction address, the processor further comprising a branch prediction unit that receives the instruction address and provides a predicted address to The instruction fetch unit further includes an instruction decoder/T line unit for receiving the instruction and providing a decoded instruction and providing an updated address in response to the decoded instruction. In a specific example, the branch prediction unit t integrated into the processor includes a branch history unit for storing branch history data, and the branch prediction unit further includes branch prediction logic for receiving The instruction address and the updated address, thereby providing the predicted address, and the 1285841 17007pif.doc history data, the branch prediction unit further includes - branch I ° eight for receiving the instruction address and Output entry data. The sub-target buffer is adapted to include the memory as explained in the above embodiment. The present invention can be easily applied to the processing of super-quantization, and the =exe/execution unit includes a -batch execution path, each path ^previously decoding H And execution unit. The ultra-quantization processing (4) is not limited to these, ... processor and g instruction-muitiple-data (SIMD) processors. Yes - provides a variety of methods. - A preferred method is to perform a read operation on a ten-character word line, the word line being in a sequence. The method includes storing a word line strobe in the squall line strobe circuit with the closed I gastric splicing, such that the word _ pass value is enabled to conditionally permit the read operation. In a related embodiment, the method further includes: receiving an instruction portion of the branch, and selecting the commanded word in response to the instruction portion, and applying the selected word line on the selected gate. A word line is firmly responsive to the word voltage and the word line strobe value, and conditionally allows this read operation. In another related embodiment, the method further includes: defining a branch history data of the & 7 portion, and obtaining the word line strobe value from the branch history data. Coincidentally, in another related embodiment, the method further includes: rotating a data item from the branch, and responding to an allowed reading operation 17 1285841 17007pif.d〇c In still another embodiment, a method of operating-branching benefits is provided, as described above. This method is suitable for two instructions, each instruction in the instruction, in the batch of one of the gate word lines, stores a corresponding data item, and, in this character = A, 'storage- Corresponding character line strobe value, this word line is strobed by Ray 3

One of them is related. After receiving the current instruction from this = ^, the branch target buffer has condition 2 outputting a data entry corresponding to the current instruction, and the output is performed from such an eight-object buffer, that is, it relates to the corresponding storage. Character line 甬 In a related embodiment, conditionally outputting the data entry further includes selecting a word line of the = gate from the batch of word lines associated with the current instruction. The selected gated word line applies a word line voltage, and the associated word line strobe circuit is used to gate the word line voltage to respond to the stored word line strobe value. At least one word line strobe value will be updated after this instruction is executed. In still another embodiment, the present invention provides a method of operating a branch prediction unit. The method is adapted to include a branch history unit, wherein the instruction stores the branch history data, and obtains a word line strobe value from the branch history data, the method further comprising storing a data item, and the data item relates to The instruction in the branch target buffer memory array, wherein the data entry is accessed in the branch target buffer via a gated word line, and the method is further included in a word line gating circuit Storing a word line 1285841 17007 pif.doc strobe value, and the word line strobe circuit is associated with the gated word line, this method conditionally allows memory arrays from the branch target buffer This data entry is output in response to this instruction received in this branch prediction unit, as well as the word line strobe value involved in this storage. In a related embodiment, the method further includes updating the branch history data and corresponding word line strobe values after each instruction is executed: for the above and other objects, features and advantages of the present invention. It is to be understood that the preferred embodiments are described in detail below, and in conjunction with the drawings, the details are as follows. The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims. The scope of the invention is defined by the scope of the appended claims. In a typical application, embodiments of the present invention provide a branching target buffer 'so that the processor has lower power consumption during execution and operation' and improves the execution speed of branch instructions, and also reduces the overall The complexity. In one aspect, the consumption of power to the processor is reduced by conditionally preventing read operations on the branch target buffer. In a related aspect, the processing of branch instructions in this processor is free of delays caused by operations that require searching and/or computing branch history information. On the other hand, however, this processor benefits from the reduced complexity of the branch prediction unit of an infrastructure. The term "processor" broadly includes any digital logic device or system, 1285841 17007pif.doc which can execute or respond to a sequence of instructions. This term includes, for example, such as central processing units (CPUs), microprocessors, digital signal processors (DPSs), reduced instruction set computer processors, and single instructions. Single-instruction-multiple-data (SIMD) processor. The official line processor is particularly suitable for integration into a branch prediction unit designed in accordance with the teachings of the present invention. Accordingly, a multi-pipelined processor will be described as an example and described as a construction and application of the present invention, and thus some of the advantages provided by the present invention are described. Figure 2 illustrates the first exemplary pipelined processor at the level of one block diagram. The processor 10, via the busbar 14, employs any of the many conventional data transmission techniques, and (4) transmits or retrieves data from the face. Memory 12 assumes storage-or multiple software programs or programs: - Programs or package programs with -string instructions. Note that _12 also assumes that the disk is associated with the instruction sequence string. This information may include data stored by the processor, and/or stored by the processor 10 in memory. The instruction returns from the memory 12 to the processing of the piano #虚搜哭社山从, ° in response to the address from the 坆 processing state. The address of a single address can be reported as a program counter (program counter, which is a good and bad) technology. Through this program counter, the processor 1 indicates which memory location (ie memory address) is recorded. , (2) T-strips, as described above, indicate a simple method to look up instructions from memory, when - or more branches in the instruction refer to 2 20 1285841 17007pif .doc becomes very complicated, this branch refers to the eight-site, and in the other-conditions, it is pointed out that the next one is pointed out - the next one is especially correct. The next address. This is the green type. Referring to FIG. 2, the pipeline processing A, the element 13, the instruction acquisition unit 13 from the record: usually includes an instruction to acquire a predicted address (such as a program body. 12 receives an instruction (take), the fan acquisition unit 13 will This instruction raises the final value to the memory 丨 2. The commander 1S decodes the instruction, that is, usually modifies the solution 15. The instruction is decoded to an execution unit 17. The at least one operation code portion of the single ritual is executed ( Or the instruction part), this has been solved by the solution One or more operations of the horse's instruction. These operations initialize the execution unit - write back to the memory, and then the H (four) result data, that is, its === order solution: 15, the instruction acquisition unit includes - instruction bit Address Me 2: ^^ Unit 19° command part usually receives and receives - other information is included by the stick--^. The branch-predicting unit I9 3 determines the "down-address" and the command does know the order. The next lower-address of the sequence to be executed: the condition of this branch instruction is determined). Therefore, the branch prediction is fed to the branch prediction unit 19. Using this information, whether the lower-industry of the above-mentioned insured is actually-instructed to be located from the lower-address indicated by the execution unit 17, generally the lower-position indicated by the eight-digit 21-single 7017 The address 'and the previously predicted " timing (ie, a "hit" condition), the processor continues to forward 21 17007pif.doc 1285841 to process the instruction sequence of this pipeline. However, if the next address indicated does not match the previously predicted instruction address (ie, the -, hit miss condition), then 'this processor flushes the pipeline' and loads it into The instruction of the next address indication. The comparison of the instruction of the next address indication with the previously predicted instruction address is suitably performed in the branch prediction unit 19. In still other details as described below, the pipelined processor 10 A branch prediction unit 19 is also provided therein to thereby provide a predicted address to the instruction fetch unit 13. Before proceeding with a more detailed description of this preferred embodiment, it should be particularly noted that the invention is also particularly suitable for super Quantized processor. Figure 3 illustrates a greatly simplified hyper-quantitative processor. Here, memory 12 supplies instructions and/or data to the over-the-counter processor 11 via bus 14 as well. Unit 39 and instruction fetch unit 33, except that instruction fetch unit 33 provides instructions to multiple execution paths 34, 35, and %, typically operates as described above. Similarly, each execution path 34, 35 And 36 provides a bit address indication to branch prediction unit 39. In the example of the hyperquantization processor described herein, three execution paths are depicted, although this number is merely exemplary and is arbitrarily chosen. Each execution path is characterized by a combined decoder/execution unit that receives instructions from a common instruction fetch unit. The hardware and functional boundaries associated with the exemplary environment of the illustrated processor are completely It is a subject of a designer's conventional design. For example, the decoding and execution functions can be easily performed in a single part of the hardware (for example, an integrated circuit (1C)) or in multiple parts of the hardware, That is, the integrated circuit of the mutual 12 1285841 17007pif.doc. Decoding and / or execution can be performed by any combination of hardware, software, firmware or any of the three common platform types. Similarly, this instruction acquisition unit The hardware and functional boundaries between the instruction decoder unit and/or the branch pre-expo are merely illustrative in this embodiment. It is contemplated that in the context of the present invention There may be a lot of changes and refinements. • In the case of this integrated processing (fourth) type, the present invention is suitable for providing a branching material, which includes a certain type of branch deletion, some storage and branch instruction related information, And storage and/or calculation of some form of branch history data. The branch 4 also illustrates the branch prediction unit 19 of the graph in the form of a block diagram. In Figure 4, the branch prediction logic 2 provides a predicted address, which is at least Provided to the instruction fetch unit 。. The branch Logic thus, as such, causes the fetch unit η to receive the instruction address and typically communicates information with the branch target buffer benefit 22 and the branch history unit 24. These three functional modules are For the purpose of illustration, the invention is not limited to a hardware layer. (4) 70 pieces, a combination. For example, in the actual implementation of the present invention, the branch history unit 24 is _ (described below) The memory function can be combined with a memory array associated with the knife target buffer 22 or with a memory device associated with the branch prediction logic 20. Similarly, the computational functions associated with branch history unit 24 may be implemented using hardware or software resources provided by branch prediction logic. More precisely, the branch prediction logic 2 receives the heart portion from the instruction fetch unit 13, typically an instruction address (ie, the value of a current program counter 23 I28m_), and then predicts whether the processor should branch to and A target address associated with this instruction, or the next instruction in the sequence of instructions. The term "predict" generally refers to a logical or computed output produced by the branch prediction logic. The generation of this output relates to the received instruction address and to the received instruction address. Branch history information. Therefore, branch prediction logic 20 can contain many logical structure-specific combinations, computing power

控制器, data registers, comparison circuits, and/or similar hardware resources may be embedded in the controller software that is used to drive the hardware resources. As is currently appropriate, the branch prediction logic 2 provides a write (WRITE) signal to the branch directory buffer $22. This write signal controls a write operation in the branch directory buffer 22. This term, READ, WRITE, is generally used herein to describe the corresponding operations that are well known in the operation of conventional memory devices, such as - Static & Access memory (9) atic Random Access Memory, sram) and dynamic random access memory (Dynamic Random Aceess M DRAM) 这样 such a determination by the branch pre-simplification 20, that is, branching to this η = τ 冉 is one "take away" condition. The branch prediction logic 2〇 does not branch to the target address, but executes this instruction ^1, Luo 20 instructions, is called "not taken, condition." The condition that the branch pre-study data is taken or not taken is dependent on the branch address: the order of the second:: is the instruction bit received, and/or is at least the branch branch. The history unit 24 is responsible for computing and storing 24 I285m prediction logic 20 to provide branch history data. The information that the basin is useful (four) is the history of Bellow any such ^ between the conditions to choose its -. A large number of traditional performances have "had proposed" that they suggest to distinguish the calculation of such data; the law 1 indicates whether a branch instruction will be executed. The invention is easy to adopt the ^ ^ algorithm or method pair in these methodologies The behavior of the branch instruction provides the test: the storage and provision of the data of the march = history is suitable for the component of the sum (4) of the sum. Each branch in the branch stores the instruction corresponding to the branch of the data entry. Ϊ = in the history unit, the historical information of the branch that stores some form of branch is mentioned. The branch history data can be stored in the branch target buffer in the same way as the corresponding branch. It can be experimentally run by running a shirt containing the 'invention', and thus the actual branching frequency of the instruction is determined. Then the branch history # is stored in the branch history ^ Prepared for subsequent applications. As is currently appropriate, the initial branch history read, if any, is updated when necessary after each subsequent execution of this instruction. In this way, the temporary branching behavior is used to update the existing branch history data. Of course, the knife history negative material does not have to be determined in advance in some way, but can, in operation, "on-the- Fly) is generated in response to the actual instruction execution. Whenever it is determined and updated regardless of the method used, the branch history data can be easily determined using a state machine. The complexity and design of a competitive 25 I2858iUc state machine is a common design choice. However, as is currently appropriate, the present invention incorporates a 2-bit, up/down saturation counter as a discrete portion of branch history unit 24. The operation and application of this 2-bit, up/down saturation counter is illustrated in the flow chart of Figure 5. Here, a 2-bit branch history data value is incremented or decremented after execution of a branch instruction, which involves whether the instruction is actually taken or not taken during execution. This branch of historical data points out the extent to which this instruction is specific, taking away the situation. For example, a branch instruction that was not taken before, from one, strongly does not take away, the state changes to one, weak Do not take away, state. The change of this state is indicated by increasing the corresponding branch historical data value from "〇〇," to "〇1". One before, one, strongly remove, state, and the instruction, by reducing the corresponding branch historical data value, and changing to a, weakly taken away state, this - change is followed - after the execution cycle, in This shot, this finger is not taken. In the presently preferred embodiment, for most applications, 2 bits have been tolerated by S to be sufficient to predict whether an instruction will be taken away. However, this is not necessarily true for all applications, and some of them may require a larger number (such as more branch history data to make - accurate take/not take The decision to go. This 'this branch history=#material definition, as well as the calculation of the algorithm used to calculate the tribute, money / or implement this selection ς a definition of a state machine, is a design Choice., / , 26

1285841 17007pif.doc Figure 4 shows the branch target buffer, which is described by inflammation, . Here, the decoder 43 receives the finger and the indicated character, and the group of words r to the memory array 40. However, in this issue: There are two;:: quality, operation, and implementation have been changed. The term, sub-grant, is used in the following embodiments to describe the word lines contemplated by the present invention. The crypto-array array 4G is suitable for use with non-volatile (non.vGlatile) memory cells such as singular random access memory cells, but other forms of memory cells can also be used. Similar to a memory array of a conventional branch target buffer, the memory array of the present invention is adapted to store a batch of data entries, wherein each data entry corresponds to an instruction and is adapted to include a branch address label and A target address. In each data entry, there are also other types of data in the &lt;hetero association, but in general, some form of branch address tag and target address are required. A currently preferred word line with a gate is shown in FIG. A gated word line typically includes a combination of a word line 7 〇 and a word line select circuit 60. As shown in Figure 6, these word line gating circuits are adapted to be associated with a corresponding word line on a one-to-one basis. The word line gating circuits are adapted to be arranged in columns in the memory array 4A. This configuration allows for the respective word line strobe values stored in these word line strobe circuits, allowing for easy updating via conventional write techniques. In a preferred embodiment, the memory array 40 includes a static random access memory array 27 1285841 17007pif.doc ::=== including a memory circuit 'it is accessed by a single J month' heartbeat machine Formed by memory cells. This can be obtained from the actual configuration of the semaphore circuit, each word, the path is pressed, the -, the word line strobe value, and the L:, l = line-related instruction branch history data is obtained from the coarse .对 对—corresponding to the access of the word line, and the branch history department 八,, 疋#, each receiving the branch instruction line in the branch target buffer, the health-data entry, the package two =:: : and 1 2 are related to the received branch instruction part = 2: 43: The character line carried is an inter-word line, that is, the word line strobe value is controlled by this: the word element疋 From the branch history data related to this instruction. The 70-line strobe value of the 和 、 and 二 一 is a branch historical data suitable for obtaining. A preferred method of obtaining will be described in the context of a consistent embodiment. This is derived from the method is just an example. Xu = the same method can be relied on from this branch to obtain a word ^ line strobe value 1 These methods will be changed according to the following ovum, the nature of the historical data, for (4) the history of this branch The t-method of the data, the size of the sub-line strobe value (ie, the number of bits), and/or the structure of the word line gating circuit and the memory circuit 0 28 I28m_c as the basis of its construction, assumed to be taken in relation to FIG. Depicting the 2-bit branch history data, and taking a single bit memory circuit in one step, and this memory circuit is associated with each word line gating circuit, then simply by using this as a branch The most meaningful bit in the historical data, you can get a competent, word line strobe value. In this example, the logical value "1" of a most significant bit indicates that the instruction one, strongly removes the state of "or, weakly, away." The logical value of a most significant bit. ',〇,,, indicates the state of this instruction, the weak ^ does not take away or "strongly does not take away." By storing this bit to a single bit associated with the word line gating circuit Memory cell, then, this refers to the eight-take away condition - the indication of acceptable accuracy, is used to control the word line. = to ^ Figure 7, - uncheck the word line 7. And in the traditional 丄&gt;, a sub-twist voltage is applied to the word line 70. Generally speaking, this = the added word line voltage 'will increase across the word ^ = potential bit. (d), in this fortune, this The word line voltage is equal to the length of the line, and is conditionally used by the associated word line strobe = 60 and the word line strobe circuit (9) is suitable for including the circuit 61 and a strobe. Logic circuit 62. μ 1 of 4 = way 2! The size of the sand material will be strobed according to the word line to be stored. Yes, however, the word line control value is any reasonable size, j is superior to controlling access to this gated word line. In Figure 7 /, four N-type transistors 'they are used for this Memory 2; 2, 29, Pif.doc 1285841 Yuan line strobe value. The logical value ("1" or "〇") of the stored word line strobe value is used as one of the strobe logic circuit 62. Input. Specifically, the word line strobe value = is input, applied to a first logic gate 82, and the logic gate also receives a write signal from the branch prediction logic. Since the first logic gate is one or Type = t, ype) logic gate, in which one or two simultaneous input logic ^ will result in a first logic output, τ, this first logic output, series,, °1, this The ^^ voltage value (ie...the second logic gate is interpreted as a logic or a high or low voltage) is applied to a second logic gate. The second logic gate is a type and The logical gate of AND cut e), the input must be, τ, to cause - the second logic in the preferred embodiment, this is from the first - 遴 relatives here The second logic output of the output, the -: word portion, that is, the line portion 71 can be responded to by an instruction address by the -X line ΓΓ 2, the word line line 72 of the word, which can only be _ this word ^ ^ select ' While in some embodiments, the selected circuit operates to receive a word line voltage from the decoder. The sub-line portion is adapted to the word line voltage and can be used as a word. An input of the line 7g pass circuit. When the word line strobe value in the sub-π line circuit 60 that is conditionally stored is allowed, the word line is selected to be energized by the word line 72. , electric &amp; is transmitted to the corresponding I2858iUc conditionally transmitted (ie, the gate control select word line, - corresponding to two: : line ίΓί! &quot;#作° That is, when this character line is selected The general value indicates that the eight-go historical data age branch instruction is very 纟 θ knife branch line-read operation is allowed = branch history data 丨丨, directory 丨丨, Tian 兀 兀 line strobe value pointed word order When it is not possible to take it away, the one-to-one operation of this selection is not allowed. Such a conditional, access operation, and write operation are unnecessary, and the write operation is updated. Therefore, when this write signal is selected by the decoder for the first sister mountain I, = σ '§ - the gate word line is selected, the direct two == pass value. In this way, not only the conditional reading and the unconditional (corresponding to the word line pro-county) write operation, the use of a minimum of hardware resources is effectively utilized. The branch target buffer that is not read by Fig. 6 further includes a read-out </ RTI> </ RTI> </ RTI> </ RTI> after a successful (eg, an allowed) read operation, receiving a data entry from δ recall, array 4G. As is currently preferred, sense amplifier 45 is configured to load (write or update) word line control values (WLCV) to respective memory circuits associated with the word line gating circuit. In accordance with the present invention, an exemplary method of operation-branch prediction unit will be described below with reference to FIG. The data entry corresponding to the -batch instruction is stored in the memory array of the branch target buffer (1〇〇). Each 31 I28584107p, doc's "knife ^ history material" was revealed by the use of a competent algorithm (1〇1). The word line gating values (WLGV) of each instruction are obtained from the branch history data (1〇2) and stored in the memory circuit corresponding to the _word 70 line gating circuit (10) ). After the data entry and the word line strobe are stored, the branch prediction unit is ready to receive the instruction part, such as an instruction address (104). This instruction is partially decoded (10)), and a corresponding word line is selected (1G6). After the word line is selected, the stored word line strobe value conditionally determines whether the word line - the gated portion is accessed - a "positive" word line strobe value indication (i.e., an indication that a branch instruction may be taken away) causes the allowed word line access (108) and outputs a corresponding data item (109). A "negative" indication of the word line strobe value (ie, an indication that the branch instruction may not be taken away) results in no further access and thus an output (11Q) from the memory array. The reference to the k 疋 and "positive" word line strobe value refers to *, which will generally correspond to the status of a specific instruction as the take-away / not take-off state. The invention designs a branch prediction unit to obtain convenience and validity, which can be connected to the branch instruction, and has, for example, allow access to the data strip 1 stored in a branch target buffer/this data item only Read from this branch target buffer, this branch does not, the corresponding branch history data in the smashing, the deletion of this data entry may need to be used to have a low instruction to take away the possibility of this branch, not Will cause read operations allowed for this branch target buffer. Therefore, the power spent on unnecessary operation is saved. 32 I285841〇7p_ For example, Fig. 9 is a diagram illustrating the results of a simulation run of an EEMBC benchmark test performed using a branch prediction unit designed in accordance with the present invention. Above the series of benchmarks indicated along the horizontal axis, a comparison is made between the branch instruction-predicted probability and the branch instruction-actual probability comparison. This specific analogy reveals approximately 4G% of the branch instruction, which is associated with the state of "not taken away", so the power consumption associated with the read operation of the branch target buffer memory array can be reduced by 40%. The present invention does not provide for such power savings, that is, the increase in complexity and the reduction in operating speed. When the instruction is received by the branch prediction unit, the instruction is directly processed by a decoder, when Then directly generate the corresponding data item output. For the ^ processing, there is no delay for the following operations, that is, ^ pre-decoding, searching and/or counting the age data of the instruction, and only generating a signal. This signal allows/disallows the operation of this binary memory - corresponding _ operation. i read &amp; in the present invention, no additional complicated lines or functions are required, conditionally allowing read operation of this branch target buffer memory Instead, a corresponding word line strobe value,, etc., is received in each instruction. The application of a sub-line strobe value in a simple character , allows/ Do not Xu ~ _ circuit take, word line storage ride should receive the command == line after the execution of each instruction, the word line strobe value can be; =. in the word line strobe Updated in the circuit. w&gt; Indeed 33 I2858ilP, doc Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and those skilled in the art, without departing from the spirit and scope of the invention The scope of protection of the present invention is defined by the scope of the appended claims. The preferred embodiments of the invention are the same as the above description. These terms are only used in the embodiments of these presentations to indicate current preferences. These terms also recognize that as the technology continues to improve other circuits, various mechanisms, and various methods will be produced by which the present invention can be effectively implemented. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will be apparent from Where: Figure 1 illustrates a conventional branch target buffer and the components needed to output a data entry from the branch target buffer. 2 is a block diagram showing an exemplary processor that can be easily integrated into a branch prediction unit and/or in accordance with the method of the present invention in accordance with the present invention. 3 is a block diagram showing an exemplary hyperquantization processor which, in accordance with the present invention, can be easily integrated into a branch prediction unit and/or in accordance with the method of the present invention. Figure 4 is a block diagram which further illustrates some additional details of a branch prediction unit in accordance with the present invention. Figure 5 is a flow chart illustrating a state machine that is readily included in a branch history unit of 34 1285841 17007 pif.doc in accordance with the present invention. Figure 6 is a block diagram showing an embodiment of a memory array of a branch target buffer in accordance with the present invention. Figure 7 is a circuit diagram further illustrating the structure of a word line having a pass gate in accordance with an embodiment of the present invention. Figure 8 is a flow chart illustrating a preferred method of operating a branch prediction unit in accordance with the present invention. Figure 9 is a graph illustrating the analogy results of a benchmark test of a branch prediction unit in accordance with the present invention. [Main component symbol description] I : Branch target buffer 2: Branch prediction logic

3: Instruction Address Decoder 4: Memory Array 5, 45: Sense Amplifier Tag Comparison Register multiplexer Program Count Value Multiplexer Logic Gate 10: Pipelined Processor II: Ultra-Quantization Processor 12: Memory 13 33: instruction fetch unit 14 · bus bar 35 1285841 17007pif.doc 15 : instruction decoder 17 : execution unit 19 , 39 : branch prediction unit 20 : branch prediction logic 22 : branch target buffer 24 : branch history unit 34 , 35 36: Execution path 40: Memory array 43: Decoder 60: Word line gating circuit 61: Memory circuit 62: Gating logic circuit 70: Word line 71: Selected word line portion 72: Gate Word line portion 80: second logic gate 82: first logic gate 36

Claims (1)

December 19曰1285841 The cover disclosed in the Ming or the drawings. Patent application scope: 1. A branch target buffer memory array comprising: a word line and an associated word line gating circuit; The word line gating circuit includes a memory circuit that stores a word line strobe value. 2. The branch target buffer memory array of claim 1, wherein the memory array is adapted to store a data entry associated with the word line. 3. The branch target buffer memory array of claim 2, wherein the word line strobe circuit further comprises a strobe logic circuit. 4. The branch target buffer memory array of claim 3, wherein the strobe logic circuit is responsive to a word line voltage applied to the word line and the word line strobe value, This makes it possible to access this data item. 5. The strobe logic circuit is further responsive to a write signal as in the branch target buffer memory array of claim 4 of the patent application. 6. The branch target buffer memory array of claim 4, wherein the access operation is a read operation on the word line. 7. The branch target buffer memory array of claim 5, wherein the access operation is a write operation to the word line. 8. The branch target buffer memory array of claim 1, wherein the memory array comprises a non-volatile memory cell array. 9. The branch target buffer memory array of claim 8, wherein the memory array is a static random access memory 37 1285841 17007pif.doc (SRAM) array. 10. The branch target buffer memory array of claim 9, wherein the memory circuit comprises a one-bit static random access memory cell. 11. The branch target buffer memory array of claim 2, wherein the data entry comprises a branch target tag and a target address. 12. The branch target buffer memory array of claim 5, wherein the memory circuit comprises a one-bit static random access memory cell that stores the word line strobe value; The strobe logic circuit includes: a first logic gate receiving a write signal and a word line strobe value as its input, thereby generating a first logic output; and a second logic gate receiving the first The logic output and the word line voltage are used as their inputs / thereby generating a second logic signal. 13. The branch target buffer memory array of claim 5, wherein the word line comprises a selected word line portion that receives the word line voltage, the word line further comprising a corresponding There is a gate word line part. 14. The branch target buffer memory array of claim 13, wherein the selected word line portion and the gated word line portion are electrically connected by a word line gating circuit. . 15. The branch target buffer memory array of claim 12, wherein the word line comprises a selected word line portion connected to 38 1285841 17007 pif.d〇c $ the word line voltage The character line further includes a corresponding branch word line portion, such as the branch target buffer record 2, _1 column, f, the selected word line portion and the The word line line knife with the gate is electrically connected by the word line gating circuit; and the / logic-path 5 hole number includes a word line voltage, and the word line lightning pressure is applied thereto. There is a _word line part. Sub-70 line price 1^. A branch target buffer memory array, which is stored in response-write selection - data entry = destination, the memory array includes: 4 for the input of poor material data; a line gating circuit that allows access to a word pass value stored in the word line gating circuit during the write operation. Conditionally allowing access to the data strip during the read operation (4) ί车8·列列nt nt, 15 of the branch target buffer described in Item 17 of the U-body array 'where the transition strobe circuit comprises: a memory circuit, (4) save money _ pass value; and ―Write signal and word line strobe value and ^ only in the vl write operation of the fortune, allowing access to this data item, sub-only in the sub-line strobe value indicates a positive identification of the case - read operation Seal, scale access conditional access. 19. The branch target buffer of claim 18, wherein the ur-th gate logic circuit receives a word line voltage as the strobe value of the word line and the word line. Electric will refer to 39 1285841 17007pif.doc in the case of a positive identification, the second two 'conditionally allow access to two = make the in-read operation memory array, where the memory array target buffer notes 21. The scope of the patent application is the first wave of 1 ▲ recalled cell array. The memory array, where the record; L is the target buffer list, and the memory = static = access memory cell. Bit static of your random access memory • branch target buffer, including · a memory array, Α 人 幻 有 有 有 有 有 有 有 有 有 有 字 字 字 字 字 字 字 字 字 字 字 字 字 字 字 字'each-selected word line portion; strobe value = path, which includes -_storage-word line one" - word line portion with gates; and partial receive-command portion, and It is suitable to select the "MW word line" in response to the instruction. The branch target buffer described in item 22 of the patent scope, the selected word line portion of the idle word line is applied. Sub 7C line voltage, the _ word line is selected by the decoder. For the branch target buffer described in claim 23, the strobe circuit further includes a strobe logic circuit to receive the The word line character string_pass_ is input for it. 25. The branch target buffer as described in claim 24, 40 The year-and-month repair M is replacing page 1285841 17007pif.doc, the word line strobe circuit, which is adapted to conditionally allow access to the gated word line of the gated word, where the gated word The line is selected by this decoder, thereby responsive to the word line voltage and the word line strobe value. 26. The branch target buffer of claim 25, wherein the access operation is a read operation. ^ +27. The branch target buffer of claim 25, wherein the word line gating circuit is adapted to receive a write signal as an input, and wherein the access operation is a write operation. The branch target buffer of claim 26, wherein the memory array comprises a static random access memory array, the memory circuit comprising a one-bit static random access memory cell The strobe logic circuit includes: a NAND gate that receives the write signal and the word line strobe value, thereby outputting a first logic signal; and, for, the input _ and the gate, receiving the character The line voltage and the first logic signal are used as input inputs, thereby outputting a second logic signal. "," "29. The branching target as described in claim 28, wherein the second logic lobes u are _ word line voltages, which are applied to the word lines of the gates The word line portion, which has strobe = is selected by the decoder. The line 30. The branch directory as described in item 22 of the patent application scope includes: , , and descendants, a sense amplifier, which is adapted to receive a data item from the selected gated gate, which has The word line of the gate is cleared by the decoding of the '41' I28584l 17〇〇7pif.doc. ^ As in the branch target buffer described in claim 30, &quot;Hai Jing Amplification includes such a line, which transmits the word line strobe value to the word line with the strobe gate Related to each, such as the patent application, the == device, , the memory array includes a static random access memory array; and each of the memory circuits of each of the memory circuits, including a one-bit static, accessing 5 cells, for receiving A word line strobe value. A branch target buffer as described in claim 32 of the patent application, each of the respective memory circuits, comprising: a second or a gate that receives the memory from the cell of the cell The = sign and the word line strobe value as its input, the signal signal; and - and Μ 'the receiving the word line voltage and the first - logic signal as input, thereby outputting a second logic signal . 34. A branch prediction unit, comprising: a branch history unit configured to store branch history data; a branch logic circuit configured to receive an age address, provide a prediction address and update the branch history data; And the knife branch shows the buffer|§, which is used to receive the address of the instruction, and includes: s - a memory array containing the word line of the gate, each - has: the gate: the yuan line storage A data entry includes a word line select power-' and the word 70-line strobe f-channel includes a - note circuit that stores the word line strobe value derived from the historical data of the branch. 42 I2858iUc 35. The branch prediction unit of claim 34, wherein the branch prediction logic circuit provides a write signal to the branch target buffer 36. The branch prediction unit of claim 35, wherein the branch prediction unit The branch history unit includes a state machine for calculating its branch history data in accordance with the branch execution history of an instruction. 37. The branch prediction unit of claim 36, wherein the branch history unit includes a branch history table storing the branch history data, and wherein the state machine of the branch history unit includes a 2-bit Up/down saturation counter. 38. The branch prediction unit of claim 36, wherein the memory array comprises a static random access memory array, the memory circuit comprising a one-bit static random access memory cell, and The word line strobe value includes a single data bit derived from the branch history data. 39. The branch prediction unit of claim 38, wherein the branch target buffer further comprises: a decoder for receiving the instruction address and corresponding to the instruction address and selecting a gate a word line; and a sense amplifier adapted to receive a data entry from the selected gated word line, the sense amplifier further comprising a line for communicating the word line strobe value to each A word line strobe circuit, the word line strobe circuit being associated with the gated word line. 40. - Branch prediction unit, including: 43 降@正. Replacement page I 1285841 17007pif.doc = branch history unit, (4) age history data. -= branch target buffer, including - batch gated words The meta-green, one-bit sub-read is accessed by the operation of the corresponding word line strobe circuit, and the branch target buffer is adapted to output an instruction portion of the branch target buffer that is received by the data, / This is the one-character line strobe value of the historical data. The sub-components hereby include 4:1. The branch prediction military element as described in claim 4, the branch prediction logic, which is used to receive the instruction part and provide a β-return ^ branch target buffer The data item that is output. Eight go to turn the 41st pin division unit, the ^. , ', ' is suitable to provide a write signal to the branch transfer buffer in the special? The branch prediction unit described in Item 41 of 1st, its historical data. ▲ 匕 分支 分支 分支 分支 分支 分支 分支 分支 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 Providing a corresponding measured bit to = this instruction address and providing - a pre-center 7 solution 3 / implementation; ^ unit for receiving this instruction, providing a 44 I2858417 pif.doc 孽 I2fl 19 &quot;&quot;&quot; a _________ d two: '! and provide in response to the execution of this decoded instruction - update its branch prediction unit includes · 2 historical units 'used to store branch history data; address 34 34 34, 'Flip to receive this instruction address and this has been updated = to provide this predicted address, and thus update this branch history data 2 target buffer 11, which is used to receive this instruction address and output A Becco entry 'This branch target buffer includes: The word line includes the word line between them, each of the inter-circuits contains __ = word read strobe Wei, (four) word line select drinker 彳Please specializes in _ 44 Lai Shu's treatment, which is the solution of the aircraft and _7^彳3 Batch execution path 'each execution path comprising a cleavage cry T6. The application of the process in item H patentable scope 45, wherein where a super Cloth quantization processor. 47 The processor 3 is as described in claim 46, wherein the processor is a vector processor or a single instruction multiple data processor. She ran the processor described in the 44th patent range, where the score was 49^^—the write signal to the branch target buffer. The history of the single-t, please refer to the processor described in item 48 of the patent scope, wherein the division of the grievance machine is in accordance with the execution history of the branch of a Japanese calendar 45 I28584〇U a history and calculate its branch history data. 50. The processor of claim 49, wherein the branch history unit comprises a branch history table that stores the branch history data. 51. The processor of claim 44, wherein the memory array comprises a static random access memory array, the memory circuit comprising a one-bit static random access memory cell, and the word The meta-line strobe value includes a single data bit derived from the branch history data. 52. The processor of claim 51, wherein the branch target buffer further comprises: a decoder for receiving the instruction address and corresponding to the instruction address and selecting a gate a word line; and a sense amplifier for receiving the data item from the selected gated word line, the sense amplifier further comprising a line that conveys the word line strobe value to the respective memory In the bulk circuit, these memory circuits are associated with these gated word lines. 46