GB0514599D0 - Branch target buffer and method of use - Google Patents

Branch target buffer and method of use

Info

Publication number
GB0514599D0
GB0514599D0 GBGB0514599.0A GB0514599A GB0514599D0 GB 0514599 D0 GB0514599 D0 GB 0514599D0 GB 0514599 A GB0514599 A GB 0514599A GB 0514599 D0 GB0514599 D0 GB 0514599D0
Authority
GB
United Kingdom
Prior art keywords
target buffer
branch target
branch
buffer
target
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB0514599.0A
Other versions
GB2416412B (en
GB2416412A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020040055635A external-priority patent/KR100591769B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB0514599D0 publication Critical patent/GB0514599D0/en
Publication of GB2416412A publication Critical patent/GB2416412A/en
Application granted granted Critical
Publication of GB2416412B publication Critical patent/GB2416412B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB0514599A 2004-07-16 2005-07-15 Branch target buffer and method of use Active GB2416412B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040055635A KR100591769B1 (en) 2004-07-16 2004-07-16 Branch target buffer storing branch prediction data
US11/080,986 US7471574B2 (en) 2004-07-16 2005-03-16 Branch target buffer and method of use

Publications (3)

Publication Number Publication Date
GB0514599D0 true GB0514599D0 (en) 2005-08-24
GB2416412A GB2416412A (en) 2006-01-25
GB2416412B GB2416412B (en) 2006-09-20

Family

ID=39457380

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0514599A Active GB2416412B (en) 2004-07-16 2005-07-15 Branch target buffer and method of use

Country Status (3)

Country Link
JP (1) JP2006031697A (en)
GB (1) GB2416412B (en)
TW (1) TWI285841B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111627481A (en) * 2020-05-20 2020-09-04 中国科学院微电子研究所 Word line decoding circuit, word line gating method, memory and electronic equipment

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8612944B2 (en) 2008-04-17 2013-12-17 Qualcomm Incorporated Code evaluation for in-order processing
JP5423156B2 (en) 2009-06-01 2014-02-19 富士通株式会社 Information processing apparatus and branch prediction method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02278428A (en) * 1989-04-20 1990-11-14 Toshiba Corp Branch control system
GB2282248B (en) * 1993-09-27 1997-10-15 Advanced Risc Mach Ltd Data memory
JP3494484B2 (en) * 1994-10-12 2004-02-09 株式会社ルネサステクノロジ Instruction processing unit
JPH0926913A (en) * 1995-07-13 1997-01-28 Toshiba Microelectron Corp Cache memory
US5740417A (en) * 1995-12-05 1998-04-14 Motorola, Inc. Pipelined processor operating in different power mode based on branch prediction state of branch history bit encoded as taken weakly not taken and strongly not taken states
JP3701409B2 (en) * 1996-10-04 2005-09-28 株式会社ルネサステクノロジ Memory system
US6011908A (en) * 1996-12-23 2000-01-04 Transmeta Corporation Gated store buffer for an advanced microprocessor
TW357318B (en) * 1997-03-18 1999-05-01 Ind Tech Res Inst Branching forecast and reading device for unspecified command length extra-purity pipeline processor
GB2344665B (en) * 1998-12-08 2003-07-30 Advanced Risc Mach Ltd Cache memory
US6757815B2 (en) * 1999-12-23 2004-06-29 Intel Corporation Single array banked branch target buffer
KR100980076B1 (en) * 2003-10-24 2010-09-06 삼성전자주식회사 System and method for branch prediction with low-power consumption

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111627481A (en) * 2020-05-20 2020-09-04 中国科学院微电子研究所 Word line decoding circuit, word line gating method, memory and electronic equipment
CN111627481B (en) * 2020-05-20 2022-02-01 中国科学院微电子研究所 Word line decoding circuit, word line gating method, memory and electronic equipment

Also Published As

Publication number Publication date
JP2006031697A (en) 2006-02-02
GB2416412B (en) 2006-09-20
TW200617777A (en) 2006-06-01
TWI285841B (en) 2007-08-21
GB2416412A (en) 2006-01-25

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