TWI285498B - Customizable ASIC and method, with substantially non-customizable portion that supplies pixel data to a mask-programmable portion in multiple color space formats - Google Patents

Abstract

An integrated circuit has a substantially non-customizable hardware portion and a mask-programmable logic portion. An image processing function common to many different makes and models of a type of electronic consumer device (for example, an image display device) is performed by the substantially non-customizable hardware portion. The substantially non-customizable hardware portion also outputs pixel data in both a first color space format and a second color space format. The mask-programmable logic portion can be mask-programmed for an individual manufacturer of electronic consumer devices such that the mask-programmable logic portion performs an additional special function specific to the electronic consumer devices of the individual manufacturer. Certain functions are better or more easily performed on pixel data in one color space format than another. Pixel data is therefore supplied to the mask-programmable hardware portion in multiple different color space formats, or in a selectable one of multiple different color space formats.

Description

1285498 When building a circuit, it is usually possible to manufacture an integrated circuit that constitutes a television electronic project at a small unit cost. Therefore, it is sometimes expected that televisions of different manufacturers are made of common electronic components, enabling electronic parts to be made in larger quantities and reducing the cost per unit of electronic parts. If televisions are to be made of common electronic components, the question of how to provide each manufacturer with its own special enhanced functional capabilities remains. A manufacturer must provide a special enhancement feature, but another manufacturer may offer a different special enhancement feature. Television manufacturers typically consider the specific nature of the enhancements that, in the consumer's eyes, can help a consumer's electronic consumer device to be separated from all other electronic consumer devices on the market. A possible solution provides common functionality in the form of a common integrated circuit. By using a common integrated circuit across multiple different styles and types of electronic consumer devices, the cost per unit of providing common functionality can be reduced. On the other hand, the functionality provided is provided by including a programmable gate array (FPGA) in each of the electronic consumer devices that have a particular enhanced feature. FPGAs can be quite expensive, but they are programmable based on the specific needs of each manufacturer. Not only does the mutual communication between the individual FPGA integrated circuits require a large number of input/output terminals (I/0 terminals), thus increasing system cost. What is expected is a better solution. Another possible solution would be to integrate circuits that implement a common functional and programmable logic portion. The programmable logic enables individual manufacturers to implement the special enhancements of the manufacturer. This integration reduces the cost associated with providing communication between the common functional parts and the programmable logic parts', but the amount of integrated circuit area used to implement the programmable logic will be very large. For example, -6- 1285498 implements programmable logic in an anti-fuse-based FPGA technology. Due to the large number of programmed transistors, the stylized current required to be programmed for anti-fusion in a fusion-resistant FPGA is supplied. Due to the existence of large stylized transistors, not only can the programmable logic part be unpredictably large, but FPGAs that are resistant to fusion often require special processes, so it is not expected to have an anti-fusion-compliant FPGA solution. The need for a special process implemented by a semiconductor manufacturing facility often results in more semiconductor manufacturing facilities to manufacture integrated circuits. On the other hand, if such an SRAM-based FPGA technology implements a programmable logic, the circuit will be unexpectedly large due to the large number of structures required to be provided. In the FPGA technology based on SRAM, a large amount of structure is needed to store and build data. Laser-assisted gate array technology is known, but devices made using these techniques are expensive and slow to produce and may have yield and other problems. Laser stylization is more suitable for prototypes than its high production. Therefore, a programmable gate array technology will allow a manufacturer to develop a programmable portion of its own integrated circuit to achieve its own special enhancement characteristics, but the resulting integrated circuit may be larger and therefore economical. The possibilities are more expensive than in the case of a large number of electronic consumer devices. SUMMARY OF THE INVENTION A novel integrated circuit includes a substantially non-developed hardware portion and a programmable gate array portion. Substantially non-developed hardware includes circuits that implement a common function. This common function exists in many styles and styles across a type of electronic consumer device. The programmable gate array is an integrated circuit portion that is developed to achieve the special enhancement characteristics expected by a particular manufacturer of electronic consumer devices. In this way, the first specific manufacturer of the electronic consumer device, the first specific manufacturer, can manufacture the integrated circuit to achieve a first enhancement characteristic for the programmable gate array of the integrated circuit made by the first manufacturer. . One of the electronic consumer devices, the second specific manufacturer, can manufacture the integrated circuit to achieve a second enhancement characteristic for the programmable gate array portion of the integrated circuit made by the second manufacturer. The ability to supply its own special enhancements to individual manufacturers of electronic consumer devices is exploited by the economies of scale associated with the manufacture of integrated circuits in larger quantities. The programmable gate array is made of a factory mask programmable gate array structure B. The programmable gate array is therefore very dense and small. The interconnection is independent of the stylization of anti-fusion. Therefore, it does not contain a large programmable transistor that is fused to a quasi-FPGA. The interconnection is not based on the SRAM and the giant cells are not based on the LUT. Therefore, there is not a large amount of memory cells to store and build data. Trying to provide an enhanced function with a maskable program can be considered unpredictable and overly expensive. During the development of an electronic consumer device, it appears that the operation of the integrated circuit wafer must be completed with a special mask, so that the programmable portion of the integrated circuit can be programmed to implement its intended function in the development system. In one example, the programmable portion must operate at a hardware operating speed along with the remainder of the integrated circuit and the development system. Therefore, it is not always possible to use the software simulation tool to receive the signal to the programmable portion and thereby generate an output signal to be supplied back to the remaining portion of the integrated circuit. It seems that it is necessary to complete the multiple operations of the integrated circuit, and then confirm that the system can be tested in the system before it can function properly. The software simulation tool cannot be used and the need to accelerate the test of a real system during system development obviously realizes a mask programmable. The enhanced nature of the gate array architecture becomes impractical, expensive and cumbersome.

• 8- 1285498 According to a first novel aspect, an interface circuit is provided on the integrated circuit together with the mask programmable gate array portion and the substantially non-developed hardware portion. The integrated circuit is placed in test mode during system development. In the test mode, the interface circuit is supplied to the non-developed hardware receiving signal in the programmable gate array portion of the integrated circuit from another normal operation. The interface circuit outputs those signals above the first terminal of the integrated circuit package. A masked programmable gate array (FPGA) external to the integrated circuit receives the signal from the first endpoint. The role of the external FPGA replaces the programmable gate array of the integrated circuit. The external FPGA receives the signal from the first endpoint and thereby produces an output signal. The output signal is supplied back to the second end of the integrated circuit package. The interface circuit receives the output signals from the second terminal and supplies those output signals to the substantially undefined hardware, instead of outputting the output signals from the programmable gate array during normal operation. The operation in the test mode thus allows an external manufacturer to implement the function of embedding the programmable gate array portion in the integrated circuit with the FPGA. Due to the hardware function of the external FPGA, the operation of the FPGA in the real-world system under development is suitable for quickly implementing the operation of the maskable gate array. Because commercial FPGAs are mass-produced, they can be purchased and used without cost. Similarly, development tools for stylized commercial and mass-produced FPGAs, as well as technical support and a large number of engineers who have previously used FPGA models, are readily available. Development tools from FPGA manufacturers that can be derived from external FPGAs can therefore be used to program or build external FPGAs during system development. In one example, the FPGA development system is the initial design. For example, the initial design may include a circuit diagram 1285498 1 t to be implemented in a maskable gate array portion of an integrated circuit. The initial design can be described in a hardware description language such as Verilog or VHDL. Regardless of how the start-up design is specified, the technology is initially mapped to the hardware of the particular external FPGA being used. Arrange and deliver the design, and 'generate build information that can be used to program the FPGA in the usual way to program the FPGA. In the case where the external FPGA is a fusion-resistance to the quasi-FPGA, the built-in information is used to program the various anti-fusion configurations of the FPGA to realize the functionality of the initial design. Multiple anti-fuse FPGAs can be programmed in this way and tried one after the other in the development system until the system is operational. In the case where the external FPGA is an SRAM-based FPGA, the same FPGA is repeatedly loaded with the build data. The FPGA is tested in the system and then re-established and retested until the system is operating as expected. When the function of the maskable gate array is implemented by an external FPGA, after the integrated circuit in the system works satisfactorily, the development tool is used, and the output can be used to shape a mask information, and the mask can be completed. The gate array unit implements the same functions implemented by the external FPGA. The start-up design is a hardware that is technically mapped to the maskable gate array. Arrange the design and send it by hand. The development tool output can then be used to make information about the mask. In one embodiment, the information is in the form of a GDS file. The mask determines where the conductive vias will or will not be placed in a single layer of the integrated circuit. The presence or absence of these conductive vias determines how the logic circuits of the development are interconnected. Using the information outputted by the self-developed system to form a mask, and using the mask to form an integrated circuit, so that the programmable circuit gate array portion of the integrated circuit is not connected to the external FPGA in the system. Implemented in the same way. Because the product version of the completed version is -10- 1285498 ^ * The body circuit only has to complete a new mask', thus reducing the production cost associated with providing a built-in circuit to a specific manufacturer. Due to the arrangement of the interface circuits, in order to develop an electronic consumer device having a special enhancement characteristic, a manufacturer of an electronic consumer device does not necessarily manufacture a multi-version integrated circuit. The first manufacturer of an electronic consumer device can make the integrated circuit have a maskable programmable gate array to achieve the special enhancement characteristics of the first manufacturer, and the second manufacturer of the electronic consumer device can make the integrated body The circuit has a maskable programmable gate array that achieves the second manufacturer's special enhancements. For each manufacturer, it is only necessary to manufacture a version of the integrated circuit (and a mask) to develop an integrated system that is part of the production integrated circuit. Since the interface circuit is coupled to an external FPGA, the integrated circuit can operate in a development system at normal operating speeds. In some embodiments, the first and second input/output terminals (I/O terminals) used as external FPGA interfaces on the integrated circuit package during testing and development are later in the formed system for other Use is useful during normal integrated circuit operation. For example, the I / 0 endpoint can be used to access the mask of the integrated circuit ® programmable gate array, so that the mask programmable gate array circuit implements another board level function and passes the I / 0 endpoint Communicates with circuitry external to the integrated circuit. These I/O endpoints and mask programmable gate arrays provide a way to address errors on the electronic consumer device system board. In some embodiments, the integrated circuit has input/output cells (interface cells) and associated input/output pads (interface pads) for coupling to the first and second I/O terminals of the package. The integrated circuit is a package that bonds these input/output cells (interface cells) and pads (interfacing pads) to the package/end terminals. However, 'S) -11- 1285498 I 1 uses the packaged integrated circuit during system development. As above. Use an I / 端点 endpoint to couple to an external FPGA. Then, when the system is mass-produced later, the production version of the integrated circuit is packaged in a different manner so that the input/output cells and pads are not externally bonded to the I / 0 terminal. This reduces the number of I/O endpoints on the raw version of the packaged integrated circuit. Therefore, the manufacturing cost of the production version of the electronic consumer device is reduced. According to the second novel point of view, one formulates Δ31 (: includes a substantially non-developed hardware portion and a mask programmable gate array portion. The maskable gate array portion is in a multiple color space format (for example, YCbC) 1*4: 4: 4 color space format and B in RGB color space format) Receive pixel data from virtually non-developed hardware. Provide pixel data in multiple color space format to the gate array of the mask. The programmable gate array is more diverse, in which it is easier to implement some enhancement functions for pixel data in a color space format, but it is easier to implement other enhancement functions for pixel data of another color space format. The present invention is not intended to define the present invention. The present invention is defined by the claims of the scope of the patent application. [Embodiment] FIG. 1 is a simplified high-order diagram according to an embodiment. System 1 is being developed by the first manufacturer of one of the consumer electronics devices. System 1 includes a masked special application integrated circuit (AS IC) 2. Integrated circuit 2 is in the system 1 implements an obvious data processing function, and implements the data processing function in other electronic consumer device systems made by other manufacturers. In an example where the electronic consumer device is a television, the common function may include a non-crossing -12- 1285498 Incorrect function, one function lowering function, certain standard function 'one gamma correction function, one digit to analog converter function' and one screen display function. Common function consists of a bundle of qualitative non-developed hardware parts 3. The non-developing part 3 receives input from the system and generates an output to the system. In an example, 'the standard cell manufacturing technology is used to realize the substantially non-developing part 3. The integrated circuit 2 further includes a factory mask. The gate array portion 4 of the program is not implemented by the standard cell, and the maskable gate array portion 4 is arranged to completely formulate the circuit. The mask programmable gate array portion 4 can receive the substantially non-developed B hardware portion. 3 input signals, using those input signals to implement an intended function, and can generate an output signal. The output signal is supplied back to the substantially non-developed hardware portion 3, in the diagram, the arrow 5 denotes an input signal source as a signal input to the maskable gate array portion 4. In the illustration, arrow 6 indicates that the output signal generated by the mask programmable gate array portion 4 is supplied back to substantially non-hardened output. The destination of the body. Although the source and destination are explained as the focus 1 In fact, the source contains the signal from many places in the non-developed hardware department 3 and the destination contains the injection into the non-developed hard A plurality of signals in the body 13 are not in place. The integrated circuit 2 further includes an interface circuit except for the substantially non-developed hardware portion and the maskable gate array portion 4. In this illustration, the interface circuit is an integrated body. The remaining portion of the circuit of the circuit 2 is not a substantially non-developed hardware portion 3 or a maskable gate array portion 4. The integrated circuit 2 can operate in a test mode and a normal single operation mode. 1. The integrated circuit 2 is placed in the system 1. At this time, 积 does not program the integrated circuit 2 as a mask to implement a special increase in the system -13 - 1285498. Make the interface circuit in test mode. In this embodiment, this is accomplished by having a programmable gate array (FPGA) development system 7 communicate with a serial interface 8 of the interface circuit via a series of busses. The serial interface 8 is received from the FPGA development system 7 via the input/output terminals (I/0 terminals) of the interface circuit for pairs 9 and 10. I / 0 terminal 9 is a data terminal DATA. I / 0 terminal 10 is a clock terminal CLK. The serial interface 8 receives the communication and sets a bit in a configuration register (not shown). The digital content of this configuration register bit is supplied via line 1 1 to the multiplexers 1 2 and 13 of the interface circuit. The multiplexer® 1 2 is controlled such that the input signal from the source 5 in the non-developed hardware unit 3 is transmitted through the multiplexer 1 2 via the line 14 (the output pin of the part 3). To the first I/O terminal 16 of the interface circuit. A clock signal on line 15 synchronized with the information content is supplied to one of the first I/O terminals 16 clock output terminal CLK21. The input signal on the first I/O terminal is sequentially supplied by an external connection point connected to the external FPGA 17I / 0 terminal. In this example, the external FPGA 17 is a commercially available FPGA that is widely used and operates as understood by many engineers. Development tools to program FPGA 17 are widely available and understood. Due to the operation of the ® interface circuit, the input signal supplied to the mask programmable gate array section 4 in the normal operation mode of the integrated circuit 2 is supplied to the external FPGA 1 in the test mode. In the test mode, the multiplexer 13 is also controlled such that the output signal supplied from the FPGA 17 is transmitted to the second I/O terminal 18 via the external connection point, through the line 197, through the multiplexer 13 and through the line 2 0 (the input pin of the portion 3) is conducted to the destination 6 which is substantially undefined in the hardware portion 3. Therefore, the interface circuit couples the FPGA 17 to the integrated circuit 2 so that the circuit inside the FPGA 17 (functionally during the test mode) can replace the -14-285498 mask programmable gate array portion 4' Stylize it to operate during normal operating mode. Thus, the 'interface circuit constituting a device couples an external FPGA to the integrated circuit such that when the maskable gate array portion of the substantially identical integrated circuit is stylized and operated in a real system, The FPGA implements a function implemented by a mask programmable gate array portion of another substantially identical integrated circuit. The FPGA development system 7 is used to illustrate the circuit design that is later implemented in the mask programmable gate array. Instructions can be given in the form of Ve r i 1 og or VHDL: hard description language. The FPGA development system 7 is used to technically map the circuit design to the hardware of the FPGA 17. Place it and deliver it. Implement timing confirmation. The build information is then output from the FPGA development system 7 and supplied to the external FPGA. The FPGA can be placed or programmed to implement the desired circuit. The FPGA 17 can be an FPGA of any suitable FPGA technology, for example, one based on anti-fusion technology, one based on SRAM technology, or one based on EEPR0M, or one based on FLASH. Once constructed, the external FPGA 17 operates in conjunction with the substantially non-developed hardware 3 of the integrated circuit 2 in the development system 1. Since the FPGA 17 implements a hardware circuit design, the system 1 can operate at the full operating speed of the system. If desired, the functionality of the FPGA 17 can be changed by changing the circuit design on the FPGA development tool 7, by mapping, placing, and then reprogramming or re-architecting the FPGA. In essence, the hardware unit 3 is not implemented in one of the functions of the system 1. This function is also available for other similar systems developed by other manufacturers. On the other hand, FpGA17 implements a special enhancement function as expected by the manufacturer of the development system 1 1285498. Once the FPGA 1 7 and the integrated circuit 2 are operating correctly in System 1, the FPGA Development Tool 7 is used to generate a semiconductor fabrication mask (or network cable, such as a step and repeat projection in the fabrication of the integrated circuit). Information about the system). This information can be, for example, a typical GDS file. During the integrated circuit 2 process, a mask or network cable can be used to form the maskable gate array 4, and the same function implemented by the external FPG A 17 in the test mode is implemented. In one embodiment, only one layer of conductive perforations is made and only a new mask is completed. The development of the conductive via layer forms a mask programmable gate array 4 that implements the same function performed by the external FPG A 17 in the test mode. The maskable gate array portion 4 is very dense and therefore small and inexpensive. The ground is disposed on the integrated circuit 2. The maskable gate array portion 4 is not an anti-fusion-compliant FPGA and therefore does not contain the large stylized transistors required to supply the stabilizing current to the anti-fuse wire during anti-fusion stylization. The maskable gate array portion 4 is not an SRAM-based FPGA and therefore does not contain a memory cell that is required to store the data in an SRAM-based FPGA architecture. Since only one layer of integrated circuit 2 needs to be developed, the cost of providing non-recurring engineering for providing a manufacturer 2 to system 1 manufacturer is reduced. Since the mask-type gate array portion 4 is of high density, the unit cost of the integrated circuit 2 is also low. In the fully production version of System 1, FPGA 17 is not provided. The programmable gate array section 4 provides the functionality previously provided by the FPGA 17 in the test mode. The interface circuit is turned on in its normal mode of operation (non-test mode) and maintained in the normal mode of operation during normal operation of system 1. The use of the synchronous design technique in the circuit design of the 16- 1285498 I t into the FPGA 17 and the circuit built into the maskable gate array section 4 help to shift the design transferability from the FPGA 1 7 to the cover. The cover can be programmed with the gate array unit 4. In one embodiment, the circuitry that is programmed into the FPGA 17 and the gate array portion 4 that is configured to be masked is clocked by the same clock signal present on the clock terminal CLK2. During operation of the normal mode of operation, the first and second sets of I/O terminals 16 and 18 are not required to be coupled to the external FPGA 17. Thus, in some embodiments, the first and second sets of I/terminals 16 and 18t can be used to provide access to and from the mask programmable gate array 4 during normal operation mode, such that The mask programmable gate array section 4 can implement another board level function. The circuit portion of the mask gate array unit 4 communicates with the circuit outside the integrated circuit via the I/〇 terminal. Therefore, the I/O terminals 16 and 18 provide a means for the manufacturer of the system 1 to resolve the faults and errors on the system 1 system board. An additional function can be provided on the system board of System 1 using I/O terminals 16 and 18. If the functionality of the maskable gate array 4 is not required in the final system 1 to solve the problem and provide additional functionality, the integrated circuit 2 can be packaged in an I/O-free terminal 16 And 18 in its fully production version of the package. The input/output cells and associated input/output pads on the integrated circuit 2 of the first and second I / 0 terminals 16 and 18 are not soldered to the package I/ in the fully manufactured package. O end. This is a low production version of the package I/O terminal on the integrated circuit, thus reducing the manufacturing cost of the production version of the integrated circuit 2. In the same way, a first manufacturer can use an FPGA development system to -17-

1285498 develops a first electronic consumer device system and then completes a single mask network cable) such that the new integrated circuit 2 is used in the system to implement a common and a first special enhancement function, and a second manufacturer can also use one The development system develops a second electronic consumer device and then completes a mask such that the new integrated circuit 2 is used in the system to implement a common function and a second special enhancement function. Although the above illustrates the method of Figure 1 relating to the television system, this method is used in the development of a number of other different types of systems. This method is useful in developing cost-sensitive, high-volume electronic consumer devices in which an integrated circuit is implemented in a number of different styles of electronic consumer devices and is implemented in only one of a certain type and 1 or style. Improve functionality. Only the single layer details in the programmable gate array can be changed to complete the integrated circuit. In order to produce a version of the integrated circuit, there is no need to re-design the layout of the body circuit. Once a version of the version has been designed, the additional cost associated with producing a different version of the integrated circuit is utilized by a large number of different manufacturer circuit designs that appeal to similar electronic consumer devices. A Specific Example FIG. 2 is a simplified system level diagram of a video display system 1 0 1 according to a specific example. For example, an antenna 106, a coaxial cable, or another video source 104 receives an incoming signal to the video display system signal through a tuner 105 in the integrated circuit 109, an IF demodulation Qin, an analog to digital digit The converter 107 travels to a display processor display processor 108 to perform deinterlacing and scaling. The display processor 108 (or the function FPGA can be a single can make the conceivable type ^ Μ. The mask is developed by the number of products: circuit 丨, because, the integrated body (sub-package I 103:. The 106 106 ° is mixed -18 · 1285498

ι I is manufactured with standard cells and fully developed circuits. The maskable programmable array portion 110 exhibits one or more enhancement functions, whether or not irrelevant or consistent with the components of the display processor 108. The self-integrated circuit 109 outputs the formed deinterlaced video to the driver 11 1 and a display device. The display device can be, for example, a cathode ray tube (CRT) 1 12, a liquid crystal display (LCD) screen 113, a plasma display 1 14 or other display device that can be used for viewing video. The video information frame is stored in an external RAM 115. A micro controller 116 is coupled to the integrated circuit 109. The microcontroller 116 can control the characteristics and/or enhancements exhibited by the integrated circuit 109. These features and 1 or enhancements may include, for example, picture-in-picture (PIP), split-picture (POP), theater 1, theater 2, format conversion, video view, panorama ratio, initial color mixing and overlay, VBI/closed captioning, Screen display (0SD), and brightness adjustment. The audio passes through the audio circuit 1 1 7 and to the speaker 1 1 8 . Fig. 3 is a more detailed view of the integrated circuit 109 of Fig. 2. The integrated circuit 109 actually inputs its two-bit video signals 埠1 1 9 and 1 20 . Receiving a digital video signal 119 A digital video signal passes through a format detector 1 2 1, through a ® FIF0122 and to a memory control block 123. If a digital video signal is stored on the digital video camera 120, the second digital video signal passes through a second format detector 124 through a second FIF01 25 to the memory control block 132. In the example of Figure 1, only one of the digital video frames 埠1 1 9 is used. The continuous video frame passes through the digital video input 埠1, 9 through the format detector 1 2 1, through the FIF0122, through the memory control block 123 and stores it in DDR, SDRAM (double data rate synchronous dynamic random access memory) ) 1 1 5. In one example, each video frame is an NTSC -19- 1285498 frame with 480 pixel scan lines, where each column contains 720 pixels. (A pixel is sometimes called a column of pixels). In this example, one pixel contains two numbers 値·· 1 ) octave luminance 値, and 2) octet color 値. Each frame consists of two fields. The first field contains an odd frame to sweep the cat line. The second field contains an even frame scan line. The first field contains the video image pixels in front of the remaining portion of the image represented by the pixels of the second field. In the hardware example of Figure 3, a field receives a continuous field of a continuous field frame and stores it in R Α Μ 1 15 . It is expected that some video display devices will be provided by "deinterlacing" video, in which the number of pixels in each pixel field is doubled. For each of the 240 lines 720 pixel field fields supplied to the integrated circuit 9, the frame to be output by the integrated circuit is 480 lines X 7 2 0 pixels. In order to convert a 240 line X 7 2 0 pixel field (referred to as "the field of interest") into a 480 line X 7 2 0 picture frame, the equivalent of three consecutive fields is taken from the RAM 1 1 5 Memory area. The first field contains the odd lines of the first frame (lines 1, 3, 5, etc.) and the second field contains the even lines of the first frame (lines 2, 4, 6, etc.). The third field is the first field containing the odd-numbered lines (lines 1, 3, 5, etc.). The intermediate field is the field of interest. The special area for which the special pixel is generated is the memory area from this field of interest. The number of pixels in the memory area is doubled. The first area is the same as the second area, and only the first area comes from the field immediately before the field of interest. The memory area of the same area of the third area and the second area, only the third area comes from the field immediately after the field of interest. The operation block 1 of the process block 丨 26 (see Fig. 3) uses the first and third blocks to determine whether there is an action in the second block. For example, if an object in a movie in the picture area defined by a block is to be moved from one field to the next, then 1285498 may detect an action. If a motion is detected in the picture area defined by the second block, a temporary interpolation method is used to generate pixels between the pixel columns of the second area. In the example where the block contains seven lines, the temporary interpolation method creates a new number in the odd column such that the number of pixels in the second block is doubled. These new pixels fill the gaps between the lines. Look at the elements in the first and third blocks to determine these new pixels. Call this "temporary" interpolation because it makes pixel information outside the field time (the second block is from the field of interest interpolation and determines the new pixel. On the other hand, as detected in the second block The action is interpolated and filled with odd lines in the second block. The space uses the pixels in the same field as the second block to determine the near-new pixel mode to focus on the number of lines in the field. 2 4 0 even lines 4 8 0 odd and even lines in this way are full of attention to the block in the field. By the deblocking block 189 of the process block 126 (see the implementation of interpolation and new The generation of pixels. The pixel block used in the above program is taken out from the RAM1 15 in the multi-line area. The multi-line block pixel is six 7 20 pixel lines. The devices 1 2 7 and 1 2 9 are stored in six columns. A buffer of pixels. The buffer is small. It stores five columns of pixels. It is coupled to the program area 126 by its own 128-bit wide buffers 127, 128 and 129. Insert a new image like FIF0130. Connect the FIF0130 to a 128-bit wide bus. Block 126. The FIF01 30 is arranged in another bus with a width of 128 bits, and the second region pixel, the even-numbered corresponding image is interpolated by space. Accordingly, it is increased to a *block 3 map) Each of the blocks of the buffers 128 is written to the processing and coupled to the -21 - 1285498 I » memory control block 1 23. The noise reduction result is output from the noise reduction area 1 90 of the processing block 1 26 and It is supplied to the memory control block 123 via the FI FO 137. Once the interpolation of the block in the field of interest is completed, the buffer 130 for newly interpolating pixels in the memory control block 123 is stored in the RAM1 15 When outputting the formed "deinterlaced" film field, the new interpolated pixel block and the original block are combined to output the "deinterlaced" area on the output bus 1 1 1 to FI. FO 1 3 2. Each pixel is represented by 16 bits and simultaneously outputs eight pixels (B all pixels, original and interpolated pixels in the memory segment row) on the bus 1 1 1 . The output bus 1 1 1 is 1 2 8 bits wide. F I FO 1 3 2 contains 960 such 128-bit wide characters. The video interleaved line passes through F I FO 1 3 2 and goes to the scaler block 1 3 3 . The scaler block 133 outputs the pixels in parallel with 16 bits. The pixels are output by the scaler block 133 and supplied to the enhancement block 135 via the multiplexer 134. The brightness adjustment is one of the examples of enhancements implemented by the enhancement block 135. Each of the _YCbCr4:4:4 pixels is 24 bits wide, and the pixels are from a boost block 135 of a pixel-by-pixel wide header 136. On each rising line of OUTCLK, three 8-bit pixel numbers (one 8-bit Y-pixel 値 '- 8-bit Cb pixel 値, and one 8-bit C r pixel 値) can appear in the busbar 1 3 6 on. The pixel passes through the multiplexer 1 37 to the color space conversion area 1 38. In the present embodiment, the color space conversion block 138 performs YCbCr4: 4:4 to RGB conversion. The pixels are output from the color space conversion block 1 38 to the color mixing multiplexer 1 40 via a 26-bit width: bus bar 1 3 9 . On each rising line of OUTCLK, three 8-bit pixel numbers (one 8-bit R pixel 一, one 8 • 22· 1285498 bit G pixel 値, and one 8-bit B pixel 値) can appear in 24 bits. The convergence of the yuan is on the 1 3 9 line. The color mixing multiplexer 1 40 provides multiplex processing capability for displaying overlapping information on the screen. The pixels are output from the color mixing multiplexer 1 40 to a gamma correction and dither block 1 4 1 . The formed pixels are output to the multiplexer 1 42. If an analog video output signal is expected, the pixel stream is output analogously from the integrated circuit 109 through a digital to analog converter (DAC) block 143. If a high resolution digital television signal is expected, the pixel stream is changed to a double pixel block 144 which is doubled by B 48 bits by the number of bits simultaneously output from the integrated circuit 109. This also results in a reduction in the rate at which information is output at signal terminals 145 and 146. The functionality displayed on the screen is provided by block 147. The letters displayed on the screen are supplied from the serial interface block 148 to the block 1 47. If you want to see more on-screen display features, the colors and fonts provide an external OSD (on-screen display) integrated circuit 149 as an option. The microcontroller 1 16 controls the various integrated circuit 109 blocks by transmitting a serial communication to the serial interface 148 of the integrated circuit 109 via a data line 150 and a clock line 1 5 1 . The serial interface 148 performs sequential writes to the appropriate one of the configuration registers 1 5 2 . The contents of the digits in the various built-in registers are supplied as control signals for controlling various other blocks. By setting a bit in the built-in register, the other blocks can be controlled or relatively small, but the fine-grained general low-order giant cell logic in the block is not linked by a program. The different ways in which structures connect to each other are freely interconnected. The circuits of these other blocks are therefore said to be substantially non-definable. The integrated circuit 1 09 includes a first phase-locked loop circuit 1 5 3 and a second phase lock circuit. 23 - 1285498 circuit circuit 1 5 4. Both use an external spar 155 as the basis for timing. The first phase locked loop circuit 153 generates an INCLK signal (IX) and a DDRCLK signal (2X). Use these signals to time the various blocks on the left side of Figure 3. INCLK goes to blocks 126, 139 and 140. The second phase locked loop circuit 154 generates an output clock OUTCLK for timing the mask programmable gate array 1 1 0 and timing the various blocks to the right of the third graph. In the test mode, the clock signal OUTCLK is also driven out of the chip to provide a clock to the synchronous logic in the external FPGA. • The mask programmable gate array 1 1 〇 is coupled to receive input signals from various sources in the remainder of the integrated circuit 109. Also coupled to the mask programmable gate array 1 1 〇, the output signals are supplied to various destinations in the remainder of the integrated circuit 109. In Fig. 3, the mask programmable gate array 1 1 〇 is coupled to the mutual connection of the sources and destinations. The mask programmable gate array unit 1 1 receives the signal passing through the bus bars 1 5 6, 1 5 7 and 158 into the program block 126 at the sequence block 126, for example, implementing a modified motion detection, solution Interlaced, and 1 or noise reduction power. The maskable gate array unit 1 1 供应 can supply its output at the output of the program block 1 2 6 . The maskable gate array portion 1 1 0 supplies its output to the FIFOs 130 and 141 via the bus bars 1 5 9 and 1 60 and the multiplexers 1 6 1 and 1 6 2, respectively. The maskable gate array portion 1 1 can be used to implement the enhanced scaler function, for example, by receiving signals through the bus bar 1 63 through the scaler block 1 3 3 . Bus 164 and multiplexer 134 may be used to supply output at an output provided by scaler block 133. -24- 1285498 i ί Masking the programmable gate array 1 1 0 The enhancement function can be implemented, for example, at the enhancement block 135. To do this, the maskable gate array portion 11 receives information that would otherwise be used by the enhancement block 135. It receives this information in parallel by FIF0165 - the third three pixels. First, the FIF0165 outputs three pixels of pixels 1, 2, and 3 extending in the vertical direction. Next, the FIF01 6 5 outputs three pixels of the pixel lines 2, 3, and 4 extending in the vertical direction. This supplies a three-pixel to mask programmable gate array 1 1 0 program that continues from top to bottom and spans the pixel frame to the right. The enhanced function results implemented by the mask modular gate array 1 1 0 are supplied at the output of the enhancement block 135. The output of the enhancement function is supplied to the color space conversion block 138 via the bus 166 and the multiplexer 137. The maskable gate array portion 1 1 0 can be implemented in the color space conversion block 1 38 and/or the gamma correction and dither block 1 1 1 , for example, to implement a development enhancement function, mask the programmable gate array The portion 1 1 0 is different from the standard color space conversion implemented by the color space conversion block 138, and for example, a color space conversion can be implemented. In order to provide such an enhanced function or an alternative color space conversion, the input to the color space conversion block 138 is supplied to the mask programmable gate array unit 1 1 0 via the bus ί 6 7 . The enhancement block 1 3 5 supplies a DCTINA active signal to the maskable gate array unit 10, indicating when valid pixel data is present on the 24 bit wide bus ί 6 7 . A mask programmable array portion 1 10 output is supplied at the output of the gamma correction and dithering block 141. This is implemented using a 24-bit wide bus 168 and multiplexer 142. The mask programmable gate array 1 1 〇 outputs an active signal (not shown) and the pixel data ' indicates when the valid pixel data is stored. -25 - 1285498 lies on the busbar 1 6 8 of 2 4 bits wide. Supplying pixel data from a source block across a bus to a maskable gate array 1 1 0 'Source block also supplies a corresponding active signal, indicating when valid pixel data exists in the bus on. DCTINA and GMAINA are two such active signals. Similarly, when the pixel data is supplied from the mask programmable array unit 1 1 0 across a bus to a destination block, the maskable gate array unit 1 1 0 also supplies a corresponding active signal, indicating When the effective pixel data is present on the bus, the signal SMXOA (not shown) is an active signal that is supplied from the mask programmable gate array 1 1 0 to the enhancement block 135. The signal DCTMXA (not shown) is an active signal that is supplied from the mask programmable gate array portion 110 to the color space conversion block 138. The signal GMXOA (not shown) is an active signal that is supplied from the mask programmable gate array portion 110 to the two-pixel block 1 44. Synchronously transfer pixel data with a clock signal. The pixel received by the calculation block determines the end of the line and the end of the picture frame. In addition, additional signals can be provided from the source block to indicate the end of the line, the end of the frame, and other conditions. It is preferable to perform some operations on the pixel data in a color space, but it is preferable to perform other operations on the pixel material in another color space. According to a new perspective, the coupled mask programmable gate array portion 110 receives pixel data in two distinct color space formats (e.g., YCbCr format and RGB format). White level enhancements, black level enhancement, color histogram extension, skin tone enhancement, horizontal DLTI' peak filtering, display control, and DCTI (digital color transient correction) are generally easier to implement in the YCbCr color space. In RGB color space -26· 1285498

Gamma correction and dithering are usually easier to implement in i I. In addition to the YCbC i* and RGB color space input, it is recalled that the mask programmable gate array 1 1 0 is connected to F I F0 1 6 5, and the pixel data of a plurality of different continuous line pixels is received as described above. The pixels supplied to the mask programmable gate array 1 1 0 may be pixels from the previous line and pixels from the current line. Receiving pixel data from three such continuous lines of pixels of a frame helps to implement a special interpolation enhancement function in the mask programmable gate array 1 1 . Receiving pixel data from three consecutive line pixels also facilitates 2D noise reduction and vertical DLTI (vertical digital brightness transient correction) in the mask programmable gate array portion 110. The integrated circuit 109 includes an I/O terminal. 169. These I/O terminals include an external clock input terminal EXTCLK 170, 16 output terminals OUT171 and 16 input terminals IN172. An external FPGA (not shown) can be coupled to the integrated circuit 109 during system development using these I/C ports. The interface circuit is not shown in Figure 3. See Figure 1 for details of an embodiment. The input signal source 5 in Fig. 1 is equal to the various signal sources supplied to the maskable gate array portion 1 in Fig. 3. The output signal destination in Fig. 1 is equal to the various signal destinations supplied from the mask programmable gate array portion 1 1 0 to the other components of the integrated circuit 1 0 9 in Fig. 3. End points 21 and 16 in Fig. 1 are equal to the end points 1 7 1 in Fig. 3. The endpoint 1 8 in Figure 1 is equal to the endpoint 1 7 2 and 1 7 0 in Figure 3. Figure 4 - 7 illustrates a specific example of a maskable gate array 1 1 . The examples in Figures 4-17 are merely an example. Any other suitable masked logic architecture can be used. (s) -27-128,5498 Fig. 4 is a plan view of the maskable gate array 1 1 第 from the top to the bottom in Fig. 3. The portion 110 is arranged in a plurality of bricks, mainly constituting a vertical extension row. The bricks labeled 1 to 5 in the figure are called "super packs". From top to bottom in each super cell, there are five super cells and an area containing horizontally extended SRAM access and control lines. The horizontal extension access and control lines are placed on top of the horizontal extension of the metallization of the integrated circuit. Although not illustrated in Fig. 4, there is a vertically extending SRAM block extending down to the center of each pair of supercells. The WD mark indicates a write data line. The RD mark indicates a read data line. The RA flag indicates a read address line. The WR flag indicates a write to the flash control line. The WA flag indicates a write address line. Super cells form a two-dimensional matrix. As shown in the figure, there are 56 super cells in this example. Therefore, there are 28 vertically extending SRAM blocks. Surrounding the two-dimensional matrix supercell is a circular input/output cell. Figure 5 is a top-down diagram of one of the supercellular structures of Figure 4. Across the two-dimensional matrix from left to right, the arrangement of consecutive supercells is essentially mirror images of each other. Note that the top five super-cells contain four logical giant cells (labeled "LOG 1C") on the left side. There is a buffer between the upper two giant cells and the next two giant cells (labeled "BC"). Except for the giant cell and the buffer and the clock cell appearing on the right next super cell, the configuration is repeated in the next super cell on the right. However, the two super cells on the left side of Figure 5 are not mirror images of each other. Note that the rightmost supercell pair contains a set of horizontal perforation symbols on its right edge. Each horizontal perforation symbol represents the location at which a horizontal conductive perforation can be configured or the location of the horizontal electrically conductive perforation is absent due to the development of the perforated mask. It is also noted that there are also vertical perforation symbols illustrated at the bottom of the supercell. again

-28- 1285498, each of these symbols represents a position at which a vertical perforation can be configured or because the perforated mask is not present. The wires that extend the vertical dimension are labeled CLK 'EX and QUAD. The CLK flag indicates the wire that can be used to transmit a clock signal. The EXP mark indicates a fast wire. A fast wire extends substantially the entire vertical length of the maskable gate array portion 110. The QUAD designation indicates that one of the four signal lines extends from the front of the vertical perforation position. The horizontal ® wire of the interconnected structure is realized on the metal layer 4 ( M4 ) of the integrated circuit. The vertical wires of the interconnected structure are realized on the metal layer (M5) of the integrated circuit. As illustrated, the entire planar plane of the Μ5 layer covers the vertically extending wires. For the semiconductor process in use, the wires are arranged side by side as close as possible. In a similar manner 'substantially 4 layers of the entire surface cover the horizontally extending wires, as far as possible in the semiconductor process in use, the wires are configured to be juxtaposed close together. These vertical and horizontal wire densities in these layers of the structure allow for interference with the largest number of potentially cross-linked conductive perforation locations in the layer. By maximizing the number of potential cross-connected conductive via locations, in order to complete the development of the integrated circuit 109, only one conductive via layer is required and only a new mask is needed. The equivalent gate density of the programmable gate array using 0.18 micron process mask is greater than 2 5 K available gates per mm2, but the large gated gate density of the QuickLogic pASIC FPGA architecture using the 0.18 micron process is 22 per nanometer. 5K available 閛, and the Xilinx Virtex Π FPGA architecture using the 0.18 micron process has a large equivalent gate density of 21. 2K available gates per mm. Except Figure 6 shows how the SRAM block is placed under the giant cell metal conductors 128549,8, and Figure 6 is similar to Figure 5. The logic portion of the electric giant cell produced in the semiconductor substrate is disposed on the right side of the giant cell in the case of the left giant cell pair or in the case of the right giant cell pair. As a result of the huge, there is no configuration between the giant cells of the giant cell logic. Only the M4 and M5 giant cells are interconnected in these areas because the SRAM block contains higher-order interconnections with the M4 and M5 giant cells. Therefore, the SRAM logic (and the transistors that need to interconnect the group logic) The lower order interconnections are arranged in the area under the left giant cell and the left giant cell. The maximum number of horizontal extensions (M4 layers) that can be used to link to the lower block is referred to the position shown in Figure 4. The SRAM block can be coupled to or (by a suitable conductive via) uncoupled to the position shown in FIG. Figure 7 is a simplified side view of a vertical conductive perforation. The metal layer 5 of the metal top circuit (indicated by M5). The metal underlayer is an integrated metal layer 4 (indicated by M4). Connect M5 and M4 to the hole on the left (a conductive plug) as a permanent conductive hole, which is present regardless of the mask. Connect M5 and M4 to the conductive vias on the right side of the potential conductive perforation location. A conductive via can be placed in this way depending on how the mask is formed. Figure 8 is a simplified side view of a horizontal conductive perforation. The metal layer 5 of the metal top circuit (indicated by M5). The metal underlayer is an integrated metal layer 4 (indicated by M4). The M5 and M4 are connected to the hole on the left side as a permanent perforation. Regardless of how the mask is formed, it connects Μ5 and M4 to the right side of the conductive perforation to represent the left side of a potential conductive crystal, and the fluoroscope is projected into a region. When a small amount of SRAM is the rightmost SRAM extension conductor, the placement layer is electrically conductive through the formation of the perforation position or the layer is the conductive wear of the product. Punch position -30- 128.5498 set. A conductive via can be placed at this location or not depending on how the mask is formed. Figure 9 is a simplified diagram of a SRAM block. Figure 10 is a diagram showing the structure of a read detector of one of the SRAM blocks. Each of the dashed square blocks in Fig. 9 represents an example of the SRAM cell structure of Fig. 9. Each SRAM block contains 16 copies of the structure of Figure 10. Therefore, each SRAM block outputs 16 bits at a time. Figure 11 shows a giant cell structure, one input/output cell on the left side (I / 0 cell), and one I / I above it. A more detailed picture of the 0 cell. The specific logic of the giant cell is illustrated on the left edge of the giant cell. This logic contains two AND gates, a multiplexer structure and a flip-flop. The I/O cells provide the input and output buffering required to link the maskable gate array 1 1 0 to the various signal sources and destinations in Figure 3. In the illustration, the conductive perforation symbol represents the location of a conductive via as desired. Additional is provided when the number of I/cells in the maskable gate array 1 1 is less than the number of sources and/or destinations at which the maskable gate array 1 1 〇 is to be coupled Multiplex and/or multiplex processing functions. An additional multiplexer can be provided to couple one of the selected plurality of sources to an I / 0 cell (using the I / 0 cell to receive the signal to the maskable gate array 1 1 0). This additional multiplexer can be controlled by the contents of one or more configuration register bits. Similarly, an additional demultiplexer can be provided to couple an I / 0 cell (using the I / 0 cell output signal from the maskable gate array 1 1 0) to a plurality of destinations selected one. This extra; multiplexer can be controlled by the contents of one or more configuration scratchpad bits. Do not use one

-31- 1285498 Demultiplexer, each destination can have a registered input, and can supply a signal to all inputs but only count the selected ones. Using one or more of the register bit contents can, for example, control the timing of which registration is entered. Other ways of expanding the number of sources and destinations at which the maskable gate array unit 110 is coupled may also be possible. Figure 12 is a detailed diagram of the giant cell structure, in which the giant cell logic is placed on the right edge of the giant cell. Figure 13 is a detailed view of the buffer and time pulse (BC) of Figure 5. The shared signal conductors / SET, CLK and / RST illustrated in Figures 1 2 and 13 are vertically extending the overall length of the five super cells in an uninterrupted manner. The conductors "1" and "0" indicate that the entire length of the five supercells extends vertically in an uninterrupted manner. These conductors are made wider and therefore more conductive than the other vertically extending conductors described. The conductor marked "1" is permanently coupled to VCC (supply voltage). The marked conductor is permanently coupled to ground potential. Fig. 14 is a schematic diagram showing the bottom-down diagram of the balanced clock-like structure of the mask programmable gate array 1 1 0 0. This structure is duplicated twice in the integrated circuit. The leaf of the first clock tree is represented by CLKTR1 (clock tree one). The leaf of the second clock tree is represented by CLKTR2 (clock tree II). The vertically extending clock tree leaflet conductors CLKTR1 and CLKTR0 in Fig. 13 are extended as shown in Fig. 14. The clock tree driver that balances the clock tree is placed in the horizontal gap between the input and output conductors of the SRAM block. As shown in Figure 14, there are three such gaps. Fig. 15 and Fig. 16 illustrate various logic gates and flip-flops which can be realized by constructing the giant cells of Fig. 12 in different ways. 1285498 Figure 1 7 shows a schematic diagram of a scan test interconnection structure. This structure links all the flip-flops of all the giant cells of the programmable gate array 1 1 0 to a long scan test displacement. In the chain of the register. In a test mode, a scan test clock signal is supplied to the SCAN CLOCK pulse line. Repeating the timing of the scan test clock signal causes the contents of the flip-flop to be removed in series from the maskable gate array unit. For the flip-flop symbol, /S I represents a scan test input pin, / SO represents a scan test output pin, and SCAN represents a scan clock input pin. > Figure 18 illustrates an interface circuit and a maskable gate array portion 110 in accordance with another embodiment. The illustrated I / 0 terminal is the I / 0 terminal of the integrated circuit 1 0 9 . The cell blocks labeled A, B, C, D, E, F, G, L, M and N are the configuration register bits of the built-in register. As noted above, the build register can be written via serial interface 148 (see Figure 3). The control signal CONTROL [40:0] contains the following inputs: sbufa, resetn, gmaina, dctina, hsync, vsync, vx-ctrll3[7:0], vx-ctrll4[7:0]; and the following output: smxoa, gmxo a , dcti mx a , vx_ctrll5[7:0] and B vx_ctrll6[7:0]. During system development, it will be packaged on the integrated circuit board of the system board; the following I/O terminals are coupled to the external FPGA: SI[15:0], S0[15:0], SO[47: 16], EXTCLK Extended output or input K, D0[23:0], DI[23:0], OUTCLK OUTPUT, OSD CLOCK, OSD OUTPUT and OSD INPUTS ° Although for the purpose of instruction, the present invention relates to certain specific embodiments. Note, but the invention is not limited thereto. For example, an i TAG tap head controller can be used to place the integrated circuit in the test mode serial interface function 128549.8. In addition to a maskable program, the ASIC can be developed to implement a manufacturer-specific:: functionality. The programmable unit 4 can include other circuits that can be used by a particular manufacturer, such as a small processor's memory area. 'Small segment analog circuits, I / 0 circuits, bus interface circuits, and special circuits that can be seen in other small segments of the actual system subset of different types of consumer electronics manufacturers (for example, fully developed or standard cell circuits) . These small sections of circuitry can be patched together and suitably programmed by the programmable inter-connected structure of the maskable gate array section 4. The programmable interconnect structure can be programmed, for example, by changing only one layer of conductive vias, wherein, as described above, the conductive vias are the same conductive via layers that define a maskable gate array. The interface circuit does not need to include a set of outputs and a set of inputs. The interface circuitry can, for example, include bidirectional communication between the AS I C and the external FPGA across a bus or other link. The control of the interface circuit does not need to span a serial interface from an external control source. The interface circuitry can be controlled in any suitable manner, for example, via the I/O terminal, the AS I C can be programmed to communicate with the external FPGA across the I/O terminal. The interface circuit can be placed in its test mode by placing a particular configuration on one or more I/O terminals of the ASIC. The maskable gate array portion 110 can also directly communicate with the memory control block 1 2 3 in some embodiments, so that the mask programmable gate array portion 1 1 can cause a memory control block 123 retrieves a piece of information from SDRM1 15 and forwards the information to a designated point, such as a maskable gate array 1 1 〇. Similarly, the maskable gate array portion 1 1 can communicate directly with the memory control block 1 2 3 to cause the memory control block to capture certain information (eg, from the mask programmable gate array portion). The information is stored in SDRAM1 15. When a block is not substantially 1285498, the hardware part is used to respond to the command temple's masked programmable gate array to issue such a command to the block. In one example, the 'memory control block 1 2 3' contains a DMA engine that executes the DMA commands it receives from a DMA command line. The maskable gate array 1 1 0 can push a life onto the DMA command queue of the DMA engine so that the DMA engine later receives the command from the DMA command and executes the DMA command. The DMA command can contain the source and destination indications of the information to be moved. In an example, the mask programmable gate array 1 1 〇 can be directly coupled to an additional external memory volume circuit of the production version system in a production version system. Contrary to the video processing power, the "substantially non-developed hardware can implement the still image processing function" and contrary to the video enhancement function, the mask programmable gate array can implement the static image enhancement function. Therefore, various modifications, adaptations and combinations of the various features of the described embodiments can be made without departing from the scope of the invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a simplified diagram of a method and a novel integrated circuit according to an embodiment. Figure 2 is a simplified block diagram of a system developed in accordance with the method of Figure 1 and the integrated circuit. Figure 3 is a more detailed block diagram of the integrated circuit of Figure 2. The substantially non-customized hardware portion occupies substantially more integrated circuit area than the maskable gate array portion. In a specific embodiment of the integrated circuit illustrated in Fig. 3, substantially no hardware portion is occupied, and an integrated circuit area of 40 mm 2 is occupied, but the maskable gate array portion is stored at 3 mm 2 . -35- 1285498 Figure 4 - 1 7 illustrates a specific example of the maskable gate array of the integrated circuit of Figure 3. Figure 18 illustrates an interface circuit in accordance with another particular embodiment. Representative symbolic description of the main part

9,10,16,18,169 11,14,15 12,13,1 34,1 37,142,1 6 1 17 101 102 103 Electronic consumer device system special application integrated circuit non-developed hardware metal layer mask Program gate array arrow tail signal source metal layer arrow destination output signal destination FPGA development system serial interface I / terminal line 162 multiplexer external FPGA video display system antenna coaxial cable -36- 1285498 104 105 106 107 108 109,149 111 112 _ 113 114 115 1 16 117 118

119,120 121,124 1 22,1 25,1 30,1 73,1 32,1 41,1 65 123 127-129 13 1 133 135 1 3 6 , 1 3 9 , 1 5 6 - 1 60,1 63, 1 66 - 1 68 138 Video source tuner IF demodulator analog to digital converter display processor integrated circuit driver cathode ray tube liquid crystal display screen plasma display random access memory microcontroller audio circuit speaker digital video input 埠Format Detector FIFO Memory Control Block Buffer Output Bus Alignment Scaler Enhancement Block Busbar Color Space Conversion Block -37- 1285498 4 <

140 color mixing multiplexer 141 gamma correction and dithering block 143 digital to analog converter 144 dual pixel block 145, 146 signal terminal 150 data line 15 1 clock line 152 built register 153, 154 phase locked loop circuit 155 crystal Stone 190 Noise Reduction Block 38-

Claims (1)

1285498 ^ r No. 94 1 3 1 468 "There are essentially non-developed parts that provide pixel applications to the maskable part of the multi-color space format to develop special application integrated circuits and methods" patent case (2006) 1 January revision) X. Patent application scope: 1. An integrated circuit that can be used for special applications, including: - substantially non-developed hardware; and - mask programmable logic, coupled to the mask The program logic unit receives the first pixel data from the substantially non-developed hardware in a first color, spatial format, and receives the second pixel data from the substantially non-developed hardware portion in a second color space format. 2. The integrated circuit of claim </ RTI> wherein the substantially non-customized hardware portion comprises a color space conversion circuit. 3. The integrated circuit of claim 1, wherein the substantially non-developed hardware portion implements a video processing function, and wherein the mask programmable logic portion is implemented by masking the program Features. 4. The integrated circuit of claim 1, wherein the mask programmable logic unit is coupled to receive the first non-developed hardware portion in a first color space format via a first parallel bus. The pixel data, the mask programmable logic unit further receives a signal from a substantially non-developed hardware portion indicating whether there is valid pixel data on the first parallel bus. 5. The integrated circuit of claim 4, wherein the mask programmable logic unit is coupled to output the third pixel data in a first color space format to a substantially non-developed manner via a second parallel bus. Hardware part, the mask can be The 1285498 logic outputs a signal to a substantially non-developed hardware portion representing whether there is valid pixel data on the second parallel bus. 6. The integrated circuit of claim 1, wherein the mask programmable logic is programmed to perform a promotional function on the first pixel data, the enhancement function being from the following group: White level enhancement, black level enhancement, color histogram extension, skin color enhancement, horizontal DLTI, peak filtering, display control, and DCTI (digital color transient correction), and wherein the first color space format is the YCbCr color space. 7. The integrated circuit of claim 1, wherein the mask programmable logic portion is programmed to perform a enhancement function on the first pixel data, the enhancement function being from the following group: Gamma correction and dithering, wherein the first color space format is an RGB color space. 8. The integrated circuit of claim 1, wherein the substantially non-developed hardware portion substantially occupies more of the integrated circuit die area than the mask programmable logic portion. 9. The integrated circuit of claim 1, wherein the integrated circuit is located in a video display device.如. The integrated circuit of claim 1, wherein the substantially non-developed hardware includes a configuration register and wherein the substantially non-developed hardware can be written by configuring information Into the configuration register to be built. i. The integrated circuit of claim 1, wherein the substantially non-developed hardware portion is implemented by at least a part of the standard cells. 1 2. The integrated circuit as claimed in claim 11 further includes: an external FPG A bonded to the interface circuit of the integrated circuit. -2- 1285498 I___ι________ ί Repair A) Replacement Page 1 3 · An integrated circuit that can be used for special applications, including: - Substantially non-developed hardware; and - Mask programmable logic, coupled to the mask The mask programmable logic receives the pixel data from the substantially non-developed hardware in a selectable one of a first color space format or a second color space format. 1 4 . The integrated circuit of claim 13 wherein the integrated circuit comprises: - a multiplexer, the multiplexer being operative to supply pixel data to the mask in a first color space format The logic supplies the pixel data to the mask programmable logic in a second color space format. 1 5 . The integrated circuit of claim 14 wherein the multiplexer is part of a maskable logic portion. 16. The integrated circuit of claim 14, wherein the multiplexer is substantially non-developed as part of the hardware portion. 1 7 · The integrated circuit of claim 13 of the patent scope further includes: bonding an external FPG A to the interface circuit of the integrated circuit. 18. A method for formulating a special application integrated circuit, comprising: implementing a video processing function in a substantially non-developed hardware portion of an integrated circuit, the substantially non-developed hardware portion having a first color a spatial format and a second color space format output pixel data; receiving pixel data in a first color space format onto a maskable logic portion of the integrated circuit; and receiving pixel data in a second color space format to The mask of the integrated circuit is above the programmable logic. Repair of the month of 1285498 (3⁄4 is replacing the page **- ' % .t:U -----------------,,-..一' 1 9 ·If the patent application scope The method of item 18, wherein the first color space format is a YCbCr color space format, and wherein the second color space format is an RGB color space format. 20 - an integrated circuit capable of formulating a special application Included: - a substantially non-developed hardware portion that implements a video processing function; and a device that receives pixel data for use in a first color space format from a substantially non-developed hardware portion, and The body receives pixel data in a second color space format, wherein the device is maskable. 21. The integrated circuit of claim 20, wherein the device includes a number of masks Logic, and wherein the device is programmed as a mask to implement a video enhancement function. 22. The integrated circuit of claim 21, wherein the substantially non-developed hardware portion comprises a color space conversion circuit .