1283968 九、發明說明： 【明所屬之技術領域】 本發明係有關於一種頻率產生器（frequency synthesizer);尤指在一 種適用於鎖相迴路(Phase-Locked Loop，PLL)頻率合成器之低雜訊充電幫 浦(charge pump)。 【先前技術】 由於近年來蜂巢式通訊系統的快速成長，對於高性能射頻(radi〇 frequency ’ RF)積體電路元件的需求量因此而增加。本地振盪器（i〇cai osci 1 lator ’ L0)則為構建這些糸統的重要元件之一。在現今的無線電收發 器（RF transceiver)裡，振盪器通常嵌入於合成器内，以求達到一個精準 的輸出頻率。因鎖相迴路(phase-locked loop，PLL)技術可於鎖定狀態下， 根據輸入訊號的頻率，輸出一所要頻率，效能可以達成一般射頻電路之設 計標準，故被廣泛的運用。 鎖相迴路技術具有整體性、低功耗、晶片面積小、高可靠度及具有功效 可預期等優點。由於整數N倍頻率合成器（integer-N frequenCy synthesizer)的比較頻率(comparison frequency)亦即相位偵測器的參考 頻率，相等於通道間距(channel spacing)或步階(step size)的大小。因 此，為了精確控制輸出訊號的頻率，必須採用低頻的參考信號，再加上一 窄頻寬(bandwidth)的迴路濾波器以維持系統的穩定。但是濾波器的頻寬越 小，頻率合成II的調整時間就，鼠在需要高速切換合成鮮的系統 時，便會落入速度及鮮準度之兩難。另一個問題則是位於載波頻率 (carrier freqUenCy)附近產生的相位雜訊(phase⑽丨％)。分頻比率 (divide ratio)越高，濾波器通道内的相位雜訊就會越嚴重。據知，在分 頻比為N倍整《倍醉合細t，通道⑽她雜訊(ίη__油咖 nmse)大約高於系統内的雜訊基準(n〇ise fl〇〇r) 2〇 ι〇伙仙。此外， !283968 輪出訊號的突波(spur)亦和迴路頻寬有關。因此在迴路頻寬及迴路效能間 存在一個損益權衡的問題。 採用分數N頻率合成（fractional-N frequency synthesis)技術可以使 用較通道間距大的比較頻率。此一技術在使用一最高可能之比較頻率時， 在相同的通道間距下，令分頻比低於整數N倍合成器的分頻比，可以相當 地降低頻道内相位雜訊。同時，使用一較高的比較頻率亦意謂較寬迴路頻 寬的可能性，故可較快達細率鎖定。而使賊通道間距高之比較頻率則 疋可以減少輸出職的突波。然而，N倍分數技術可能使得迴路裡存在週期 性干擾(disturbances)，而引起大分數突波(frac1：i〇nai spurs)。 充電幫浦電路為鎖相迴路裡_根本的單位，因為這個電路主宰了電壓控 制震盪l§(voltage control 〇sciliator)輸出頻率，因此，要實現一具高 速切麵率的無線發ϋ，便需制_高速充前浦。酬，高速充電 幫浦在切換頻率日B__swltehln請脱)可能於輸出訊號裡，造成 尖波(spike)。這種狀況將降低鎖相迴路或頻率合成器的效·，而在實現一 無線電收發器時，使得訊號的品質及明確性降低。因此，由消減雜訊的觀 點來看’降低充電幫浦的操作速较可行的。但由於充電幫浦的操作速率 為比較頻率所操控，若紐較解提高贿得充電幫雜訊基準增高。因 此在充電幫浦的操作速率及雜訊效關存在_個損益權衡的問題。 有鑑於此，本發明的主要目的，在於提供一低雜訊充電幫浦。 【發明内容】 有鑑於此’本發明的主要目的，在於減低頻率合成時產生之雜訊。 根據上述之目的，本判提出—翻於鎖相迴路⑽)頻率合成器之低 ^充^4縣伽的—方面來說，該充電幫浦包含有—時間控制哭 (tl_g咖㈣㈣及數個充電幫浦電路⑽卿-卿_lts)。該時 間控制器，藉轉收-參考錢，以產缝個她轉疊之魏訊號。每 1283968 一致能訊號的頻率相當於將該參考信號的頻率除以該致能訊號之個數。該 等數個充電幫電路，並聯在-起，並根_等致能訊麟以時序交錯 (time interleaved)的方式運作，分別於一第一及一第二控制訊號作用時， 產生數個淨輸出電流，而該等淨輸出電流群則匯流聚集產生一充電幫浦電 流。因此’每-充電幫浦電路的運作解為該參考㈣解之兄倍，而爪 則係該等充電幫浦電路之個數。 就本發明的另-方面來說，本發明亦揭式了一低雜訊頻率合成器，包含 #：-fe^I^I§(lowpass filter) (voltagecontrol oscillator)、-分頻器（frequency divider)、一相位細器⑽咖 detector)、以及數個充電幫浦電路(咖哪—p卿。簡⑽。該等數個 充電幫浦電路，並聯在-起，並以時序交錯(time—interleaved)的方式提 供-充電幫浦電流。該低通紐器，根據該充電幫浦電流，產生一頻率控 制電壓。該電壓控制紐H，根據該鮮控制，提供—具可變頻率之 輸出日植。該分，將該輸出日械依照預定分頻比㈣池邮〇)予以 分頻，輸ii-已分植。該她侧器，細該已分麟脈及—參考信 號門之相位差用以產生_第—及―第二控制訊號。該雜個充電幫浦電 路則^刀別根據口亥第-及该第二控制訊號產生數個淨輸出電流。因此，該 寻數個淨輸電流會s流於—共同輸出端產生該充電幫浦電流。 在本發明的-個實施例中，一低雜訊充電幫浦可由一時間控制器 *ng controller) ^ (reference current source) 個充電幫浦電路所組成。該_控繼，藉由接收—參考㈣，以產生數 !283968 個相位不重豐之致m每―致能峨的頻率相當於將該參考信號的頻 率除以該致能訊號之個數。該參考電流源，職提供—偏壓電流。該等並 聯在-起之數個充電幫浦電路，具—制輸出端，且根據該等致能訊號群 以時序交錯的方式運作，分繼生數個淨輸出f流。_㈣輸出電流群 則匯流聚集於該共同輸出端產生—充電幫浦電流。每—充電幫浦電路包含 有兩個開關元件（switches)及兩個電流導引單元(current对沈贞职 units)。-第-開關元件，柄接至該參考電流源及接收一第一控制訊號， 當該第-控制訊號致能時，將該偏_流鏡射，以作為一充電電流(卿_叩 cUrrent)。-第-電流導引單元，祕至該第—開關元件及該共同輸出端 之間’用以導引該充電電流。另—方面，_第二開關元件雜接至該參考 电流源及接收-第二控制減，當該第二控制訊號致能時，將該偏壓電流 鏡射，以作為-放電電流(pump_d〇wn current)。一第二電流導引單元，耦 接至.亥第—開關元件及該共同輸出端之間，用以導引該放電電流。具體說 來’違第-及销二電流導引單元由時間控制騎產生—滅應致能訊號 所控制。當相對應致能訊號作用日夺，該充電電流便輸入該共同輸出端，而該 放電電流則由該制輪出端放出。如此—來，該共同輸出端便產生其中該 等淨輸出電流之一。 為使本發批上述目的、特徵和優點能更鶴易懂，下文特舉—較佳實 施例，並配合所附圖式，作詳細說明如下。 【實施方式】 第1圖為根據本發明之-鎖相迴_率合成器。此鮮合成器· 1283968 接收-頻率為‘的參考信號，產生-頻率4且相位與⑽㈣同步的 輸出時脈。如圖所示，此一頻率合成器100包含有一相位偵測器11〇、 一充電幫浦120、-低通濾'波器13G、-電壓控制震S|| 14G以及一分頻器 150。此-頻率合成器1〇〇更可進-步包含-時間控制器16〇及一鎖定_ 器（lockdetector·。相位侧器110可以偵測出似㈣及一個回授訊號 間的相位誤差，發送-控制訊號至充電幫浦12〇，使其輸出電流 至低通濾波器130或發送-控制訊號廣至充電幫浦12〇，使其令低通濾波 器130放出電流。典型的控制訊號⑽及厦為—個脈衝，且其寬度相當於 間的相位差。同時，轉接至鎖定偵測器17〇， 由偵測器17G做相位校準的檢測。當似：與似㈣的相位—致時，侧器 170便進入鎖定狀態（i〇cked c〇nditi〇n),並發送出一個狀態訊號& ,以 藉此顯示進入鎖定狀態。時間控制器議亦接收參考訊號及由侧器 170輸出之狀態訊號么^。當^㈣顯示已進入鎖定狀態時，時間控制器16〇 會產生數個相位不重豐(n〇n-〇verlapping)之致能訊號，其中，每一致能訊 號的頻率相當於將該等參考信制鮮除以錄訊號之雛。在此， 若致能訊號有mj固’則致能訊號群則可表示為1位元的訊號取巧。在尚 未進入鎖定狀糾’時間控繼⑽則會載人—預設值至办:1]，以提供頻 率擷取及追蹤用。 在本發明中’充電幫浦12〇由所個充電幫浦電路並聯一起且皆接收控制 机號丨7?及訊號zw。如圖;[所示，此奶個充電幫浦電路標示為12〇—卜i2〇—m， 且充電幫浦電路120-1〜1201分別接收相對應的訊號咖:1]，再根據訊號1283968 IX. Description of the invention: [Technical field to which it belongs] The present invention relates to a frequency synthesizer; in particular, to a low frequency suitable for a phase-locked loop (PLL) frequency synthesizer Charge pump. [Prior Art] Due to the rapid growth of the cellular communication system in recent years, the demand for high-performance radio frequency (RF) integrated circuit components has increased. The local oscillator (i〇cai osci 1 lator ’ L0) is one of the important components for building these systems. In today's RF transceivers, the oscillator is typically embedded in the synthesizer to achieve a precise output frequency. Because the phase-locked loop (PLL) technology can output a desired frequency according to the frequency of the input signal in the locked state, the performance can achieve the design standard of the general RF circuit, so it is widely used. The phase-locked loop technology has the advantages of integrity, low power consumption, small wafer area, high reliability, and predictable power efficiency. Since the comparison frequency of the integer-N frequenCy synthesizer, that is, the reference frequency of the phase detector, is equal to the channel spacing or the step size. Therefore, in order to accurately control the frequency of the output signal, a low-frequency reference signal must be used, plus a narrow-bandwidth loop filter to maintain system stability. However, the smaller the bandwidth of the filter, the adjustment time of the frequency synthesis II, the mouse will fall into the dilemma of speed and freshness when it needs to switch the synthesized system at high speed. Another problem is the phase noise (phase(10)丨%) generated near the carrier frequency (carrier freqUenCy). The higher the divide ratio, the more severe the phase noise in the filter channel. It is known that in the frequency division ratio is N times the whole process, the channel (10) her noise (ίη__油咖nmse) is higher than the noise standard in the system (n〇ise fl〇〇r) 2〇 〇〇伙仙. In addition, the spur of the !283968 turn-off signal is also related to the loop bandwidth. Therefore, there is a trade-off between the loop bandwidth and the loop performance. The fractional-N frequency synthesis technique can be used to compare frequencies with larger channel spacing. In this technique, when using the highest possible comparison frequency, the division ratio is lower than the integer N times the synthesizer's division ratio at the same channel spacing, which can considerably reduce the phase noise in the channel. At the same time, the use of a higher comparison frequency also means the possibility of a wider loop bandwidth, so that a finer lock can be achieved faster. The comparison frequency of the thief channel spacing is high, so that the output surge can be reduced. However, the N-fold fraction technique may cause periodic disturbances in the loop and cause large fractional surges (frac1: i〇nai spurs). The charging pump circuit is the _ fundamental unit in the phase-locked loop, because this circuit dominates the voltage control 〇sciliator output frequency. Therefore, to achieve a high-speed tangent rate wireless hairpin, it is necessary to manufacture _High speed charge before the Pu. Remuneration, high-speed charging The pump is switched off on the switching frequency day B__swltehln) may cause spikes in the output signal. This condition will reduce the effectiveness of the phase-locked loop or frequency synthesizer, and the quality and clarity of the signal will be reduced when implementing a radio transceiver. Therefore, from the point of view of reducing noise, it is more feasible to reduce the operating speed of the charging pump. However, because the operating speed of the charging pump is controlled by the frequency of comparison, if the New Zealand solution is improved, the charging of the bribe will increase the noise reference. Therefore, there is a problem of profit and loss trade-off between the operation rate of the charging pump and the noise efficiency. In view of this, the main object of the present invention is to provide a low noise charging pump. SUMMARY OF THE INVENTION The main object of the present invention is to reduce noise generated during frequency synthesis. According to the above purpose, the present invention proposes to turn over the phase-locked loop (10) of the frequency synthesizer, and the charging pump includes - time control crying (tl_g coffee (four) (four) and several Charging pump circuit (10) Qing-Qing _lts). The time controller, by means of the transfer-reference money, was used to produce a Wei signal that she had folded. The frequency of the uniform signal per 1283968 is equivalent to dividing the frequency of the reference signal by the number of the enable signals. The plurality of charging circuits are connected in parallel, and the roots are operated in a time interleaved manner to generate a plurality of nets in the case of a first and a second control signal. The current is output, and the net output current groups are converged to generate a charging pump current. Therefore, the operation of the per-charge pump circuit is the brother of the reference (4) solution, and the claws are the number of the charging pump circuits. In another aspect of the invention, the invention also discloses a low noise frequency synthesizer comprising: #:-fe^I^I§(lowpass filter) (voltagecontrol oscillator), -frequency divider (frequency divider) ), a phase cleaner (10) coffee detector, and several charging pump circuits (Cana-P Qing. Jane (10). These several charging pump circuits, connected in parallel, and time-interleaved (time-interleaved) The method provides a charging pump current. The low-passing device generates a frequency control voltage according to the charging pump current. The voltage control button H, according to the fresh control, provides a variable frequency output. This point, the output of the Japanese machine according to the predetermined frequency division ratio (four) pool postal) is divided, the input ii- has been planted. The side of the side, the phase difference between the reference signal and the reference signal gate is used to generate the _th- and second control signals. The hybrid charging pump circuit generates a plurality of net output currents according to the mouth-and-second control signals. Therefore, the number of net currents flowing s will flow to the common output to generate the charging pump current. In an embodiment of the invention, a low noise charging pump can be composed of a time controller * ng controller) ^ (reference current source) charging pump circuit. The _ control, by receiving - reference (four), to generate the number of !283968 phases is not heavy. The frequency of each enable 相当于 is equivalent to dividing the frequency of the reference signal by the number of the enable signal. The reference current source is provided by a bias current. The plurality of charging pump circuits are connected in series, and the output terminals are operated in a time-interleaved manner according to the group of enabled signals, and a plurality of net output f streams are successively generated. _ (4) Output current group The convergence is concentrated at the common output to generate a charging pump current. Each of the charging pump circuits contains two switching elements and two current steering units (current to sinking units). a first switching element, the handle is connected to the reference current source and receives a first control signal, and when the first control signal is enabled, the partial current is mirrored as a charging current (clear_叩cUrrent) . a first current guiding unit between the first switching element and the common output terminal for guiding the charging current. On the other hand, the second switching element is mixed to the reference current source and the receiving-second control is reduced. When the second control signal is enabled, the bias current is mirrored as a discharge current (pump_d〇). Wn current). A second current guiding unit is coupled between the first switching element and the common output terminal for guiding the discharging current. Specifically, the 'discrimination-and-sale two-current guiding unit is controlled by the time-controlled rider------------- When the corresponding enable signal is active, the charging current is input to the common output terminal, and the discharge current is discharged from the output end of the wheel. As such, the common output produces one of the net output currents therein. In order to make the above objects, features and advantages of the present invention more comprehensible, the following detailed description of the preferred embodiments and the accompanying drawings are set forth below. [Embodiment] Fig. 1 is a phase-locked back-rate synthesizer according to the present invention. This fresh synthesizer · 1283968 receives a reference signal with a frequency of ', produces an output clock with a frequency of 4 and a phase synchronized with (10) (d). As shown, the frequency synthesizer 100 includes a phase detector 11A, a charging pump 120, a low pass filter 13G, a voltage control oscillator S|| 14G, and a frequency divider 150. The frequency synthesizer 1 further includes a time controller 16 and a lock detector. The phase side device 110 can detect a phase error between (4) and a feedback signal, and send - Control signal to the charging pump 12〇, so that it outputs current to the low-pass filter 130 or the transmit-control signal to the charging pump 12〇, causing the low-pass filter 130 to discharge current. Typical control signal (10) and It is a pulse, and its width is equivalent to the phase difference between the two. At the same time, it is switched to the lock detector 17〇, and the detector 17G performs the phase calibration detection. When the phase is similar to the phase (4) The side device 170 enters a locked state (i〇cked c〇nditi〇n), and sends a status signal & to thereby enter the locked state. The time controller also receives the reference signal and is output by the side device 170. The status signal is ^. When the ^ (4) display has entered the locked state, the time controller 16 产生 will generate a number of phase non-heavy (n〇n-〇verlapping) enable signal, wherein the frequency of each consistent signal Equivalent to dividing the reference letter by the number of the recording signal Here, if the enable signal has mj solid', the enable signal group can be expressed as a 1-bit signal. If the lock has not yet entered the lock, the time control (10) will carry the person-preset value to: 1], to provide frequency acquisition and tracking. In the present invention, 'charging pump 12' is connected by a charging pump circuit in parallel and both receive control unit number ?7? and signal zw. As shown in the figure; The milk charging pump circuit is labeled as 12〇—i2〇—m, and the charging pump circuits 120-1~1201 respectively receive the corresponding signal coffee: 1], and then according to the signal
I 1283968 取1] ’以時序交錯的方式操作。當 頻率為心// 疋狀心牯母一充黾ΐ浦電路運作 …亚輸出電流/八7至共同輪出 同輸出端1峨生1電細心峨纏職 们頻壓控制_ 14◦，電壓控制震_ 壓嘛爾輸出時脈％的辭仏，其中輸出頻率心是可變動 的刀為150則是用來將該似邮的頻率根據預定分頻比予以分頻，輸出 li〇 m ^150 ^ 〇 ^ 夕>卜销請亦可是i分數嶋邮麵_ l裏勺·代表小數點，N及f分別代表分頻比的整數和小數部份。 為使本發.特徵能更明顯紐，下文特舉一實施例—充電幫浦丨2〇。在 此的電晶體包含11通道(n如聰1)以及p通道的MOS電晶體，皆具有一個閘 極(gate)、-個汲極(drain)及一個源極(s〇urce)。電晶體是一個對稱 勺衣置口此真正;及極及源極的指定只能在電極加上電壓時判斷。關於 本文中雜和祕的命名是以最歧使關命絲命名的。請參關2，舉 例說明，充電幫浦120包含有但並不侷限只能有，兩個充魏浦電路^ 及120-2，擁有一共同輸出端125。參考電流源21〇提供充電幫浦12〇一個偏 1¾仙。電晶體Q1A-B、Q2A-B及Q3A-B是一個電流鏡的結構，提供一電 流至共同輸出端125。同樣地，電晶體Q4A-Β、Q5A-B及Q6A-B亦是一類似的 電流鏡結構，用來由共同輸出端125放出一電流。 每一個充電幫浦電路都會根據控制訊號呀及浙於内部輸出一充電電 1283968 流或使放出-放電電流。如圖所示，充電幫浦電路⑽韻電晶歸c、q2c、 Q5C^ Q6C^ Q7A-F^»ZW , ^tMQ1D . ⑽、Q5D、Q6D、Q8A-F以及Q8U-Z組成。每個充電幫浦電路皆具有相同的 架構，且可分成主要幾個部份，包括有兩個_元件及兩個電流導引單元。 就充電幫浦電路12G-1而言，電晶體_啊做為開關，分別在閘極接收控 制訊號砂及皿。電曰曰曰师A—F在充電幫浦電路⑽一版演著電流導引的角 色’1¾接於開關元件QIC及共同輸出端125之間，為一電流導引單元幽。同 樣地，電晶體Q7U-Z構成-電流導引單元226，雛至開關元件_及共同輸 出端125間。開關電晶體Qlc及Q6C皆經由電流鏡電路輕接至參考電流源 210。電晶體Q2C，相對應於電流鏡内電晶體卿，則是位於開關元件肌及 驗導引單tl224之間。在本發明的一個實施例中，電流導引單元224可規 劃為-閘極關模式，其巾，電晶娜級電晶贿_接成—個差動對； 此差動對分別由電晶體Q7C—D及電晶體奴£_{?控制。電晶體Q7a的汲極接地， 閑極則福接至電晶體Q7C及Q7D峡極。相同地，電晶體⑽的沒極接至共同 輸出端125，閘極則耦接至電晶體Q7E及電晶體Q7F的汲極。電晶體Q7A及電 晶體Q7B的源極則一起連接至電晶體Q2C的汲極。電晶體Q7])的汲極耦接至一 偏壓電壓心，且於閘極接收致能訊號研丨]。電晶體Q7C的源極則是耦接至一 ^、應黾壓^^，且於閘極接收致能訊號即]。另一方面，電晶體QW的源極李馬 接至偏壓電壓匕，且於閘極接收致能訊號面]。電晶體Q7E的源極則是耦接 仏應電’且於閘極接收致能机號耶]。訊^虎即]為訊號即]的補數 (complement)。此外，電晶體q2C的閘極耦接至電晶體q2^q2B的閘極。電 1283968 晶體QIC的源極墟至供應電仏，沒極至電晶體卿的源極且於閑極. 接收控制訊號UP。 同樣地’電晶體Q5C的連接於開關元件Q6C及電壓導引單元226之間，並 相對應於電流鏡内電晶體⑽。在本發明的一個實施例中，電流導引單元腳 亦規劃為閘極開關模式，其中，電晶體_及電晶體⑽雛成一差動對； 此差麟分別由電晶體Q7X-W及電晶體Q7Y-Z控制。電晶體q7u的沒極接至供 應電壓，閘極則耦接至電晶體Q7X及Q7W的汲極。同樣地，電晶體阶^的 . 汲極接至共同輸出端125，閘極則耦接至電晶體q7Y及電晶體Q7Z的汲極。晶 修 體Q7U及電晶體Q7V的源極則一起連接至電晶體Q5C的汲極。電晶體Q7X的源 極減至另-偏壓電壓&，且於閘極接收致能訊號雨。電晶體Q7W的源極 則是接地，且於閘極接收致能訊號可丨]。另一方面，電晶體Q7Z的源極耦接 至偏壓電壓匕2，且於閘極接收致能訊號可1]。電晶體Q7Y的源極則是接地， 且於閘極接收致能訊號^]。此外，電晶體Q5C的閘極耦接至電晶體Q5A及Q5B 的閘極。電晶體Q6C的源極則是接地，汲極耦接至電晶體Q5C的源極且於閘 極接收控制訊號厦。 參 下文將參照圖2及圖3說明充電幫浦電路120-1及120-2的運作狀況。 操作時，電晶體Q1B-D會於控制訊號π作用時打開，使得偏壓電流鏡射 為充電電流/㈣及/wp2 ;而電晶體Q6B-D則於控制訊號懦作用時打開，使得 偏壓電流/^鏡射為放電電流/制及/紀。充電電流及放電電流分別 與偏壓電流/_的大小成比例。此外，每一充電電流值實質上相等於每一放 電電流值。在致能訊號則作用時，即為邏輯1，雨為〇時；電晶體Q7C、 12 1283968 咖、Q7W及Q7Z會被打開，而電晶體⑽⑽⑽及奶則是被關上 在此時，«電壓師⑽ntlal她鄕）L身㈣將會分別被調至夠 南或夠低的電壓值，而其他的差動電壓％及。亦是會被分別調至夠低或 夠高的電壓值。因此當電晶體⑽及Q7V被打開運作時，電晶雜及_ ,被關上，流經電晶體Q2C的電流心會輸出至共同輪出端⑵，同時流 ’·、二电晶體Q5C的電流/制則會由共同輸出端125放出。 當致能訊號停止作用時，即·為邏輯〇，雨為邏輯i的時候一 轉Q7D、Q7E、Q7X謂會被打開，而電晶隸、q7f、_及^ 疋_上。在這鋪況下，聽電壓〜及％將會分職糊低或夠高 的電壓值’而其他的絲電壓％及‘亦會分別被調至夠高或夠低的^ 2因此當電晶⑽A被打開運作時，電晶體Q7B則會被關切停止輪出 毛流/明至該共同輸出端125 ’同時電晶體_被打開，電晶體⑽則會被 哥上％机J制便會經由電晶體_流向供應電壓&，以停止電流/由节 共同輪出端125放出。因此，當致能訊號刚停止侧時，充電幫浦"電路X 12〇-ι的淨輸出綠將被電流導引單元224及226給阻擋住。因為致能诚 二二的鮮都是1，但是相位不重疊，故同一時間内，只有一二 电農浦$路可以提供電流，縣提高或降低鮮控制電歡，其它的充電 “:路顺畴’贿錢供電流。在這個實關巾，充電幫浦電路12〇—1 可以雜電流U翻輸出端⑵或將電流L由該共同輸_ 125放出， 充电’浦电路120一2則在此時被使失能，而無法將電流I 1283968 takes 1] 'operating in a time-interleaved manner. When the frequency is the heart / / 疋 牯 牯 一 一 一 一 电路 ... 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚 亚Controlling the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ^ 〇^ 夕> 卜 请 请 请 卜 卜 卜 卜 卜 i i i i i i i · · · · · · · · · · · · · · · · · · · · · 代表 · In order to make the features of the present invention more obvious, an embodiment is described below - a charging pump. The transistor here includes 11 channels (n, such as Sung 1) and p-channel MOS transistors, each having a gate, a drain, and a source (s〇urce). The transistor is a symmetrical scoop of the mouth; this is true; and the designation of the pole and source can only be judged when the electrode is applied with voltage. About the naming of the miscellaneous and secret in this article is named after the most ambiguous. Please refer to 2, for example, the charging pump 120 includes but is not limited to only two, the two charging Weipu circuit ^ and 120-2, has a common output 125. The reference current source 21〇 provides a charge of 12 4 仙. Transistors Q1A-B, Q2A-B, and Q3A-B are a current mirror configuration that provides a current to a common output 125. Similarly, transistors Q4A-Β, Q5A-B, and Q6A-B are also a similar current mirror configuration for discharging a current from a common output terminal 125. Each charging pump circuit will discharge or discharge the discharge current according to the control signal and the internal output of a charging electric 1283968. As shown in the figure, the charging pump circuit (10) is composed of c, q2c, Q5C^Q6C^Q7A-F^»ZW, ^tMQ1D. (10), Q5D, Q6D, Q8A-F and Q8U-Z. Each charging pump circuit has the same architecture and can be divided into major parts, including two_components and two current steering units. In the case of the charging pump circuit 12G-1, the transistor _ ah is used as a switch, and the control signal sand and the dish are respectively received at the gate. The electrician A-F is connected to the switching element QIC and the common output terminal 125 in the charging pump circuit (10). The current steering angle is connected to the switching element QIC and the common output terminal 125. Similarly, the transistor Q7U-Z constitutes a current guiding unit 226 which is connected between the switching element _ and the common output terminal 125. The switching transistors Qlc and Q6C are all connected to the reference current source 210 via a current mirror circuit. The transistor Q2C, which corresponds to the current mirror in the current mirror, is located between the switching element muscle and the test guide t1224. In an embodiment of the present invention, the current guiding unit 224 can be planned to be a gate-off mode, and the towel is electrically connected to the differential pair; the differential pair is respectively composed of a transistor Q7C-D and transistor slaves _{? control. The drain of the transistor Q7a is grounded, and the idle pole is connected to the transistor Q7C and Q7D. Similarly, the gate of the transistor (10) is connected to the common output terminal 125, and the gate is coupled to the drain of the transistor Q7E and the transistor Q7F. The sources of transistor Q7A and transistor Q7B are connected together to the drain of transistor Q2C. The drain of the transistor Q7]) is coupled to a bias voltage core and receives a enable signal at the gate. The source of the transistor Q7C is coupled to a ^, should be pressed ^ ^, and receive the enable signal at the gate]. On the other hand, the source of the transistor QW is connected to the bias voltage 匕 and receives the enable signal surface at the gate]. The source of transistor Q7E is coupled to 仏 电 and receives the enabler at the gate. The news is the complement of the signal. In addition, the gate of the transistor q2C is coupled to the gate of the transistor q2^q2B. Electricity 1283968 Crystal QIC source from the market to the supply of electricity, no end to the source of the crystal crystal and idle. Receive control signal UP. Similarly, the transistor Q5C is connected between the switching element Q6C and the voltage guiding unit 226, and corresponds to the intra-electron transistor (10). In one embodiment of the present invention, the current guiding unit foot is also planned as a gate switching mode, wherein the transistor _ and the transistor (10) are formed into a differential pair; the difference is formed by the transistor Q7X-W and the transistor respectively. Q7Y-Z control. The gate of the transistor q7u is connected to the supply voltage, and the gate is coupled to the drains of the transistors Q7X and Q7W. Similarly, the drain of the transistor is connected to the common output terminal 125, and the gate is coupled to the drain of the transistor q7Y and the transistor Q7Z. The source of the crystal repair body Q7U and the transistor Q7V are connected together to the drain of the transistor Q5C. The source of transistor Q7X is reduced to the other-bias voltage & and the enable signal is received at the gate. The source of the transistor Q7W is grounded and the enable signal is received at the gate. On the other hand, the source of the transistor Q7Z is coupled to the bias voltage 匕2, and the enable signal is received at the gate 1]. The source of the transistor Q7Y is grounded and receives the enable signal ^] at the gate. In addition, the gate of transistor Q5C is coupled to the gates of transistors Q5A and Q5B. The source of the transistor Q6C is grounded, the drain is coupled to the source of the transistor Q5C and receives the control signal at the gate. The operation of the charging pump circuits 120-1 and 120-2 will be described below with reference to Figs. 2 and 3. During operation, the transistor Q1B-D will be turned on when the control signal π acts, so that the bias current is mirrored as the charging current /(4) and /wp2; and the transistor Q6B-D is turned on when the control signal 懦 acts, making the bias The current / ^ mirror is the discharge current / system and /. The charging current and the discharging current are proportional to the magnitude of the bias current /_, respectively. In addition, each charge current value is substantially equal to each discharge current value. When the enable signal is active, it is logic 1 and the rain is 〇; the transistors Q7C, 12 1283968, Q7W and Q7Z are opened, and the transistors (10) (10) (10) and milk are closed at this time, «voltage division (10) ntlal her 鄕) L body (four) will be adjusted to a voltage value that is sufficiently south or low enough, and other differential voltages are equal. It is also adjusted to a voltage value that is low enough or high enough. Therefore, when the transistors (10) and Q7V are turned on, the electro-crystals and _ are turned off, and the current flowing through the transistor Q2C is output to the common wheel terminal (2) while flowing the current of the transistor Q5C. The system is then released by the common output 125. When the enable signal stops, ie, it is logical, when the rain is logic i, Q7D, Q7E, Q7X will be turned on, and the electric crystal is on, q7f, _ and ^ 疋_. Under this condition, the listening voltage ~ and % will be divided into low or high enough voltage values 'and the other wire voltage % and ' will be adjusted to be high enough or low enough ^ 2 so when the crystal (10) When A is turned on, transistor Q7B will be concerned about stopping the hair flow/light to the common output terminal 125' while the transistor _ is turned on, and the transistor (10) will be powered by the machine. The crystal_ flows to the supply voltage & to stop the current/discharge from the joint common wheel end 125. Therefore, when the enable signal is just stopped, the net output green of the charging pump "circuit X 12〇-ι will be blocked by the current guiding units 224 and 226. Because the two of the two are the same, but the phases do not overlap, so at the same time, only one or two electric farms can provide current, the county raises or lowers the fresh control electric, other charges ": smooth Domain 'bribery money for current. In this real off towel, charging the pump circuit 12〇-1 can be mixed current U (output) or the current L is discharged from the common output _ 125, charging 'pu circuit 120 2 is in At this time, it is disabled, and the current cannot be
Hr , . P 洳 2 铜 主 共同輸出端125或由其放出，反之亦然。 13 1283968 通常輸入一電路點（node)的電流為正，放出則為負。如圖3所示，充電 電流‘及‘可被表不為正向的波形而放電電流4及&則被表示為負向 白刪。根據克希荷夫電流定律(KlrchhQff s咖咖W，充電幫浦 電路120-1及120-2的淨輸出電流則可分別表示為：7 = 、· 〇' - 1 up\ - Idn'反 ㈣-42。電流4及會匯流於該共同輸出端125產生充電幫浦電汸i 已說明充電幫浦電路120-1及120-2以時序交錯的方式運作，且其速率 為傳統的充電幫浦的1/2，在使用相同的比較頻率下其雜訊改盖了 ' 聊2 = 6dB。因此，使用m個充電幫浦電路其雜訊便會改善加啊仙。孰 習此項技藝者應該知道，利用本發明的原理，便可思量使用其它的電晶體 技術來實現圖2的電晶體電路。 本發明雖以較佳實施例揭露如上，然其並非用以限定本發明，任何孰 習此項技藝者，在不脫離本發明之精神和範圍内，當可做些許的更動與潤 飾因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖為根據本發明之一鎖相迴路頻率合成器。 第2圖為根據本發明之—實施例，充電幫浦電路之示意圖。 第3圖為根據圖2的充電幫浦運作特徵之波形圖。 【主要元件符號說明】 〇〇鎖相迴路頻率合成器；110〜相位债測器；120〜充電幫浦； 〜低通據波器；14Q〜電壓控制震盪器；⑽〜分頻器； 160〜時間控制器;170〜鎖定侧;勝偏壓電流源； 概〜第-電流導料元；226~第二電流導引單元。 14Hr, . P 洳 2 The copper main common output 125 is either discharged or vice versa. 13 1283968 Normally, the current input to a circuit node is positive, and the current is negative. As shown in Fig. 3, the charging currents 'and ' can be represented as positive waveforms while the discharging currents 4 and & are represented as negative-direction white deletions. According to Kirchhoff's current law (KlrchhQff s café, the net output currents of the charging pump circuits 120-1 and 120-2 can be expressed as: 7 = , · 〇' - 1 up\ - Idn' (4) - 42. The current 4 and the current sinking at the common output terminal 125 generate a charging pump. The charging pump circuits 120-1 and 120-2 are illustrated to operate in a time-interleaved manner, and the rate is a conventional charging pump. 1/2, when using the same comparison frequency, its noise changed to ' Chat 2 = 6dB. Therefore, using m charging pump circuit, its noise will improve the increase. This skill should be It is to be understood that the crystal circuit of Figure 2 can be implemented using other transistor techniques using the principles of the present invention. The present invention has been disclosed above in the preferred embodiments, but is not intended to limit the invention, The scope of the present invention is defined by the scope of the appended claims, and the scope of the invention is defined by the scope of the appended claims. 1 is a phase locked loop frequency synthesizer in accordance with the present invention. 2 is a schematic diagram of a charging pump circuit according to an embodiment of the present invention. Fig. 3 is a waveform diagram of an operation characteristic of a charging pump according to Fig. 2. [Description of main component symbols] 〇〇 phase-locked loop frequency synthesizer; 110 ~ phase debt detector; 120 ~ charging pump; ~ low pass data device; 14Q ~ voltage control oscillator; (10) ~ frequency divider; 160 ~ time controller; 170 ~ lock side; win bias current source; ～〜第电流导导元;226~第二电流导导。 14