JP2000165234A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a PLL circuit where jitter is reduced and the highest operating frequency is increased while suppressing increase in its layout required area. SOLUTION: A PLL circuit mounted on an application specific integrated circuit ASIC is mainly configured with a PLL module PLL 1 that has a comparatively excellent external disturbance characteristic by using an internal voltage VPL that is generated by an internal voltage generating circuit VG and has a comparatively stable voltage for a main operating power supply and that has a comparatively high frequency multiple rate but a comparatively lower maximum operating frequency and generates an intermediate frequency clock signal PCLK based on a reference clock signal ECLK supplied externally and with a PLL module PLL2 that uses a power supply voltage VCC for a main operating power supply, has an external disturbance characteristic which is inferior to that of the PLL module PLL1, has a comparatively high maximum operating frequency, has less phase jitter because the frequency multiple rate is comparatively small, and generates an internal clock signal ICLK, based on the intermediate frequency clock signal PCLK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL (Phas).
e Locked Loop) circuit, for example, A
The present invention relates to a PLL circuit mounted on a logic integrated circuit device such as an SIC (application-specific integrated circuit) and a technique particularly effective for use in improving characteristics of the PLL circuit.

[0002]

2. Description of the Related Art There is a PLL circuit for generating an internal clock signal which is phase-locked to a reference clock signal supplied from the outside, and there is a logic integrated circuit device such as an ASIC including a modularized PLL circuit as a clock signal source. . P
The LL circuit selectively outputs an up signal or a down signal having a pulse width corresponding to a phase difference between the reference clock signal and the internal clock signal or a frequency-divided signal thereof. A charge pump circuit that generates a control voltage having a potential corresponding to the phase difference according to an up signal and a down signal, and a voltage control type oscillator that generates the internal clock signal with its oscillation frequency controlled according to the potential of the control voltage. Including. Generally, the frequency of the internal clock signal generated by the PLL circuit is an integer multiple of the externally supplied reference clock signal. Therefore, the frequency of the reference clock signal to be externally supplied can be reduced as compared with the machine cycle of a digital system including an ASIC or the like, and the cost of the transmission path can be reduced.

[0003]

Prior to the present invention, the present inventors engaged in the development of an ASIC equipped with a PLL circuit and noticed the following problems. That is, A
The machine cycle of digital systems including SIC etc.
Although the speed is still increasing, the frequency of the externally supplied reference clock signal is subject to restrictions on the transmission path. Therefore, a method has been taken to deal with this by exclusively increasing the frequency multiplication factor of the PLL circuit. I have. However, when the frequency multiplication factor of the PLL circuit is increased, the frequency of the phase comparison between the reference clock signal and the internal clock signal by the phase comparison circuit is correspondingly reduced, the feedback loop characteristic is reduced, and the jitter of the PLL circuit is increased. This is particularly serious when the frequency multiplication factor of the PLL circuit is not an integer ratio and a frequency dividing circuit is also provided on the reference clock signal side, and the phase comparison frequency of the PLL circuit further increases on the reference clock signal side. It is reduced to one division ratio of the dividing circuit provided.

In order to cope with this, the present inventors have proposed that an internal voltage having a relatively stable potential is generated based on an externally supplied power supply voltage, and that this internal voltage is used as an operating power supply for a PLL circuit. I thought, but if you take this approach,
Although the disturbance characteristics of the PLL circuit with respect to the power supply voltage fluctuation are certainly improved and the power supply jitter due to the power supply voltage fluctuation is reduced, particularly when a so-called series regulator is used as the internal voltage generating circuit, the use of the PLL circuit due to the drop in the potential of the operating power supply. The highest frequency decreases. further,
In order to cope with this, a method using a booster circuit as an internal voltage generating circuit or a so-called RC or LC smoothing circuit composed of a resistor or an inductance and a capacitor may be considered. In order to cover the operating current of the PLL circuit, the layout required area of the booster circuit is increased. In the latter case, the RC or LC time constant cannot be increased due to the limitation of the layout area on the chip surface. No significant jitter reduction effect can be obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a PLL circuit which suppresses an increase in the required area of the layout, and reduces the jitter and raises the maximum usable frequency.

[0006] Another object of the present invention is to increase the scale of A
A method for configuring a PLL circuit suitable for an SIC or the like is provided.
An object of the present invention is to improve the performance and reduce the power consumption of an IC and the like and a digital system including the same.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a PL mounted on an ASIC or the like
The L circuit has a relatively good disturbance characteristic by using the internal voltage VPL of a relatively stable potential generated by the internal voltage generating circuit as its main operation power supply, and has a relatively large frequency multiplication factor. A first PLL circuit that generates a first internal clock signal based on an externally supplied reference clock signal having a relatively low maximum use frequency, and a first PLL circuit that uses an external power supply voltage as its main operating power supply. PLL
Although it has inferior disturbance characteristics as compared with the circuit, it has a relatively high maximum frequency and a relatively small frequency multiplication factor, so that it has little phase jitter and a relatively high frequency based on the first internal clock signal. And a second PLL circuit for generating a second internal clock signal.

Further, the PLL circuit is provided with one first P
An LL circuit and a plurality of the second PLL circuits commonly receiving a first internal clock signal as an output signal thereof are configured based on a semiconductor device on which an ASIC or the like is formed. They are distributed and arranged near the corresponding functional blocks on the board surface.

According to the above-described means, in a relatively low frequency band, the first P having a relatively large frequency multiplication factor is used.
The first internal clock signal is generated by the LL circuit while suppressing the power supply jitter. In the relatively high frequency band, the second PLL circuit having a relatively small frequency multiplication factor and a relatively small layout required area is used. The second internal clock signal can be generated while suppressing the phase jitter by increasing the phase comparison frequency. As a result, the PL mounted on an ASIC or the like can be suppressed while suppressing an increase in the required layout area.
It is possible to reduce the jitter of the entire L circuit, increase the maximum frequency used, and increase the frequency multiplication factor as a whole.

Further, in an ASIC or the like whose scale is increasing, a first internal clock signal of a relatively low frequency is distributed to a second PLL circuit which is distributed and arranged, and a second phase of a relatively high frequency is divided into a plurality of second phases. Therefore, the machine cycle of a digital system including an ASIC or the like as a component can be sped up, and its high performance and low power consumption can be achieved.

[0012]

FIG. 1 is an overall block diagram of a first embodiment of a PLL circuit to which the present invention is applied. FIG. 2 is a circuit diagram of one embodiment of the internal voltage generation circuit VG included in the PLL circuit of FIG.
FIG. 4 shows a PLL module PLL1 (first PL).
L circuit) and PLL2 (second PLL circuit) are shown in block diagrams of one embodiment, respectively. FIG. 5 also shows the PLL modules PLL1 and PL1 shown in FIGS.
A characteristic comparison diagram of one example of L2 is shown. Based on these figures, the PLL circuit and the internal voltage generation circuits VG, PL
The configuration, operation, and features of the L modules PLL1 and PLL2 will be described.

The PLL circuit of this embodiment is mounted on a predetermined ASIC, although not particularly limited, and the PLL circuit
As a clock signal source of a digital system having C as a constituent element, it generates an internal clock signal ICLK having a frequency, for example, about 16 times that of a reference clock signal ECLK supplied from the outside. The circuit elements constituting each block in FIG. 1 are, together with other circuit elements constituting the ASIC, a well-known MOSFET (Metal Oxide Semiconductor Field Effect Transistor. In this specification, the MOSFET is an insulated gate field effect transistor). Are formed on one semiconductor substrate surface such as single crystal silicon by an integrated circuit manufacturing technique. In the following description,
Although internal clock signal ICLK is shown as a single-phase clock signal, it may actually be a multi-phase clock signal.

Referring to FIG. 1, a PLL circuit according to the present embodiment uses an intermediate clock signal PCLK (first signal) having a predetermined frequency based on a reference clock signal ECLK supplied from an external clock generator via an external terminal ECLK. A PLL module PLL1 for generating an internal clock signal).
A PLL module PLL2 for generating an internal clock signal ICLK (second internal clock signal) having a predetermined frequency based on the intermediate clock signal PCLK, and further from an external power supply via external terminals VCC and VSS. An internal voltage generation circuit VG that generates a predetermined internal voltage VPL based on an external power supply voltage supplied, that is, a power supply voltage VCC and a ground potential VSS. The PLL module PLL1 uses the power supply voltage VCC, the internal voltage VPL, and the ground potential VSS as its main operation power supplies, and the PLL module PLL2 uses the power supply voltage VCC and the ground potential VSS as its operation power supplies. The internal clock signal ICLK is A
It is distributed to other functional blocks (not shown) of the SIC.

Here, although not particularly limited, internal voltage generating circuit VG is a so-called series regulator as shown in FIG. 2, and is a P-channel MOSFET provided between power supply voltage VCC and internal voltage supply point VPL.
P1 is included. The gate of MOSFET P1 is coupled to the output terminal of operational amplifier OA1. Operational amplifier OA1
Is supplied with a predetermined reference voltage VR. The inverting input terminal − is connected to the internal voltage supply point V
PL, that is, coupled to the drain of MOSFET P1, and coupled to ground potential VSS via capacitor C1.

Internal voltage V at internal voltage supply point VPL
When the potential of PL is lower than the reference voltage VR, the operational amplifier O
A1 amplifies the potential difference between the two voltages to lower its output voltage, that is, the potential of the gate voltage of MOSFET P1. Therefore, the conductance of MOSFET P1 increases, and accordingly, the potential of internal voltage VPL increases. On the other hand, when the potential of the internal voltage VPL becomes higher than the reference voltage VR, the operational amplifier OA1 amplifies the potential difference between these voltages to increase its output voltage, that is, the potential of the gate voltage of the MOSFET P1. For this reason, the conductance of MOSFET P1 decreases, and accordingly, internal voltage VP
The potential of L decreases.

From the above, the potential of the internal voltage VPL is automatically controlled so that the reference voltage VR becomes the central potential, and is set to a stable potential which is hardly affected by the potential fluctuation of the power supply voltage VCC. However, the absolute value of the internal voltage VPL is determined by the MOSFET between the power supply voltage VCC and the internal voltage supply point VPL.
P1 is provided, and its conductance is controlled to be the above-mentioned predetermined value, whereby the voltage is reduced by the voltage drop of MOSFET P1, and the potential of internal voltage VPL is reduced to power supply voltage VC.
The potential becomes lower than C.

Next, the PLL module PLL1 is shown in FIG.
As shown in FIG. 2, one input terminal receives a reference clock signal ECLK, and the other input terminal receives a basic clock signal VC which is an output signal of the voltage controlled oscillator VCO1.
The phase comparator circuit PD1 receives the frequency-divided signal of K1, that is, the feedback clock signal FCK1. Output signals of the phase comparison circuit PD1, that is, an up signal UP1 and a down signal DN1
Is supplied to a charge pump circuit CP1, and a control voltage VC1, which is an output signal of the charge pump circuit CP1, is supplied to a voltage controlled oscillation circuit VCO1. Further, an output signal of the voltage control type oscillation circuit VCO1, that is, a basic clock signal VCK1 passes through a clock buffer CB1 and then becomes a PLL module P
After being supplied to LL2 and frequency-divided by the frequency dividing circuit FD1 at a predetermined ratio, it is supplied to the phase comparison circuit PD1 as the feedback clock signal FCK1.

In this embodiment, the reference clock signal E
Although CLK is not particularly limited, for example, 14.3 MHz
(Megahertz) pulse signal having a relatively low frequency, and an intermediate clock signal PCL as an output signal thereof.
K is, for example, eight times the reference clock signal ECLK, that is, 1
The pulse signal has a frequency of about 14.4 MHz. Further, a voltage-controlled oscillation circuit VCO1 mainly including an analog circuit, and a part of circuits of the charge pump circuit CP1 and the clock buffer CB1 corresponding to an interface with the voltage-controlled oscillation circuit include the internal voltage generation circuit VG. Voltage VPL and ground potential VS generated by
S is the main operating power supply, and the other circuits are
CC and the ground potential VSS are the main operation power supplies.

The phase comparison circuit PD1 of the PLL module PLL1 compares the phase, that is, the frequency, of the reference clock signal ECLK and the feedback clock signal FCK1, and generates an up signal UP1 or a down signal DN1 having a pulse width corresponding to the difference.
Are formed selectively. That is, the phase comparison circuit PD1
When the phase of the feedback clock signal FCK1 lags behind the reference clock signal ECLK, the up signal UP1 is selectively set to the high level only during a period corresponding to the phase difference, and the down signal DN1 is kept at the low level. On the contrary, the phase of the feedback clock signal FCK1 is changed to the reference clock signal EC.
When the signal has advanced compared to LK, the down signal DN1 is selectively set to the high level only during the period corresponding to the phase difference, and the up signal UP1 is kept at the low level.

On the other hand, the charge pump circuit CP1 integrates the high level of the up signal UP1 and the down signal DN1 which are the output signals of the phase comparison circuit PD1, and controls the potential of the control voltage VC1 which is the output signal. That is, when the up signal UP1 is at a high level, the charge pump circuit CP1 controls the control voltage VC1 according to the pulse width thereof.
Is selectively increased, and when the down signal DN1 is set to the high level, the control voltage VC is set in accordance with the pulse width.
1 is selectively lowered. The control voltage VC1 is supplied to the voltage-controlled oscillation circuit VCO1 as described above.

The voltage controlled oscillation circuit VCO1 generates a basic clock signal VCK1 having a frequency corresponding to the potential of the control voltage VC1 supplied from the charge pump circuit CP1. That is, the voltage-controlled oscillation circuit VCO1 increases the frequency of the basic clock signal VCK1 as an output signal as the potential of the control voltage VC1 increases, and the basic clock signal as the potential of the control voltage VC1 decreases. Lower the frequency of VCK1. Thus, the center frequency of the basic clock signal VCK1 is controlled to be eight times the reference clock signal ECLK.

The frequency dividing circuit FD1 includes, for example, 3
It includes a bit counter and divides the frequency of the basic clock signal VCK1 by, for example, ８, and then supplies it as a feedback clock signal FCK1 to the phase comparison circuit PD1.

As described above, the phase comparison circuit PD1, the charge pump circuit CP1, the voltage control type oscillation circuit VCO1 and the frequency division circuit FD1 perform control so that the phases and frequencies of the reference clock signal ECLK and the feedback clock signal FCK1 match. . Therefore, the feedback clock signal FC
K1 is a pulse signal that is phase-synchronized with the reference clock signal ECLK and has the same center frequency.

On the other hand, the voltage-controlled oscillation circuit VCO1, which is mostly analog circuits, and its periphery require an internal voltage VPL having a relatively stable potential, and the PLL module PLL1 is shown again on the left side of FIG. As described above, the power supply voltage VCC and the internal voltage VPL are used as main operating power supplies. Therefore, despite having a relatively large frequency multiplication factor of 8 times, that is, several times to several tens times, the PLL module PLL1 has good disturbance characteristics that are not easily affected by power supply voltage fluctuations. Is small enough. However, the potential of the internal voltage VPL is lower than the power supply voltage VCC.
Because of the lower speed, the operation speed is correspondingly slower, and the operating frequency of the system may not be satisfied as it is.
In this application, the frequency required by the system is 228.8 MHz.
Assume that the PLL module PLL1 cannot directly output the frequency. In addition, since the frequency multiplication factor is large, the frequency of phase comparison between the reference clock signal ECLK and the feedback clock signal FCK1 by the phase comparison circuit PD1 is small, the phase jitter is slightly increased, and the internal voltage generation circuit for improving the disturbance characteristics is improved. The necessity of a compensation circuit or the like makes the circuit configuration somewhat complicated.

Next, the PLL module PLL2 is constructed as shown in FIG.
As shown in FIG. 3, the output signal of the PLL module PLL1, that is, the intermediate clock signal P
A phase comparison circuit PD2 that receives the CLK and receives a feedback clock signal FCK2, that is, a frequency-divided signal of the reference clock signal 2, at the other input terminal. This phase comparison circuit PD2
Output signals, that is, an up signal UP2 and a down signal DN
2 is supplied to a charge pump circuit CP2, and a control voltage VC2, which is an output signal of the charge pump circuit CP2, is supplied to a voltage controlled oscillation circuit VCO2. The output signal of the voltage-controlled oscillation circuit VCO2, that is, the basic clock signal VCK2 is supplied to a functional block (not shown) of the ASIC as an internal clock signal ICLK after passing through a clock buffer CB2, and is also supplied to a predetermined ratio by a frequency dividing circuit FD2. , And then the feedback clock signal FCK
2 is supplied to the phase comparison circuit PD2.

In this embodiment, the intermediate clock signal P
CLK is a pulse signal having a frequency of, for example, about 114.4 MHz, and the internal clock signal ICLK is a pulse having a relatively high frequency, for example, twice the intermediate clock signal PCLK, that is, 228.8 MHz. Signal. Also, a voltage-controlled oscillation circuit VC
All blocks of the PLL module PLL2 including O2 include an externally supplied power supply voltage VCC and a ground potential VS
Let S be its main operating power supply.

As in the case of the PLL module PLL1, the phase comparison circuit PD2 of the PLL module PLL2
Are the intermediate clock signal PCLK and the feedback clock signal FC
The phase, that is, the frequency of K2 is compared, and an up signal UP2 or a down signal DN2 having a pulse width corresponding to the difference is selectively formed. Further, the charge pump circuit CP2 integrates the high level of the up signal UP2 and the down signal DN2 which are the output signals of the phase comparison circuit PD2, and controls the potential of the control voltage VC2 which is the output signal. Further, the voltage-controlled oscillation circuit VCO2 includes a charge pump circuit CP2
And generates a basic clock signal VCK2 having a frequency corresponding to the potential of the control voltage VC2 supplied from. And
The frequency dividing circuit FD2 includes, for example, a 1-bit counter (not shown). The frequency dividing circuit FD2 divides the frequency of the basic clock signal VCK2 by half, and then supplies the frequency as the feedback clock signal FCK2 to the phase comparing circuit PD2.

As described above, the phase comparison circuit PD2, the charge pump circuit CP2, the voltage control type oscillation circuit VCO2, and the frequency division circuit FD2 perform control so that the phases and frequencies of the reference clock signal ECLK and the feedback clock signal FCK2 match. . Therefore, the feedback clock signal FC
K2 becomes a pulse signal that is phase-synchronized with the intermediate clock signal PCLK and has the same center frequency, whereby the internal clock signal ICLK has a frequency 16 times that of the reference clock signal ECLK. A phase-synchronized pulse signal is obtained.

On the other hand, all blocks constituting the PLL module PLL2 use an externally supplied power supply voltage VCC as an operation power supply, as shown again on the right side of FIG. For this reason, the disturbance characteristics of the PLL module PLL2 are slightly inferior to those of the PLL module PLL1, and the power supply jitter is slightly increased. However, the operation speed is increased by using the power supply voltage VCC without potential drop as the main operation power supply. As a result, the highest usable frequency is increased, and the device can operate sufficiently at a high frequency such as the above-mentioned 228.8 MHz. Further, by setting the frequency multiplication factor to 2, the intermediate clock signal PC by the phase comparison circuit PD2 is set.
The frequency of phase comparison between the LK and the feedback clock signal FCK2 increases, the phase jitter decreases, and the circuit configuration is simplified because an internal voltage generation circuit and a compensation circuit for enhancing disturbance characteristics are not required. The required layout area as a module is reduced.

As described above, in the PLL circuit of this embodiment, the PLL module PL whose use maximum frequency is relatively low, has good disturbance characteristics, and has a large frequency multiplication factor.
L1, for example, 11 based on an externally supplied reference clock signal ECLK of, for example, about 14.3 MHz.
After the generation of the intermediate clock signal PCLK of about 4.4 MHz, the disturbance characteristics thereof are changed to the PLL module PLL1.
The PLL module PLL2, which is inferior to the above but has a lower frequency multiplication factor but has a higher maximum use frequency, allows the above 11
For example, an internal clock signal I of about 228.8 MHz based on the intermediate clock signal PCLK of about 4.4 MHz
CLK is generated.

In other words, in the PLL circuit of this embodiment, the reference clock signal ECL of about 14.3 MHz is used.
K is the first PLL module PLL with low power supply jitter
1, the intermediate clock signal PCL of about 114.4 MHz which is close to the highest frequency used by the PLL module PLL1.
After the frequency is rapidly increased to 8 times as K, the frequency is increased to 22 times by the PLL module PLL2 having a small phase jitter.
The internal clock signal ICLK of about 8.8 MHz is used. As a result, the frequency multiplication factor of the PLL circuit as a whole increases, the maximum frequency used increases, and the internal clock signal ICLK having a sufficiently high frequency can be obtained based on the reference clock signal ECLK having a sufficiently low frequency. , The total amount of jitter is reduced.

FIG. 6 is a block diagram showing a second embodiment of the PLL circuit to which the present invention is applied. In addition,
Since this embodiment basically follows the embodiment shown in FIGS. 1 to 5, only the differences will be described.

Referring to FIG. 6, the PLL circuit of this embodiment includes a PLL module PLL1 (first PLL circuit) receiving a reference clock signal ECLK, and an output signal of the PLL module PLL1, that is, an intermediate clock signal PCLK.
(1st internal clock signal) commonly received four PLs
L modules PLL21 to PLL24 (second PLL circuit). Among them, PLL module PLL1
Is the internal voltage V in addition to the externally supplied power supply voltage VCC.
PL operates as its main operating power supply, for example, 14.
For example, an intermediate clock signal PCLK of about 114.4 MHz is generated based on a reference clock signal ECLK of about 3 MHz. Also, PLL modules PLL 21 to PLL
24 operates with the power supply voltage VCC as its main operation power supply, and for example, 2 operates based on the intermediate clock signal PCLK.
Internal clock signals ICLK1 to ICLK of about 28.8 MHz
CLK4 (second internal clock signal) is generated and supplied to the corresponding functional block of the ASIC.

In this embodiment, the PLL module P
LL1 has operating characteristics corresponding to the PLL module PLL1 of FIG.
24 have operating characteristics corresponding to the PLL module PLL2 of FIG. Also, the PLL module P
LL21 to PLL24 are distributed and arranged respectively close to the corresponding functional blocks on the semiconductor substrate surface, and each of these PLL modules PLL21 to PLL24 is connected to a single-phase intermediate clock signal via a relatively long signal wiring. PCLK is distributed as a reference clock signal.

That is, in the PLL circuit of this embodiment, a digital system which operates synchronously in accordance with the internal clock signals ICLK1 to ICLK4 without directly distributing a plurality of phases of internal clock signals having a relatively high frequency to each functional block. It is possible to reduce the influence of wiring resistance and parasitic capacitance of signal wiring for clock distribution, promote the speeding up of the system, and reduce the power consumption due to charging and discharging of these signal wiring. . Further, PL
The L modules PLL21 to PLL24 do not require an internal voltage generation circuit or a compensation circuit for enhancing the disturbance characteristics,
The required layout area is relatively small. As a result, in this embodiment, an effect similar to that of the above-described embodiment of FIGS. 1 to 5 can be obtained while suppressing an increase in the required area of the layout of the entire PLL circuit and reducing its power consumption. It is.

The functions and effects obtained from the above embodiment are as follows. That is, (1) a PL mounted on a logic integrated circuit device such as an ASIC.
The L circuit has a relatively good disturbance characteristic by using the internal voltage VPL of a relatively stable potential generated by the internal voltage generating circuit as its main operation power supply, and has a relatively large frequency multiplication factor. By using a first PLL circuit for generating a first internal clock signal based on a reference clock signal supplied from an external source and a power supply voltage supplied from an external source as a main operating power supply, Although it has inferior disturbance characteristics as compared with the first PLL circuit, its maximum frequency of use is relatively high and its frequency multiplication factor is relatively small, so that its phase jitter is small, and based on the first internal clock signal, With the configuration based on the second PLL circuit that generates the second internal clock signal having a relatively high frequency, the power supply jitter can be reduced by the first PLL circuit in a relatively low frequency band. The first PLL circuit generates the first internal clock signal with a relatively large frequency multiplication factor while suppressing the phase comparison frequency with a relatively small frequency multiplication factor in a relatively high frequency band. The effect is obtained that the second internal clock signal can be generated while suppressing the jitter.

(2) In the above item (1), the PLL circuit includes one first PLL circuit and a plurality of second PLL circuits commonly receiving a first internal clock signal as an output signal thereof.
And a second PLL circuit,
By distributing and disposing the corresponding functional blocks on the surface of the semiconductor substrate in close proximity, the first internal clock signal having a relatively low frequency is distributed to the dispersively disposed second PLL circuit,
Since a polyphase second internal clock signal having a relatively high frequency can be generated, the influence of the wiring resistance of the signal wiring, the parasitic capacitance, and the like can be suppressed, and the power consumption due to charging and discharging can be reduced. The effect is obtained.

(3) According to the above items (1) and (2), the jitter of a PLL circuit mounted on an ASIC or the like is reduced while the increase in the required layout area is suppressed, and the maximum frequency used is increased. The effect that the frequency multiplication factor can be enlarged is obtained. (4) According to the above items (1) to (3), an effect is obtained that the machine cycle of a digital system including an ASIC or the like as a component can be speeded up, and its performance and power consumption can be reduced. .

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIGS. 1 and 6, the reference clock signal ECL is used.
K, intermediate clock signal PCLK, internal clock signal IC
LK and specific frequencies of ICLK1 to ICLK4 and their ratios can be set arbitrarily. Further, the block configuration of the entire PLL circuit is not restricted by these embodiments, and the polarity of the power supply voltage is also the same. PLL module PLL1 and PLL module P
The LL2 and the PLLs 21 to 24 are not necessarily required to have a module form.

In FIG. 2, the circuit configuration of the internal voltage generation circuit VG can take various embodiments. In FIG.
The PLL module PLL1 can include various compensating circuits and the like for improving the disturbance characteristics.
The block configuration of the PLL modules PLL1 and PLL2 shown in (1) can take various embodiments. In FIG. 6, a second PLL circuit provided in the PLL circuit, that is, P
The number of the LL modules PLL21 to PLL24 can be set arbitrarily, and the internal clock signal ICL as an output signal thereof is output.
The frequencies of K1 to ICLK4 can also be set individually and arbitrarily.

In the above description, the invention made mainly by the present inventor is referred to as the application field AS
The case where the present invention is applied to a PLL circuit with a built-in IC has been described. However, the present invention is not limited to this. For example, the present invention is also applicable to various types of logic integrated circuit devices having a single PLL circuit or a similar PLL circuit. it can. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a PLL circuit requiring at least a relatively large frequency multiplication factor and low jitter, and an apparatus or a system including the same.

[0043]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a PLL circuit mounted on a logic integrated circuit device such as an ASIC has a relatively good disturbance characteristic by using an internal voltage VPL generated by an internal voltage generating circuit and having a relatively stable potential as its operation power supply. A first PLL circuit for generating a first internal clock signal based on an externally supplied reference clock signal having a relatively large frequency multiplication factor but having a relatively low maximum frequency of use, and an externally supplied By using a power supply voltage as a main operating power supply, the first PLL circuit has a disturbance characteristic inferior to that of the first PLL circuit. However, since the highest use frequency is relatively high and the frequency multiplication factor is relatively small, phase jitter is small. , And a second PLL circuit that generates a second internal clock signal having a relatively high frequency based on the first internal clock signal. In the pass, the first of P
The first internal clock signal is generated by the LL circuit at a relatively large frequency multiplication factor while suppressing the power supply jitter, and in the relatively high frequency band, the second PLL circuit makes the relatively small frequency multiplication factor. The second internal clock signal can be generated while increasing the phase comparison frequency to suppress the phase jitter.

Further, the PLL circuit is connected to one of the first P
An LL circuit and a plurality of second PLL circuits commonly receiving a first internal clock signal as an output signal of the LL circuit, wherein the second PLL circuit is a corresponding functional block on a semiconductor substrate surface. , The first internal clock signal having a relatively low frequency is distributed to the second PLL circuit which is distributed and arranged, and the polyphase second internal clock signal having a relatively high frequency is distributed. Therefore, the influence of the wiring resistance and the parasitic capacitance of the signal wiring for clock distribution can be suppressed, and the power consumption due to the charge and discharge can be suppressed.

As described above, the jitter of the PLL circuit mounted on the logic integrated circuit device such as the ASIC is reduced while suppressing the increase in the required layout area, the maximum use frequency as a whole is raised, and the frequency multiplication factor is increased. In addition to increasing the size, it is possible to increase the speed of a machine cycle of a digital system including an ASIC or the like as a component, and to achieve higher performance and lower power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a PLL circuit to which the present invention is applied.

FIG. 2 is a circuit diagram showing one embodiment of an internal voltage generation circuit of the PLL circuit of FIG. 1;

FIG. 3 is a PLL module PLL1 of the PLL circuit of FIG. 1;
FIG. 3 is a block diagram showing one embodiment of the present invention.

FIG. 4 is a PLL module PLL2 of the PLL circuit of FIG. 1;
FIG. 3 is a block diagram showing one embodiment of the present invention.

FIG. 5 is a PLL module PLL1 of the PLL circuit of FIG. 1;
FIG. 4 is a comparison diagram of operating characteristics showing one embodiment of the present invention and PLL2.

FIG. 6 is a block diagram showing a second embodiment of the PLL circuit to which the present invention is applied;

[Explanation of symbols]

VG: Internal voltage generating circuit, PLL1 to PLL2: P
LL module, VCC: power supply voltage or its input terminal, VSS: ground potential or its input terminal, VPL ...
Internal voltage, ECLK ... Reference clock signal, PCLK ...
... Intermediate clock signal, ICLK... Internal clock signal.
OA1 ... Opamp, VR ... Reference voltage, P1 ... P
Channel MOSFET, C1 ... Capacitance. PD1 to PD
2, a phase comparison circuit, CP1 to CP2, a charge pump circuit, VCO1 to VCO2, a voltage controlled oscillation circuit,
FD1 to FD2 frequency divider circuit, CB1 to CB2 clock buffer, UP1 to UP2 up signal, DN1
... DN2 ... down signal, VC1 to VC2 ... control voltage, VCK1 to VCK2 ... basic clock signal, FCK
1 to FCK2 feedback clock signal. PLL21 to PL
L24: PLL module, ICLK1 to ICLK4
...... Internal clock signal.

Claims (5)

[Claims] The present invention has a relatively good disturbance characteristic, a relatively large frequency multiplication factor, a relatively low maximum frequency for use, and a first clock based on a reference clock signal supplied from the outside. PLL for generating internal clock signal of
Having a disturbance characteristic inferior to the first PLL circuit;
A second PLL having a relatively small frequency multiplication factor, having a relatively high maximum frequency used, and generating a second internal clock signal based on the first internal clock signal;
And a circuit. 2. The first PLL circuit according to claim 1, wherein the first PLL circuit uses an internal voltage which is generated based on an external power supply voltage and has a relatively stable potential as a main operation power supply or a part thereof. The second PLL circuit has a relatively good disturbance characteristic, and its maximum use frequency is relatively low. The second PLL circuit uses the external power supply voltage as a main operation power supply, thereby providing the first PLL circuit with the first PLL circuit. A PLL circuit having a disturbance characteristic that is inferior to that of a circuit and having a maximum use frequency relatively high. 3. The PLL circuit according to claim 1, wherein the PLL circuit includes a plurality of the second PLL circuits that commonly receive the first internal clock signal. 4. The PLL circuit according to claim 3, wherein the plurality of second PLL circuits are distributed and arranged close to corresponding functional blocks on a semiconductor substrate surface. 5. The method according to claim 1, wherein the PLL circuit and the first and second PLL circuits are:
A PLL circuit mounted on a predetermined logic integrated circuit device as a module.