TWI283827B - Apparatus and method for efficiently updating branch target address cache - Google Patents

Abstract

A microprocessor with a write queue for a branch target address cache (BTAC) is disclosed. The BTAC is read in parallel with an instruction cache in order to predict a target address of a branch instruction in the accessed cache line. In one embodiment, the BTAC is single-ported; hence, the single port must be shared for reading and writing. When the BTAC needs updating, such as when a branch target address is resolved, the microprocessor stores the branch target address and related information in the write queue. Thus, the write queue potentially enables updating of the BTAC to be delayed until the BTAC is not being read, such as when the instruction cache is idle, a misprediction by the BTAC is being corrected, or the prediction by the BTAC is being overridden. If the write queue becomes full, then it updates the BTAC anyway.

Description

I28382l7828twfl.doc/〇〇6 / 95-9-13 IX. Description of the invention: The present invention relates to a branch prediction of a microprocessor, and in particular to a method for utilizing a predictive branch target address cache Branch prediction. Prior Art Modern microprocessors are microprocessors for pipelines (PiPeline). That is, several instructions can be operated simultaneously in different blocks or pipeline stages of the microprocessor. By John L. Hennessy and David A. Patterson in his book: Computer Architecture: A Quantitative Approach (second edition in 1996 by Morgan Hoffman Press (San Francisco, California)) The definition pipeline is: "an implementation technique railway multiple instructions are overlapped in execution. It provides an excellent description of the pipeline: the pipeline is similar to the assembly line. In the vehicle assembly line, there are In many steps, each step makes some contribution to the assembly of the vehicle. Although for different vehicles, the operation of each step is parallel to the other steps. In the computer pipeline, each pipeline of the pipeline completes one part of the command. Similar to the assembly line, Different steps complete different parts of the different instructions in parallel. Each step is called a pipe stage or a pipe segment. These stages are connected to each other to form a pipeline, and instructions are entered from one end, and processed through these stages. And output in the other end, just like the assembly line handles the vehicle. The processor operates according to the clock cycle. In general, at each clock cycle, the instruction proceeds from one of the pipelines of the microprocessor to another 1283822. 8twf1.doc/006

95-9-13 One stage. In the vehicle assembly line, if the line worker is idle because there is no vehicle to be assembled, the line's output or performance may decrease. Similarly, if a microprocessor's pipeline is idle because there is no instruction to operate during a clock cycle, which is usually referred to as a pipeline bubble, the performance of the microprocessor may degrade. One of the possible causes of pipeline air bubbles is the branch instruction. When processing a branch instruction, the processor must determine the destination address of the branch instruction and begin fetching the instruction at the target address rather than at the address below the branch instruction. Even if the branch instruction is a status branch instruction (that is, it is necessary to determine whether the branch is to be executed according to whether a specific condition exists or not), in addition to determining the target address, the processor must determine whether the branch instruction is to be carried out. Because the pipeline phase that ultimately determines the target address and/or branch outcome (i.e., whether the branch is to be executed) is typically below the instruction capture phase, bubbles may be generated. To solve this problem, modern microprocessors typically apply branch prediction mechanisms to predict target addresses and branch results early in the pipeline. One example of a branch prediction mechanism is a branch target address cache (BTAC) that predicts the branch result and the target address in parallel with an instruction fetch instruction from one of the microprocessors. When the microprocessor executes the branch instruction and finally decides to execute the branch and determine its target address, the address of the branch instruction and its target address are written into the BTAC. The next time the branch instruction is fetched from the instruction cache, the branch instruction address will hit the BTAC and the BTAC can output the branch instruction target address early in the pipeline. A valid BTAC can eliminate or reduce the number of bubbles waiting to be determined by the branch instruction to improve processor performance. However, when the BTAC predicts an error I swims S and replaces η 丄28jiS/2428twfl.doc/006 .11——————— » 95-9-13, the part of the pipeline for the error capture instruction Must be abandoned 'and must take the correct instructions, when the instruction abandon and capture occurs, it will cause bubbles in the pipeline. When the microprocessor pipeline is deeper, the effectiveness of the BTAC is more critical to performance. The effectiveness of BTAC is primarily the role of BTAC's hit rate. One of the factors affecting the BTAC hit rate is the number of different branch instructions for the target address it stores. BTAC is more efficient by storing more branch instruction target addresses. However, the area of the microprocessor chip is always limited, so the area of a given functional block (such as BTAC) is made as small as possible. One factor that affects the actual area of BTAC is the size of the storage cell in which the target address and related information are stored in the BTAC. In particular, the area of the germanium cell is smaller than the area of the germanium cell. A BTAC composed of a unit cell can only be read or written in a timed pulse period and cannot be read and written at the same time, but a BTAC composed of a plurality of cells can be simultaneously read and written in a timed pulse period. However, the area of the multi-turn BTAC is larger than that of the 單埠BTAC. This means that given the allowed real area of the BTAC, the number of target addresses that can be stored by the BTAC must be less than the number of target addresses that the BTAC can store, thus reducing the effectiveness of the BTAC. Therefore, from this point of view, 單埠BTAC is better. However, since 單埠BTAC can only read or write in a single clock cycle and cannot read and write at the same time, this fact reduces the validity of BTAC due to false misses. In the period in which the BTAC needs to be read, when the BTAC is being written, such as updating the BTAC with a new target address or invalidating a certain target address, a false fall occurs. In this case, the BTAC must be frustrated by the read because it cannot supply the target address that may have been 128382,7 28twfl .doc/00 ( Γ 9 repair replace 95-9-13 exists in the BTAC because The BTAC is being written. Therefore, there is a need for a method and apparatus that can reduce the false nulls in a single BTAC. Another phenomenon that may reduce the effectiveness of the BTAC is that the BTAC will store the target address of the branch instruction multiple times. The phenomenon may occur in multi-way set-associative BTAC. Because BTAC space is limited, redundant target address storage will reduce BTAC validity, because redundant BTAC items can store the target bit of another branch instruction. The longer the pipeline, the larger the number of stages, the more likely the extra target address will be stored in the BTAC. The most common case of the same branch instruction being cached multiple times in the BTAC is the tight loop of the code (tight loop) Within the first execution of the branch instruction and its target address is written to the BTAC, such as to the second direction, because the second direction is the oldest unused. However, before the target address is written to the BTAC, the branch Instruction again That is, the BTAC checks the fetched instruction cache address, because the target address is not written into the BTAC. Then, the target address is written to the BTAC a second time. The BTAC read of the different branch instructions inserted in the instruction set causes the second direction to be no longer. If the longest is unused, the other direction, such as the first direction, will be selected to write the target address a second time. Now, the same The target address of the branch instruction exists twice in the BTAC. This is a waste of BTAC space and will reduce the validity of the BTAC, because the second write is likely to cover the effective target address of another branch instruction. Therefore, it is required A method and apparatus for avoiding wasted BTAC space caused by redundant cache of the target address of the same branch instruction. Even a combination of certain conditions related to BTAC predictability can cause a deadlock in the microprocessor. BTAC's branch prediction combination, horizontal ^28twfl.doc/〇〇6 9,' Μ, Λν 95-9-13 cross-instruction cache boundary line branch instruction, and processor bus transaction transaction predictive instruction acquisition Fact, it will cause mistakes In this case, there is a need for a method and apparatus for avoiding dead junctions in a microprocessor that uses predictive BTAC. SUMMARY OF THE INVENTION The present invention provides a write queue to delay writes of BTAC, Until the BTAC is not read, the pseudo-following rate is reduced. In one aspect, the present invention provides a write queue that improves the efficiency of a branch target address cache (BTAC) within a microprocessor. The entry queue includes a request input that receives a request to update the BTAC. This requirement includes a branch instruction target address. The write queue also includes a plurality of storage elements that store the request received by the request input. The write queue also includes control logic coupled to the storage elements to write one of the requests stored in the storage elements to the BTAC in response to one or more predetermined conditions. In another aspect, the invention provides a microprocessor. The microprocessor includes an instruction cache that provides a cache line of the instruction byte in response to an instruction fetch address. The microprocessor also includes a branch target address cache (BTAC) coupled to the instruction cache to predict a branch target address stored in one of the branch instructions in the cache line. The microprocessor also includes a write queue coupled to the BTAC for storing a branch target address for updating the BTAC. In another aspect, the present invention provides a method of updating a branch target address cache (BTAC) within a microprocessor. The method includes the steps of: generating a request to update the BTAC; storing the request in a queue; to 1283827s 28twfl - doc/006:

95-9-13 And after this storage step, the BTAC is updated according to the request. In another aspect, the present invention provides a computer data signal embodied in a transmission medium, including computer readable code to provide a microprocessor. The code includes a first code that provides an instruction cache and provides a cache line for one of the instruction bytes in response to an instruction fetch address. The program code includes a second code, providing a branch target address cache (BTAC) coupled to the instruction cache to predict a branch target address of a branch instruction stored in the cache line. The code includes a third code, providing a write column, called to the BTAC, to store a branch target address for updating the BTAC. The present invention has the advantage that it can reduce the amount of false fall caused by the BTAC being written to the BTAC to increase the efficiency of the BTAC. In addition, the present invention can be applied to 單埠BTAC instead of using a larger area of BTAC to reduce the area of BTAC. In addition, the present invention enables BTAC to store more target addresses and is therefore more efficient than BTACs of similar size. The above and other objects, features, and advantages of the present invention will become more apparent and understood. A block diagram of a microprocessor 100 in accordance with one embodiment of the present invention is shown. The microprocessor 100 includes a pipeline microprocessor. Microprocessor 100 includes an instruction capture device 102. The instruction fetcher 102 fetches instructions 138 from a memory (e.g., system memory) coupled to the microprocessor 100. In one embodiment, the command extractor 102 is from the cache line I28382^28t wf 1 .doc/〇|)6.

The memory capture instruction in the basic unit of 95-9-13. In one embodiment, the instructions are length variable instructions. That is, all instructions within the microprocessor's instruction set are of different lengths. In one embodiment, microprocessor 100 includes a microprocessor that is inherently compatible with an instruction set that is inherently variable in the X86 architecture instruction set. Microprocessor 100 also includes an instruction cache 104 coupled to instruction fetcher 102. The instruction cache 104 receives the cache line of the instruction byte output by the instruction fetcher 102 and caches the instruction cache line used by the microprocessor 100. In one embodiment, the instruction cache 104 includes a 64 KB 4-way instruction set in conjunction with an Ll (leveM) cache. When an instruction falls within the instruction cache 104, the instruction cache 104 notifies the instruction fetcher 102, which responsively retrieves the cache line including the frustration command from the memory. A current capture address 162 is input to the instruction cache 104 to select the cache line. In one embodiment, the cache line within the instruction cache 104 includes 32 bytes. The instruction cache 104 also generates an instruction cache idle signal 158. When the instruction cache 104 is idle, the instruction cache 1 〇 4 is generated as a true instruction cache idle signal 158. When the instruction cache 1〇4 is not read, the instruction cache 104 is idle. In one embodiment, if the instruction cache 104 is not read, the BTAC 142 of the microprocessor (discussed in detail below) is also unread. Microprocessor 100 also includes an instruction buffer 106 coupled to instruction cache 104. The instruction buffer 106 receives the cache line of the instruction byte from the instruction cache 1〇4 and temporarily stores the cache lines until it is normalized to an explicit instruction that can be executed by the microprocessor 1. In one embodiment, the instruction buffer 106 includes four entries to store up to four cache lines. Instruction buffer 1-6 generates an instruction buffer full full signal 156. When the instruction buffer 106 12

I283822.S

When 95-9-13 is full, the instruction buffer 106 generates a true instruction buffer full full signal 156. In an embodiment, if the instruction buffer 106 is full, the BTAC 142 cannot be read. The microprocessor 1 also includes an instruction normalizer 108 coupled to the instruction buffer 106. The instruction normalizer 108 receives the instruction byte from the instruction buffer 106 and thereby generates a normalized instruction. That is, the instruction normalizer 108 looks at a string of instruction bytes within the instruction buffer 1〇6, determines which bytes include the next instruction and its length, and outputs the next instruction and its length. In one embodiment, the normalized instructions include instructions that are substantially compatible with the x86 architectural instruction set. The instruction normalizer 108 also includes a logic circuit that generates a branch target address, referred to as a substitute prediction target address 174. In one embodiment, the branch target address generation logic circuit includes an adder that adds a offset of a relative branch instruction to the branch instruction address to generate a substitute prediction target address 174. In one embodiment, the logic circuit includes a branch target buffer to generate a target address of the indirect branch instruction. In one embodiment, the logic circuit includes a call/backhaul stack to generate a target address for the call and return command. The command specification 108 also includes a predictive replacement signal 154. The instruction normalizer 108 produces a true prediction replacement signal 154 to replace the branch prediction made by the BTAC 142 within the microprocessor 100, as will be described in detail below. That is, if the target address generated by the logic circuit in the instruction normalizer 108 does not conform to the target address generated by the BTAC 142, the instruction normalizer 108 generates a prediction replacement signal 154 that is true to make the prediction of the BTAC 142 The fetch instruction is discarded and causes the microprocessor 100 to branch to the alternate prediction target address 174. In one embodiment, the instruction is discarded and the microprocessor 100 branches 1283827s 28twfl .doc/

95-9-13 By the time the super-predicted target address 174 is replaced, the BTAC 142 cannot be read. Microprocessor 100 also includes a normalized instruction queue 112 coupled to instruction normalizer 108. The normalized instruction queue 112 receives the normalized instructions output from the instruction normalizer 108 and temporarily stores the normalized instructions until they are translated into microinstructions. In one embodiment, the normalized command queue 2 includes items that store up to 12 normalized instructions, although Figure 12 shows only four items. Microprocessor 100 also includes an instruction translator 114 coupled to a normalized instruction queue 112. The instruction translator 114 translates the normalized instructions stored in the normalized instruction queue 112 into microinstructions. In one embodiment, microprocessor 100 includes a reduced instruction set computer (RISC) core that executes microinstructions of the native or reduced instruction set. Microprocessor 100 also includes a post-translation command queue 116 coupled to instruction translator 114. The post-translation command queue 116 receives the translated micro-instructions from the instruction translator 114 and temporarily stores the micro-instructions until they are executable by the pipeline of the remaining microprocessors. Microprocessor 100 also includes a register stage 118 coupled to post-translation command queue 116. The scratchpad stage 118 includes a plurality of registers to store the instruction operators and results. The scratchpad stage 118 includes a user visual register file to store the user visual status of the microprocessor 100. Microprocessor 100 also includes an address stage 122 coupled to a scratchpad stage 118. Address stage 122 includes address generation logic that generates a memory address for a memory access instruction, such as a load or store instruction and a branch instruction. 1283827s 28twf 1 .doc/006

The microprocessor 100 also includes a data stage 124 coupled to the address stage 122. The data phase 124 includes logic for loading data from memory and one or more caches of data loaded from the memory. The microprocessor 1 also includes an execution stage 126 coupled to the data stage 124. Execution phase 126 includes execution units that execute instructions, such as arithmetic and logic units that execute arithmetic and logic instructions. In an embodiment, execution stage 126 includes an integer execution unit, a floating point execution unit, an MMX execution unit and an SSE execution unit. Execution phase 126 also includes branch instructions to determine the logic circuitry. In particular, execution stage 126 determines if the branch instruction is to be executed and if the branch instruction previously misdetected by BTAC 142 is to be executed. In addition, the execution phase 126 determines if the branch target address previously predicted by the BTAC 142 is measured by the BTAC 142, i.e., is incorrect. If the execution p segment 120 determines that the previous branch prediction is incorrect, the execution phase 126 generates a true branch misdetection signal 152 such that the instruction fetched due to the BTAC 142 misdetection is discarded and the microprocessor is The branch branches to the correct address 172. In one embodiment, the BTAC 142 cannot be read while the instruction is discarded and the microprocessor is branched to the correct address 172. Microprocessor 100 also includes a storage phase 128 coupled to execution stage 126. The storage phase 128 includes logic that stores data in memory in response to storing microinstructions. The storage phase 128 produces a correct address 172. The correct address 172 includes the correct branch target address of the branch instruction. That is, the correct address 172 is the non-predictive target address of the branch instruction. When the branch instruction is executed and determined, the correct address Π2 is also written to the BTAC 142, which will be described in detail below. The storage phase 128 also generates a BTAC write request 176 to update the BTAC 142. BTAC write request 176 will refer to Figure 7 for details 1283827 « 28twf 1 .doc/006

95-9-13 Detailed description. Microprocessor 100 also includes a write back stage 132 coupled to storage stage 128. The write back phase 132 includes logic to write the result of the instruction to the scratchpad stage 118. Microprocessor 100 also includes BTAC 142. The BTAC 142 includes a cache memory that can cache the target address and other branch prediction information. The BTAC 142 generates a predicted target address 164 in response to receiving one of the addresses 182 from a multiplexer 148. In one embodiment, the BTAC 142 includes a cache memory that is shared by the read and write accesses of the BTAC 142, thereby causing the BTAC 142 to have a false miss probability. BTAC 142 and multiplexer 148 will be detailed below. The microprocessor 1A also includes a second multiplexer 136 coupled to the BTAC 142. Multiplexer 136 selects one of the six inputs to output a current capture address 162. One of the inputs is a next fetch address 166 generated by an adder 134, and the adder 134 adds the size of the cache line to the current fetch address 162 to generate the next fetch address 166. After a cache line is normally retrieved from the instruction cache 104, the multiplexer 136 selects the next capture address 166 to output the current capture address 162. Another input is the currently retrieved address 162. The other input is the BTAC prediction target address 164, if the BTAC 142 indicates that a branch instruction exists in the cache line selected from the current capture address 162 of the instruction cache 104 and the BTAC 142 predicts the branch instruction To be executed, multiplexer 136 selects BTAC prediction target address 164. The other input is the correct address 172 received from the storage phase 128, and the multiplexer 136 selects the correct address 172 to correct for a branch misdetection. The other input is the substitute predicted target address 174 received from the instruction normalizer 108, and the multiplexer 136 9-128383⁄4 828 twfl.doc/006 95-9-13 selects the replacement predicted target address 174 to replace the BTAC test target. Address 164. The other input is a current command indicator 168 that points to the address of the instruction currently being normalized by the instruction normalizer 1-8. Multiplexer 136 selects the current command indicator 168 to avoid deadlock conditions, as described below. The microprocessor 1A also includes a BTAC write queue (BWQ) 144 coupled to the BTAC 142. The BTAC write queue 144 includes a plurality of storage elements to temporarily store the BTAC write request 176 until it can be written to the BTAC 142. The BTAC write queue 144 receives the branch misdetection signal 152, which replaces the signal 154, the instruction buffer full signal 156, and the idle signal 158 is cached with the instruction. Advantageously, the BTAC write queue 144 can utilize the BTAC write request 176 to delay the update of the BTAC 142 until the appropriate time indicated by the input signals 152-158, ie, the time that the BTAC 142 has not been read, to increase the efficiency of the BTAC 142. Will be detailed below. The BTAC write queue 144 generates a BTAC write queue address 178 that is input to the multiplexer 148. The BTAC write queue 144 also includes a register that stores one of the front queue depths 146. The queue depth 146 indicates the number of valid BTAC write requests 176 currently stored in the BWQ 144. The initial 値 of the queue depth 146 is zero. Each time a BTAC write request 176 is stored in the BTAC write queue 144, the queue depth 146 is incremented. Each time a BTAC write request 176 is removed from the BWQ 144, the queue depth 146 is reduced. The BTAC write queue 144 will be detailed below. Referring now to Figure 2, there is shown a detailed block diagram of a portion of a microprocessor in accordance with Figure 1 of the present invention. Figure 2 shows the BTAC write queue 144 'BTAC142 and the multiplexer 148 of Figure 1, plus an arbiter 202, and a 3-input I283827s28 coupled between the BTAC write queue 144 and the BTAC 142. Π V \ vy twfl .doc/006

95-9-13 Multiplexer 206. Although the multiplexer 148 of Figure 1 receives only two inputs, the multiplexer 148 is a 4-input multiplexer, as shown in Figure 2. As shown in Figure 2, the BTAC 142 includes a read/write input, an address input and a data input. As shown in FIG. 1, multiplexer 148 receives the current capture address 162 and the BWQ address 178. In addition, multiplexer 148 also receives a redundant TA address 234 and a dead node address 236, which will be described in detail with reference to Figures HM1 and 12-13, respectively. The multiplexer 148 selects one of its four inputs based on a control signal 258 generated by the arbiter 202 for output as an address data 182 of FIG. 1, which is input to the bit of the BTAC 142. Address input. The multiplexer 206 receives a redundant TA data signal 244 and a dead junction data signal 246, which will be described in detail with reference to Figures 10-11 and 12-13, respectively. The multiplexer 206 also receives a BWQ data signal 248 from the BTAC write queue 144 which updates the BTAC 142 data for the current BTAC write queue 144. The multiplexer 206 selects one of the three inputs based on one of the control signals 262 generated by the arbiter 202 to output a data signal 256 that is input to the data input of the BTAC 142. Arbiter 202 arbitrates the complex source of access to the BTAC 142. When BTAC 142 is read or written, arbiter 202 generates a signal 252 to the read/write input of BTAC 142 to control it. The arbiter 202 receives a BTAC read request signal 212 that represents one of the requirements for reading the BTAC 142 using the current capture address 162 in parallel with the read of the instruction cache 162 using the current capture address 162. . The arbiter 202 also receives a redundant target address (TA) request signal 214 representative of one of the same branch instructions in the selected instruction set to invalidate the redundant TA address 234 within the BTAC 142. 128382,7

One of the requirements of 95-9-13 will be described below. The arbiter 202 also receives a dead-end request signal 216 representing the set of instructions selected to be mis-detected by the dead-end address 236, one of the branch instructions not invalidating one of the BTACs 142 across the cache boundary line. A request will be described below. Arbiter 202 also receives a BWQ non-null signal 218 output from the BTAC write queue 144, which represents at least one request to be processed to update an item within the BTAC 142 within the selected set of instructions of the BWQ address 178, This will be described below. Arbiter 202 also receives a BWQ full full signal 222 from the BTAC write queue 144 output, which represents that the BTAC write queue 144 is full of the BTAC 142 in the selected instruction set to update the BWQ φ address 178. The pending requirements for one of the projects will be described below. In one embodiment, the arbiter 202 assigns priority as shown in Table 1 below, where 1 represents the highest priority and 5 represents the lowest priority: 1- Dead knot requirement 216 2- BMQ Full 222 3- BTAC read request 212 4- ΤΑ ΤΑ Requirement 214 5- BWQ Non-empty 218 φ Referring now to Figure 3, a detailed block diagram of BTAC 142 in accordance with Figure 1 of the present invention is shown. As shown in FIG. 3, the BTAC 142 includes a target address array 302, a tag array 304, and a counter array 306. Each array 302, 304 and 306 receives the address 182 of Figure 1. The embodiment of Figure 3 shows a 4-way instruction set in conjunction with BTAC 142 cache memory. In another embodiment, the BTAC 142 includes a 2-way instruction set joint cache memory. In one embodiment, the target address array 302 and the tag array 304 are 單埠, but 19 1283827s, 8 twf 1 .doc/006 7 1 曰 曰 替换 替换 95 95 95 95 95 95 There is a double 埠 with a read 埠 and a write 埠 because the update frequency of the counter array 306 is higher than the update frequency of the target address array 302 and the tag array 304. The target address array 302 includes an array of storage elements to store a target address array item 312 that can cache branch target addresses and associated branch prediction information. The contents of the target address array item 312 will be described below with reference to FIG. The tag array 304 includes an array of storage elements for storing tag array entries 314 that store address tags and associated branch prediction information. The contents of the label array item 314 will be described below with reference to Figure 5. The counter array 306 includes an array of storage elements for storing counter array items 316 that store branch result prediction information. The contents of counter array item 316 will be described below with reference to Figure 6. Each target address array 302, tag array 304, and counter array 306 are planned in a 4-way direction, as shown, the 0th direction (way 0), the 1st direction (way 1), the 2nd direction (way 2) and 3rd direction (way 3). Preferably, the target address array 302 stores two items or a part in each direction to cache the branch target address and the predictive branch information, represented by A and B, so that if two branch instructions exist in the fast Within the line, BTAC142 can predict the appropriate branch instruction. Each array 302-306 is indexed by address 182 of Figure 1. The lower bits of address 182 select the cache lines in each of arrays 302-306. In one embodiment, each array 302-306 includes 128 instruction sets. Therefore, BTACI42 can quickly fetch up to 1024 target addresses, and each instruction set has 4 addresses for each direction (4 directions for each instruction set). Preferably, arrays 302-306 are indexed by bits [11:5] of address 182 to select a 4-way instruction set within BTAC 142. 20 128382] 28 twfl .doc/006 95-9-13 Referring now to Figure 4, the contents of the target address array item 312 in accordance with Figure 3 of the present invention are shown. The target address array item 312 includes a branch target address (TA) 402. In one embodiment, the target address 402 includes a 32-bit address that is fetched from the previous execution of the branch instruction. The BTAC 142 provides a target address 402 for the predicted TA output 164. The target address array item 312 also includes a start field 404. The start field 404 represents a byte offset of the first byte of the branch instruction within one of the cache lines output from the instruction fetch 104 in response to the current fetch address 162. In one embodiment, a cache line includes 32 bytes; therefore, the start field 404 includes 5 bits. The target address array item 312 also includes a wrap bit 406. The traversal bit 406 is true if the predicted branch instruction spans the two cache lines of the instruction cache 104. BTAC 142 provides a VS 406 for B_wrap signal 1214, which will be discussed below with reference to Figure 12. Referring to Figure 5, the contents of the tag array item 314 in accordance with Figure 3 of the present invention are shown. The tag array item 314 includes a tag 502. In one embodiment, tag 502 includes a high order 20 bit of the address of the branch instruction, the branch instruction causing a related item within the target address array 302 to store a predicted target address 402. If the entry is valid, BTAC 142 compares tag 502 with the higher order 20 bits of address 182 of Figure 1 to determine if the entry matches address 182, i.e., if address 182 hits BTAC 142. The tag array entry 314 also includes an A valid bit 504 if the target bit in the A portion of the associated item in the target address array 302 is 1283822, 8twfl .doc/006 95-9-13

If address 402 is valid, then A valid bit 504 is true. The tag array entry 314 also includes a B valid bit 506 that is true if the target address 402 in the B portion of the associated item within the target address array 302 is valid. The tag array entry 314 also includes a 3-bit lru field 508 indicating which of the four directions of the selected instruction set is lru (Least Recently Used). In an embodiment, when the BTAC branch is executed, the BTAC 142 only updates the lru bit 508, that is, only when the BTAC 142 predicts that a branch instruction will be executed and the microprocessor 1 branches to the BTAC 142 according to the prediction. When the predicted target address 164 is predicted, the BTAC 142 updates the lrii field 508. When the BTAC branch is being executed, the BTAC 142 is updated during the period in which the BTAC 142 is not read and the BTAC is not required to be written to the queue 144. Lru field 508. Referring to Figure 6, the contents of counter array item 316 in accordance with Figure 3 of the present invention are shown. Counter array item 316 includes a predicted state A counter 602. In one embodiment, the predicted state A counter 602 is a 2-bit saturation counter, each time the microprocessor 1 determines that the relevant branch instruction is to be executed, 'it counts up; each time the relevant branch instruction is not executed , it counts down. When counting up, the predicted state A counter 602 is saturated with the binary carry of b'11; when counting down, the predicted state A counter 602 is saturated with the binary carry of b'00. In an embodiment, if the predicted state A counter 602 is then b'll or b'10, the BTAC 142 predicts that the branch instruction associated with the A portion of the selected target address array item 312 is to be executed; otherwise ' BTAC142 predicts that branch instructions should not be executed. Counter Array Item 316 22 1283827 828twfl .doc/006

95-9-13 also includes a prediction state B counter 604 that operates similarly to the predicted state A counter 602, but is associated with portion B of the selected target address array item 312. The counter array item 316 also includes an A/Blru bit 606 〇 A/Blm bit 606 in the binary 606 bit 値 represents that the selected target address array item 312 part A is the oldest unused; otherwise, It is the B portion of the selected target address array item 312 that is the longest unused. In one embodiment, when the branch instruction arrives at the storage phase 128 that determines the branch result (i.e., the branch is to be executed), the Α/Β1ηι bit 606 along with the predicted state A and B counters 602 and 604 are Update. In one embodiment, the update counter array item 316 does not require the use of a BTAC write queue 144 because the counter array 306 includes a read buffer and a write buffer, as shown in FIG. Referring now to Figure 7, the contents of the BTAC write request 176 in accordance with Figure 1 of the present invention are shown. Figure 7 shows the information generated by the storage phase 128 for updating an BTAC 142 entry into the BTAC write request signal 176 of the BTAC write queue 144, which is also the item stored in the BTAC write queue 144. The content inside, as shown in Figure 8. The BTAC write request 176 includes a branch instruction address bit 702, which is the address of the previous execution branch instruction to update the BTAC 142. When the write request 176 then updates the BTAC 142, the higher order 20 bits of the branch instruction address field 702 are stored in the tag field 502 of the tag array entry 314 of FIG. The lower order 7-bit [11:5] of the branch instruction address field 702 is used as the index of BTAC142. In an embodiment, the branch instruction address field 702 is a 32-bit field. The BTAC Write Request 176 also includes a start field 708 to store 1283822,

8twf1.doc/006

95-9-13 is in the beginning field 404 of Figure 4. The BTAC write request 176 also includes a traversing bit 712 for storage in the traverse 406 of FIG. The BTAC Write Request 176 also includes a Write Enable A field 714 which indicates whether the A portion of the selected target address array item 312 is to be updated using the information specified by the BTAC Write Request 176. The BTAC Write Requirement 176 also includes a Write Enable B field 716' which indicates whether the B portion of the selected target address array item 312 is to be updated using the information specified by the BTAC Write Request 176. The BTAC Write Request 176 also includes an Invalid A Field 718 which indicates whether the A portion of the selected Target Address Array Item 312 is to be invalidated. The invalidation of the A portion of the selected target address array item 312 includes: clearing the A significant bit of the 5th figure. The BTAC write request 176 also includes an invalid B field 722, which represents whether or not to invalidate. Part B of the selected target address array item 312. Invalidating the portion B of the selected target address array item 312 includes clearing the B significant bit 506 of FIG. The BTAC Write Request 176 also includes a 4_bit to field 724 which specifies which direction the four directions of the selected instruction set are to be updated. The field 724 is fully decoded. In one embodiment, when the microprocessor 100 reads the BTAC 142 for branch prediction, the microprocessor 100 decides to place it in the field 724 and forwards the buffer to the storage phase 128 through the pipeline stage. To be included in the BTAC write request 176. If the microprocessor 100 is updating an existing item in the BTAC 142, that is, if the current address of the address 162 is hit in the BTAC 142, the microprocessor 1 sets the direction of the existing item in the field 724. . If the microprocessor 1 is writing a new item in the BTAC 142, such as a new branch instruction, the microprocessor 100 will select the longest unused instruction set for the selected BTAC142 24 128383⁄4 8twfl .doc/006 95-9-13 instruction set. Located in the field 724. In one embodiment, when the microprocessor 100 reads the BTAC 142 to obtain a branch prediction, the microprocessor 100 determines the oldest unused direction from the Ini field 508 of Figure 5. Referring now to Figure 8, there is shown a block diagram of a BTAC write in accordance with Figure 3 of the present invention. The BTAC write queue 144 includes a plurality of storage elements 802 to store the BTAC write request 176 of FIG. In one embodiment, the BTAC write queue 144 includes six storage elements 802 to store six BTAC write requests 176, as shown. The BTAC write queue 144 also includes a valid bit 804 associated with each BTAC write request item 802; if the associated item is valid, the valid bit 804 is true; if the associated item is invalid, the valid bit 804 is false. The BTAC write queue 144 also includes control logic 806 coupled to the storage element 802 and the active bit 804. Control logic circuit 806 is also coupled to bank depth register 146. When a BTAC write request 176 is loaded into the BTAC write queue 144, the control logic 806 increases the queue depth 146; when the BTAC write request 176 is removed from the BTAC write queue 144, the control logic 806 is reduced. The queue depth is 146. Control logic circuit 806 receives BTAC write request signal 176 from storage stage 128 of FIG. 1 and stores the received request in item 802. Control logic circuit 806 also receives branch misdetection signal B2' prediction replacement signal 154' command buffer full full signal 156 and instruction cache idle signal 158 of Figure 1. When the queue depth 146 is greater than zero, the control logic circuit 806 generates a BWQ non-empty signal 218 of Figure 2 that is true. When the queue depth 146 is equal to the total number of items 802 25 1283822,

When 丨E replaces page I 95-9-13 (8 in the embodiment of Fig. 8), control logic circuit 806 generates a BWQ full full signal 222 of Fig. 2 which is true. When control logic circuit 806 generates a true BWQ non-empty signal 218, control logic circuit 806 writes BTAC to the branch instruction address 702 of the oldest (or bottommost) item 802 of queue 144, which is set to BWQ in FIG. Within address signal 178. Moreover, when control logic circuit 806 generates a true MWQ non-empty signal 218, control logic circuit 806 also writes BTAC to fields 706-724 of Figure 7 of the oldest (or bottommost) item 802 of queue 144. It is set in the BWQ data signal 248. Referring now to Figure 9, a flow chart showing the operation of the BTAC write queue 144 in accordance with Figure 1 of the present invention is shown. The process begins at decision block 902. At decision block 902, the BTAC write queue 144 determines whether the BTAC write queue 144 is full by determining whether the queue depth 146 of FIG. 1 is equal to the total number of entries in the BTAC write queue 144. If full, the flow jumps to block 918 to update BTAC 142; otherwise, the flow jumps to decision block 904. At decision block 904, the BTAC write queue 144 determines whether the instruction cache 104 of FIG. 1 is idle by examining the instruction cache idle signal 158. If idle, the process jumps to decision block 922 to update BTAC 142 if necessary because BTAC 142 may not be read; otherwise, flow jumps to decision block 906. At decision block 906, the BTAC write queue 144 determines if the instruction buffer 106 of FIG. 1 is full by checking the instruction buffer full full signal 156. If full, if necessary, the flow jumps to decision block 922 to update BTAC 142 because BTAC 142 may not be read; otherwise, flow jumps to decision block 908. 26 I283827828t wf 1 .doc/ _牟Replacement page At decision block 908, the BTAC write queue 144 determines whether the BTAC 142 branch prediction has been replaced by examining the predicted replacement signal 154. If so, if necessary, the flow jumps to decision block 922 to update BTAC 142 because BTAC 142 may not be read; otherwise, flow jumps to decision block 912. At decision block 912, BTAC writes queue 144 by checking the branch for misdetection. Signal 152 determines if the BTAC 142 branch prediction has been corrected. If so, if necessary, the flow jumps to decision block 922 to update BTAC 142 because BTAC 142 may not be read; otherwise, flow jumps to decision block 914. At decision block 914, the BTAC write queue 144 determines if the BTAC write request 176 has been generated. If not, the process jumps back to decision block 902; otherwise, the process jumps to block 916. At decision block 916, the BTAC write queue 144 loads the BTAC write request 176 and increments the queue depth 146. The BTAC write request 176 is loaded into the topmost invalid entry of the BTAC write queue 144, and the entry is then marked as valid. The process jumps back to decision block 902. At decision block 918, the BTAC write queue 144 updates the BTAC 142 with the oldest or bottom item written into the queue 144 by the BTAC and reduces the queue depth 146. The BTAC writes to the queue 144 and then moves down one item. By setting the branch instruction address block 702 of the oldest picture to the BWQ address signal 178 and the other part of the oldest BTAC write request 176 to the BWQ data signal 248, the BTAC writes The entry queue I44 updates the BTAC 142 with the oldest entry in the queue 144 using the BTAC. In addition, the BTAC writes the BWQ non-empty signals 218 to 27 that are asserted by the queue 144.

I283822.S twf1.doc/006

95-9-13 Arbiter 202 of Figure 2. If the flow jumps from decision block 902 to block 918, the BTAC write queue 144 also issues the true BWQ full full signal 2228 to the arbiter 202 of FIG. Flow moves from block 918 to decision block 914. It is noted that if the BTAC read request signal 212 is also in the pending period, the BTAC write queue 144 issues the BWQ full full signal 222 and the arbiter 202 allows the BTAC write queue 144 to access the BTAC 142; then the BTAC 142 will It will be lost, but if the effective target address of the branch instruction predicted by BTAC142 exists in the BTAC 142 and the cache line specified by the current address 162 is selected, the failure is false. However, advantageously, by delaying the writing of BTAC 142 to BTAC 142 in most cases, BTAC writes 伫歹 [J 144 can reduce the possibility of BTAC 142 false fall, as shown in Figure 9. Shown. At decision block 922, control logic 806 determines if the BTAC write queue 144 is empty by determining if queue depth 146 is equal to zero. If so, the flow jumps to decision block 914; otherwise, the flow jumps to decision block 922 to update BTAC 142 because BTAC 142 may not be read. Referring now to Fig. 10, there is shown a block diagram of a logic circuit in the microprocessor 100 in accordance with the first embodiment of the present invention for invalidating the redundant target address in the BTAC. Figure 10 shows that tag array 304 of BTAC 142 of Figure 3 receives address 182 of Figure 1 and responsively generates four tags, labeled tagO 1002A, tagl 1002B, tag2 1002C and tag3 1002D, collectively referred to as tag 1002. Tag 1002 includes a label 502 of Figure 5 that is transmitted from 4 to 4 of tag array 304. In addition, tag array 304 responsively generates 8 valid bits [7:0], designated 1004, which is 4 28 I283827828t from tag array 304.

Wf1.doc/006

95-9-13 A valid bit 504 and B valid bit 506 are transmitted to the respective directions. The microprocessor 1A also includes a comparator 1012 coupled to the tag array 304, which receives the address 182. In the embodiment of FIG. 10, the comparator 1012 includes four 20-bit comparators, each comparator comparing the higher order 20 bits of the address 182 with the associated tag 1002 to generate four matching signals, designated as matchO 1006A, Matchl 1006B, match2 1006C and match3 1006D are collectively referred to as match signal 1006. If the address 182 matches the associated tag 1002, the comparator 1012 generates a match signal 1006 that is true. Microprocessor 100 also includes control logic circuit 1014 coupled to comparator 1012, which receives matching signal 1006 and valid signal 1004. If the selected instruction set of the tag array 304 has a complex signal 1006 with a true match and at least one valid bit 1004, the control logic circuit 1014 stores a true TA flag. Within the 1024, more than one valid target address representing the same branch instruction is stored in the BTAC 142. In addition, control logic circuit 1014 causes address 182 to be loaded into redundant TA address register 1026. Finally, control logic circuit 1014 loads the redundant TA invalidation data into redundant TA invalid data register 1022. In one embodiment, the data stored in the redundant TA invalid data register 1022 is similar to the BTAC write request 176 of FIG. 7, except that the branch instruction address 702 is not stored because of the address of the branch instruction. Stored in the redundant TA address register 1 〇 26; and also does not store the target address 706, the start bit 708, and the traverse bit 712, since it is irrelevant within the invalid BTAC 142 item; thus, when When redundant TA invalidation is performed, the target address array 302 is not written, and only the tag array 304 is updated to I283827828t wf 1. doc/006 9.

95-9-13 This extra BTAC142 item is invalid. The output of the redundant TA invalid data register 1022 includes the redundant TA invalid data signal 244 of FIG. The output of the redundant TA flag register 1024 includes the redundant TA requirement 214 of FIG. The output of the redundant TA address register 1026 includes the redundant TA address 234 of FIG. In one embodiment, the generation equation for the direction 724 stored in the redundant TA invalid data register 1022 and the redundant TA flag register 1024 is shown in Table 2 below. In Table 2, the effective bit [3] includes the logical OR result of the A significant bit [3] 504 and the B significant bit [3] 506; the valid bit [2] includes the A significant bit [2] 504 and The logical OR result of B significant bit [2] 506; the valid bit [1] includes the logical OR result of A valid bit [1] 504 and B valid bit [1] 506; and the valid bit [0] includes The logical OR result of A valid bit [〇] 504 and B valid bit [0] 506. RedundantInvalWay[3]=(valid[3]&match[3])&((valid[0]&match[0])| (valid[ l]&match[l])|(valid[2 ]&match[2]));

RedundantInvalWay[2]=(valid[2]&match[2])&((valid[0]&match[0])| (valid[l]&match[l]));

RedundantInvalWay[l]=(valid[l]&match[l])&(valid[0]&match[0]);RedundantInvalWay[0]=0; /*Way 0 will never be invalid*/ RedundanInAFlag=((valid[3]&match[3])&(valid[2]&match[2]))| ((valid[3]&match[3])&(valid[l ]&match[l]))| ((valid[3]&match[3])&(valid[0]&match[0]))| ((valid[2]&match[2 ])&(valid[l]&match[l]))| ((valid[2]&match[2])&(valid[0]&match[0]))| ((valid [I]&match[l])&(valid[0]&match[0])); In order to invalidate the redundant target address of Figure 10, the appropriate operation is 30 1283827s 28twfl .doc/006

95-9-13, as shown in Figure 11, a series of instructions are executed as an example, which can generate redundant target address items of the same branch instruction in BTAC142. The first current capture address 162 of Figure 1 is input to the instruction cache 104 and the BTAC 142. The cache line selected by the first current capture address 162 includes a branch instruction called branch-A. The first current capture address 162 selects one of the instruction sets within the BTAC 142, referred to as the instruction set N. Inward of the instruction set N, none of the tags 1002 match the first current capture address 162; therefore, the BTAC 142 is lost. In this case, the longest unused orientation represented by lru値508 is 2. Therefore, the information about the update of BTAC 142 of branch-A is sent down the pipeline, together with the branch-A which represents the need to be updated to 2. Next, a second current capture address 162 is input to the instruction cache 1 〇 4 and BTAC 142. The cache line selected by the second current capture address 162 includes a branch instruction, called branch-B. The second current capture address 162 also selects the instruction set N and hits the 3 direction of the instruction set N; then, the BTAC 142 generates a hit. In addition, the BTAC 142 updates the command set N to lru 508 for 1 direction. Next, because branch-A is part of the compact loop of the code, the first current capture address 162 is again input to the instruction cache 104 and BTAC 142, and the instruction set N is again selected. Since the first execution of branch-A did not reach the storage phase 128 of Figure 1, BTAC 142 did not utilize the target address of branch-A for updates. Then, the BTAC 142 is again defeated. However, the longest unused position referred to by lru値508 this time is 1, because lru5〇8 is updated in response to the hit of branch-B. Therefore, the information about the second execution of the branch-A update BTAC 142 is sent down the pipeline, along with the second execution of the branch-A, which must be updated. 31 I283822.S, )& /f 1 . doc/00 6 1 9 repair (A) replacement staff 95-9-13 Next, the first branch-A reaches the storage phase 128 and generates a BTAC write request 176 updates the direction of instruction set N to 2 using the target address of branch-A, which will be performed subsequently. Next, the second branch-A arrives at the storage phase 128 and generates a BTAC write request 176 to update the direction of the instruction set N to 1 using the target address of branch-A, which will be performed subsequently. Therefore, the same branch instruction, branch-A, two valid items exist in BTAC142. One of these items is redundant and makes the use of BTAC 142 less efficient because the redundant item can be used by another branch instruction and/or can take up the φ valid target address of another branch instruction. Referring now to Figure 11, there is shown an operational flow diagram of the redundant target address device in accordance with Figure 10 of the present invention. Flow begins at block 1102. At block 1102, the arbiter 202 allows the BTAC read request 212 of FIG. 2 to access the BTAC 142, causing the multiplexer 148 to select the current capture address 162 to be placed on the address signal 182 of FIG. 1 and generate the Control signal 252 of FIGURE 2 is representative of the reading of BTAC 142. Next, the lower order bit of the currently retrieved address 162 is passed through the address 182 as an index to select the command set of the BTAC 142. Flow continues to block 1104. # At block 1104, comparators 1〇12 compare all four of the instruction sets of the selected BTAC 142 to the tag 1〇〇2 of FIG. 10 and the high order bits of the current fetch address 162 set on the address signal 182. The element is generated to produce the match signal 1006 of FIG. Control logic circuit 1014 receives match signal 1006 and valid bit 1004 of FIG. Flow continues to block 1106. At block 1106, control logic circuit 1014 determines if more than one valid tag match has occurred. That is, according to the valid bit 1004 and the matching letter 32 1283 82l7s 2 81 wf 1 .doc/|§.6, the screen is replaced by the page 95-9-13, the control logic circuit 1014 determines whether or not There are more than two valid directions in the instruction set of the BTAC 142 selected by the current address 162 to have a valid matching tag 1002. If so, the flow continues to block 1108; otherwise, the process ends. At block 1108, control logic circuit 1014 stores a true TA flag register 1024, stores address 182 in excess TA address register 1026, and stores invalid data in redundant TA invalid data register 1022. In particular, the control logic circuit 1014 stores the write enable field A 714, the write enable B field 716, the invalid A block 718, and the invalid B field 722 in the redundant TA invalid data register 1022. . In addition, control logic circuit 1014 stores the header field 724 of Table 2 as described in FIG. 10 in a redundant TA invalid data address register 1022. Flow continues to block 1112. At block 1112, the arbiter 202 allows the redundant TA request 214 of FIG. 2 to access the BTAC 142, causing the multiplexer 148 to select the redundant TA address 234 to be placed on the address signal 182 and generate the control signal 252 of FIG. To indicate the writing of BTAC142. Next, the lower order bits of the redundant TA address 234 are passed through the address 182 as an index to select the instruction set of the BTAC 142. The BTAC 142 receives the redundant data signal 244 output by the redundant TA data register 1022 and invalidates the directions pointed to by the field 724 in the selected instruction set. Flow ends at block 1112. Referring now to Figure 12, there is shown a block diagram of a deadlock avoidance logic circuit within the microprocessor 100 in accordance with the present invention. Figure 12 shows the BTAC 142 of Figure 1, the instruction cache 104, the instruction buffer 106, the instruction normalizer 108, the normalized instruction queue 112 and the multiplexer 136, and the control logic 1014 of Figure 10. 33 1283827m twf 1 . d oc/006 ψ 丨 1 1 replacement page 95-9-13 As shown in Fig. 12, the microprocessor 100 also includes a dead knot invalid data register 1222, a dead knot flag register 1224, And a dead-tie address register 1226, the instruction normalizer 108 decodes the instructions stored in the instruction buffer 106, and if the instruction normalizer 1 解码 8 decodes the branch instructions across the two cache lines, The true F_wrap signal 1202. In particular, when the instruction normalizer 108 decodes the branch instruction across the two cache lines, once the decoded one of the first cache lines in the instruction buffer 106 is decoded, the first branch line is decoded. In part, regardless of whether the instruction normalizer 108 has been decoded and not stored in the other portion of the traversal branch instruction in the second cache line in the instruction buffer 106, the instruction normalizer 1 产生 8 is generated as True F_wrap signal 1202. The F_wrap signal 1202 is input to the control logic circuit 1014. When the current capture address 162 is lost, the instruction cache 104 is generated as a true fall signal 1206. The drop signal 1206 is input to the control logic circuit 1014. When the current capture address 162 input to the instruction cache 104 is predicted, that is, when the current capture address 162 is a predictive address, the instruction cache 104 is generated as one of the true prediction signals 1208, For example, when the multiplexer 136 selects the BTAC prediction target address 164 as the current capture address 162. The predictive signal 1208 is input to the instruction cache 104. In one embodiment, the instruction cache 104 sends the prediction signal 1208 to the instruction fetcher 102 of FIG. 1 such that the instruction fetcher 102 discards the fetch from the predictive memory address of the memory to the instruction fetch 104. The reason for the cache line will be described below with reference to Figure 13. 34 1283 8Z7: 28twfl .doc/006

95-9-13 BTAC 142 generates an Execute/Do Not Execute (T/NT) signal 1212 which is output to control logic circuit 1014. The true T/NT signal 1212 represents the address 182 hits the BTAC 142, and the BTAC 142 predicts that a branch instruction is included in the cache line provided by the instruction cache 104 in response to the current capture address 162, representing the The branch instruction is to be executed, and the target address of the branch instruction is set on the BTAC prediction target address signal 164 on behalf of the BTAC 142. The BTAC 142 generates a T/NT signal 1212 based on the predicted state A 602 or the predicted state B 604 of Figure 6, depending on whether the BTAC 142 uses the A or B portion during branch prediction. The BTAC 142 also generates a B"vrap signal 1214 that is output to the control logic circuit 1014. The traversal bit 406 of Figure 4 of the selected BTAC target address array item 312 is set to a B_wrap signal 1214. Thus, the false representation of the B_w:rap signal 1214 represents that the BTAC 142 predicts that the branch instruction does not span the two cache lines. In one embodiment, control logic circuit 1014 temporarily stores B_wrap signal 1214 to maintain the B of B_wrap signal 1214 obtained from previous BTAC 142 access. Control logic circuit 1014 also produces the current command indicator 168 of Figure 1. Control logic circuit 1014 also produces a control signal 1204 which is an input select signal for multiplexer 136. If the control logic circuit 1014 detects the deadlock state (ie, the temporarily stored B-wrap signal 1214 is false, and the F_wrap signal 1202, the nulling signal 1206 and the prediction signal 1208 are true), this will be detailed below. Then, the control logic circuit 1014 stores a token in the dead-tag flag register 1224 to indicate that there is a dead-end state, so that the item in the BTAC 142 causing the dead-end state is invalidated. In addition, the control logic circuit 1014 loads 128383⁄4

28twf 1 .doc/006

95-9-13 Dead knot invalid data to the dead knot invalid data register 1222. In one embodiment, the data stored in the dead-end invalid data register 1222 is similar to the BTAC write request 176 of Figure 7; except for the branch instruction address 702 not stored, because the address of the branch instruction is stored Within the dead node address register 1226; and the target address 706 is not stored, the start bit 708 and the traverse bit 712, because within an invalid BTAC 142 item, these bits are irrelevant; thus, when performing a dead knot In the case of invalidation, the target address array 302 is not written, and only the tag array 304 is updated to invalidate the mis-tested items of the BTAC 142. The output of the dead-end invalid data register 1222 includes the dead-end data signal 246 of FIG. The output of the dead-tie flag register 1224 includes the dead-end request 216 of Figure 2. The output of the dead-tie address register 1226 includes the dead-end address 236 of Figure 2. The direction 724 stored in the dead-end invalid data register 1222 is caused by the BTAC 142 causing the dead-end state. If the control logic circuit 1014 detects the deadlock state, after invalidating the misdetected item, the control logic circuit 1014 also generates a control signal 1204 to cause the multiplexer 1306 to select the current command indicator 168 to cause micro The branch of processor 100 causes the cache line including the misdetected branch instruction to be retrieved again. Referring now to Figure 13, there is shown an operational flow diagram of the deadlock avoidance logic circuit in accordance with Figure 12 of the present invention. Flow begins at block 1302. At block 1302, the current capture address 162 is input to the instruction cache 104 and to the BTAC 142 via the address signal 182. In Fig. 13, the current capture address 162 is referred to as the capture address A. The flow continues to block 1304. 1283822 28twfl .doc/006

95-9-13 At block 1304, the instruction cache 104 provides a cache line (referred to as cache line A) designated by the capture address A to the instruction buffer 106, the cache line A including the first branch instruction Part, but does not include all of the branch instructions. The flow continues to block 1306. At block .1306, in response to the retrieved address A, the BTAC 142 predicts that the branch instruction in the cache line A will be executed and set on the T/NT signal 1212, generating a false B_wrap signal 1214 and a prediction target. The address is located on the BTAC prediction target address 164. Flow continues to block 1308. At block 1308, control logic circuit 1014 controls multiplexer 136 to select BTAC prediction target address 164 as the next current capture address 162, referred to as capture address B. Control logic circuit 1014 also produces a prediction signal 1208 that is true because BTAC prediction target address 164 is predictive. The flow continues to block 1312. At block 1312, the instruction cache 104 is generated as a true fail signal 1206 to indicate that the branch address B is dropped within the instruction cache 104. Normally, the command extractor 102 may retrieve the lost cache line from the memory; however, because the prediction signal 1208 is true, the command normalizer 108 does not retrieve the cache line from the memory, for the reason that it will be underneath. description. Flow continues to block 1314. At block 1314, instruction normalizer 108 decodes cache line A in instruction buffer 106 and generates a true F_wi*ap signal 1202 because the branch instruction spans the two cache lines. The instruction normalizer 108 waits for the next cache line to be stored in the instruction buffer 106 so that it can normalize the branch instructions to output to the normalized instruction queue 112. The flow continues to block 1316. 1283822 28twfl .doc/〇)〇6 95-9-13 At block 1316, control logic circuit 1014 determines whether the temporarily stored B_wrap signal 1214 is false, whether the F_wrap signal 1202 is true, and whether the null signal 1206 is true.値 and prediction signal 1208 is true; this includes the dead knot state described below. If so, the process continues to block 1318; otherwise, the process ends. At block 1318, control logic circuit 1014 invalidates the BTAC 142 item causing the dead-end state, as described with reference to FIG. Next, when the capture address A is input to the BTAC 142 next time, the BTAC 142 will fail, because the item causing the dead state is now invalidated. Flow continues to block 1322. At block 1322, control logic circuit 1014 controls multiplexer 136 to branch to current instruction indicator 168 as described with reference to FIG. In addition, when control logic circuit 1014 controls multiplexer 136 to select current command indicator 168, control logic circuit 1014 generates a predicted signal 1208 that is false because the current command indicator 168 is not a predictive memory address. It is likely that the current instruction indicator 168 will hit the instruction cache 104; however, if there is no hit, the instruction fetcher 102 will retrieve the cache line specified by the current instruction indicator 168 from the memory because the prediction signal 1208 represents the current Command indicator 168 is not predictive. Flow ends at block 1322. If the decision block 1316 is true, the reason for the dead state is that the necessary condition for the dead knot is present. The first cause of a dead knot is a multi-byte branch instruction that spans two different cache lines. That is, the first portion of the branch instruction byte is located at the end of the first cache line, and the second portion of the branch instruction byte is located at the beginning of the next cache line. Because of the possibility of crossing the branch instruction, the BTAC142 must store the prediction one 38 1283827s

95-9-13 Whether the branch instruction crosses the information of the cache line, so that the control logic circuit 1014 knows whether to capture the next cache line to obtain the branch instruction before extracting the cache line located at the target address 164 The lower half of the byte. If BTAC142 stores incorrect prediction information, BTAC142 may incorrectly predict that the branch instruction does not span, but actually spans. In this example, the instruction normalizer 108 will utilize the first half of the branch instruction to decode the cache line and detect that a branch instruction already exists, but not all of the branch tuples are available for decoding. The instruction normalizer 108 will wait for the next cache line. The pipeline will wait for more instructions to be normalized to execute. The second condition causing the dead knot condition is that because the BTAC 142 predicts that the branch instruction does not straddle, the branch control logic circuit 1014 retrieves the cache line implied by the target address 164 of the BTAC 142 output (no next step is taken) Cache line). However, the target address 164 falls within the instruction cache 104. Therefore, the instruction normalizer 1〇8 waits for the next cache line to be retrieved from the memory. The third situation that causes a deadlock situation is that the microprocessor chipset does not anticipate that instructions will be fetched from certain memory address ranges and if the microprocessor generates an instruction from an unanticipated memory address range. At the time of the acquisition, the microprocessor chipset may cause the system to be idle or cause other undesirable system conditions. Predictive addresses, such as destination address 164 output by BTAC142, may cause instruction fetches from unanticipated memory address ranges. Thus, the microprocessor 1 does not draw a lost cache line from one of the predictive BTAC prediction target addresses 164 of the memory. Therefore, the instruction normalizer 1〇8 and other parts of the pipeline are waiting for another 39 1283827s 950·Λ3 day repair (jk) is replacing page I 2 81 wf 1 . d 〇c / Ο 6 95-9-13 Take the line. At the same time, the command extractor 102 waits for the pipeline to signal that a non-predictive capture is to be performed. In the case of a non-dead knot, for example, if the target address 164 hits the instruction cache 104, the instruction normalizer 108 normalizes the branch instruction (although it utilizes incorrect bytes) and normalizes it. The branch instruction is provided to the execution phase of the branch, which detects the misdetection and corrects the misdetection of the BTAC 142, thereby causing the prediction signal 1208 to become false. However, in the event of a deadlock, the execution will never detect a misdetection because the instruction normalizer 108 does not provide the normalized branch instruction to the execution phase of the branch because the instruction normalizer 108 is still waiting for the next Cache line. Therefore, a dead knot occurs. However, the dead-end avoidance logic circuit of Fig. 12 can effectively prevent the occurrence of a dead-end condition, as described in Figs. 12 and 13, thus allowing the microprocessor 100 to operate properly. Although the invention has been described in detail, its features and advantages, the invention may include other embodiments. For example, although the write queue is related to 單埠BTAC, in some microprocessor architectures, false nulls may occur in multiple BTACs, albeit at a lower frequency. Therefore, the write queue can be applied to reduce the false drop rate of the multi-turn BTAC. In addition, in some microprocessors that do not read the BTAC, there may be other cases than those described herein in which the requirements listed in the write queue can be written to the BTAC. In addition, while the invention has been described in detail, its features and advantages, the invention may include other embodiments. In addition to the use of hardware to implement the present invention, the present invention can also be embodied in computer readable code (e.g., computer readable code, data, etc.) in a computer usable (e.g., readable) medium. The computer code may fulfill the functionality or manufacture of the disclosed invention or both. For example, general programming languages (eg, C, C++, JAVA, etc.); GDSII database; 128383⁄4 2 8 twf1.doc/006

95-9-13

Hard description language (HDL), including Verilog HDL, VHDL, Altera HDL (AHDL), etc.; or other existing programs and/or circuits (also known as summary). The computer code can be loaded into any conventional computer usable (eg, readable) medium including semiconductor memory, magnetic disk, optical disk (eg, CD-ROM, DVD-ROM, etc.); The form is implemented in a computer usable (eg, readable) transmission medium (eg, a carrier wave, or other medium including digital, optical, or analog media). Therefore, the computer code can be transmitted over the communication network including the Internet and the corporate network (instruction tranet). It should be understood that the present invention can be implemented in a computer code (for example, a part of the core of the IP, such as a microprocessor core, or a system level design, such as a system single chip (SOC)) and converted into an integrated body. Part of the hardware of the circuit. In addition, the present invention can be implemented as a combination of hardware and computer code. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

BRIEF DESCRIPTION OF THE FLOW FIG. 1 shows a block diagram of a microprocessor in accordance with the present invention. Fig. 2 is a partial block diagram showing a portion of a microprocessor in accordance with Fig. 1 of the present invention. Fig. 3 is a partial block diagram showing a portion of the BTAC according to Fig. 1 of the present invention. Fig. 4 is a block diagram showing the contents of the target address array item in accordance with Fig. 3 of the present invention. Figure 5 shows the contents of the tag array item according to Fig. 3 of the present invention 41 128382^

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Block diagram of 95-9-13. Fig. 6 is a block diagram showing the contents of a counter array item according to Fig. 3 of the present invention. Fig. 7 is a block diagram showing the contents of the BTAC write request in accordance with Fig. 1 of the present invention. Fig. 8 is a block diagram showing the BTAC write queue according to Fig. 3 of the present invention. Fig. 9 is a flow chart showing the operation of the BTAC write queue according to Fig. 1 of the present invention. Figure 10 is a block diagram showing the redundant target address invalidation logic circuit of the BTAC in the microprocessor in accordance with the first embodiment of the present invention. Fig. 11 is a flow chart showing the operation of the redundant target address device in accordance with Fig. 10 of the present invention. Figure 12 is a block diagram showing the dead-end avoidance logic circuit in the microprocessor in accordance with Figure 1 of the present invention. Figure 13 is a flow chart showing the operation of the deadlock avoidance logic circuit according to Fig. 12 of the present invention. Schematic Description = 100: Microprocessor 102: Instruction Extractor 104: Instruction Cache 106: Instruction Buffer 108: Instruction Normalizer 112: Normalized Instruction Array 114: Instruction Translator 1283827, 828 twfl .doc/ 006

95-9-1 3 116: Post-translation command queue 118: Register stage 122: Address stage 124: Data stage 126: Execution stage 128: Storage stage 132: Write back stage 134: Adder 136, 148, 206 ··Multiplexer 138: Instructions

142 : BTAC 144 : BTAC write queue (BWQ) 146 : 深度 column depth 152 : branch misdetection signal 154 : predictive replacement signal 156 : command buffer full full signal 15.8 : command cache idle signal 162 : current capture bit Address 164: Prediction target address 1 6 6 : Next acquisition address 168: Current instruction indicator 172: Correct address 174: Replace prediction target address 176: BTAC write request 178: BTAC write queue address 43

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95-9-13 182: Address 202: Arbiter 212: BTAC Read Requirement Signal 214: Excess Target Address (ΤΑ) Requirement Signal 216: Dead End Requirement Signal 218: BWQ Non-empty Signal 222: BWQ Full Full Signal 234: Redundant address 236: dead node address φ 244: excess data signal 246: dead junction data signal 248: BWQ data signal 252, 258, 262, 1204: control signal 256: data signal 302: target address array 304: label array 306: Counter Array 312: Target Snapshot® 314: Tag Array Item 316: Counter Array Item 402: Branch Destination Address 404, 708: Start Field 406: Across Byte 502: Label 504: Α Valid Bit 44 1283827, 81 wf 1

95-9-13 506: B valid bit 508: lru field ^ 602: predicted state A counter 604: predicted state B counter 606: A/Blru bit 702: branch instruction address field 706: target address 712 : Horizon Bit 714: Write Enable A Field · 716: Write Enable B Field 718: Invalid A Field 722: Invalid B Field 724: Direction Field 802: Storage Element 804, 1004 ·· Valid Bits 806, 1014: Control Logic Circuit 1002: Tag 1006: Matching Off 1012: Comparator 1022: Extra TA Invalid Data Register 1024: Extra TA Flag Register 1026: Extra TA Address Register 1202 : F_wrap signal 1206: Falling signal 1208: Predicted signal 45 128383⁄4 828twf 1 .d 哔 月 曰 曰 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行B-wrap signal 1222: dead knot invalid data register 1224: dead knot flag register 1226: dead node address register

46

Claims (1)

1283827s 27828twfl .doc/006 顼 委 明 明 明 明 明 明 来 来 明 明 明 明 Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε Ε The efficiency of one of the branch target address caches in the processor, the write queue device includes: a request input unit, receiving a request to update the branch target address cache, the request including a branch instruction target address; a plurality of storage elements storing the requirements received by the request input unit; and the control logic circuit 'affining to the storage elements, and storing in the storage elements in response to one or more predetermined conditions One of these requirements is written to the branch target address cache. 2. The write queue device of claim 1, further comprising: a cache idle input unit coupled to the control logic circuit for accessing one another parallel to the branch target address cache When the instruction cache is idle, the one or more predetermined conditions for which the branch target address cache is not read are specified - 〇 3 · The write queue device described in claim 1 of the patent scope includes : a buffer full full input unit, affinity to the control logic circuit, because an instruction buffer is full, which specifies one of the one or more predetermined conditions in which the branch target address cache is not read, wherein The instruction buffer accesses an instruction fetch receive instruction from a cache parallel to the branch target address. 4. The write queue device of claim 1, further comprising: a predictive replacement input unit coupled to the control logic circuit because 1283822 8twf 1 -doc/006 95-9-13 The branch target address cache completes that one of the first branch instruction predictions is replaced by a second branch instruction prediction done by the branch prediction logic circuit in the microprocessor, which specifies the branch target The address cache is one of the one or more predetermined conditions that were not read. 5. The write queue device of claim 1, further comprising: a branch misdetection input unit coupled to the control logic circuit, wherein the branch target address cache is detected to complete a branch instruction False detection, which specifies one of the one or more established conditions in which the branch target address cache is not read. 6. The write queue device of claim 1, further comprising: a therapy column full signal register coupled to the control logic circuit, specifying that all storage components are being stored to be written to the One of the one or more established conditions required for one of the branch target address caches. 7. The write queue device of claim 1, further comprising: a plurality of valid bit registers, coupled to the control logic circuit, each valid bit register indication being stored in a corresponding Whether the requirement in the storage element is valid or not. The writing device according to claim 1, wherein the request further comprises a memory address of the branch instruction. 9. The write queue device of claim 1, wherein the branch target address cache is a ~N-to-instruction set joint cache, wherein the request further comprises specifying that the request is to be written to The information of the N direction in the branch target address cache. 48 1283822, 8twfl .doc/006 95-9-13 10. A microprocessor comprising: an instruction cache, providing a cache line of one of the instruction bytes in response to an instruction fetch address; a branch target address cache, coupled to The instruction cache, predicting a branch target address stored in one of the branch instructions in the cache line; and a write queue coupled to the branch target address cache for storing the branch target address The branch target address of the cache. 11. The microprocessor of claim 10, wherein if the write queue is not empty, when the instruction cache is idle, the write queue utilizes the branch target addresses First update the branch target address cache. 12. The microprocessor of claim 10, further comprising: an instruction buffer coupled to the instruction cache to store zero or more cache lines received from the instruction cache. 13. The microprocessor of claim 12, wherein if the write queue is not empty, when the instruction buffer indicates that it is full, the write queue utilizes the branch targets One of the addresses to update the branch target address cache. 14. The microprocessor of claim 1, further comprising: a branch prediction logic coupled to the write queue, wherein the branch target address cache completes one of the branch instructions After a prediction, the branch prediction logic completes a second prediction of the branch instruction, wherein the microprocessor replaces the first prediction with the second prediction. 15. The microprocessor of claim 14, wherein if the write queue is not empty, the microprocessor utilizes the second prediction to 49 1283827s 28twf 1 .doc/006 watt 1: When the first prediction is replaced by 95-9-13, the write queue updates the branch target address cache with one of the branch target addresses. 16. The microprocessor of claim 10, further comprising: a branch decision logic coupled to the write queue to correct one of the branch instructions of the branch target address cache . 17. The microprocessor of claim 16, wherein if the write queue is not empty, the microprocessor corrects the misdetection of the branch instruction completed by the branch target address cache. The write queue updates the branch target address cache with one of the branch target addresses. 18. The microprocessor of claim 10, wherein if the write queue becomes full, the write queue updates the branch target address cache using one of the branch target addresses . 19. The microprocessor of claim 10, wherein the write queue is being written to the branch target address cache, and if the branch target address cache is read, the branch target bit The address cache has failed. 20. The microprocessor of claim 10, wherein the branch target address cache comprises a memory array to store a plurality of branch target addresses. 21. The microprocessor of claim 10, wherein the branch target address cache comprises a memory array to store a plurality of branch! 22. A method of updating a branch target address cache in a microprocessor, the method comprising the steps of: generating a request to update the branch target address cache; storing the request in a queue; and 128383⁄4 278 28twfl .doc/00 6. Έι条 (笑笑妈妈i 95-9-13) After the storing step, the branch target address cache is updated according to the request. 23. The method of claim 22, wherein the branch target is updated The address cache step is performed in one of the clock cycles of the microprocessor after the storing step. 24. The method of claim 22, further comprising: determining whether the branch target address cache is Not being read; wherein if the branch target address cache is not being read, the update step is performed. 25. The method of claim 24, further comprising: fusing the branch to the branch One of the target address caches is idle and determines whether the branch target address cache is not being read. 26. The method of claim 24, further comprising: an instruction buffer Fully determining whether the branch target address cache is not being read, wherein the instruction buffer receives an instruction outputted from an instruction cache coupled to the branch target address cache. Scope 22 The method of the present invention further includes: determining whether one of the first branch instruction predictions completed by the branch target address cache is replaced by one of the second branch instruction predictions performed by other branch prediction logic circuits in the microprocessor; And if the first branch instruction prediction completed by the branch target address cache is replaced by the second branch instruction prediction, the updating step is performed. 28. The method according to claim 22, further comprising: Determining whether the branch target address cache has misdetected a branch instruction; if the branch target address cache has misdetected a branch instruction, then 8twfl.doc/006 哞September 13th revision) is replacing page 95 -9-13 Perform this update procedure. 29. The method of claim 22, further comprising: determining whether the queue is full; wherein the update step is performed if the queue is full. 52 128382,7: 28twf 1 .doc/006 f 97ΊΤ 95-9-13 instruction cache is idle, a misprediction by the BTAC is being corrected, or the prediction by the BTAC is being overridden. If the write queue becomes full, then It updates the BTAC anyway. VII. Designated representative map: (1) The representative representative of the case is: (1). (2) A brief description of the component symbols of this representative diagram: 10〇: Microprocessor W2: Instruction fetcher 104: Instruction cache 106: Instruction buffer 1〇8: Instruction normalizer 112: Normalized instruction f 114: instruction translator 116: post-translation instruction queue 118: register stage 122: address stage · 124: data stage 126: execution stage 128: storage stage 132: write back stage 134: adder 136: multiplexer : Command 142 : BTAC 2^28twf 1 .doc/006 95-9-13 144 : BTAC write queue (BWQ) 146 : 深度 column depth 148 : multiplexer 152 : branch misdetection signal 154 : prediction replacement signal 156 : Instruction Buffer Full Completion Signal 158: Command Cache Idle Signal 162: Current Capture Address 164: Prediction Target Address 166: Next Capture Address 168: Current Instruction Indicator 172: Correct Address 174: Replace Prediction Target Address 176: BTAC write request 178: BTAC write queue address 182: Address VIII. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: