TW200414034A - Apparatus and method for efficiently updating branch target address cache - Google Patents

Abstract

A microprocessor with a write queue for a branch target address cache (BTAC) is disclosed. The BTAC is read in parallel with an instruction cache in order to predict a target address of a branch instruction in the accessed cache line. In one embodiment, the BTAC is single-ported; hence, the single port must be shared for reading and writing. When the BTAC needs updating, such as when a branch target address is resolved, the microprocessor stores the branch target address and related information in the write queue. Thus, the write queue potentially enables updating of the BTAC to be delayed until the BTAC is not being read, such as when the instruction cache is idle, a misprediction by the BTAC is being corrected, or the prediction by the BTAC is being overridden. If the write queue becomes full, then it updates the BTAC anyway.

Description

200414034 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a branch prediction of a microprocessor (branch predicti ο η), and in particular to a branch prediction using a predictive branch target address cache. . Previous technique # ί

Modern microprocessors are pipelined (P i Pe 1 i n e) microprocessors. That is, several instructions can operate simultaneously in different blocks or pipeline stages of a microprocessor. By John L. Hennessy and David A. Patterson in his book: Computer Architecture: A

Quantitative Approach (Second Edition by Morgan Huffman Press (San Francisco, California) in 1996) defines the pipeline as: "an implementation technique where multiple instructions overlap with each other (animp 1 ementati ο η technique by multiple instructions are overlapped in execution). It provides an excellent description of pipelines: A pipeline is similar to an assembly line. In a vehicle assembly line, there are many steps, each of which makes some contribution to the assembly of the vehicle. Although for different vehicles, each The operation of the steps is parallel to other steps. In the computer pipeline, each pipeline of the pipeline completes a part of the instruction. Similar to the assembly line, different steps complete different parts of the parallel ^ different order. Each step is called after the pipe.卩 都 段 (pipe; ΓΓ ^ Γ ?: ^ (ρ1γ segraent) ° The two ends of the & 出 " let you enter from the first corner, process through these stages, and output in other knowledge that the squid is like an assembly line handling a vehicle. Each time: ί! The processor operates according to the clock cycle.-In general, the instructions from the microprocessor pipeline are _ Forward to another stage

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Page 8 200414034 V. Description of the invention (2) One stage. In a vehicle assembly line, if workers on the line are idle because there are no vehicles to be assembled, the production or performance of the line will decrease. Similarly, if a microprocessor's pipeline is idle because there are no instructions to operate in a clock cycle, which usually refers to this state as a pipeline bubble, the performance of the microprocessor will decrease. One of the possible causes of pipeline bubbles is branch instructions. When processing a branch instruction, the processor must determine the destination address of the branch instruction and start fetching the instruction at the target address instead of the next address after the branch instruction. Even if the branch instruction is a status branch instruction (that is, whether the branch is to be executed according to whether a specific condition exists), in addition to determining the target address, the processor must determine whether the branch instruction is to be executed. carried out. Because the pipeline stage that finally determines the target address and / or branch result (that is, whether the branch is to be executed) is usually below the instruction fetch stage, a bubble may be generated. To solve this problem, modern microprocessors generally use branch prediction mechanisms to predict target addresses and branch results early in the pipeline. An example of a branch prediction mechanism is a branch target address cache (BTAC), which is parallel to fetching an instruction from an instruction cache of the microprocessor to predict the branch result and the target address. When the microprocessor executes the branch instruction and finally decides to execute the branch and determine its target address, the address of the branch instruction and its target address are written into the BAT AC. The next time the branch instruction is fetched from the instruction cache, the branch instruction address will hit the B T A C and the B T A C can output the branch instruction target address early in the pipeline. Effective B T A C eliminates or reduces bubbles waiting for branch instruction decision

12828twf.ptd Page 9 200414034

5. Description of the invention (3) Quantity to improve processor performance. However, when the part of the pipeline of the bta error fetch instruction must be discarded, when! Is detected, make sure that the instruction is' when the instruction abandonment and fetch occurs, and ^ is necessary to get a positive bubble. When the microprocessor's pipeline is deeper, BTAC 2 is effective 1 = the key to the gas performance. It will also be one of the factors that affect the effectiveness of B T AC. Store more points. The element that is micro-processed into the chip surface (such as BTAC) is the size of the target address and (c e 1 1). Special area. It is not possible to simultaneously advance into a given clock cycle by the port cell unit or write, which is greater than the single-chun BTAC. From this point of view, the number of target addresses that can be stored in a multi-port BTAC is stable. The main reason is that BTAC is the target instruction stored in the product. The area is always limited and the area becomes smaller. The related information is that the BTAC line composed of the port is read and written, but reading at the same time means that the false target bit amount, so the BTAC is not the address of the target address compared with the hit rate. 'Therefore, the area of the unit cell existing in the BTAC that can affect the BTAC as small as possible is written by the multi-port unit cell in a given clock. However, it is necessary to set a small number of BTAC sites to reduce the number of BTAC sites. The number of two branch instructions f is effective. However, the BTAC that can only be read as a unit cell of a given function in a multicell unit cycle can be allowed to actually face the efficiency of a single BTAC in the area of the BTAC. Therefore, however, because the port B T A C can only read or write within a given clock cycle, and cannot read and write at the same time, this fact will reduce the effectiveness of BTAC due to f a 1 s e miss. In the cycle that BTAC needs to be read, when the port BTAC is being written, such as updating the BTAC with a new target address or invalidating a target address, a false fall occurs. In this case

12828twf.ptd Page 10 200414034 V. Description of the invention (4), BTAC must fail the read because it cannot supply the target address that may already exist in BTAC because the BTAC is being written. Therefore, there is a need for a method and a device that can reduce the falsification of anomalous BTAC. Another phenomenon that may reduce the effectiveness of BTAC is that BTAC stores the target address of a branch instruction multiple times. This phenomenon may occur in a multi-way set-associative BTAC. Because the BTAC space is limited, excess target address storage will reduce the effectiveness of BTAC, because the redundant B T A C item can store the target address of another branch instruction. The longer the pipeline, that is, the larger the number of stages, the more likely the extra target addresses will be stored in the BTAC. The most common case where the same branch instruction is cached multiple times in BTAC is in a tight loop of code. The first execution of a branch instruction and its target address are written to the BTAC, such as to the second direction, because the second direction is the longest unused. However, before the target address is written to the BTAC, the branch instruction reappears, that is, the instruction cache fetch address of the B T AC check fails, because the target address has not been written to the BTAC. The target address is then written a second time to the BTAC. If a BTAC read that inserts a different branch instruction into the instruction set makes the second direction no longer the longest unused, the other direction, such as the first direction, will be selected to write the target address a second time. Now, the target address of the same branch instruction exists twice in the BTAC. This is a waste of BTAC space and reduces BTAC validity, because the second write is likely to overwrite a valid target address of another branch instruction. Therefore, there is a need for a method and apparatus that can avoid the waste of useful BTAC space caused by the excess cache of the target address of the same branch instruction.

12828twf.ptd Page 11 200414034 V. Description of the Invention (5) Furthermore, the combination of certain conditions related to the predictability of BTAC will cause dead knots in the microprocessing (d e a d 1 0 c k). The combination of B T A C's branch prediction, branch instructions that cross the instruction cache boundary, and the fact that the processor bus will trade predictive instruction fetches can cause erroneous conditions and cause deadlocks in some cases. Therefore, what is needed is a method and apparatus that can avoid dead-knot conditions in microprocessors employing predictive BTAC. SUMMARY OF THE INVENTION The present invention provides a write queue to delay the writing of BTAC until the B T AC is unread, thereby reducing the false fall rate. In one aspect, the present invention provides a write queue that improves the efficiency of a branch target address cache (BTAC) in a microprocessor. The write queue includes a request input, and a request is received to update the B T AC. The request includes a branch instruction target address. The write queue also includes a plurality of storage elements that store the request received by the request input. The write queue also includes control logic circuitry coupled to the storage elements and writing one of the requirements stored in the storage elements to the BTAC in response to one or more predetermined conditions. In another aspect, the invention provides a microprocessor. The microprocessor includes an instruction cache that provides a cache line of instruction bytes in response to an instruction fetch address. The microprocessor also includes a branch target address cache (BTAC), which is coupled to the instruction cache and predicts a branch target address of a branch instruction stored in the cache line. The microprocessor also includes a write 伫 歹 | J, which is coupled to the BTAC and stores a branch target address for updating the BTAC.

12828twf.ptd Page 12 200414034 —: Five of the ten more microprocessors, description of the invention (6) In another point of view,-q 王 人 7TV 丨 ~ Do singal shishi address branch cache (BTAC) method. The second and second steps of the method: generate a request to update the BTAC; store the request a γ and update it according to the request after the storing step ^ Ding Huan, in another view, the present invention provides a still ^ . Computer data signals, including computer-readable = on a transmission medium processor. The code includes the first code, and the second is to provide a command imitation address at a micro-instruction fetch address, and to provide an instruction imitation-81 command cache. The response "encloses the second code and provides one; ^ = two blocks to fetch. The program has 2 target addresses. The program = including 1 = a branch of a branch instruction 'is coupled to the BTAC to store the first code and provide a write address. The store is used to update the BTAC.支 目 # The advantages of the present invention are inferior to the fact that "there is no reason why K should be written when BTAC is read ^ AC ^ 5 A single" bTaC "can be applied to increase the efficiency of BTAC. This BTAC ^ In order to reduce the BTac JAC, rather than the large application area BTAC 〇 'address' and therefore more efficient U month f makes it possible to store the ^ ^ ^ for the purpose of making the present invention more understandable, the following addiction and other purposes The detailed description is as follows: The advantages of the best embodiment of 1 * υσ can be explained more clearly. The ear is also an example, and the figure of the figure is combined. For details, reference is made to FIG. 1, ',,, not according to the present invention. One of Fangfeng, a microprocessor of 100, compared to a multi-port ZUU414UJ4 of similar size. 5. Description of the invention (Ό pipeline microprocessor Block diagram. The microprocessor includes the instruction fetcher 1 〇 The microprocessor 100 includes-refers to-fetches instructions from the microprocessor 1 (7 extractor 102 body) 1 3 8. In a h, a redundant memory (for example, the basic unit of system memory access line (granu ~ 5 embodiment, the instruction fetcher 102 is from the fast one embodiment, the instruction is the memory in the county g Instruction. All instructions in the instruction set can be extended. In other words, in the microprocessor, the microprocessor 100 includes: i ΐ f are all different. The eight Cui Kuo private set is essentially compatible with one of the microprocessors of the X 8 6 wooden private set with variable instruction length. The microprocessor 100 also includes an instruction cache i 04, which is coupled to instruction fetch. 1 0 2. Instruction cache 1 04 Receives the instruction line of the instruction fetcher 丨 〇 2 cache line and caches the microprocessor 丨 〇 subsequent use of the instruction cache line. In an implementation In the example, the instruction cache 丨 〇4 includes a 64-way 4-way instruction set combined with L 1 (1 eve 1-1) cache. When an instruction falls into the instruction cache 丨 〇4 , The instruction cache 1 0 4 will notify the instruction fetcher 1 0 2, which in response retrieves the cache line including the failed instruction from the memory. A current fetch address 1 6 2 is input to the instruction cache 1 〇, 4 to select the cache line. In one embodiment, the cache line in the instruction cache 104 includes 32 bytes. The instruction cache 1 〇4 also generates an instruction cache idle signal 1 5 8 When the instruction cache 1 0 4 is idle, the instruction cache 1 104 generates the instruction cache idle signal 1 5 8 which is a true value. When the instruction cache 104 is not read, the instruction cache 104 will be idle. In one embodiment, if the instruction cache 104 is not read, the BTAC142C of the microprocessor will be discussed in detail below). The microprocessor 100 also includes an instruction buffer 106, which is switched to the instruction fast.

12828twf.ptd Page 14 200414034 V. Description of the invention (8) Take 1 0 4. The instruction buffer 1 06 receives the instruction byte cache lines from the instruction cache 1 0 4 and temporarily stores the cache lines until it is normalized into explicit instructions that can be executed by the microprocessor 100. In one embodiment, the instruction buffer 106 includes 4 items (entry) to store up to 4 cache lines. The instruction buffer 1 0 6 generates an instruction buffer full signal 1 5 6. When the instruction buffer 106 is full, the instruction buffer 106 generates a true instruction buffer full signal 156. In one embodiment, if the instruction buffer 106 is full, then B T A C 1 4 2 cannot be read. The microprocessor 100 also includes an instruction normalizer 108, which is coupled to the instruction buffer 106. The instruction normalizer 108 receives instruction bytes from the instruction buffer 106 and thereby generates a normalized instruction. That is, the instruction normalizer 108 looks at a string of instruction bytes in the instruction buffer 106, determines which bytes include the next instruction and its length, and outputs the next instruction and its length. In one embodiment, the 'normalized instructions include instructions that are essentially in the X 8 6 architecture 4 command set. The instruction normalizer 108 also includes a logic circuit that generates a branch target address, which is called a replacement prediction target address 174. In one embodiment, the branch target address generation logic circuit includes an adder that adds a deviation from a branch instruction to the branch instruction address to generate a substitute predicted target address 174. In one embodiment, the logic circuit includes a branch target buffer to generate a target address of an indirect branch instruction. In one embodiment, the logic circuit includes a call / backhaul stack to generate target addresses for call and return instructions. The instruction normalizer 1 0 8 also includes a predictive replacement signal 1 5 4 ° The instruction normalizer 1 0 8 generates a true prediction replace signal 1 5 4 to replace the microprocessor 1 0 0

12828twf.ptd Page 15 200414034 V. The branch prediction made by BTAC 142 in the description of the invention (9) will be described in detail below. That is, if the target address generated by the logic circuit in the instruction normalizer 1 08 does not match the target address generated by BTAC1 42, the instruction normalizer 1 08 generates a true prediction replacement signal 1 5 4 so that The instruction fetched by the BTAC 1 4 2 prediction is abandoned and the microprocessor 100 branches to the replacement prediction target address 1 74. In one embodiment, BTAC1 42 cannot be read during the time the instruction is abandoned and the microprocessor branches to 1000 to the replacement predicted target address 174. The microprocessor 100 also includes a normalization instruction queue 1 12 coupled to the instruction normalizer 108. The normalized instruction queue 1 1 2 receives the normalized instructions output from the instruction normalizer 108 and temporarily stores the normalized instructions until it is translated into a micro instruction. In one embodiment, the normalization instruction queue 1 12 includes items that store up to 12 normalization instructions, although Figure 4 shows only 4 items. The microprocessor 100 also includes an instruction translator 1 1 4 coupled to the normalized instruction queue 1 1 2. The instruction translator 1 1 4 translates the delta normalized instructions stored in the normalized instruction queue 1 1 2 into micro instructions. In one embodiment, the microprocessor 100 includes a reduced instruction set computer (RISC) core, which executes micro instructions of itself or the reduced instruction set. The microprocessor 100 also includes a post-translated instruction queue i 6 which is coupled to the second post-translated instruction queue 116 and receives the instruction translator " 4 to temporarily store the micro-instructions until it can be used by other micro-instructions.

12828twf.ptd Page 16 200414034 V. Description of the Invention (1) The microprocessor 100 is also complicated. This includes a register stage 1 1 8 which is coupled to a tank swallowing instruction 0 1 16. The register stage is exposed to the translated operators and results. The register stage includes a plurality of register registers for storing instructions to store the user 100 of the microprocessor 100 as a register register section 118. The address stage 122 includes bracket- / site-position stage 122, which is transferred to the register stage. Seven into the bracket bracket address generation logic circuit to generate a register address. Memory instructions and branch instructions). The micro-assessment cuisine 2 04 also includes a resource ㈣ 枓 & 1 1 1 24 includes loading data from the memory to fetch one or more caches from the data loaded in the memory. The power and decision microprocessor 100 also includes an execution stage i 2 6 coupled to the data stage 124. The execution stage 126 includes execution units that execute instructions, such as arithmetic and logic units that execute arithmetic and logic instructions. In one embodiment, the execution section 126 includes an integer execution unit, a floating-point execution unit, a MM × execution unit, and an SS £ execution unit. Execution phase 126 also includes branch instructions to determine logic circuits. In particular, execution · phase 126 determines whether branch instructions are to be executed and whether BTAC 1 4 2 is to be misjudged before branch instructions are to be executed. In addition, execution phase 1 2 6 determines BTAC 1 4 2 Whether the previously predicted branch target address was misdetected by BTAC 1 4 2, that is, whether it is incorrect. If the execution stage 丨 2 6 determines that the previous branch prediction is incorrect, the execution stage 1 2 6 produces a true value The branch mis-measures the signal 1 5 2 so that the instruction fetched due to the BTAC 1 42 2 mis-measures is abandoned and the microprocessor 100 branches to the correct address 1 72. In one embodiment, After the instruction is abandoned and the microprocessor 100 branches to the correct

12828twf.ptd Page 17 200414034 V. Description of Invention (li)-BTAC 142 cannot be read during the period of address 1 72. The microprocessor 100 also includes a storage stage 218, which is coupled to the execution stage $ 126. The storage phase 1 2 8 includes a logic circuit for storing data in the memory in response to the storage microinstruction. The storage phase 28 generates a correct address 172. The correct address 1 72 includes the correct branch target address of the branch instruction. That is, the correct address 1 72 is the non-predictive target address of the branch instruction. When the branch instruction is executed and determined, the correct address 172 is also written to BTAC 142, which will be described in detail at the end. The storage phase 28 also generates a BTAC write request 176 to BTAC142 ° BTAC write request 176 will be described in detail with reference to FIG. 7. The microprocessor 1 0 0 also includes a write back stage 3 2, which is coupled to the storage stage 1 2 8. The write-back stage 1 3 2 includes writing the instruction result to the scratchpad stage 1 1 8 logic circuit. Microprocessor 100 also includes BTAC142. BTAC142 includes cache memory that caches target addresses and other branch prediction information. bTAC 丨 42 generates a predicted target address 1 6 4 in response to receiving an address 1 8 2 from a multiplexer 1 4 8. In a consistent embodiment, b T A C 1 4 2 includes a port cache memory, which is shared by BTAC142 read and write accesses, thus making BTAC142 have a chance of false miss. The BTAC142 and multiplexer 148 will be described in detail under Ma. The & microprocessor 100 also includes a second multiplexer 136 coupled to the BTAC 142. The multiplexer 136 selects one of the six inputs to output to a current fetch address 162. One of the inputs is one generated by an adder 134. _ fetch address 1 6 6 'Adder 1 3 4 adds the size of the current capture address 16 2 to the cache line to generate the next capture Address 1 6 6. In the cache from the command cache

200414034 V. Description of the invention (12) Take a quick, after the line, the multiplexer 136 selects the next capture address 166 to output into the current capture address 162. The other input is the current fetch address 162. The other input is BTAC prediction target address 1 64. If BTAC142 indicates that a branch instruction exists in the current fetch address cached from the instruction 1 04 4 6 2 in the cache line selected by BTAC 1 4 2 predicts that the branch instruction will be executed, then the multiplexer 1 3 6 selects the BTAC prediction target address 1 6 4. The other input is the correct address 1 7 2 received from the storage stage 1 2 8 and the multiplexer 1 3 6 selects the correct address 1 7 2 to make a false detection on a branch. The other input is the replacement prediction target address 174 received from the instruction normalizer 丨 08, and the multiplexer 3 6 selects the replacement prediction target address 174 to replace the BTAC test target address 164. The other input is one = if the instruction index 1 6 8 points to the address of the instruction currently being normalized by the instruction normalizer 108. The multiplexer 136 selects the current instruction index 168 to avoid deadlock situations, as described below. The microprocessor 100 also includes a BTAC write queue (BWQ) 144, which is combined to BTAC 142. The BTAC write queue 144 includes a plurality of storage elements to temporarily store the BTAC write request 176 until it can be written to the BTAC 142. ΒΤΑ (: write to Suining column 1 4 4 receives the branch misdetection signal 1 5 2, the prediction replaces the signal 1 5 4, the instruction buffer full signal 1 5 6, and the instruction cache idle signal 158. Favorable The BTAC write queue 144 can delay the update of BTAC 142 by using the BTAC write request & ~ 176 until the appropriate time indicated by the input signals 52 ~ 158, that is, the time when BTAC 142 is not read, In order to increase the efficiency of BTAC142, it will be detailed below. BTAC write queue 144 generates a BTAC write queue address 178, which is input to multiplexer 148. BTAC write queue 144 also includes storing a current sacrifice ' ^

12828twf.ptd Page 19 (13) 200414034 V One of the registers of depth 146. The queue depth 146 indicates the number of valid BTAC write requirements 176 currently stored in mqi44. The initial value of the queue depth 146 is zero. Each time a BTAC write request 176 is stored in the BTAC write queue 144, the queue depth 1 4 6 increases. Each time a BTAC write request is removed from BWQ144, the queue depth 146 decreases. The BTAC write queue 144 is detailed below. Referring now to Fig. 2, a detailed block diagram of a portion of a microprocessor according to Fig. 1 of the present invention is shown. Figure 2 shows the BTAC write queue 144, BTAC 1 ° 4 2 and the multiplexer 148 of Figure 1, another arbiter 202 is added, and the BTAC write queue 144 and the BTAC1 42 are coupled. Of 3-input multiplexer 206. Although the multiplexer 148 of FIG. 1 receives only two inputs, the multiplexer 148 is a 4-input multiplexer, as shown in FIG. 2. As shown in Figure 2, BTAC142 includes a read / write input, a bit address input, and a data input. As shown in Figure 1, the multiplexer 1 4 8 receives the current fetch address 6 2 and the BWQ address 1 78. In addition, the multiplexer 1 48 also receives an extra TA address 2 34 and a dead node address 2 3 6, which will be described in detail with reference to Figs. 10-n and 12-13 respectively. Multiplexer. 148 selects one of its four inputs according to a control signal 258 generated by the arbiter 202 to output one of the address data 182 in the first figure, which is input to the BTAC Enter the address of 142. The multiplexer 2 0 6 receives an excess TA data signal 2 44 and a dead knot data signal 2 4 6, which will be described and described in detail with reference to FIGS. 10_n and 12_13 respectively. The multiplexer 206 also receives one of the BWQ data # 2 2 8 transmitted from the BTAC write queue 144, which is the current b τ AC write to the queue 1 4 4 and the data of the BTAC 1 42 needs to be updated. Multiplexer 2 0 6 generates one according to the arbiter 2 0 2

12828twf.ptd Page 20 200414034 V. Description of the invention (14) ---- Control signal 2 6 2 and select one of the three inputs to output a data signal 2 5 6 which is input to the data input of the BTAC142. ~

The arbiter 2 0 2 arbitrates the multiple sources that the BTAC 142 requested access to. When the BTAC142 is read or written, the arbiter 202 generates a signal 252 to the read / write input of the field BTAC142 to control it. The arbiter 202 receives a BTAC read request signal 2 1 2, which represents that the read of the instruction cache 1 0 4 using the current fetch address is parallel to the current fetch address 1 6 2 and One of the requirements for reading BTAC142. The arbiter 202 also receives a redundant target address (τα) request number 214 'which represents a request to invalidate one of the redundant items of the same branch instruction in the instruction set selected by the redundant TA address 234 in the BTAC142, Will be described below. The arbiter 2 0 2 also receives a dead-knot request signal 2 1 6 'It represents that the branch instruction in the instruction set selected by the dead-knot address 2 3 6 is mis-measured within the BTAC1 42 of the cache boundary. One of the requirements for invalidation of a project will be described below. The arbiter 2 0 2 also receives a BWQ non-empty signal 218 output from the BTAC write queue 144, which represents at least one request pending to update the BWQ address 1 78 within the BTAC 1 42 selected instruction set. One of the projects, which will be described below. The arbiter 2 0 2 also receives a BWQ full signal 2 2 2 output from the BTAC write queue 144, which represents that the BTAC write queue 144 is filled with the instruction set selected to update the BWQ address 178. The pending requirements for one of the items in the BTAC142 will be described below. In one embodiment, the arbiter 2 0 2 specifies the priority, as shown in the table below. 1 of which 1 represents the highest priority and 5 represents the lowest priority: 1-Dead knot request 2 1 6

12828twf.ptd Page 21 200414034 V. Description of the invention (15) 2- BMQ full 222 3- BTAC read requirement 2 1 2 4- Excess TA requirement 214 5- BWQ non-empty 218 Now refer to Figure 3, showing Detailed block diagram of BTAC 142 of Figure 1 of the invention. As shown in FIG. 3, the B T A C 1 4 2 includes a target address array 3 0 2, a tag array 3 0 4, and a counter array 3 0 6. Each array 3 0 2, 3 0 4 and 3 0 6 receives the address 1 8 2 of the first figure. The embodiment of Figure 3 shows a 4-way instruction set in conjunction with BTAC142 cache memory. In another embodiment, BTAC142 includes 2-way instruction set joint cache memory. In one embodiment, the target address array 3 0 2 and the tag array 3 0 4 are dual ports, but the counter array 3 0 6 is a dual port with a read port and a write port, because the counter array 3 The update frequency of 0 6 is higher than the update frequency of the target address array 302 and the tag array 304. The target address array 3 0 2 includes an array of storage elements to store a target address array item 3 1 2 capable of caching branch target addresses and related branch prediction information. The contents of the target address array item 3 1 2 will be described below with reference to FIG. 4. The label array 3 0 4 includes a storage element array to store a label array item 3 1 4 that can store an address label and related branch prediction information. The contents of the label array item 3 1 4 will be described below with reference to FIG. 5. The counter array 3 06 includes a storage element array to store a counter array item 3 1 6 that can store branch result prediction information. The contents of the counter array item 3 1 6 will be described below with reference to FIG. 6. Each target address array 302, label array 304, and counter array

12828twf.ptd Page 22 200414034 V. Description of the Invention (16) The 3 06 series is planned in 4 directions, as shown in the 0th direction (way 0), the 1st direction (way 1), and the 2nd direction (way 2) With the third direction (way 3). Preferably, the target address array 3 2 stores 2 items or a part in each direction to cache the branch target address and predictive branch information, represented by A and B, so that if two branch instructions exist Within the cache line, BTAC 1 4 2 can predict appropriate branch instructions. Each array 3 0 2-3 0 6 is indexed by the address 1 8 2 in the first figure. The lower bits of address 1 8 2 select the cache lines within each array 3 2-3 0 6. In one embodiment, each of the arrays 302-306 includes 128 instruction sets. Therefore, BTAC1 42 can cache up to 1024 target addresses, each direction of each instruction set (each instruction set has 4 directions) has 2 addresses. Preferably, the arrays 3 2-3 0 6 are indexed by bits [1 1: 5] at address 1 8 2 to select the 4-way instruction set in BTAC 142. Referring now to Fig. 4, the contents of the target address array item 3 12 according to Fig. 3 of the present invention are shown. The target address array item 3 1 2 includes a branch target address (T A) 402. In one embodiment, the target address 4 2 includes a 3 2 -bit address, which is quickly obtained from a previous execution of a branch instruction. The BTAC 142 provides a target address 4 02 for a predicted TA output of 164. The target address array item 3 1 2 also includes an initial stop 4 0 4. The start field 4 0 4 represents the byte offset of the first byte of the branch instruction within one of the cache lines output from the instruction cache 1 104 in response to the current fetch address 16 2 ( byte 〇ffset). In one embodiment, a cache line includes 32 bytes; therefore, the starting block 404 includes 5 bytes. The target address array item 3 1 2 also includes a span (w r a p) bit 4 0 6. If the predicted branch instruction crosses the two cache lines of the instruction cache

12828twf.ptd Page 23 200414034 5. In the description of the invention (π), crossing the bit 4 0 6 is true. The BTAC142 provides the crossing bit 406 of the B-wrap signal 1214, which will be discussed below with reference to FIG. 2. Please refer to Fig. 5 'for the contents of the label array item 3 1 4 according to Fig. 3 of the present invention. The label array item 3 1 4 includes a label 50 2. In one embodiment, the tag 502 includes the high-order 20 bits of the address of the branch instruction, and the branch instruction causes a related item in the target address array 3 02 to store a predicted target address 402. If the item is valid, B τ A c 丨 4 2 compares the label 5 〇2 with the high-order 20 bits of the address 1 8 2 in the first figure to determine whether the item matches the address 182, that is, the address 182 Whether to hit within BTAC142. The label array item 3 1 4 also includes an A effective bit 5 0 4. If the target address 4 2 in the A part of the relevant item in the target address array 3 2 2 is valid, A is valid. Bit 5 04 is true. The label array item 3 i 4 also includes a B effective bit 506. If the target address 402 in the B part of the relevant item in the target address array 3 002 is valid, the B Valid bits 5 0 6 are true. The label array entry. Item 314 also includes a 3-bit lru field of 508, which indicates which of the four directions of the ^ instruction set is lru (Uast RecenUy

Used, long unused). In one embodiment, when the βτac branch is executed, BTAC 1 4 ^, updates the 1 ru block 5 08. That is, β TAC 1 4 2 will be updated only when ^ prediction rm is executed and the microprocessor 100 branches according to the prediction to the prediction target address 1 6 4 The lru field 5 08 ^ while the BTAC branch is being executed, during the period when btacm2 is not read and the queue 144 is not written using BTAC,

Page 24 200414034 V. Description of the invention (18) BTAC142 will update the lru stop 5 0 8. Please refer to FIG. 6 'to show the contents of the counter array item 3 1 6 according to the 3rd figure of the present invention. The counter array item 3 1 6 includes a predicted state a counter 6 02. In one embodiment, 'the predicted state A counter 602 is a 2-bit saturation counter. Each time the microprocessor 100 decides to execute a related branch instruction, it counts up, and the parent and child do not perform the correlation. When a branch instruction is issued, it counts down. When counting up, the prediction state A counter 602 is saturated with b '; [i bis carry value; when counting down, the prediction state A counter 602 is saturated with b' 00 bis carry value. In one embodiment, if the value of the prediction state A counter 6 〇 2 is b 1 1 or b ′ 1 0 ′, then BTAC1 42 predicts the branch instruction related to part A of the selected target address array item 3 1 2 To be executed; otherwise, the BTA c 4 4 predicts that the branch instruction will not be executed. The counter array item 3 丨 6 also includes a pre- =, whose operation is similar to that of the predicted state A counter > one, / / about the part B of the selected target address array item 3 1 2. . Decimal array 'column item 316 also includes an A / Blru bit 606 ° A / Blru bit 6 0 6 b 1-the carry value represents the selected target address array item 3 1 2 A part is The longest unused; $%, then the B part of the array 312 is the longest to go to Tian Shi ^, yi ^ 丄 丨 Ping Huan only, to lay the soil together-Ba Shi Chuli r unused. In an embodiment, when the branch instruction arrives on the day of the cut, the storage stage bit (that is, whether the branch is to be executed or not) is stored in the storage stage bit 606 and the predicted state A and B counter 602 In the embodiment, the update of the counter array item 3 1 6 does not require the use of BTAC write 俨 ... μ m ^ & π χ ^ Known column 144, because the count array 3 0 6 includes a continuous access port and a Write port,

12828twf.ptd Page 25 200414034

V. Description of the invention (19) Please refer to FIG. 7 to show the content of the request for writing B T A c according to FIG. 1 of the present invention. FIG. 7 shows the information input to the BTAC write queue 丨 44 The input of the BTAC write request signal 176 generated by the storage phase 128 for the new BTAC142 item, which is also stored in the BTAC write queue 14 The contents of the project are shown in Figure 8. 4 β T A C write request 1 7 6 includes a branch instruction address block 702, whose B is to update the address of the previously executed branch instruction of the BTAC142. When the write & request 1 7 6 then updates BTAC 1 4 2, the high-order 20 bits of the branch instruction address field 7 0 2 are stored in the label field of the label array item 3 1 4 in FIG. 5 . 5 0 2. The lower order 7 bits [丨 i ·· 5] of the branch instruction address 襕 2 are regarded as the index of BTAC1 4 # 2. In an embodiment, the branch instruction address field 702 3 2 -bit is set aside. The TAC write request 1 76 also includes a start field 708 to be stored in the start block 404 of the map. The BTAC write request 176 also includes a straddle bit 712 to be stored in the stride bit 406 of Figure 4.矣-, entry request 176 also includes a write enable A block 714, which replaces ^ 5 with the information specified by BTAC write request 176 to update the selected item 1 = part A in item 312. The write request 176 also includes 1 7factory # — field 7U, which represents whether to use the information of the BTAC write request 12 or “疋” to update the selected target address array item 312 w. If you want to enter f, 176 also includes an invalid eight block 718, which is represented by ί ί: ί Part A of the target address array item 312. Invalidation ... Part A of the address array item 312 includes: Clear Figure 5

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Page 26 200414034 V. Description of the invention (20) The A valid bit 504 ° BTAC write request 176 also includes an invalid B stop 7 2 2 'It represents whether the selected target address array item is to be invalidated 3 丨Part B in 2. Invalidating part b of the selected target address array item 3 丨 2 includes: clearing the B valid bit 50β in FIG. 5. The BTAC write request 176 also includes a 4-bit direction field 724, which specifies which of the four directions of the selected instruction set to update. The field 7 2 4 is fully decoded. In one embodiment, when the microprocessor 100 reads BTAC142 to get the branch = test, the microprocessor 100 decides to put the value in the field 7 2 4 and pass the official line stage to the The value is sent down to the storage stage 2-8 to be included in the BTAC write request 176. If the microprocessor 10 () is updating an existing item in BTAC142, that is, if the current fetch address 丨 62 hits BTAC1 42, the microprocessor 100 will set the direction of the existing item to Within 4 stops. If the microprocessor 100 is writing a new item in BTAC142, for example, a new branch instruction, the microprocessor 丨 〇〇 sets the selected direction of the B τ A c 1 4 2 instruction set to the direction field Within 724. In one embodiment, when the micro processor ^ 0 takes BTAC1 42 to obtain the branch prediction, the microprocessor 100 determines the longest unused direction from the lru block 5 of FIG. 5. Force 3 Referring now to Figure 8, a block diagram of BTAC columns 1 4 4 according to Figure 3 of the present invention is shown. ^ Eight dozen RT ^ A ^ writes, column 144 includes a plurality of storage elements 802 to store the seventh figure, including six etch / ^ requirements 176. In one embodiment, the BTAC write queue 1 44 includes 6 memory elements 802 to store the ^ BTAC writer request 1 to 6, as shown, the BTAci entry queue 44 also includes a valid bit 804, related to each required item 8 0 2; if the related item is valid, the effective bit

12828twf.ptd Page 27 200414034

Zhen Jing Ru Ru Guan 4: If the item is invalid, the effective bit 804 is false. r 7Γ ^ Φ8Π9 'includes a control logic circuit 806, which is coupled to the storage file 802 and the effective bit 804. Control logic to storage " ϊί ^ Λ11146 ° 7βΛ / β ^ When entering the column 144, the control logic circuit 806 adds C to write H to write Λ requires 176 to move from BTAC to write to column 144 ^ i system logic 3 series electric f , P white & 1 28 The BTAC writer request signal from 丨 76 and connected == to be stored in item 8 0 2. The control logic circuit 806 also receives the key of the W diagram == 2, and replaces the signal 154 with the page test. The instruction buffer is full and the L idle cache signal 158. When the queue depth 146 is greater than 0, the buck logic circuit 806 generates a BWQ non-empty signal 218 of FIG. 2 which is true. When the value of the roll depth 146 is equal to the total number of items 8 0 2 (the implementation in FIG. 8 ^ ^ is 8) 犄, the control logic circuit 8 0 6 generates the BWQ full number of the second image 2 2 2 . When the control logic circuit 80β generates a true BWQ non-empty signal to ^, the control logic circuit 806 writes BTAC to the branch of the oldest (or the most) item 8 of queue 144, the instruction address. 7 〇 2 is located in bw Q address letter ^ 1 78 in Figure 1. In addition, when the control logic circuit 806 generates the true MWQ non-empty f-number 218, the control logic circuit 806 also writes ^ person () into the ^ (or bottom) item 802 of the queue 144 Columns 706 to 724 in Figure 7 are located in 6 ”(3 Assets No. 248). Zhuxin now refers to Figure 9 and shows the operation flowchart of BTAC writer column 1 4 4 according to Figure 1 of the present invention. Process Start at decision block 9 02. Rather at decision block 902, BTAC writes queue 144 by determining

12828twf.ptd Page 28 200414034 V. Description of the invention (22) The queue depth 1 4 6 is equal to the total number of items in the BTAC write queue 1 4 4 to determine the BTAC write 彳 queue 1 4 4 full. If it is full, the flow jumps to block 9 1 8 to update B T A C 1 4 2; otherwise, the flow jumps to decision block g 04. In the decision block 9 0 4 ′ B T A C is written to the queue 1 4 4 by checking the instruction cache idle signal 1 5 8 to determine whether the instruction cache 104 of the first figure is idle. If idle, the process jumps to decision block 9 2 2 to update B Δ Δ C 1 4 2 because BTAC 1 4 2 may not be renewed; otherwise, the process jumps to decision block 9 0 6 〇 at decision block 9 0 6 'BTAC write queue 1 4 4 Determine whether the instruction buffer 1 06 in the first figure is full by checking that the instruction buffer is a full signal 1 5 6. If full, if necessary, the process jumps to decision block 9 2 2 to update BTAC142 because BTAC142 may not be read; otherwise, the process jumps to decision block 9 0 8. 'At decision block 908, the BTAC write queue 144 determines whether the BTAC1 42 branch prediction has been replaced by checking the prediction signal 154. If yes, if necessary, the flow jumps to decision block 9 22 to update BTAC142 because B T A C 1 4 2 may not be read; otherwise, the flow jumps to decision block 9 丨 2. At decision block 912 ', the BTAC writes queue 144 by checking the score. The signal 152 is measured to determine whether the BTAC1 42 branch prediction has been corrected. If yes, if necessary, the process jumps to decision block 9 22 to update BTAC1 42 because BTAC 1 4 2 may not be read. Otherwise, the process jumps to decision block 9 丨 4. In decision block 914 'BTAC write 伫Column 144 determines whether BTAC write request 176 has been produced. If not, the flow jumps back to decision block 9202. Then, the flow jumps to block 9 1 6. 'no

12828twf.ptd Page 29

200414034 At block 916, the BTAC write queue 144 loads the BTAC write request 176 and increases the queue depth 146. The BTAC write request 176 is loaded into the invalid item at the top of the B-TAC write queue 144, and then the item is marked as valid. The process jumps back to decision block 902. At block 9 1 8, the B T A C write queue 4 4 updates the BTAC142 with the oldest or bottom item in the b T A C write queue 144 and reduces the queue depth 1 4 6. B Tj C writes to queue 1 4 4 and moves down one item. By setting the value of the branch instruction address bit 702 of the oldest item in Figure 7 to the MQ address letter 178 'and the other part of the oldest BTAC write request 176 to the BWQ tribute, = No. 24 8, BTAC write queue 144 uses the oldest item in BTAC write queue 144 to update BTAC 142. In addition, the BTAC write queue 144 issues a true BWQ non-empty signal 21 8 to the arbiter 2 02 of FIG. 2. If the flow jumps from decision block 902 to block 918, the BTAC write queue 144 also issues a true B W Q full signal 2 2 2 8 to the arbiter 2 0 2 of FIG. 2. The flow jumps from block 9 1 8 to decision block 9 1 4. Note that 'if the BTAC read request signal 212 is also pending, the BTAC write column 144 issues the BWQ full signal 2 2 2 and the arbiter 2 0 2 allows the BTAC write queue 144 access BTAC142; then BTAC142 will fail ', but if the effective target address of the branch instruction predicted by BTAC 1 4 2 exists in the cache line specified by the current fetch address 1 6 2 in BTAC 1 4 2, this fails The system is false. However, it is advantageous that by delaying the writing of BTAC142 until BTAC142 is not read in most cases, the BTAC write queue 1 4 4 can reduce the possibility of BTAC 1 4 2 false failure, such as Figure 9 shows.

12828twf.ptd Page 30 200414034 V. Description of the invention (24) In the decision block 9 2 2, the control logic circuit 8 determines whether the BTAC write queue 44 is empty by determining whether the queue depth 146 is equal to 0. If again, the SlL process jumps to decision block 9 1 4; otherwise, the process jumps to decision block g 2 2 to update BTAC142 because BTAC142 may not be read. Reference is now made to Fig. 10 ', which is a block diagram of a logic circuit in the microprocessor 100 according to Fig. 1 of the present invention that invalidates an excess target address in the BTAC. Fig. 10 shows that the tag array 304 of BTAC142 in Fig. 3 receives the address 1 8 2 in Fig. 1 and generates 4 tags responsively, labeled tag 〇 丨 〇〇2 a, tagl 1002B, tag2 1002C, and tag3 1002D. Collectively referred to as the label 1002. The label 1002 includes the label 5 0 2 of the fifth figure transmitted from the label array 304 in each direction. In addition, the tag array 3 responsively generates 8 significant bits [7: 0] 'labeled 1004, which are A significant bits 504 and B significant bits transmitted from the tag array 304 in each direction 506. The microprocessor 1 0 0 also includes a comparator 1 0 12 which is coupled to the tag array 3 0 4 and which receives the address 1 8 2. In the embodiment of FIG. 10, the comparator 10 12 includes four 20-bit comparators, and each comparator compares the local 20 bits of the address 1 8 2 with the related tag 1 〇〇2 To generate four matching signals, labeled as matchO 1006A 'matchl 1006B, match2 1006C and match 3 1 0 0 6 D, collectively referred to as the matching signal 1 006. If the address 1 8 2 matches the relevant tag 1 0 0 2, the comparator 1 〇 1 2 generates a true value matching signal 1 0 0 6 ° The microprocessor 1 0 0 also includes the control logic circuit 1 〇 4 Coupled to the comparator 10 12, the circuit 10 14 receives a matching signal 1 006 and a valid signal 1 004.

12828twf.ptd Page 31 200414034 V. Description of the invention (25) If there is a complex number in the direction of the selected instruction set of the tag array 304 and a value matching signal 1 0 0 6 and at least one valid bit that is true, 1 〇〇, the control logic circuit 1014 stores a truth value in the redundant TA flag temporarily to represent more than one target with the same branch instruction; the address is stored in BTAC142. In addition, the control logic circuit 1014 stores the extra TA address register 1026. Finally, the control logic circuit 8 loads the redundant TA invalid data into the redundant invalid data register 1022. In one embodiment, the BTAC write request stored in the redundant TA invalid data register 1022 is similar to that in FIG. 7 except that the branch instruction address 7 0 2 is not stored because the branch instruction The address is stored in the redundant ta address temporarily as 1026; and the target address 706, the starting bit 708, is not stored. It is irrelevant that it is in the invalid btaci42 project. In addition, when the TA is invalidated, the target address array 302 will not be written, and only the tag array 304 will be updated to invalidate the redundant M M Η item. The output of the Duo TA invalid data register 1022 includes as many as in Fig. 2 and the remaining TA invalid data signal 2 44. The redundant TA flag register _24 includes the redundant request 214 of FIG. 2. The output of the redundant address register includes the redundant address 2 34 of FIG. 2. In one embodiment, the generation equation of the direction value 7 2 4 stored in the redundant TA invalid data register 〇 02 2 and the redundant τ A flag 'is shown in Table 2 below. In m24, the significant bit t1 [3] includes the logical OR result of a significant bit [3] 504 and 3 significant bits [3] 506; the significant bit [2] includes A significant bit [2] Logic 0R result of 504 and B significant bit [2] 5 0 6; significant bit [丨] includes logic of a significant bit [1] 5 0 4 and B significant bit [1] 506. R result; and significant bits

Page 32 12828twf.ptd 200414034 V. Description of the invention (26) [0] includes the logical OR result of A significant bit [0] 504 and B significant bit [0] 506.

RedundantInvalWay [3]-(valid [3] & match [3]) & ((valid [0] & match [0]) | (valid [l] & match [l]) | (valid [2 ] & match [2]));

RedundantInvalWay [2] = (valid [2] & match [2]) & ((valid [0] & match [0]) | (valid [l] & match [l]));

RedundantInvalWay [l] = (valid [l] & match [1]) & (val id [0] & match [0]);

RedundantInvalWay [0] = 0; / 氺 Way 0 will never be invalidated 氺 /

RedundanlnAFlag two ((val id [3] & match [3]) & (valid [2] & mat

ch [2])) I ((valid [3] & match [3]) & (valid [l] & match [l])) I ((valid [3] & match [3]) & (valid [0] & match [0])) I ((valid [2] & match [2]) & (valid [l] & match [l])) IC (valid [2] & match [2]) & (valid [0] & match [0])) l ((valicUH & matchElD & CvalifHiH &matcmO])); It is appropriate to make the redundant target address in Figure 10 invalid. The operation, as shown in FIG. 11, is described by taking a series of instructions as an example, which can generate redundant target address items of the same branch instruction in BTAC 142. The first current fetch address 16 in Figure 1 is input to the instruction cache 1 04 and BTAC1 42. The cache line selected for the first current fetch address 1 62 includes a branch instruction called branch-A. The first current fetch address 162 selects one instruction set in BTAC 142, which is called instruction set N. There is no index in the instruction set N.

12828twf.ptd Page 33 200414034 V. Description of the invention (27) The signature 1002 matches the first current retrieval address 162; therefore, BTAC142 fails. In this example, the longest unused direction represented by the lru value 508 is two. Therefore, the information on the update of branch-A BTAC1 42 is sent down the pipeline, along with branch-A, which must be updated on behalf of 2. Next, enter a second current fetch address 16 2 into the instruction cache 1 104 and BTAC1 42. The cache line selected by the second current fetch address 162 includes a branch instruction called branch-B. The second current fetch address 1 6 2 also selects instruction set N and hits 3 directions of instruction set N; then, BTAC142 generates a hit. In addition, the lru value 508 of the 'BTAC142 update instruction set N is one-way. Then 'because branch-A is part of the compact loop of the code, enter the first current fetch address 1 62 to the instruction cache 1 04 and BTAC1 42 again, and select instruction set N again. Because the first execution of branch-A did not reach the storage stage 1 2 8 of Figure 1, B T A C 1 4 2 did not use the target address of branch-A to update. Then, BTAC142 failed again. However, the longest unused direction pointed to by the ilru value 508 this time is 1, because iru508 was updated in response to the hit of branch B. Therefore, the information about the second execution of branch-A BTAC 142 is sent down the pipeline, along with the second execution of branch-A, which must be updated to represent i. Then, the first branch-A reaches the storage stage 1 2 8 and generates a B T A C write request 1 7 to use the target address of branch-A to update the direction 2 of the instruction set N, which will be performed later. Then 'the second branch-A reaches the storage stage 1 2 8 and generates a BTAC write request 1 76 to use the target address of branch-A to update the direction of instruction set N, which will be carried out later. Therefore, the same branch instruction, branch /,

12828twf.ptd Page 34 200414034 V. Description of the Invention (28) -A, two valid items exist in BT A C 142. One of these items is redundant and makes the use of BTAC142 inefficient, because the redundant item can be used by another branch instruction and / or will take up a valid target address of another branch instruction. Referring now to Fig. 11, there is shown a flowchart of the operation of the redundant target address device according to Fig. 10 of the present invention. The process starts at block 1 102. At block 1 1 02, the arbiter 2 0 2 allows the BTAC read request 212 of Figure 2 to access BTAC 142, causing the multiplexer 148 to select the current fetch address 1 6 2 to be set at the address of Figure 1 The signal 1 8 2 is generated and the control signal 2 5 2 in FIG. 2 is generated to represent the reading of BTAC1 42. Then, the low-order bits currently fetching address 1 62 pass through address 182 and serve as an index to select the instruction set of BTAC1 42. The process continues to block 1 104. At block 1104, the comparator 1012 compares all four directions of the selected instruction set of the BTAC142 to the 10th direction label 1002 of FIG. 10 and the higher-order bit of the currently fetched address 1 6 2 set on the address signal 182. Unit to generate the matching signal 1006 of the figure. The control logic circuit 1014 receives the matching signal 1006 in FIG. 10 and the effective bit 10 04. Flow continues to block 1106. /. At block 1106, the control logic circuit 1014 determines whether a valid tag match occurs. That is, according to the valid bit 1004, the logic circuit 1014 of the S system determines whether there are currently more than 2 bits in the instruction set of the selected BTAC 142, and there is 1 kg ^ 002. If yes, the flow continues to block 丨 108; otherwise, ^ 2, sign at block 1108, and the control logic circuit 丨 ○ 4 stores _ ^ = two beams.

Flag register 1 0 24, the address 182 is stored in the excess, and the address is temporarily stored in the register.

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Page 35 200414034 V. Description of the invention (29) 1 0 2 6 and storing invalid data in redundant TA invalid data. $ Do n’t, the control circuit circuit 1014 stores the writer's message field as the true value ", the entry to the moon β field 7 1 β, the invalid A field 7 1 8 and the invalid β field 7 2 2 Yu Xiyu TA Invalid Data Register 1102. In addition, the control logic circuit ι〇ΐ4: Ϊ described in Table 2 as the value of the direction block 724 is stored in the redundant TA Invalid Material Address Register 1102. The flow continues to the block U2. The oblique R τ 9 blocks 1 1 1 2, the arbiter 2 0 2 allows the extra T in the second figure Α requires 2 1 4 access to BTAC142, causing the multiplexer 148 to select the extra bits The address 234 is set on the address signal 丨 82 and generates the control signal 2 5 2 of FIG. 2 to instruct the writing of BMy 42. Then, the lower-order bits of the excess TA address 2 3 4 are treated as the address 182 Select the index of the instruction set of BTAC142. If BTAC142 receives more, the extra data signals output by TA lean material register 〇22 will invalidate the directions pointed by the direction block 7 2 4 in the selected instruction set. Rushi is tied at block 1112. Reference is now made to Fig. 12 which shows a block diagram of the microprocessor's dead-knot avoidance logic circuit according to the present invention. ^ Σ Fig. 12 shows BTAC142 in Fig. 1, instruction cache 104, instruction buffer, 106, instruction normalizer 108, instruction queue after normalization 12 and multiplexer 136 ', and control logic circuit 1 in Fig. 10 〇14. As shown in FIG. 12, the microprocessor 100 also includes a dead-knot invalid data register 1222, a dead-knot flag register 1224, and a dead-knot address 1 2 2 6. The normalizer 1 0 8 Decode the instruction stored in the instruction buffer 106 and if the instruction normalizer decodes the points across the two cache lines

12828twf.ptd Page 36 200414034 V. Description of the invention (30) If the instruction is 30, it will generate the F_wrap signal that is true 丨 2 02. In particular, when the instruction normalizer 108 decodes a branch instruction that spans two cache lines, once it has been decoded, it stores one of the cross branches in the first cache line stored in the instruction buffer 106. The first part of the instruction, regardless of whether the instruction normalizer 丨 0 8 has decoded the other part of the cross-branch instruction in the second cache line that is not yet stored in the instruction buffer 丨 06, instruction specification丨 〇8 produces true F_wrap signal 1202 aF — wrap signal 1202 is input to the control logic circuit 10 14 ° When the current fetch address 1 6 2 fails, the instruction cache 1 〇4 is generated as the true value The fall signal is 1 2 0 6. The fail signal 1 2 0 6 is input to the control logic circuit 1014 ° When input to the instruction cache 1 0, the current fetch address 1 6 2 is predicted, that is, when the current fetch address 1 6 2 is a In the case of a predictive address, the instruction cache 1 0 4 generates a prediction signal 1 2 0 which is one of the true values. For example, when the multiplexer 1 3 6 selects the BTAC prediction target address 1 6 4 as the current fetch address 1 6 2 o'clock. The prediction signal 1 2 0 8 is input to the instruction cache 1 104. In one embodiment, the instruction cache 1 104 sends the prediction signal 1 2 0 8 to the instruction fetcher 1 0 2 in FIG. 1, so that the instruction fetcher 1 2 abandons the predicted memory address from the memory. Retrieve the cache line that falls within the instruction cache 104. The reason will be described below with reference to Figure 13. BTAC142 generates an execute / not execute (T / NT) signal 1212, which is output to the control logic circuit. 1 0 1 4. The T / NT signal which is the true value 1 2 1 2 represents that the address 1 82 hits BTAC1 42 and represents that BTAC1 42 predicts that a branch instruction is included in the instruction cache in response to the current fetch address 1 62. 4 provided cache

12828twf.ptd Page 37 200414034 V. Description of the invention (31) In the line, it means that the branch instruction is to be executed, and on behalf of BTAC 142, the target address of the branch instruction is set on the BTAC predicted target address signal 1 64. The BTAC142 generates a T / NT signal 1212 according to the value of the prediction state A 6 0 2 or the prediction state B 6 0 4 in FIG. 6, depending on whether the BTAC 142 uses the A or B part in the branch prediction. The BTAC142 also generates a B_wrap signal 1214 and outputs it to the control logic circuit 1014. The selected BTAC target address array item 312 in FIG. 4 has a value of span bit 406 set to β-wrap signal 214. Therefore, the false value of the B_wrap signal 1214 represents that BTAC1 42 predicts that the branch instruction does not cross the two cache lines. In one embodiment, the control logic circuit 1014 temporarily stores the B_wrap signal 1214 to maintain the value of the B-wrap signal 1214 obtained from the previous BTAC142 access. Control, the logic circuit 1014 also generates the current instruction index 168 of FIG. The control logic circuit 104 also generates a control signal 2104, which is an input selection signal of the multiplexer 136. If the control logic circuit 丨 〇 丨 4 detects the dead-knot state (that is, the temporarily stored B-wrapk bluff 12 14 is a false value, and the F-wrap signal 丨 202, the failure signal and the prediction signal 1 2 0 8 are true Value), which will not be detailed at the end, then control = f 5 S = 1 014 stores a true value in a dead knot flag register 1 2 24 with t Ϊ dead knot state 'so that the BTAC142 causing the dead knot state Temporary storage of dead data invalid 2 Logic 2 t ί1 Manned dead data invalid data temporary register 1 2 2 2 η The same as in the example of f, stored in dead knot request 1 except that the branch instruction address m is not stored Outside, because the branch refers to

12828twf.ptd 200414034 V. Description of the invention (32) The address of the order is stored in the dead-end address register 1 22 6; and the target address 7 0 6 'start bit 7 0 8 and straddle bit are not stored 7 1 2, because in an invalid BTAC1 42 item, these bits are irrelevant; therefore, when dead-knot invalidation is performed, the target address array 3 0 2 is not written, and only the tag array = 3 0 4 Updated to invalidate mistested BTAC142 items. The output of the dead knot invalid tribute register 1 2 2 2 includes the dead knot data signal 2 4 6 in FIG. 2. The output of the dead knot flag register 1224 includes the dead knot request 216 of FIG. 2. The output of the dead-node address register 226 includes the dead-node address 236 in FIG. 2. The value 7 2 4 stored in the dead knot invalid data register 丨 2 2 2 is filled by the corresponding direction of the BTAC 142 that caused the dead knot state. If the control logic circuit 104 detects a dead-knot state, the control logic circuit 丨 丨 4 also generates a value on the control signal 1024 to make the multiplexer after invalidating the mismeasured item. 3 0 6 selects the current instruction index 丨 6 to cause a branch of the microprocessor 100, so that the cache line including the mismeasured branch instruction can be retrieved again. Referring now to FIG. 13, the operation flow and process diagram of the dead knot avoidance logic circuit according to FIG. 12 of the present invention are shown. The process starts at block 1 3 02. At block 1 3 0 2, the current captured address 1 6 2 is input to the instruction cache 104 and input to the BTAC142 via the address signal 1 8 2. In Figure 13, the current fetch address 16 is referred to as fetch address A. The process continues to block 1 3 0 4. In block 1 304, instruction cache 1 04 provides the cache line designated by fetch address A (referred to as cache line A) to instruction buffer 1 06. Cache line A includes the branch instruction. The first part does not include all of the branch instructions. The flow continues to block 1 3 0 6.

12828twf.ptd Page 39 200414034 V. Description of the invention (33) At block 1 3 0 6 in response to the fetch address A, BTAC142 predicts that the branch instruction in the cache line A will be executed and set to the / NT signal 丨On 2 1 2, a B ~ wrap signal 1 2 1 4 with a false value is generated, and a prediction target address is set on the BTAC prediction target address 1 6 4. The process continues to block 1 3 0 8. At block 1 3 0 8, the control logic circuit 1 0 1 4 controls the multiplexer 1 3 6 to select the BTAC prediction target address 1 6 4 as the next current fetch address 1 6 2 and is called fetch address B. . The control logic circuit 1 0 1 4 also generates a prediction signal 1 2 0 8 'which is a true value because the B T A C prediction target address 16 4 is predictive. The process continues to block 1 3 1 2. In block 1 3 1 2, the instruction cache 1 0 4 generates a failure signal of true value 1 2 0 6 to represent that the branch address B falls into the instruction cache 1 104. Normally, the instruction fetcher 102 may fetch the missed cache line from the memory; however, because the prediction signal 12 08 is true, the instruction normalizer 1 08 does not fetch the missed fast memory. Take the line, the reason will be described below. The flow continues to block 1314. At block 1 3 1 4 'the instruction normalizer 1 0 8 decodes the cache line A in the instruction buffer 1 q 6 and generates a true F-wrap signal 1 2 0 2 because this The branch instruction spans two cache lines. The instruction normalizer 1 0 8 waits for the next cache line to be stored in the instruction buffer 106, so that it can complete the normalization of the branch instruction to output it to the normalized instruction queue 1 12. The process goes to block 1 3 1 6. In block 1 3 1 6, the control logic circuit 1 0 1 4 decides whether the temporarily stored B_wrap signal 1214 is a false value, and whether F — wrap signal 1 2 0 2 is a true value, and the frustrating signal 1 2 0 Whether 6 is true and the prediction signal 1 2 0 8 is true '

12828twf.ptd Page 40 200414034 V. Description of the invention (34) value; this includes the dead knot state described below. If yes, the process continues to block 1 3 1 8; otherwise, the process ends. At block 1 3 1 8, the control logic circuit 1 0 1 4 invalidates the BTAC1 42 item that caused the dead knot state, as described with reference to FIG. 12. Then, the next time the capture address A is input to the BTAC 142, the BTAC 142 will fail, because the item that caused the deadlock status is now invalidated. The process continues to block 1 3 2 2. At block 1 3 2 2, the control logic circuit 1 0 1 4 controls the multiplexer 1 3 6 to branch to the current instruction index 1 6 8 as described with reference to FIG. 12. In addition, when the control logic circuit 1 0 1 4 controls the multiplexer 1 3 6 to select the current instruction index 1 6 8, the control logic circuit 1 0 1 4 generates a prediction signal 1 2 0 8 which is a false value because the current instruction index 1 6 8 is not a predictive memory address. It is likely that the current instruction pointer 1 6 8 will hit the instruction cache 1 104; however, if there is no hit, the instruction fetcher 102 will retrieve the cache specified by the current instruction pointer 1 6 8 from memory. Line, because the predicted signal 1 2 0 8 represents the current instruction indicator 1 6 8 is not predictive. The process ends at block 1 3 2 2. If the decision block · 1 3 1 6 is true, the reason for the existence of a dead knot is that the necessary conditions for the dead knot exist. The first situation that causes the deadlock is a multi-byte branch instruction that spans two different cache lines. That is, the first part of the branch instruction byte is located at the end of the first cache line, and the second part of the branch instruction byte is located at the beginning of the next cache line. Because of the possibility of spanning branch instructions, the BTAC1 42 must store information that predicts whether a branch instruction crosses the cache line, so that the control logic circuit 104 knows whether to fetch the next cache line to fetch Located at the target address 1 6 4

12828twf.ptd Page 41 200414034 V. Description of the invention (35) 'Before the line is taken, the root half of the instruction byte of the broadcast branch is taken. If BTAC 142 a 2 > 2? Prediction information, BT AC 1 4 2 may mistakenly predict that ^ # 二 Λ Q loose span ’but actually has a span. In this example, the instruction specification "^ will use the first half of the branch instruction to decode the cache line and detect / then σ has a branch instruction, but not all the bytes of the branch instruction have been used for decoding . The instruction normalizer 108 will wait for the next cache line. e Haiguan, = will always wait for more instructions to be normalized to execute. Eight f f is dead, the second case is because the BTAC142 predicts that the branch instruction does not cross, the branch control logic circuit 1 0 1 4 fetches the

The cache line implied by the target address 1 64 output by BjAC1 42 (the next cache line is not retrieved) ° However, the target address 1 64 falls into the instruction cache 1 04. So 'the instruction normalizer 108 waits for the next cache line to be fetched from memory. The third situation that causes the deadlock situation is that the microprocessor chipset is unpredictable, it will fetch instructions from certain memory address ranges, and if the microprocessor generates instructions from an unexpected memory address range When fetching, the 'microchip crystal chip group' may leave the system idle or cause other undesirable system conditions. Predictive addresses, such as BTAC 142's target address 1 6 4 ′ may cause instruction fetches from unexpected memory address ranges. Therefore, 'the microprocessor 100 does not retrieve a missed cache line from one of the predictive BTAC predicted target addresses 1 β 4 in the memory. So the 'instruction normalizer 108 and the rest of the pipeline are waiting for another cache line. At the same time, the instruction fetcher 02 waits for the pipeline to inform it to perform a non-predictive fetch. In non-knot situations, such as if the

12828twf.ptd Page 42 200414034 V. Explanation of the invention (36) The target address 1 6 4 hits the instruction cache 1 0 4 and the instruction normalizer 1 0 8 will normalize the branch instruction (although it is incorrectly used Bytes) and the normalized branch instruction is provided to the execution phase of the branch. The execution phase will detect the mismeasurement and correct the mismeasurement of BTAC 1 4 2 so that the predicted signal 1 2 0 8 becomes a false value. . However, in the case of a dead knot, the execution will never be able to detect false positives, because the instruction normalizer 108 did not provide the normalized branch instruction to the execution stage of the branch, because the instruction normalizer 108 still Waiting for the next cache line. Therefore, a dead knot situation occurs. However, the dead-knot avoidance logic circuit in Fig. 12 can effectively prevent the occurrence of the dead-knot situation, as shown in Figs. 12 and 13, so that the microprocessor 100 can operate properly. Although the invention and its objects, features, and advantages have been described in detail, the invention may include other embodiments. For example, although the write queue is related to the port BTAC, in some microprocessor architectures, spurious failure may also occur in the multi-port BTAC, albeit at a lower frequency. Therefore, the write queue can be applied to reduce the false failure rate of multi-port BTAC. In addition, in some microprocessors that have not read BTAC, there may be other situations besides those described here, where the requirements listed in the write queue can be written to BTAC. In addition, although the present invention and its objects, features, and advantages have been described in detail, the present invention may include other embodiments. In addition to using hardware to implement the present invention, the present invention can also be implemented in computer-readable codes (such as computer-readable codes, data, etc.) in computer-usable (eg, readable) media. The computer code can perform the functions or manufacture of the disclosed invention or both. For example, you can use general programming languages (such as C, C ++, J A V A, etc.); G D S I I database; hard description language (hard description language,

12828twf.ptd Page 43 200414034 V. Description of the Invention (37) HDL), including Verilog HDL, VHDL, Altera HDL (AHDL), etc .; or other existing programs and / or circuits (that is, summary) capture tools. Computer code can be loaded into any conventional computer-usable (eg, readable) medium including semiconductor memory, magnetic disks, and optical disks (eg, CD-ROM, DVD-ROM, etc.); Forms are implemented on computer-usable (eg, readable) transmission media (eg, carrier waves, or other media including digital, optical, or analog media). Therefore, the computer code can be transmitted on a communication network including the Internet and the corporate network (command tran e t). It should be understood that the present invention can be implemented in computer code (for example, part of an IP (Intellectual Property Right) core, such as a microprocessor core, or for a system-level design, such as a system-on-a-chip (S0C)) Part of the hardware of the circuit. In addition, the present invention can be implemented as a combination of hardware and computer code. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

12828twf.ptd Page 44 200414034 Brief Description of Drawings Figure 1 shows a block diagram of a microprocessor according to the present invention. Figure 2 shows a detailed block diagram of a portion of a microprocessor according to Figure 1 of the present invention. Figure 3 shows a detailed block diagram of a portion of the BTAC according to Figure 1 of the present invention. Fig. 4 is a block diagram showing the contents of a target address array item according to Fig. 3 of the present invention. Fig. 5 is a block diagram showing the contents of a label array item according to Fig. 3 of the present invention. Fig. 6 is a block diagram showing the contents of a counter array item according to Fig. 3 of the present invention. Fig. 7 is a block diagram showing the contents of a B T A C write request according to Fig. 1 of the present invention. Fig. 8 shows a block diagram of a BTAC write queue according to Fig. 3 of the present invention. Fig. 9 shows a flowchart of the operation of the BTAC write queue according to Fig. 1 of the present invention. -Fig. 10 shows a block diagram of the redundant target address invalid logic circuit of the BTAC in the microprocessor according to Fig. 1 of the present invention. FIG. 11 shows a flowchart of the operation of the redundant target address device according to FIG. 10 of the present invention. Fig. 12 shows a block diagram of a dead-knot avoidance logic circuit in the microprocessor according to Fig. 1 of the present invention. Figure 13 shows the dead-knot avoidance logic circuit according to Figure 12 of the present invention.

12828twf.ptd Page 45 200414034 A simple illustration of the operation flow chart. Graphical description: 100 microprocessor 102 instruction fetcher 1 04 instruction cache 106 instruction buffer 108 instruction normalizer 112 normalized instruction queue 1 14 instruction translator 116 instruction queue after translation 118 register stage 122 address phase 124 data phase 126 execution phase 128 storage phase 132 write-back phase · 134 force ii processor 136:, 148, 2 0 6: multiplexer 138 instruction 142 BTAC 144 BTAC write queue (BWQ) 146 queue depth 152 branch mismeasured signal

12828twf.ptd Page 46 200414034 Brief description of the diagram 1 5 4: Predictive replacement signal 1 5 6: Instruction buffer full signal 1 5 8: Instruction cache idle signal 1 6 2: Current mining address 1 6 4: Predicted target address 1 6 6: Next operation address 1 6 8: Current instruction index 1 7 2: Correct address 1 7 4: Replace predicted target address 1 76: BTAC write request 1 7 8: BTAC write Queue address 1 8 2: Address 2 0 2: Arbiter 2 1 2: BTAC read request signal 214: Extra target address (TA) request signal 2 1 6: Dead-knot request signal 218: BWQ non-empty signal -2 2 2: BWQ full signal 2 3 4: Extra TA address 2 3 6: Dead node address 2 44: Extra TA data signal 2 4 6: Dead node data signal 2 4 8: BWQ data signal 2 5 2, 2 5 8, 2 6 2, 1 2 0 4: control signal

12828twf.ptd Page 47 200414034 Brief description of the diagram 2 5 6: Data signal 3 0 2: Target address array 3 0 4: Tag array 3 0 6: Counter array 3 1 2: Target address array item 3 1 4: Label array item 3 1 6: Counter array item 4 0 2: Branch target address 4 0 4, 7 0 8: Start field 4 0 6: Stride bit 5 0 2: Label 5 0 4 ·· A valid bit Element 5 0 6 · B effective bit 5 0 8: 1 ru Field 6 0 2: Prediction state A counter 6 0 4: Prediction state B counter 606: A / Blru bit · 7 0 2: Branch instruction address Field 7 0 6: target address 7 1 2: stride bit 7 1 4: write enable A field 71 6: write enable B field 7 1 8 · invalid A booth 7 2 2 · Void B

12828twf.ptd Page 48 200414034 Brief description of the diagram 7 2 4: To the field 8 0 2: Storage element 8 0 4, 1 0 0 4 ·· Effective bit 8 0 6, 1 0 1 4: Control logic circuit 1 0 0 2: Tag 1 0 0 6 ·· Matching signal 1 0 1 2: Comparator 1 0 2 2: Extra TA invalid data register 1 0 2 4: Extra TA flag register 1 0 2 6: Extra TA address register 1202: F_wrap signal 1 2 0 6: Failure signal 1 2 0 8: Prediction signal 1212: Execute / do not execute (T / NT) signal 1214: B_wrap signal 1 2 2 2: Dead knot invalid data temporary storage Register 1 2 2 4: Dead-Knot Flag Register 1 2 2 6 · Dead-Knot Address Register

12828twf.ptd Page 49

Claims (1)

200414034 6. Scope of Patent Application 1. A write queue to improve the efficiency of a branch target address cache (BTAC) in a microprocessor. The write queue includes: a request for input, a request for update The branch target address cache, the request includes a branch instruction target address; a plurality of storage elements, which store the requests received by the request input end; and a control logic circuit, which is coupled to the storage elements, and responds to One or more of the predetermined conditions write one of the requests stored in the storage elements to the branch target address cache. 2. The write queue described in item 1 of the scope of patent application, further comprising: a cache idle input, coupled to the control logic circuit, and accessing an instruction fast when parallel to the branch target address cache. When taken as idle, one of the one or more predetermined conditions that specifies that the branch target address cache is not read. 3. The write queue as described in item 1 of the scope of patent application, further including: a buffer full input coupled to the control logic circuit, because an instruction buffer is full, it specifies that the branch target address is fast Fetch one of the one or more established cases that have not been read, wherein the instruction buffer receives instructions from an instruction cache that is accessed in parallel to the branch target address cache. 4. The write queue as described in item 1 of the scope of patent application, further comprising: a prediction replaces an input and is coupled to the control logic circuit because one of the first branch instruction prediction systems completed by the branch target address cache It is replaced by a second branch instruction prediction performed by a branch prediction logic circuit in the microprocessor, which specifies that the branch target address cache is not read in one of the one or more predetermined cases. 12828twf.ptd Page 50 200414034 6. Scope of patent application 5. The write queue as described in item 1 of the scope of patent application, including: a branch mis-test input, coupled to the control logic circuit, because the The branch target address cache completes a branch instruction misdetection, which specifies that the branch target address cache is not read in one of the one or more predetermined cases. 6. The writing queue described in item 1 of the scope of patent application, further comprising: a queue full input, coupled to the control logic circuit, designating that all storage elements are storing to be written to the branch target address Cache one requires one of the one or more established situations. 7. The write queue described in item 1 of the scope of patent application, further comprising: a plurality of valid bits, coupled to the control logic circuit, each valid bit indicates whether the requirement stored in the corresponding storage element is Is effective. 8. The write queue according to item 1 of the scope of patent application, wherein the request further includes a memory address of one of the branch instructions. 9. The write queue as described in item 1 of the scope of patent application, wherein the branch target address cache is an N-direction instruction set joint cache, wherein the request further includes specifying that the request is to be written to the Which N-direction information in the branch target address cache. 1 0 · — A microprocessor including: an instruction cache, providing a cache line of instruction bytes in response to an instruction fetch address; a branch target address cache (BTAC), coupled to the instruction cache Instruction cache, which predicts a branch target address of a branch instruction stored in the cache line; and a write queue coupled to the branch target address cache and stored for updating the branch target address cache Take the branch target address. 12828twf.ptd Page 51 200414034 VI. Patent application scope 1 1. The microprocessor described in item 10 of the patent application scope, wherein if the write queue is not empty, when the instruction cache is idle, Then the write queue uses one of the branch target addresses to update the branch target address cache. 12. The microprocessor as described in item 10 of the scope of patent application, further comprising: an instruction buffer that fits into the instruction cache and stores zero or more cache lines received from the instruction cache. 1 3. The microprocessor according to item 12 of the scope of patent application, wherein if the write queue is not empty, when the instruction buffer indicates that it is full, the write queue uses these One of the branch target addresses to update the branch target address cache. 14. The microprocessor according to item 10 of the scope of patent application, further comprising: a branch prediction logic circuit coupled to the write queue, wherein one of the branch instructions is completed at the branch target address cache. After a prediction, the branch prediction logic circuit completes a second prediction of the branch instruction, wherein the microprocessor uses the second prediction to replace the first prediction. 15. The microprocessor according to item 14 of the scope of patent application, wherein if the write queue is not empty, when the microprocessor uses the second prediction to replace the first prediction, the write The queue uses one of the branch target addresses to update the branch target address cache. 1 6 · The microprocessor described in item 10 of the patent application scope, further including: 12828twf.ptd Page 52 200414034 VI. Scope of Patent Application The branch decision logic circuit is coupled to the write queue to correct a false test of one of the branch instructions completed by the branch target address cache. 17. The microprocessor according to item 16 of the scope of patent application, wherein if the write queue is not empty, when the microprocessor corrects the branch target address cache, the branch instruction is completed. In the case of a false detection, the write queue uses one of the branch target addresses to update the branch target address cache. 18. The microprocessor according to item 10 of the scope of patent application, wherein if the write queue becomes full, the write queue uses one of the branch target addresses to update the branch target address. Cache. 19. The microprocessor according to item 10 of the scope of patent application, wherein when the write queue is writing to the branch target address cache, if the branch target address cache is read, the branch The destination address cache fails. 20. The microprocessor according to item 10 of the patent application scope, wherein the branch target address cache includes a port memory array to store a plurality of branch target addresses. 2 1. The microprocessor according to item 10 of the scope of patent application, wherein the branch target address cache includes a port memory array to store address tags of a plurality of branch instructions. 2 2. A method for updating a branch target address cache (BTAC) in a microprocessor, the method includes the following steps: generating a request to update the branch target address cache; storing the request in a frame Column; and after the storing step, the branch target address cache is updated according to the request. 12828twf.ptd Page 53 200414034 6. Application for Patent Scope 2 3. The method as described in Item 22 of the Patent Application Scope, wherein the step of updating the branch target address cache is performed by the microprocessing after the storage step Within one of the clock cycles. 2 4. The method described in item 22 of the scope of patent application, further comprising: determining whether the branch target address cache is not being read; wherein if the branch target address cache is not being read, Then perform this update step. 25. The method as described in item 24 of the scope of patent application, further comprising: determining whether the branch target address cache is not being read because one of the instruction caches coupled to the branch target address cache is idle. take. 26. The method according to item 24 of the scope of patent application, further comprising: determining whether the branch target address cache is not being read because an instruction buffer is full, wherein the instruction buffer receives from The instruction output from an instruction cache coupled to the branch target address cache. 27. The method as described in item 22 of the scope of patent application, further comprising: determining whether one of the first branch instruction predictions completed by the branch target address cache is predicted by the micro processing, and other branch prediction logic circuits in the device. One of the completed second branch instruction prediction substitutions; wherein if the first branch instruction prediction completed by the branch target address cache is replaced by the second branch instruction prediction, the updating step is performed. 2 8. The method as described in item 22 of the scope of patent application, further comprising: determining whether the branch target address cache has misdetected a branch instruction; wherein if the branch target address cache has misdetected a branch instruction , Then perform the update step. 12828twf.ptd Page 54 200414034 VI. Scope of patent application 29. The method described in item 22 of the scope of patent application further includes: determining whether the queue is full; where if the queue is full, then Perform this update step. 3 0. — A computer data signal that can be implemented in a transmission medium, including: computer-readable code that provides a microprocessor, the code includes: the first code that provides an instruction cache to respond to Provides one cache line of instruction byte at an instruction fetch address; the second code provides a branch target address cache (branch target address cache), which is coupled to the instruction cache to predict A branch target address of a branch instruction stored in the cache line; and a third code that provides a write column and is compiled into the branch target address cache to store and update the branch Branch target address of the target address cache. 12828twf.ptd Page 55