TWI283804B - An over-voltage protection apparatus for power converters - Google Patents
An over-voltage protection apparatus for power converters Download PDFInfo
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1283804 九、發明說明: 【發明所屬之技術領域】 本發明為一種過電壓保護 供應器之過電壓保護裝置。 特別是指一種應用於電源1283804 IX. Description of the Invention: [Technical Field] The present invention is an overvoltage protection device for an overvoltage protection supply. Especially refers to one applied to the power supply
【先前技術】 目前各種的電源供應器p紐 、去、 、、工此約提供穩定調整的電壓與雷 。為了符合安規(safety)的者旦 号里,電源供應器必須提供過電壓 以確保發生回授開路時造成輸出電壓過高的 作,精由限制電源供應器的輪 本身與電_,咖賴源供應器 細二考’係為習知的電源供應器示意圖。該電源供 切換式控制器q,用來控概源供絲。電阻^ ^各CsT提供-個初始的電源,絲啟動切換式控制器切。 定輕電源供應器_電壓V。,_式控制器以 ‘二供給功率開關Ql,用以切換—變壓11 Τι。該 文1 辅助繞組Να、—次侧繞組ΝΡ與二次側繞組Ns。 H 1的切換後,輔助繞組A產生—反射電壓VAUx :,體整流器^進―步提供電源給該城式控制器A。 端獅,%與輪㈣壓V°有密切賴係,因此在供應 切換作:供應雙Vdd也與輸出電壓V。有密_關係。在 ,7 Ul _授端FB ’依照迴授訊號Vfb使得切換訊 源供應器轉料叫⑽連接到電 行韻1出電壓v〇,輸出電壓V〇透過光耦 1283804[Prior Art] At present, various power supply units, switches, and, and the like, provide stable voltage and lightning. In order to comply with the safety of the safety, the power supply must provide overvoltage to ensure that the output voltage is too high when the feedback is open, and the power supply is limited by the power supply. The supplier's second test is a schematic diagram of the conventional power supply. This power supply is used by the switching controller q to control the source supply. Resistor ^ ^ Each CsT provides an initial power supply, and the wire starts the switching controller to cut. Fixed light power supply _ voltage V. The _ type controller uses ‘two supply power switch Q1 to switch—transform 11 Τι. The auxiliary winding Να, the secondary winding ΝΡ and the secondary winding Ns. After the switching of H 1 , the auxiliary winding A generates a reflected voltage VAUx : the body rectifier provides power to the city controller A. The lion, % and the wheel (four) pressure V ° are closely related, so in the supply switching: supply double Vdd also with the output voltage V. There is a secret _ relationship. In the 7 Ul _ grant FB ′ according to the feedback signal Vfb, the switching source supply is called (10) connected to the electrical output 1 output voltage v 〇, the output voltage V 〇 through the optocoupler 1283804
DD Κΐ^χ(ν〇+νρ)]-ν〇 复 ...............(1) 2 vF為輪出二極體整流器Dg的順向壓降;Vd為二極體整流 ™ ItT ™AUX^?Mil TiDD Κΐ^χ(ν〇+νρ)]-ν〇复..................(1) 2 vF is the forward voltage drop of the wheel-out diode rectifier Dg; Vd Diode RectifierTM ItT TMAUX^?Mil Ti
S為吏壓器T!的二次侧繞組Ns的繞組匝數。 【發明内容】 有鑑於此,本發明一種過電壓保魏置,應用S is the number of winding turns of the secondary winding Ns of the squeezing device T!. SUMMARY OF THE INVENTION In view of this, the present invention provides an overvoltage protection application.
藉由不_比鮮位輕錢供絲㈣朗郎; =高的誤動恤,再經由累進計數誤動作發生二 田發生的持績時間到達一預設值,本發明過電屋保護裝置 :週期性截止電職應器之驅動訊號,來關輸出電壓,並可 提供問鎖截止電源供應!!之驅動訊號,㈣賴止輸出 用以進行保護動作。 本發明過電壓保護裝置包括有一振盡器輪出-時脈訊號, 同時’使用-過電壓訊賴取比較單元棘_感測訊號與二臨 界訊號,經比較運算感測訊號與臨界訊號後,輸出一保護訊號。 保護訊號被傳送到一累進觸發單元。累進觸發單元係累進計數 該保護訊號,等該保護訊號的計數到達一預設值後,即輪出一 截止訊號到-閃鎖單元,閃鎖單元產生一閃鎖訊號到—驅動訊 號產生單元’用以停止輸出驅動訊號到功率開關。 7 1283804 本發明過電壓保護裝置不僅提供電源供應器於回授開路與 供應電壓過高時,促使電源供應器產生保護動作,更可透過累 進計數誤動作發生的持續時間,用以避免負載端於特定時間内 而幸又大輸出電壓時進行不當的保護。因此本發明過電壓保護電 路實可提供電源供應最完備的保護方案。 【實施方式】 請參考第二圖,為本發明電路架構示意圖。本發明過電壓 保護裝置使用於電源供應器中,包括有:一過電壓訊號彌取比 較單元 測訊號並將之與-臨界訊號進行比較運算,用以產生一保護訊 號sPT; -累進觸發單元28連接於過電壓訊號齡比較單元 與-振盪器22’係根據-時脈訊號CLK用來接收保護訊號 以累進計數保護訊號sPT。 當保護訊號SPT的計數到達一預設值後,累進觸發單元28 會輸出-截止訊號SOTF; i鎖單元21連接於累進觸發單元 鲁28 ’係接收截止訊號S0FF,以產生一問鎖訊號LATCH; 一驅動 訊號產生單7G 10連接於問鎖單元21與振盡器22,係接收時脈 訊號CLK與閃鎖訊號LATCH,用以停止輸出一驅動訊號Vp職 到一功率_ Ql,用來關截止輸出電壓V。,以達到過電壓保 護;及-驅動訊號控制單元25連接於驅動訊號產生單元1〇,係 接收一供應電壓感測訊號vB與一第二臨界訊號Vt2,第二臨界 訊號VT2為電源供應器的峰值輸出電壓v〇之限制值。當供應電 壓感測sfl號VB上升到第二臨界訊號Vn時,驅動訊號控制單元 8 1283804 25輸出-清除訊號CLR到驅動訊號產生料1(),用以週期性 截止驅動訊號vPWMa功率開㈤Qi,電源供應器的峰值輸出電 壓V〇因而得到限制,以達到過電壓保護。 復參考第二圖’其中本發明過電壓保護裝置進一步包括有 一重置單70 24連接於一供應電壓Vdd、閂鎖單元21與振盪器 22,係接收時脈訊號CLK與閂鎖訊號LATCH,並於接收閂鎖 訊號LATCH後一設定時間内,輸出一重置訊號贈到問鎖單 _ 兀21,用以重置閂鎖單元21的輸出。重置單元24進一步連接 一供應電壓vDD,並於供應電壓Vdd提供的電壓量不足時,接 收一低電壓訊號,以輸出重置訊號RST到閂鎖單元21。 配合第二圖,第三圖為本發明第一實施例電路方塊示意 圖。其中該過電壓訊號擷取比較單元23為一過電壓比較器 231 ’過電壓比較器231之一輸入端接收一第一臨界訊號Vti, 另一輸入端接收一供應電壓感測訊號¥6,係比較運算第一臨界 訊號vT1與供應電壓感測訊號Vb,用以輸出一第一保護訊號 # 到累進觸發單元28。 當電源供應裔發生回授開路而造成輸出電壓過高時,由 於反射電壓vAUX與輸出電壓v〇有密切的關係,因此在供應端 VDD上的供應電壓VDD也會隨之升高,進而使得供應電壓感測 讯唬vB的值也相對提高,因此在本第一實施例中係利用此對應 關係,使肖_過比㈣231作為過賴訊麵取比較單元 23,同時設計第-臨界城Vti的絲調整電源供應器輸出電 壓的臨界限制。當供應電壓感測訊號Vb的值大於第一臨界訊號 9By the use of no lighter than the fresh light (four) Lang Lang; = high mis-sports, and then through the progressive count misoperation, the occurrence time of the second field reaches a preset value, the present invention over the house protection device: cycle The power-off signal of the power cut-off device is used to turn off the output voltage, and the power supply for the lock is cut off! The drive signal, (4) depends on the output for protection action. The overvoltage protection device of the present invention includes a vibrating device wheel-to-clock signal, and the 'use-overvoltage signal is used to compare the unit's spine_sensing signal and the second critical signal, and after comparing the sensing signal and the critical signal, A protection signal is output. The protection signal is transmitted to a progressive trigger unit. The progressive triggering unit progressively counts the protection signal, and when the count of the protection signal reaches a preset value, a turn-off signal is sent to the flash lock unit, and the flash lock unit generates a flash lock signal to the drive signal generation unit. To stop outputting the drive signal to the power switch. 7 1283804 The overvoltage protection device of the invention not only provides the power supply device to cause the power supply to generate protection action when the feedback open circuit and the supply voltage are too high, but also can prevent the load end from being specific to the specific time through the progressive counting malfunction. Fortunately, when the output voltage is large, improper protection is performed. Therefore, the overvoltage protection circuit of the present invention can provide the most complete protection scheme for power supply. [Embodiment] Please refer to the second figure, which is a schematic diagram of the circuit architecture of the present invention. The overvoltage protection device of the present invention is used in a power supply device, comprising: an overvoltage signal to draw a comparison unit test signal and compare it with a -critical signal to generate a protection signal sPT; - a progressive trigger unit 28 The connection to the overvoltage signal age comparison unit and the oscillator 22' is used to receive the protection signal according to the -clock signal CLK to progressively count the protection signal sPT. When the count of the protection signal SPT reaches a preset value, the progressive trigger unit 28 outputs a cutoff signal SOTF; the lock unit 21 is connected to the progressive trigger unit Lu 28's receive cutoff signal S0FF to generate a lock signal LATCH; A driving signal generating unit 7G 10 is connected to the question locking unit 21 and the vibrating unit 22, and receives the clock signal CLK and the flash lock signal LATCH for stopping outputting a driving signal Vp to a power _ Ql for closing Output voltage V. The driving signal generating unit 25 is connected to the driving signal generating unit 1 , and receives a supply voltage sensing signal vB and a second critical signal Vt2 , and the second critical signal VT2 is the power supply. The limit value of the peak output voltage v〇. When the supply voltage sensing sfl number VB rises to the second critical signal Vn, the driving signal control unit 8 1283804 25 outputs a clear signal CLR to the driving signal generating material 1 () for periodically turning off the driving signal vPWMa power on (5) Qi, The peak output voltage V〇 of the power supply is thus limited to achieve overvoltage protection. Referring to the second figure, wherein the overvoltage protection device of the present invention further includes a reset unit 70 24 connected to a supply voltage Vdd, the latch unit 21 and the oscillator 22, receiving the clock signal CLK and the latch signal LATCH, and A set time is outputted to the challenge lock _ 兀 21 for resetting the output of the latch unit 21 within a set time after receiving the latch signal LATCH. The reset unit 24 is further connected to a supply voltage vDD, and when the amount of voltage supplied from the supply voltage Vdd is insufficient, a low voltage signal is received to output a reset signal RST to the latch unit 21. The third figure is a schematic block diagram of a circuit according to a first embodiment of the present invention. The overvoltage signal acquisition unit 23 receives an initial threshold signal Vti for one of the overvoltage comparators 231, and the other input receives a supply voltage sensing signal of ¥6. The first threshold signal vT1 and the supply voltage sensing signal Vb are compared to output a first protection signal # to the progressive trigger unit 28. When the power supply supplier has a feedback open circuit and the output voltage is too high, since the reflected voltage vAUX is closely related to the output voltage v〇, the supply voltage VDD at the supply terminal VDD also rises, thereby making the supply The value of the voltage sensing signal vB is also relatively increased. Therefore, in the first embodiment, the correspondence relationship is utilized, so that the Xiao_over ratio (four) 231 is used as the over-the-surface matching unit 23, and the first critical city Vti is designed. Wire adjusts the critical limit of the power supply output voltage. When the value of the supply voltage sensing signal Vb is greater than the first critical signal 9
電位之清除訊號CLR到驅動訊號產生單元1〇,使驅動訊號VpWM 為低電位,進而使功率開關❻截止,用以提供週期性截止電源 供應器之驅動訊號來限制輪出電壓。 上述說明中,本發明第一實施例係在電源供應器發生回授 開路而造成輸出電壓V〇過高時,藉由供應電壓感測訊號VB頂 到第一臨界訊號VT1的持續時間到達累進觸發單元28的預設值 1283804 vT1時’過電壓比較器231會 到該累進觸發單元28,此時人料—保護訊號% 號sPT1的累_,當累料元28則進行第—保護訊 到達-預設值後,即輪出28禮第—保護訊號Sm 對驅動訊號產生單元1G進行邮 =^_鎖單心,以 停止輸出驅動訊號vPW_功率聽動域產生單元10 定時間内需較大輸itll:壓時進行1用"场免貞載端於特 實際的過賴賴。其巾_ ^ ’達到電源供應器 預W又值為一汁數週期Tcount。 雍己u —圖細11為本發明電路波形示意®。當電源# =厂生酬路㈣㈣壓V。撕,柿;^,、 增加。在時間1^時,供應感測訊號 : 4 L界訊就Vti’此時過電壓比較器231輸出一低 =位的第-保護訊號%到累進觸發單元28。接著,累進觸發 單元28開始進行累進禮的動作,以準備對轉訊號產生單元 10進行閃鎖。再則’在時間T2〜T3時,回授開路使得供應電壓 感測訊號VB_上升’胁時間μ,供應糕_訊號% 會頂到第二臨界滅Vt2,此時驅動減控鮮元25會輸出低The potential clear signal CLR to the driving signal generating unit 1 〇 causes the driving signal VpWM to be low, thereby turning off the power switch , to provide a driving signal for periodically turning off the power supply to limit the wheeling voltage. In the above description, the first embodiment of the present invention reaches the progressive trigger by supplying the voltage sensing signal VB to the duration of the first critical signal VT1 when the output voltage V is too high when the power supply is opened and the output voltage V is too high. When the preset value of unit 28 is 1,283,804 vT1, the overvoltage comparator 231 will go to the progressive triggering unit 28, at this time, the accumulation of the protection signal % sPT1, and the accumulation of the protection element 28, the first protection message arrives. After the preset value, the 28th ceremonial-protection signal Sm is sent to the driving signal generating unit 1G to stop the output driving signal vPW_the power listening domain generating unit 10 needs to lose a large amount of time. Itll: 1 when using the pressure and the field is free of charge. Its towel _ ^ ' reaches the power supply. The pre-W value is the number of cycles Tcount.雍己u - Figure 11 is a schematic diagram of the circuit waveform of the present invention. When the power supply # = factory life road (four) (four) pressure V. Tear, persimmon; ^,, increase. At time 1^, the sense signal is supplied: 4 L. At Vti', the overvoltage comparator 231 outputs a low-level first-protection signal % to the progressive trigger unit 28. Next, the progressive triggering unit 28 starts the action of the progressive ritual to prepare for the flashing of the transcription number generating unit 10. Then, at time T2~T3, the feedback open circuit makes the supply voltage sensing signal VB_ rise to the threat time μ, and the supply cake_signal% will top to the second critical extinction Vt2. Low output
$二實施例電路方塊示意 23為一回授比較器232, 三臨界訊號VT3,另一輸入 圖。其中該過電壓訊號擷取比較單元23 回授比較器232之一輸入端接收一第三£ 端接收一電壓回授感測訊號vFB,係 • VT3與該電壓回授感測訊號VFB, 到該累進觸發單元28。 係比較運算該第三臨界訊號 用以輪出一第二保護訊號s 日田電源供應、器發生回授開路而造成輪出電壓v〇過高時,電 壓回授感測訊號Vfb的值也會相對的提高,因此在本第二實施 例中係利用此對應_ ’使用1授比較器232,同時設計該第 二臨界訊號VT3的值來限制電源供應器的峰值輸出電壓。當電 壓回授感測訊號vFB的值大於第三臨界訊號Vt3時,回授比:器 232會輸出第一次的第二保護訊號sPT2到該累進觸發單元28, 此時累進觸發單元28則進行第二保護訊號SpT2的累進計數。當 累進觸發單元28計數第二保護訊號SpT2到達一預設值後,即^ 出一截止訊號S0FF到該閂鎖單元21,以對驅動訊號產生單元1〇 進行閃鎖’使得驅動訊號產生單元10停止輸出驅動訊號VpwM 到功率開關Qi,用以避免負載端於特定時間内需較大輸出電壓 時進行不當的保護,達到電源供應器實際的過電壓保護。 上述說明中,本發明第二實施例係在電源供應器提供輸出 功率給負載使用時,藉由電壓回授感測訊號vFB頂到第三臨界 1283804The circuit block diagram 23 of the second embodiment is a feedback comparator 232, a triple critical signal VT3, and another input map. The overvoltage signal acquisition unit 23 receives a third terminal to receive a voltage feedback sensing signal vFB, and the VT3 and the voltage feedback sensing signal VFB, to the The trigger unit 28 is progressive. Comparing and calculating the third critical signal for rotating a second protection signal s. The Hita power supply is turned on and the circuit is turned on, and the voltage of the feedback feedback signal Vfb is relatively high. Therefore, in the second embodiment, the corresponding comparator 232 is used, and the value of the second critical signal VT3 is designed to limit the peak output voltage of the power supply. When the value of the voltage feedback sensing signal vFB is greater than the third critical signal Vt3, the feedback ratio: 232 outputs the first second protection signal sPT2 to the progressive triggering unit 28, and the progressive triggering unit 28 performs The progressive count of the second protection signal SpT2. After the progressive triggering unit 28 counts the second protection signal SpT2 to reach a predetermined value, a cutoff signal S0FF is outputted to the latching unit 21 to flash lock the driving signal generating unit 1 such that the driving signal generating unit 10 Stop outputting the drive signal VpwM to the power switch Qi to avoid improper protection when the load terminal needs a large output voltage within a certain time to achieve the actual overvoltage protection of the power supply. In the above description, the second embodiment of the present invention is based on the voltage feedback sensing signal vFB to the third threshold when the power supply supplies the output power to the load.
訊號%的持續時間到達累進觸發單元28的預設值(即計數週期 tco丽)後’本發㈣電壓倾裝置齡停止触驅祕號VpwM 到功率關Ql,關碱止如電壓達職源供應器 實際的過電壓保護。 再則,本發明第二實施例之電路動作原理及其波形相較於 第-實施例,僅在累進觸發單元28接收的保護訊號&來源不 同外,其餘係皆相同,在此不加贅述。配合第二圖,第六圖為 鲁本發明第三實施例電路方塊示意圖。其中該過電壓訊號擷取比 較單元23為一過電壓比較器23卜一回授比較器232與一連接 單元233所組成。過電壓比較器231比較運算一第一臨界訊號 vT1與一供應電壓感測訊號Vb,用以產生一第一保護訊號SpTi; 回授比較器232比較運算一第三臨界訊號Vt3與一電壓回授 感測訊號Vfb,用以產生一第二保護訊號SPT2 ;連接單元233連 接於該過電壓比較器231、該回授比較器232與該累進觸發單元 28,係將該第一保護訊號SpTi與該第二保護訊號SpT2傳送到該 累進觸發單元28。 當電源供應器發生輸出端開路而造成輸出電壓V〇過高 柃,供應電壓感測訊號Vb與電壓回授感測訊號Vfb的值也會相 對的提高,因此在本第三實施例中係利用此對應關係,使用一 由過電壓比較器231、回授比較器232與連接單元233所組成之 過電壓訊號擷取比較單元23,同時設計該第一臨界訊號Vn與 4第二臨界訊號Vts的值來調整電源供應器輸出電壓的臨界限 制0 12 ΐ28*3δ〇4 萬供應電壓感測訊號νΒ的值大於第一臨界訊號ντι,過電 楚比車乂器231產生第一保護訊號sPT1;或當電壓回授感測訊號 Vfb的值大於第二臨界訊號vTS時’回授比較器2^2也會產生第 二保,訊號SPT2。第-保護訊號“與第二保護訊號—透過 迷接單元233形成保護訊號SpT’然後被傳送到該累進觸發單元 8此時累進觸發單元μ則進行保護訊號&的累進計數。當 2濩訊號SPT計數到達一預設值(即計數週期Τ_τ)後,即輸出 > —截止訊號SGFF_關單元21,以魅動訊號產生單元1〇 進行閃鎖,使得驅動訊號產生單元1〇停止輸出驅動訊號% 】力率開關Qi ’用以避免負載端於特定時間内需較大輸出電壓 時進行不當的保護’達到電源供應器實際的過電壓保護。 上述說明中,本發明第三實施例係在電源供應器提供輸出 f率給負載使用時,藉由供應電壓感測訊號%頂到第—臨界訊 tVT1的持續時間’並且電壓回授感測訊號VFB頂到第三臨界訊 ,^ %的__來崎電源供應器是否有過電壓之現象,若 $寺:達累進觸發單⑦28的預設值(即雜職Τ_τ) ^關I明過輕保縣置係會停止輪出麟峨VpwM到功率 =間職止輸出輕Vq,以軸電源供應器 實際的過 % Μ保護。 路方圖’弟七圖為本發明累進觸發單元之—實施例電 ,方塊示思圖。累進觸發單元28包括有:一維持單元284連接 s至過^壓訊號擷取比較單元23與顧器22,係接收保護訊號 PT A脈喊CLK ’用以延遲保護訊號&的狀態,並輸出一 13 1283804 上下訊號UP/DOWN。一上下計數單元282連接至維持單元284 與振盪器22,係接收上下訊號UP/D0WN與時脈訊號CLK以 進行°十數運算。上下计數單元282根據上下訊號up/D〇WN之 啟用(ON)而使得上下計數單元282可向上計數,並根據上下訊 號UP/DOWN之停用(0FF)而使得上下計數單元撕可向下計 數’並於向下賴結束時停止計數,於向上計數結束時輸出高 電位之截止喊sGFF。其巾’雜贿CLKm蚊驅動訊號 Vpwm的切換頻率與維持單元284的維持時間。 上述說明中的維持單元284係由兩個D型正反器2842盥 2844來實現,當維持單元284接_低電位之倾訊號&時、。 為了防止接㈣瞬_接地彈跳(ground bGunee)或切換突波 (switching spike)的雜訊,維持單元284需要配合振盪器22產生 的時脈訊號CLK,时㈣賴城&的㈣,並輸出高電 位之上下訊號UP/DOWN。 復參考弟二圖’閃鎖單元21係可藉由—個D型正反器來實 現,其時脈端係連接到累_發單元28,係接收高準位之截: 訊號S〇FF用以輸出低準位之⑽訊號latch。低準位之閃鎖訊 號LATCH係連接至驅動訊號產生單元1〇中之一 d型正反哭⑼ 的D輸入端,使得D型正反_ D輸人端為低餘,進而°使 驅動訊號產生Itg 1G A鐵止軸職VpwM,輯到問鎖 護之目的。當電源供應器受到_保護時,其輸出端所麵接的 電子裝置將無法正常運作。 ^ 配合第-圖’請參考第八圖,係為本發明的重置單元電路 1283804 方塊示意圖。本發明過電壓保護裝置所使用之重置單元24連接 至閂鎖單元21,係可以藉由兩種方式來達到輪出低電位之重置 訊號RST,以重置閂鎖單元21。重置單元24係可以依據電源 供應器之重新啟動電源而使得供應電源VDD重新啟動,來輪出 重置訊號RST,用以進行重置閂鎖單元21。該重置單元24也 可以根據閃鎖訊號LATCH產生後一設定時間内,輸出重置訊號 RST,用以進行重置該閂鎖單元21。 该重置單元24包含彼此串聯連接的電晶體2401、2402與 2403所組成的分壓電阻,用以輸出可反映較低的供應電壓Vdd 之低電壓訊號Vlv。透過反相器2405,該低電壓訊號Vlv控制 電晶體2412的導通或截止。一旦可以獲得供應電壓Vdd,並且 電晶體2412係為截止狀悲’定電流源2411係對重置電容2413 進行充電。兩個NAND閘2415與2416組成一 SR暫存器。NAND 閘2415與2416的第一輸入端係分別連接到NAND閘2410與 2415的輸出端。NAND閘2416的第二輸入端係連接到重置電 容2413。透過反相器2404,NAND閘2415的第二輸入端係連 接到振盪器22之時脈訊號CLK。在NAND閘2415的輸出端, 依據重置電容2413上的低電位產生低電位之重置訊號RST。當 重置電容2413充電到高電位後,重置訊號RST係為停用,並 且產生時脈訊號CLK。重置電容2413的電容值與定電流源2411 的電流值決定重置訊號RST的脈波寬度。 重置單元24又包含電晶體2414、反相器2417與計時器 2418。電晶體2414係與重置電容2413並聯連接,用以對重置 15 1283804 電容2413進行放電。計時器2418的輸出端控制電晶體2414的 導通或截止。計時器2418的時脈端連接到時脈訊號CLK,依照 時脈訊號CLK的時間基準用以產生該時間延遲。透過反相芎 2417 ’計時器2418的重置端連接到閂鎖訊號LATCH,依據問 鎖訊號LATCH的停用(高電位),計時器2418的重置端為低電 位,計時器2418的輸出為低電位,電晶體2414係為截止。〜 旦閂鎖訊號LATCH係為啟用(低電位),計時器2418的重置端 為高電位,計時器2418也將係為啟用。當計時器2418達到它 的設定時間,計時器2418的輸出為高電位,電晶體2414將導 通來對重置電容2413進行放電,並產生重置訊號RST來重置 閂鎖單元21。 綜上所述,本發明過電壓保護裝置不僅提供電源供應器於 回授開路與供應電壓過高時,促使電源供應器產生保護動作, 更可透過累進計數誤動作發生的持續時間,用以避免負載端於 特定時間内需較大輸出電壓時進行不當的保護。因此本發明過 電壓保護電路實可提供電源供應最完備的保護方案。 16 1283804 【圖式簡單說明】: 第一圖為習知的電源供應器示意圖; 第二圖為本發明電路架構示意圖; 第三圖為本發明第一實施例電路方塊示意圖; 第四圖為本發明電路波形不意圖, 第五圖為本發明第二實施例電路方塊示意圖; 第六圖為本發明第三實施例電路方塊示意圖; 第七圖為本發明累進觸發單元之電路方塊示意圖;及 第八圖為本發明的重置單元電路方塊示意圖。 【主要元件符號說明】 閂鎖單元21 振盪器22 過電壓訊號擷取比較單元23 重置單元24 驅動訊號控制單元25 累進觸發單元28 驅動訊號產生單元10 電流比較器231 電壓比較器232 連接單元233 上下計數單元282 維持單元284 17 1283804 D型正反器2842、2844 電晶體 2401、2402、2403、2412、2414 反相器 2404、2405、2417 電容2413 定電流源2411 NAND 閘 2415、2416 計時器2418 φ 變壓器1 切換式控制器Ui 感測電阻Rs 電流感測訊號Vcs 迴授訊號VpB 反射電壓Vaux 功率開關(^ _ 供應電壓Vin 電流感測訊號vcs 電壓回授感測訊號vFB 第二臨界訊號Vt2 重置訊號RST 時脈訊號CLK 驅動訊號VpwM 功率開關(^ 18 1283804 保護訊號SPT 截止訊號S〇FF 閂鎖訊號LATCH 供應電壓Vdd 第一臨界訊號Vti 第一保護訊號Spti 第三臨界訊號Vt3 • 第二保護訊號sPT2After the duration of the signal % reaches the preset value of the progressive trigger unit 28 (ie, the counting period tco 丽), the current (fourth) voltage tilting device age stops the touch drive secret number VpwM to the power off Ql, and the base is stopped as the voltage reaches the source supply. The actual overvoltage protection. Furthermore, the circuit operation principle and waveform of the second embodiment of the present invention are the same as those of the first embodiment except that the protection signal & source received by the progressive trigger unit 28 is different, and the rest are the same. . With reference to the second figure, the sixth figure is a schematic diagram of the circuit block of the third embodiment of the invention. The overvoltage signal acquisition comparison unit 23 is composed of an overvoltage comparator 23 and a feedback comparator 232 and a connection unit 233. The overvoltage comparator 231 compares and calculates a first critical signal vT1 and a supply voltage sensing signal Vb for generating a first protection signal SpTi; the feedback comparator 232 compares a third critical signal Vt3 with a voltage feedback The sensing signal Vfb is used to generate a second protection signal SPT2; the connecting unit 233 is connected to the overvoltage comparator 231, the feedback comparator 232 and the progressive triggering unit 28, and the first protection signal SpTi is The second protection signal SpT2 is transmitted to the progressive trigger unit 28. When the output terminal is open and the output voltage V is too high, the values of the supply voltage sensing signal Vb and the voltage feedback sensing signal Vfb are relatively increased, and thus are utilized in the third embodiment. In this correspondence, an overvoltage signal acquisition unit 23 composed of an overvoltage comparator 231, a feedback comparator 232 and a connection unit 233 is used, and the first critical signal Vn and the second critical signal Vts are simultaneously designed. The value is used to adjust the critical limit of the power supply output voltage 0 12 ΐ 28 * 3 δ 〇 4 million supply voltage sensing signal ν Β value is greater than the first critical signal ν τι, the over-powered Chubi 231 231 generates the first protection signal sPT1; or When the value of the voltage feedback sensing signal Vfb is greater than the second critical signal vTS, the feedback comparator 2^2 also generates a second guarantee, signal SPT2. The first protection signal "and the second protection signal - the protection signal SpT' is formed by the connection unit 233 and then transmitted to the progressive trigger unit 8. At this time, the progressive trigger unit μ performs the progressive counting of the protection signal & After the SPT count reaches a preset value (ie, the counting period Τ_τ), the output > - cutoff signal SGFF_off unit 21 is used to perform the flash lock by the charm signal generating unit 1 so that the driving signal generating unit 1 stops the output driving. Signal %] force rate switch Qi 'to avoid improper protection when the load terminal needs a large output voltage within a certain time' to reach the actual overvoltage protection of the power supply. In the above description, the third embodiment of the present invention is in the power supply The supplier provides the output f rate to the load, by supplying the voltage sensing signal % to the duration of the first critical tVT1 and the voltage feedback sensing signal VFB is topped to the third critical signal, ^% of __ Whether there is overvoltage phenomenon in the power supply of Laisaki, if the temple: reaches the preset value of the progressive triggering list 728 (ie, miscellaneous Τ _τ) ^ Guan I Ming will pass the light protection county will stop taking the 峨 峨 VpwM to the work = Inter-service output light Vq, which is protected by the actual power supply of the shaft power supply. The road diagram 'the seventh diagram is the progressive trigger unit of the present invention—the embodiment of the electric, block diagram. The progressive trigger unit 28 includes A sustaining unit 284 is connected to the overvoltage signal acquisition unit 23 and the processor 22, and receives the protection signal PT A and calls CLK' to delay the state of the protection signal & and outputs a 13 1283804 up and down signal UP. /DOWN. A top-and-bottom counting unit 282 is connected to the maintaining unit 284 and the oscillator 22, and receives the up-and-down signal UP/D0WN and the clock signal CLK for the tens of operations. The upper and lower counting unit 282 is based on the up-and-down signal up/D〇WN The ON/OFF unit 282 can be counted up, and the upper and lower counting units can be counted down according to the deactivation (0FF) of the up and down signals UP/DOWN, and the counting is stopped at the end of the downward direction. At the end of the upward counting, the output of the high potential is turned off, and the switching frequency of the CLKm mosquito driving signal Vpwm is maintained and the holding time of the maintaining unit 284. The maintaining unit 284 in the above description is composed of two D-type flip-flops 2842.盥 2844 To achieve, when the sustain unit 284 is connected to the _ low potential rake number &, in order to prevent the ground bGunee or switching spike noise, the maintenance unit 284 needs to cooperate with the oscillator. 22 generates the clock signal CLK, when (4) Laicheng & (4), and outputs the high-level signal UP/DOWN. The second reference picture of the flash-lock unit 21 can be used by a D-type flip-flop The clock terminal is connected to the accumulating unit 28, and receives the truncation of the high level: the signal S〇FF is used to output the (10) signal latch of the low level. The low-level flash lock signal LATCH is connected to the D input of one of the d-type positive and negative crying (9) in the driving signal generating unit 1〇, so that the D-type positive and negative _D input terminal is low, and thus the driving signal is Produce Itg 1G A iron stop shaft VpwM, and ask for the purpose of lock protection. When the power supply is protected by _, the electronics connected to its output will not function properly. ^ With the first figure, please refer to the eighth figure, which is a block diagram of the reset unit circuit 1283804 of the present invention. The reset unit 24 used in the overvoltage protection device of the present invention is connected to the latch unit 21, and the reset signal RST of the low potential can be turned on in two ways to reset the latch unit 21. The reset unit 24 can restart the supply power VDD according to the power supply of the power supply to turn off the reset signal RST for resetting the latch unit 21. The reset unit 24 may also output a reset signal RST for resetting the latch unit 21 according to the generation of the flash lock signal LATCH. The reset unit 24 includes voltage dividing resistors composed of transistors 2401, 2402, and 2403 connected in series to each other for outputting a low voltage signal Vlv that reflects a lower supply voltage Vdd. The low voltage signal Vlv controls the turn-on or turn-off of the transistor 2412 through the inverter 2405. Once the supply voltage Vdd is available, and the transistor 2412 is turned off, the constant current source 2411 charges the reset capacitor 2413. Two NAND gates 2415 and 2416 form an SR register. The first input terminals of NAND gates 2415 and 2416 are coupled to the outputs of NAND gates 2410 and 2415, respectively. A second input of NAND gate 2416 is coupled to reset capacitor 2413. Through the inverter 2404, the second input of the NAND gate 2415 is coupled to the clock signal CLK of the oscillator 22. At the output of the NAND gate 2415, a low potential reset signal RST is generated in accordance with the low potential on the reset capacitor 2413. When the reset capacitor 2413 is charged to a high potential, the reset signal RST is deactivated and the clock signal CLK is generated. The capacitance value of the reset capacitor 2413 and the current value of the constant current source 2411 determine the pulse width of the reset signal RST. The reset unit 24 in turn includes a transistor 2414, an inverter 2417, and a timer 2418. The transistor 2414 is connected in parallel with the reset capacitor 2413 for discharging the reset 15 1283804 capacitor 2413. The output of timer 2418 controls the turn-on or turn-off of transistor 2414. The clock terminal of the timer 2418 is coupled to the clock signal CLK for generating the time delay in accordance with the time reference of the clock signal CLK. Through the reverse phase 芎 2417 'the reset end of the timer 2418 is connected to the latch signal LATCH, according to the deactivation (high potential) of the lock signal LATCH, the reset terminal of the timer 2418 is low, and the output of the timer 2418 is At low potential, the transistor 2414 is off. ~ The latch signal LATCH is enabled (low potential), the reset terminal of timer 2418 is high, and timer 2418 is also enabled. When the timer 2418 reaches its set time, the output of the timer 2418 is high, the transistor 2414 will be turned on to discharge the reset capacitor 2413, and a reset signal RST is generated to reset the latch unit 21. In summary, the overvoltage protection device of the present invention not only provides a power supply to cause the power supply to generate a protection action when the feedback open circuit and the supply voltage are too high, but also can prevent the load from being generated by the duration of the progressive count malfunction. Improper protection when a large output voltage is required for a specific time. Therefore, the overvoltage protection circuit of the present invention can provide the most complete protection scheme for the power supply. 16 1283804 [Simplified description of the drawings]: The first figure is a schematic diagram of a conventional power supply; the second figure is a schematic diagram of a circuit structure of the present invention; the third figure is a circuit block diagram of the first embodiment of the present invention; 5 is a circuit block diagram of a second embodiment of the present invention; FIG. 6 is a circuit block diagram of a third embodiment of the present invention; and FIG. 7 is a circuit block diagram of a progressive trigger unit of the present invention; Eight Diagrams are block diagrams of the reset unit circuit of the present invention. [Main component symbol description] Latch unit 21 Oscillator 22 Overvoltage signal acquisition comparison unit 23 Reset unit 24 Drive signal control unit 25 Progressive trigger unit 28 Drive signal generation unit 10 Current comparator 231 Voltage comparator 232 Connection unit 233 Up-and-down counting unit 282 Maintenance unit 284 17 1283804 D-type flip-flops 2842, 2844 transistors 2401, 2402, 2403, 2412, 2414 Inverters 2404, 2405, 2417 Capacitor 2413 Constant current source 2411 NAND gate 2415, 2416 Timer 2418 φ Transformer 1 Switching controller Ui Sensing resistor Rs Current sensing signal Vcs Feedback signal VpB Reflecting voltage Vaux Power switch (^ _ Supply voltage Vin Current sensing signal vcs Voltage feedback sensing signal vFB Second critical signal Vt2 Heavy Set signal RST clock signal CLK drive signal VpwM power switch (^ 18 1283804 protection signal SPT cutoff signal S〇FF latch signal LATCH supply voltage Vdd first critical signal Vti first protection signal Spti third critical signal Vt3 • second protection Signal sPT2
清除訊號CLRClear signal CLR
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TW94115434A TWI283804B (en) | 2005-05-12 | 2005-05-12 | An over-voltage protection apparatus for power converters |
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TW94115434A TWI283804B (en) | 2005-05-12 | 2005-05-12 | An over-voltage protection apparatus for power converters |
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TWI283804B true TWI283804B (en) | 2007-07-11 |
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CN101877545B (en) | 2009-04-30 | 2012-07-18 | 鸿富锦精密工业(深圳)有限公司 | Power module |
TWI396353B (en) * | 2009-05-22 | 2013-05-11 | Hon Hai Prec Ind Co Ltd | Power supply module |
TWI560965B (en) | 2015-07-16 | 2016-12-01 | Actron Technology Corp | De-glitch circuit and de-glitch method and short circuit protection device |
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