TWI283439B - Ionized physical vapor deposition (IPVD) process - Google Patents

Ionized physical vapor deposition (IPVD) process Download PDF

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TWI283439B
TWI283439B TW94106350A TW94106350A TWI283439B TW I283439 B TWI283439 B TW I283439B TW 94106350 A TW94106350 A TW 94106350A TW 94106350 A TW94106350 A TW 94106350A TW I283439 B TWI283439 B TW I283439B
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Taiwan
Prior art keywords
deposition system
deposition
substrate
nnd
power
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TW94106350A
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Chinese (zh)
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TW200539261A (en
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Frank M Cerio Jr
Jacques Faguet
Bruce D Gittleman
Rodney L Robison
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Tokyo Electron Ltd
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Priority claimed from US10/138,049 external-priority patent/US6755945B2/en
Priority claimed from US10/811,326 external-priority patent/US7901545B2/en
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW200539261A publication Critical patent/TW200539261A/en
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Publication of TWI283439B publication Critical patent/TWI283439B/en

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Abstract

An iPVD system is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a process which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang within a vacuum chamber. The iPVD system is operated at low target power and high pressure > 50 mT to sputter material from the target. RF energy is coupled into the chamber to form a high density plasma. A small RF bias (less than a few volts) can be applied to aid in enhancing the coverage, especially at the bottom.

Description

1283439 九、發明說明: 編 本申請案係與經讓渡且為制申請中之美專 號20030034244有關,茲將其併入以作參考。』甲明案公開 【發明所屬之技術領域】 本發明係關於通孔及渠溝結構在半導體晶圓 有關於利用離子麟材料來形成基板之阻障層 之高深寬比通孔及渠溝結構的金屬化。 曰之石夕曰曰固 【先前技術】1283439 IX. INSTRUCTIONS: The present application is related to the transfer of the patent application No. 20030034244, which is hereby incorporated by reference. The invention relates to a high aspect ratio through hole and a trench structure of a through hole and a trench structure in a semiconductor wafer having a barrier layer formed by using an ion lining material to form a substrate. Metalization.曰之石夕曰曰固 [Prior Art]

在通孔及渠溝結構於半導體晶圓上之金屬化中,五兩 有良好側壁包覆之阻障層及種晶層。 u八雨要具 離子化PVD沈積係躲先進IC晶圓中之阻障層 薄f通孔及渠溝結構中,離子化PVD触了良好側壁 對離子化沈積之要求即麟更為重要,是故吾人離 PVD製程,其底部及側壁包覆極為均衡’且可將突出部分最 因此’有必要更進一步控制金屬之階梯包覆(step c〇ver 或者一般於沈積步驟期間所形成之突懸(〇verhang)。 【發明内容】 、^發明提供一種離子化物理蒸氣沈積(iPVD)系統之操作方 Ϊ :該方法包含··將一圖案化基板設置於iPVD系統之處理i内之 ,,台上;利用低淨沈積(LND)製程以沈積一阻障層,其中吾人 須調整晶圓檯上之偏壓,以於醜化基板之場區域中建&超&沈 積速率;利用無淨沈積(NND)製程而將一種晶層沈積於圖案化基 板上,其中吾人須調整晶圓台上之偏壓,以令圖案化基板^場^ 域中產生約等於零之沈積速率。 【實施方式】 一 =sar等人之美國專利申請案公開號2〇〇3〇〇34244(與本案共 同申請中且讓渡予本申請案之受讓人)中揭露了一種利用順序沈 1283439 ™之製程。雖然利用此類型順序已較先 月! 甘田良了大懸或覆蓋層(overburden),但在沈積順序期 間^某些突懸或覆蓋層會形成,且其在_順序中並不會被完 全去除。 之枯it ί明了—種在單—真空室内進行多次沈積及侧 -ίϊ 1Ϊ製 積步驟中,突懸基本上無法受到控制,較 在_底部前用於儘可能沈積愈多底部包覆之 二7 # I’ ^將材料重新分配至侧壁並減少會增加線電阻之底 邻包覆,減少犬懸可在後續蝕刻步驟中達成。 _ 、>,種料化物理鼠_ (獅)祕之操作方 索/其L二1上1:統之處理室内,將材料沈積至晶圓台上之圖 iLN==f上來,阻障層,其中吾人須調整晶圓 ;圖案化基板之%區域中建立超低沈積速率;例如吾人可 亥方=以無淨沈積⑽)iPVD製絲將種晶層沈積於圖案 部,壁上,其中吾人須調整晶圓台上之偏 壓,以令圖案化基板之場區域中產生約等於零之沈積 溝所ίϊΐίίϊί理基板之上表面,且編深寬比通孔及渠 賴奈切^速率面;此處職之超_物小於約每分 二1LND *NND製程;·製程典型上係於獅 :備j真:處爹至中施行,其中待塗佈之基板係受支撐於一支架 上。在-處觀體處理室巾轉—高密度電漿,處理氣體可 3已料蒸氣(通常利用雜法)之惰性氣 ^人3度利用處理室外部之誘導搞合,藉由將RF能量 ίΐίί,體來作離子化,RF能量將處理氣體及—部分塗佈材 料兩者離子化,其可為僅數伏特之低電漿電壓,亦 離子化塗佈材料接著即藉由控制基板上^偏】 而被導引至基板上,以塗佈並/或飿刻基板。本發明之LND及励 1283439 製程係實施iPVD製程,但如下方所述範例般地降低其沈積速率, ’ 吾人控制ipVD製程之參數以於面對基板表面之電漿或基板之場區 、 域上產生LND或NND結果,當以如此方式進行控制時,以在各種 =同範例中所陳述方式來施行之iPVD製程,即可產生所期望之阻 障層或種晶層之沈積結果,而不致在特徵部開口附近產生突懸。 • 、在材料處理系統中,晶圓或其他基板係設置於可包含加熱及 /或冷卻元件之支架(例如夾頭)上;在本發明之一實施例中, ^ 設置了包含獨特加熱器元件之改良支架,該加熱器元件包含封裝 於石英中之高純度碳線材。 - •茲^本發明之方法的示範實施例說明於下,其將揭露一種利 用iPVD系統之沈積技術,該沈積技術係藉由一助熔劑而將離子化 金屬沈積至基板之場區域表面,來金屬化高深寬比通孔及渠溝, 此舉將會在特徵部侧壁產生一通量。此技術並不以蝕刻順^來控 ^金屬之,角(conformality),沈積製程為俾使消除或儘量減少 突懸或覆蓋層,以減少仰賴或需要蝕刻步驟來作為突懸控制之狀 ‘況。在所述之實施例中,該製程為首先沈積一薄阻障金屬層(如 Ta或TaN),接著沈積一種晶金屬層(如Cu)。 在此根據本發明一實施例之製程中,吾人係利用離子化膜沈 積(iPVD)製程來將材料沈積至具有尺寸小於約13〇咖之通孔或 .φ渠溝之高深寬比結構中。 , $發明a月顯與先前技術不同,先前技術中教示以高偏壓功 f之南DG功轉增加儲性,或者在不同真空處理㈣實施數個 積與侧步驟之賴;此種製程之特徵在於極低的沈積速率。 =吾人可減少DC功率,以將沈積速率降低至小於1()—; 此外或或者,在沈積期間極少或無偏壓施加至晶圓。 一圖1顯示根據本發明一實施例之晶圓橫截面之簡圖。在所例 =之實施射,通孔結構11具有沈積在通孔結構側壁16上之金 •屬膜^及沈積於通孔結構底部15上之金屬膜1〇。經修改後之 •侧製程係用以將金屬膜10沈積至形成於半導體晶® 12之層間 1283439 t電f 13中之通孔結構11 *,當金屬離子18沈積於日圓12上 時,在產生突懸結構14之通孔入口處金屬 、=曰 ΐ側壁及本發明之方法提供了一種 所二 統之示範•在 至處理室即之氣 原27、—賴合至處理㈣之即偏壓產生 π以及一耦合至處理室30之Dc電源24。 奴入ΐ ipID系統包含一控制器50,該控制器5〇係搞合至處理室、 ϊ 統23、輛合至麗力控制系統29、輕合至第一 rf 源耦σ至第一卯源28、並耦合至dc電源24。 …理Ϊ組更包含一天線26、一耦合至該天線之視窗 ΐ二S: fi向之活動沈積擋板33、一靶材25、以及-耦合 組34。RF源可自RF產生器27供應至天線 可二二tlfi30中建立誘導式麵合電漿;該永久磁鐵組 射,且可祕在树25上技生雖隨道, 々山天fJ6可設置於處理室30 +之介電窗31後方之處理室30 板i3最好由金屬材料所形成,其係設置於處理 t τί見由31以避免沈積至視窗31;控制器50可用來In the metallization of the via hole and the trench structure on the semiconductor wafer, the barrier layer and the seed layer are coated with a good sidewall. u I want to have an ionized PVD deposition system to hide the barrier layer in the advanced IC wafer. In the thin hole and the trench structure, the ionized PVD touches the good sidewall. The requirement for ionization deposition is even more important. Therefore, when we are away from the PVD process, the bottom and sidewall coatings are extremely well-balanced and it is necessary to further control the step coating of the metal (step c〇ver or generally formed during the deposition step). 〇verhang). [Invention] The invention provides an operation method of an ionized physical vapor deposition (iPVD) system: the method comprises: setting a patterned substrate in the processing i of the iPVD system, on the stage Using a low net deposition (LND) process to deposit a barrier layer, where we have to adjust the bias on the wafer stage to build & super & deposition rates in the field of the smear substrate; use no net deposition (NND) The process deposits a layer of crystal on the patterned substrate, wherein we have to adjust the bias voltage on the wafer stage to produce a deposition rate approximately equal to zero in the patterned substrate field. [Embodiment] One = sar Wait for The process of utilizing the sequence of 1283439 TM is disclosed in the patent application publication No. 2〇〇3〇〇34244 (which is hereby incorporated by reference in its entirety assigned to the assignee of the present application). The first month! Gan Tianliang has a large overhang or overburden, but during the deposition sequence ^ some overhang or overburden will form, and it will not be completely removed in the _ order. In the single-vacuum chamber for multiple depositions and side-curing steps, the overhang is basically uncontrollable, and is used to deposit as much as possible of the bottom cladding as well as 7 # I' ^ Re-distribution of the material to the sidewalls and reduction will increase the bottom-side coating of the line resistance, reducing the canine suspension can be achieved in subsequent etching steps. _ , >, seeding physical mouse _ (Lion) secret operating cable / its L 2 1 upper 1: In the processing room, the material is deposited onto the wafer table iLN==f, the barrier layer, where we have to adjust the wafer; the ultra-low deposition rate is established in the % area of the patterned substrate For example, I can make a square = no net deposition (10)) iPVD silk will The seed layer is deposited on the pattern portion, the wall, wherein the person has to adjust the bias voltage on the wafer table to cause the deposition surface of the patterned substrate to have a surface equal to zero, and the surface of the substrate is widened. More than the through hole and the channel Reiner's rate surface; here the super_object is less than about 2LND *NND process per minute; · The process is typically attached to the lion: preparation j true: at the execution to the middle, where to be coated The substrate is supported on a support. In the treatment of the room towel - high-density plasma, the processing gas can be 3 vapors (usually using the miscellaneous method) of the inert gas ^ 3 degrees using the treatment outside the induction, by RF energy ΐ ΐ The body is ionized, and the RF energy ionizes both the processing gas and the partial coating material, which can be a low plasma voltage of only a few volts, and the ionized coating material is then controlled by the substrate. It is guided onto the substrate to coat and/or engrave the substrate. The LND and Excitation 1283439 process of the present invention implements the iPVD process, but the deposition rate is reduced as described in the following example. 'We control the parameters of the ipVD process to generate the field or domain of the plasma or substrate facing the substrate surface. LND or NND results, when controlled in such a way, the iPVD process performed in the manners stated in the various = same examples can produce the desired deposition results of the barrier or seed layer without being characterized A sudden suspension occurs near the opening of the part. • In a material processing system, a wafer or other substrate is disposed on a support (eg, a collet) that can include heating and/or cooling elements; in one embodiment of the invention, ^ is provided with a unique heater element A modified stent comprising a high purity carbon wire encapsulated in quartz. - An exemplary embodiment of the method of the present invention is described below, which will disclose a deposition technique utilizing an iPVD system that deposits ionized metal onto the surface of a field region of a substrate by a flux to metal The high aspect ratio vias and trenches will create a flux on the sidewalls of the features. This technique does not control the metal, the conformality, and the deposition process to eliminate or minimize the overhang or cover layer to reduce the dependence or need an etching step as the state of the suspension control. . In the illustrated embodiment, the process is to first deposit a thin barrier metal layer (e.g., Ta or TaN) followed by a layer of crystalline metal (e.g., Cu). In accordance with an embodiment of the present invention, an ion PV film deposition (iPVD) process is used to deposit material into a high aspect ratio structure having vias or .φ trenches having a size of less than about 13 Å. , the invention a month is different from the prior art, the prior art teaches that the south DG work of the high bias work f increases the storage, or the different vacuum processes (four) implements several product and side steps; It is characterized by an extremely low deposition rate. = We can reduce the DC power to reduce the deposition rate to less than 1 () - or additionally, or with little or no bias applied to the wafer during deposition. 1 shows a simplified cross-section of a wafer in accordance with an embodiment of the present invention. In the case of the example, the via structure 11 has a gold film deposited on the sidewall 16 of the via structure and a metal film 1 deposited on the bottom 15 of the via structure. The modified side process is used to deposit the metal film 10 to the via structure 11* formed in the layer 1283439 t of the semiconductor crystal 12, and when the metal ion 18 is deposited on the yen 12, The metal, the sidewall of the through hole at the entrance of the suspension structure 14 and the method of the present invention provide a demonstration of the second embodiment. • In the process chamber, that is, the gas source 27, which is coupled to the treatment (4), the bias is generated. π and a DC power source 24 coupled to the processing chamber 30. The ipID system includes a controller 50 that is coupled to the processing chamber, the system 23, the vehicle to the Lili control system 29, and is coupled to the first rf source coupling σ to the first source. 28. And coupled to the dc power source 24. The control group further includes an antenna 26, a window coupled to the antenna, a movable deposition baffle 33, a target 25, and a coupling group 34. The RF source can be supplied from the RF generator 27 to the antenna to establish an induced surface-faced plasma in the two or two tlfi30; the permanent magnet is fired, and the secret can be secreted on the tree 25, although the technique can be set, the Laoshantian fJ6 can be set in The processing chamber 30 behind the dielectric window 31 of the processing chamber 30 is preferably formed of a metal material, which is disposed at a process t τίί 31 to avoid deposition to the window 31; the controller 50 can be used

5 /f率大小以及何時將其施加至天線,例如自RF 產,至天線26之ICP源可於沈積製程期間在不同功率位準 間切換。 RF產生器27之操作頻率範圍可自丨MRz至1〇〇 ΜΙίζ,例如可 採用約13. 56 MHz之操作頻率’或者亦可採用其他頻率。 iPVD處理模組亦包含利用一 z_傳動器35耦合至處理室之晶 1283439 積H月間,基板至電源距離一般可為150至275麵。 過一 Hi m納200刪或300麵晶圓,例如晶圓21可透 ΐ處L广圖曰ί:控制之開口 (未圖示)而被傳輸ϊ (未圖干)卜jr圓可被位於晶圓台22内之基板升降銷 Jit 晶圓台22中之裝置作機械式地轉調, 表=0 21自傳輸糸統接收過來,其即可下降至晶圓自22之上 靜雷ίϋ獨’晶®21可被撐托於晶®台22之頂部處,例如 器5〇Vm Ι、、Λ帝I曰曰圓21 ,溫度,以獲得最佳通孔金屬化。控制 22並對制晶圓溫度’此外,藉由使冷卻流體通過晶 盘:圓21 =\圓作適當溫控亦可控制晶圓溫度。晶圓台22 之f接觸可藉由提供兩者間之_氣體傳導來達 不致聚隼㈣° 步驟細糾控制,以確保薄層金屬沈積 +致域域,尤其在通孔結狀麵處。 谓 最好約至-3(TC 貨低度,最好為低於0<t, 其可電曰力=;_用RF偏壓產生器28而供應至晶圓台22,且 「㈣1150可用來決定應提供之砂偏>1 期$將何喊加至晶®台,例如吾人可在沈積 雜在晶® 21上提供淨負碰之位準。、 ^ 13. 56ΜΖ 1 MHZ ^ 1〇0 MHZ ^ ^ 1283439 c ίΐίί可藉域體供應系統23而被供應至處理室30,卢 =體了,:含金屬氣體或雜氣麵其;=可J =鼠氣’亦可為任何其他惰性氣雜,或可相容4= μ ffiff可利用壓力控制系統29來控制。例如:處理褒骑 可藉由氣體ί、1$統23而被供應至處理室3〇;處理麵 ^田 ===·?:維持於真空狀態;控制器可 之"丨L速及化予作用,並因此控制處理室壓力。 、 DC電力可自一電源24供應至靶材25; 期望里後’即可減少或鱗送至練25 ^ 減緩或停止沈積製卜在某些案例中,藉由將 2積ίί狀’須完全切斷電源,即可實質上減緩並 ,作之惰性氣_力介於3G與13G mTQrr之間:==2) 分塵下供應反應性紐;⑷6—9奴可變基板至 = 以背侧氣體加熱或冷卻進行靜電輕擊;以及(6) θ ,() ,材料性質之表面進行限制沈積至可去 護,以避免粒子產生。 月糸凡仟之保 iPVD系統之一般概念係說明於併入於此以作The 5/f rate and when it is applied to the antenna, such as from RF, to the ICP source of antenna 26 can be switched between different power levels during the deposition process. The operating frequency range of the RF generator 27 can range from zMRz to 1〇〇 ΜΙίζ, for example, an operating frequency of about 13.56 MHz can be used or other frequencies can be used. The iPVD processing module also includes a crystal that is coupled to the processing chamber by a z_actuator 35. The substrate-to-power supply distance is generally 150 to 275. After a Hi m nano 200-cut or 300-sided wafer, for example, the wafer 21 can be transported through the opening of the L-map: control opening (not shown) ϊ (not shown) the jr circle can be located The substrate lift pins in the wafer table 22 are mechanically transferred from the device in the wafer table 22, and the table =0 21 is received from the transmission system, and it can be lowered to the wafer from above 22 to the static mine. Crystal® 21 can be supported at the top of the Crystal® table 22, such as 5 〇Vm Ι, Λ 曰曰 I 曰曰 21, temperature, for optimal through-hole metallization. Control 22 and wafer temperature' In addition, the wafer temperature can be controlled by passing the cooling fluid through the wafer: circle 21 = \ circle for proper temperature control. The f-contact of the wafer table 22 can be controlled by providing a gas-to-gas conduction between the two to ensure a thin layer of metal deposition + domain, especially at the via junction. It is preferably about -3 (TC low, preferably less than 0; t, its electric power =; _ is supplied to the wafer table 22 by the RF bias generator 28, and "(4) 1150 can be used Decide which sand offset should be provided for the first time. For example, we can provide a net negative touch on the deposited product. ^, ^ 13.56ΜΖ 1 MHZ ^ 1〇0 MHZ ^ ^ 1283439 c ίΐίί can be supplied to the processing chamber 30 by the domain supply system 23, which is: metal-containing gas or a gas-containing surface; = J = mouse gas can also be any other inert gas Miscellaneous, or compatible 4 = μ ffiff can be controlled by the pressure control system 29. For example, the processing cymbal can be supplied to the processing chamber 3 by the gas ί, 1$ system 23; processing surface ^ field === ·?: Maintained in a vacuum state; the controller can control the process chamber pressure and control the chamber pressure. DC power can be supplied from a power source 24 to the target 25; Or scales sent to practice 25 ^ slow down or stop sedimentation in some cases, by 2 pieces of 状 ' 'must completely cut off the power supply, you can substantially slow down and make inert gas _ force between Between 3G and 13G mTQrr: ==2) Reactive reactivity is supplied under dust separation; (4) 6-9 slave variable substrate to = electrostatic tapping with back side gas heating or cooling; and (6) θ , () , material The surface of the nature is deposited to the extent that it can be removed to avoid particle generation. The general concept of the iPVD system is included in this article.

在處鐘軒電財轉高金屬離子位準, 此種弹性位柯容許流至晶圓之金屬通量減少, 古J I化金屬通量。此種方案之必然結果為製程可制於^ 月胰包覆(conformal fi lm coverage )。 控制器50可用以提供控制資料給系統元件,並自系統元件接At the place where Zhongxuan Electric Finance turned to a high metal ion level, this elastic position allows the metal flux flowing to the wafer to be reduced, and the metal flux is reduced. The inevitable result of this scheme is that the process can be made into a conformal fi lm coverage. Controller 50 can be used to provide control information to system components and from system components

1283439 ^製程及/或狀態資料,例如控制器5G可包含u己 之雷二^ ί/η/Ί200以及監測來自iPVD_2GG之輸出 且M;f if ΐϋ埠l再者’控制器5G可與系統耕交換資訊, 场2ηΓ “己,體中,程式可用以根據製程處方來控制上述iPVD系 制器5G可用來分析製程及/或狀態資料, 態資料触材製程及/或狀態資料,並利用 來,二制t改5製程3〆或控制系統元件;此外,控制器50可用 制二程及〈或狀態資料’以比較製程及,或狀態資料與靶材 2壬扣/或狀悲資料,並利用比較結果來預測、避免、及/或宣 告錯誤。 ώ - f ^材表面處之雜管磁鐵之場作用下被捕獲的主濺鍍電聚 Μ 賴出塗佈材料,並進人被濃密二次賴所占據之處理空 =區域,其中—實質部分之材料失㈣子而形成塗佈材料之正離 千,將一負偏壓施加至基板支架上之晶圓,此舉會吸引濺鍍材料 之正離子自二次電漿區域朝向並抵達基板表面上,其入射角接近 垂直基板,俾使濺鎪材料之正離子可進入晶圓基板上之 洞’以覆蓋這些渠溝及孔洞之底部。 々、 在一實施例中使用圓錐形把材,但此並非本發明之必要條 件者可採用其他乾材型態。該iPVD系統提供下列特徵及性質: (1)需要最少操作員勞力及最小可能工具組來施行例行任務,(2) 將RF及DC電源與晶圓分離至可能之最佳程度,(3)提供設計及操 作之相對簡易性,(4)容許來源之快速修復或更換,包含整體内^ 來件之快速更換,(5)提供模組之内部組件,以及(6)維持& 屏蔽完善’以避免輻射進入操作環境中。 圖3疋根據本發明一實施例之沈積系統操作方法之簡化流程 -、。在例示實施例中,施行低淨沈積(LND)製程後,接著施$‘ 淨沈積製裎(NND);在另一實施例中,可施行其他步驟,包含f 一 LND製程、單一 NND製程、以及LND製程與顧D製程之各種不 1283439 同組合。方法300由310開始。 在315中,已圖案化基板/晶圓可設置於此處所述之處理室 之晶圓台上;或者可採用非圖案化基板/晶圓,處理室可為例如 沈積室。 •在320中,施行一第一製程。在一實施例中,第一製程可包 含施行LND製程,且LND製程可於處理室中施行;在另一實施例 中,可施f NND製程,處理室中可建立高密度電漿,且高密度電 漿可包含高濃度金屬離子及大量處理氣體離子,已圖案化基板可 曝露於南密度電漿中。在一實施例中,晶圓台可垂直調整。 吾人可調整處理室壓力、處理室溫度、基板溫度、處理氣體 化學品、處理氣體流速、靶材材料、lcp功率、基板位置、靶材功 率、以及基板偏壓功率至少其中之一,以建立包含在已圖案化基 ,之場區域中之超低沈積鱗的沈積速率。#吾人施行^ 製程時,材料可被沈積人已圖案化基板之特徵部巾,而 致在特徵部之開口處產生突懸材料。 — pL:D ί 2含LND前處理時間、LND處理時間、或LND後處 ^睥;在另-實施例中’吾人可採用不同時間。LND 刖處理時間可自約〇秒變化至約5〇秒;⑶理 秒變,=500秒;且LND後處理時間可自約。秒變化至了約自5= 行ϊ人可利用離子化物理蒸氣沈積處理室來施 ίΐη ^ H在貫施财,可其他_之沈積室(例如 PVD至、CVD至、及pECVD室)來施行LND製程。 板偏ίίίίΐ二=系統可包ί基板偏壓產生11,其可將基 產生器,在ud製^不需要基板偏麼 沈=°在LND製_/,基板偏^功率H 值,圍:之第一數值。在另一實施例中,LND製 偏壓功率可調整至大於濺朗值以下之範财之 人可使用-_器,而基板偏壓功率可改變至^適歹= 12 1283439 步,以確保實質上不致產生突懸。 基板偏壓產生恭可為一 RF產生器,且RF產生器可在 MHz至約1GG MHz之頻率範圍中操作,例如RF產生器可在約 MHz下操作;基板偏壓功率範圍可自約〇· 〇 w至約麵列 基板偏壓功率範圍可自約130 w至約200 w。 此外’沈積系統可包含一乾材及一乾材電源,該 將可將LND縛電力提供至姆;在另一實施例中,2 材電源,例減設置之姆可為魏形式。在LND製程期間Ϊ ^可將UD城f源難至可建立LND沈積餘,树電源 调整至LND區域中之—數值。在另一實施例中,於製程期間, 吾人可將LND树電源調整至大於區域(圖7)中之—數值 如^士可採用-苎制器,且⑽靶材功率可調整至將製程最適化 之地步’以確保貫質上不致產生突懸。 吾人可膽LND歸功率,膽已随化基板之場區域中達 到超低沈積速率、,超低沈積速率係小3〇 nm/min。 乾材賴、可為DG麵;在另_實施射,練魏可為 二"!z頻率範圍中操作之RF產生器。L峰材 力率之耗圍可自約1G w至約2GGGW,例如LND練功率範圍可自 約800 W至約1600 W。 干观^ J目 沈積,統可更包含—耦合至練之永久磁鐵組。 产齡統更包合合至處理室之壓力控㈣統,且該壓力 二龎ί 至少—部* LND處理時間之期間建立LND處理 f ^ lOOmTorr^ 例如$LND處理室壓力之範圍可為約2〇 至約7〇虹⑽。 芬一♦沈積系統可包含-天線、-輕合至該天線以 f窗、一麵合至該介電窗之活動沈積擋板、以 =至敍線以提供ICP功率給該天線之一 ICP源;或者可採 中凌ΐ 功率可加以調整,以於lnd製程期間在處理室 同岔又電水,例如可使用一控制器,且可改變ICP功率來 13 1283439 將製程最適化,以確保實質上不致產生突懸。 ICP源可為一 RF產生器,且其可在自約彳nM =員率範圍内操作,例如ICP源可在約13·、56 MHz ^车約100 MHz 功率之範圍可自約_ w至約_ w,例如^^乍」 圍可自約3000 W至約6000 W。 P功率之範 應系可二 ===:=,該_ 處理室中;處_可^:=====流入 含金屬氣體、或其組合。 ” 3虱軋體、或 教jiif Γγ包、含氯、氣、氪、氡、或氤、或其組合;含全屬 亂體可包含銅⑽、鈕㈤、鈦㈤、铷(Ru)、銥3金屬 (A1)、銀(Ag)或鉑(pt)或其組合。 )紹 層可中’LND製斷㈣沈積—阻障層,例如該阻障 旦在某些案例中,晶圓可自處理室移開,而在另一室 篁,吾人可利用例如光學數位輪廓⑽P)工具;此外 播 描式電子顯微鏡(SEM)資料及^/或TEM資料。 π用押 在犯5中,實施查詢以決定何時停止施行第一製程。在決 停止第一製程時,方法300繼續進行至330 ;當決定將不停止第一 製,時,方法300即分路回行至320且方法3〇〇如圖3所示繼續 進行,例如一或更多L·沈積製程可實施一或更多次。 、 /々在330中,實施查詢以決定何時施行第二製程。在決定將施 行第二製程時,方法300繼續進行至335;當決定將不施行第二製 程時,方法300即分路進行至355並結束。 在335中,可施行第二製程。來自第一製程之製程可用以決 定將依第二製程來施行之製程類型。 •在一實施例中,第二製程可包含施行一 NND製程,且該 製程可在相同處理室内施行,或者丽D製程可在不同處理室中施 行;在其他實施例中,第二製程可包含一或更多LND製程。 1283439 理别處理時間、_處理時間、或nnd後處 ‘ί間1或其組S ;在另一實施例中,吾人可採用不同時間。NND 刖處理時間可自約〇秒變化至約5G秒;_處理時間可自約 秒變化至約500秒,例如自約2〇秒至約謂秒; 處 間可自約0㈣化域5Q秒。 後處理時 處理室條件可加以改變,且可實施NND製程 ^壓力、處理室溫度、基板溫度、處理氣體化學 、ICP功率、基板位置姻功率、或基1283439 ^Process and / or status data, such as controller 5G can include U Lei Lei 2 ^ ί / η / Ί 200 and monitor the output from iPVD_2GG and M; f if ΐϋ埠 l then 'controller 5G can be ploughed with the system Exchange information, field 2ηΓ “, in the body, the program can be used to control the above iPVD system controller according to the process prescription 5G can be used to analyze process and / or status data, state data contact process and / or status data, and use, The system can be used to compare the process and/or the status data with the target data and the data, and use Compare the results to predict, avoid, and/or declare errors. ώ - f ^ The main splashing of the trapped magnets under the action of the field of the magnets on the surface of the material, the coating material is applied, and the people are thickened. The occupied empty space = area, where - the material of the substantial part is lost (four) and the coating material is formed to be a thousand, and a negative bias is applied to the wafer on the substrate holder, which will attract the positive of the sputtering material. The ions face and arrive from the secondary plasma region On the surface of the board, the incident angle is close to the vertical substrate, so that the positive ions of the splash material can enter the hole on the wafer substrate to cover the bottom of the trench and the hole. 々 In one embodiment, a conical material is used. However, this is not a requirement of the present invention, and other dry material types may be used. The iPVD system provides the following features and properties: (1) requires minimum operator labor and the smallest possible tool set to perform routine tasks, (2) The RF and DC power supplies are separated from the wafer to the best possible extent, (3) providing relative ease of design and operation, and (4) allowing rapid repair or replacement of the source, including rapid replacement of the entire component, (5) Providing internal components of the module, and (6) maintaining & shielding perfection to avoid radiation entering the operating environment. Figure 3 is a simplified flow of a method of operation of a deposition system in accordance with an embodiment of the present invention. In the process of performing a low net deposition (LND) process, a net deposition process (NND) is then applied; in another embodiment, other steps may be performed, including an f-LND process, a single NND process, and an LND process. Gu The various processes of the D process are not the same as 1283439. The method 300 begins with 310. In 315, the patterned substrate/wafer can be placed on a wafer stage of the processing chamber described herein; or an unpatterned substrate can be used. The wafer, the processing chamber can be, for example, a deposition chamber. • In 320, a first process is performed. In one embodiment, the first process can include performing an LND process, and the LND process can be performed in the process chamber; In the embodiment, the f NND process can be applied, and a high-density plasma can be established in the processing chamber, and the high-density plasma can include a high concentration of metal ions and a large amount of processing gas ions, and the patterned substrate can be exposed to the south density plasma. In an embodiment, the wafer table can be vertically adjusted. We can adjust at least one of process chamber pressure, process chamber temperature, substrate temperature, process gas chemistry, process gas flow rate, target material, lcp power, substrate position, target power, and substrate bias power to establish inclusion The deposition rate of ultra-low deposition scales in the field of the patterned base. When the process is performed, the material can be deposited by the person to pattern the characteristic portion of the substrate, so that the protruding material is generated at the opening of the feature portion. – pL:D ί 2 contains LND pre-processing time, LND processing time, or LND after ^; in another embodiment, we can use different times. The LND treatment time can vary from about leap seconds to about 5 seconds; (3) the second change, = 500 seconds; and the LND post-processing time can be self-contained. The second has changed from about 5 to = 可 可 可 可 可 可 离子 离子 离子 离子 离子 离子 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 离子 , , , , , , , , , , , , LND process. The board is ίίίί 2 = system can be packaged ί substrate bias generation 11, which can be used in the ud system, no need to substrate bias = ° in LND system _ /, substrate bias ^ power H value, around: The first value. In another embodiment, the LND bias power can be adjusted to a value greater than the splash value, and the substrate bias power can be changed to ^ 歹 = 12 1283439 steps to ensure the substantial There is no sudden suspension. The substrate bias is generated as an RF generator, and the RF generator can operate in a frequency range from MHz to about 1 GG MHz, for example, the RF generator can operate at about MHz; the substrate bias power range can be from about 〇· The 偏压w to about the surface substrate bias power can range from about 130 w to about 200 w. In addition, the deposition system may comprise a dry material and a dry material power supply, which will provide LND binding power to the ohms; in another embodiment, the 2 material power supply, and the reduced power setting may be in the Wei form. During the LND process, it is difficult to establish the LND deposition margin and the tree power supply is adjusted to the value in the LND region. In another embodiment, during the manufacturing process, the LND tree power supply can be adjusted to be larger than the area (Fig. 7) - the value can be adjusted, and (10) the target power can be adjusted to optimize the process. The point of chemistry is to ensure that there is no overhang in the quality. In our case, the LND can return to the power, and the bile has reached an ultra-low deposition rate in the field of the substrate, and the ultra-low deposition rate is 3 〇 nm/min. Dry material Lai can be DG surface; in another _ implementation, training Wei can be the second "! z frequency range operating RF generator. The L-peak force rate can range from about 1 GW to about 2 GGGW. For example, the LND power can range from about 800 W to about 1600 W. Dry view ^ J. Deposition, the system can be further included - coupled to the permanent magnet group. The age of the age is more integrated into the pressure control of the processing chamber (four) system, and the pressure is two 至少 at least - part of the LND processing time to establish LND processing f ^ lOOm Torr ^ For example, the range of $LND processing chamber pressure can be about 2 〇 to about 7 〇 rainbow (10). The Fenyi ♦ deposition system may comprise an antenna, an optical deposition baffle that is coupled to the antenna with a f window, one side to the dielectric window, and a ~ to a line to provide ICP power to the ICP source of the antenna. Or the power can be adjusted to adjust the power in the processing chamber during the lnd process. For example, a controller can be used, and the ICP power can be changed to optimize the process to ensure the essence. Does not cause sudden suspension. The ICP source can be an RF generator, and it can operate within a range of approximately 彳nM = the rate of the member, for example, the ICP source can range from about _w to about 13 GHz to about 56 MHz. _ w, for example ^^乍, can range from about 3000 W to about 6000 W. The P power specification should be two ===:=, in the _ processing chamber; at _ can be: ===== inflow metal-containing gas, or a combination thereof. "3" rolling body, or teach jiif Γ γ package, containing chlorine, gas, hydrazine, hydrazine, or hydrazine, or a combination thereof; containing all of the disorder can include copper (10), button (five), titanium (five), bismuth (Ru), 铱3 metal (A1), silver (Ag) or platinum (pt) or a combination thereof. ) The layer can be 'LND fracture (four) deposition - barrier layer, for example, the barrier can be in some cases, the wafer can be self- The processing chamber is removed, and in another chamber, we can use, for example, an optical digital contour (10) P) tool; in addition to the scanning electron microscope (SEM) data and ^/ or TEM data. π is used in the crime 5, the implementation of the query To determine when to stop the first process. When the first process is stopped, the method 300 proceeds to 330; when the decision will not stop the first system, the method 300 branches back to 320 and the method 3 Continuing as shown in Figure 3, for example, one or more L. deposition processes may be performed one or more times. / / In 330, a query is performed to determine when to perform the second process. When deciding that the second process will be performed, The method 300 proceeds to 335; when it is determined that the second process will not be performed, the method 300 branches to 355 and ends. A second process may be performed at 335. The process from the first process may be used to determine the type of process to be performed in accordance with the second process. • In an embodiment, the second process may include performing an NND process, and the process Can be performed in the same processing chamber, or the Li D process can be performed in different processing chambers; in other embodiments, the second processing can include one or more LND processes. 1283439 Identify processing time, _ processing time, or after nnd At the same time, we can use different time. The NND treatment time can vary from about leap seconds to about 5G seconds; the processing time can vary from about seconds to about 500 seconds. For example, from about 2 sec to about seconds; the interval can be from about 0 (four) to 5Q seconds. The processing chamber conditions can be changed during post-processing, and the NND process can be implemented, pressure, process chamber temperature, substrate temperature, process gas Chemistry, ICP power, substrate position power, or base

^或其組合,而將沈積速率自LND沈積速率改變成_沈積速 積Ϊ率可包含場沈積速率,其為材料在已圖案化基板 之琢£域中之沈積速率;場沈積速率之範圍係自約—1() nm/min至 約+10 nm/mm,例如場沈積速率之範圍可自約—3 nm/min至約+3 nm/min。NND沈積速率可包含側壁沈積速率,其為材料在已圖案化 土板之二或更多特徵部之一或更多侧壁上的沈積速率,侧壁沈積 速ί之範_自約° nm/min至約+1° nm/min,例如織沈積速率 之範圍係自約0 nm/min至約+5 nm/min ; NND沈積速率可包含底面 沈積速率,其即為材料在已圖案化基板之—歧多特徵部之二或 更多底面上的沈積速率,底面沈積速率之範圍係自約-10 nm/min 至約+10 nm/min,例如底面沈積速率之範圍可自約—5 nm/min至約 +5 nm/min 〇 在至少一部分NND處理時間之期間,材料可沈積至已圖案化 ^之特徵部㈣上,而實f上並未沈積材料於已圖案化基板之 場區域中’在至少一部分臟)處理時間之期間,材料可沈積至已 圖案化基板之特徵部底面上或自其上移除,而實質上並未沈積材 料於已圖案化基板之場區域中。 在至少一部分NND處理時間之期間,可將基板偏壓產生器操 作於約13.56 MHz T,且基板偏壓功率之範圍可自約5〇〇 w至約 1500 W ’例如基板偏壓功率之範圍可自約75〇 w至約9〇〇 w。於 15 1283439 _D期間,可將基板偏壓功率調整至在大於濺鍍閾值之範圍中之一 或更多數值’例如吾人可使用控制器,且可改變基板偏 將製程最適化,以確保在已圖案化基板之場區域中實質 生淨沈積。 、 ^ 又 把材功率之範圍可自約議W至約刪W,例如 範圍可自約450 w至約55G W; ICP功率之範圍可自約2_ w 約loooo w,例如靶材功率之範圍可自約3〇〇〇 w至約6〇卯评。 此外,,至少一部分_處理時間之期間,_處理 流入處理室處理氣體可包含惰性氣體、含氮 體、或含金屬氣體、或其組合。 收3乳轧 腿及含氣體可包含N2, N〇, 及顺3,而含氧氣體可包含〇2,⑽, 惰性氣體可包含氬、氦、氪、氡、或氤、或 氣體可包含銅(CU)、组(Ta)、鈦(Ti)、飯(Ru)、銀(,ir3 1 (A1 ),、銀(Ag)或鉑(pt)或其組合。 、 當吾人在不同處理室中施行NND製時 第室之第二晶圓台上;第二處理ϊϊΐίίΤϊ ^電水’知讀賴可包含㈣度金雜子及大量處理氣趙 第二巧室中可建立適當處理室條件,且可施行_ :人32?室1力、處理室溫度、基板溫度、處理氣3二 扣、處理耽體^速、乾材材料、lcp功率、基板位置 予 或基板偏Μ功率或其組合’以建立麵沈積速率。 1率、 施例中’沈積純可包讀合至第Lu-f板偏驗生11 ’第二基板懸產生H可為-第二砂弟一 第fRF產生器可在自1驗至100 MHz之頻率範圍下接^杰/且 u圍n't約13.56 mhz之頻率下操作;第二^板偏ϋ〇 至約例如基板物率=;力 1283439 在至少一部分NND處理時間之期間,基板偏壓功率可加以 整至濺鍍閾值以上範圍内之一或更多數值,例如可使用一控^ 器,且第二基板偏壓功率可改變至將製程最適化之地步,以^保 在已圖案化基板之場區域中實質上不致發生淨沈積。 ” NND沈積速率可包含場沈積速率,其為材料在已圖案化基板 之場區域中之沈積速率;場沈積速率之範圍係自約—1〇 nm/min至 約+10 nm/min,例如場沈積速率之範圍可自約—5 nm/min至約+5 nm/min。丽0沈積速率可包含侧壁沈積速率,其為材料在已圖案化 基板之一或更多特徵部之一或更多側壁上的沈積速率,側壁沈 速率之範圍係自約0 nm/min至約+1〇 nm/min,例如侧壁沈積速率 攀之範圍可自約0 nm/min至約+5 nm/min ; NND沈積速率可包含底面 沈積速率,其即為材料在已圖案化基板之一或更多特徵部之一或 更多底面上的沈積速率,底面沈積速率之範圍係自約一 1〇 nm/mi:n 至約+10 nm/min,例如底面沈積速率之範圍可自約—5 nm/min至約 +5 nm/min 〇 在另一實施例中,沈積系統可包含一第二靶材,且第二 電源可提供第二把材功率給第二姆,第二乾材電源可為一 Dc電 源,在另一實施例中,第二靶材電源可為一卯產生器,其可在自 約1 MHz至約1〇〇 MHz之頻率範圍内操作,第二靶材功率之範圍 φ可自、、勺100 W至1500 W ’例如第二乾材功率之範圍可自約450 w 至約550 W。 =外,沈積系統可包含-第二天線、一麵合至該第二天線以 二第二處理室壁之第二介電窗、—齡至該第二介電窗之第二 楚一沈積擋板、以及麵合至該第二天線以提供第二ICP功率給該 玄二天線之-第二ICP源;絲可採用不同之配置。第二lcp功 =可加以調整,以於LND製程_在第二處理室中建立高密度電 二如可使用-控制器’且可改變第二電力功率來將製程最適 化’以確保實質上不致產生突懸。 - 第二1CP源可為一 RF產生器,且其可在自約1·〇 MHz至約 17 1283439 圍内操作,例如第二ICP源可在約13.56 MHz 例如第二Γγρ if 一1CP功率之範圍可自約2000 W至約10000 W, 一1功率之範圍可自約3000 W至約6000 W。 二&gt;1力^告例中,沈積系統可包含一耦合至第二處理室之第 處理時該第二屬力控制系統可用以在至少一部分賺 可為m建立獅處理麵力,該讎處理室勤之範圍 一翁&lt;§*/〇£ 1*^&quot;知例中,沈積系統亦可包含柄合至第二處理室之第 第二氣體供應系統可用以於至少―部分‘ 處理氣體流入第二處理室中處理氣體 合。w乳體、各氮氣體、含氧氣體、或含金屬氣體、或其組 ω及tt氣體可包含N2,N0,齡及題3,而含氧氣體可包含〇2,船, ;fa; (^:;^ ;f ⑻、銀㈤或心)=。),(_ 驟:製程可肋施行-歧多下列步 阻障層。、 曰 &gt;设種0日層,沈積一阻障層;以及修復一 第二製程可包含_製程或LND製程。 停止mu ,決定何時停止施行第二製程。在決定 製程“咖即tr回r定將不停止第二 進行3如次:或更如圖3所示輯 二製程期間取得,且可用以決定何時停止第 板溫度資d理:r處理室壓力資料、處理室^^度資料、基 X體化學品資料、處理氣體流速資料、乾材材 1283439 料資料、ICP功率資料、基 功率資料、處辦間資料 f 材功率資料、基板偏遷 量△某些案例中,晶圓可處室=料而,組合。 I ’例如吾人可彻光學數位 ^ ’❿在另-室中進行測 用SEM資料及/或TEM資料。 )工具;此外,吾人可利 以決定何時停何時停止第二製程;或者厚度資料可用 mtlll ° 施;當決定將不施行附加製程時加製麟345中實 附加製程可包含LND製程、^H0 Ί路至355並結束。 製程、沈積/餘刻製程、清潔製程、ϋ習知沈積製程、餘刻 何時完成;量測資料可包含處7可用以決定步驟 =資料、處理氣體化學品資料、=氣資= 材枓負料、ICP功率資料、基板位置資迷貝枓、靶材 壓功率資料、處理時間資料、或製程^方基板偏 量,例如吾人可利用光學數位輪廉(0Dj工室中進行測 用SEM資料及/或TEM資料。 /、,此外,吾人可利 以決定4何何時停止第二製程;或者厚度資料可用 圖4顯不根據本發明一實施例之千益、士#在,丨 上再ί前J理時間期間’可建立處理工:里基:可7载至曰!!△ 上再進入處理室,且晶圓台可設定在處理高度;處理 19 1283439 處理室中以增加處理室壓力;基板可 此外,可啟動背侧氣體冷卻。 電力夾持於aa5]台上; 處理間,吾人可麟理_私處理室巾,以” DC電源;於製程期間,可提供所期 ΐίi ,/於_雜_,村提供所期望之_ ΐ)Λϊ ;此外’吾人可加以調整RF_電源,於⑽製程期^率 0所期望之LNDRF偏壓功率至乾材,且於_製 曰 可提供所期望之NND RF偏壓功率至靶材。 功間,亦^ or a combination thereof, and changing the deposition rate from the LND deposition rate to the deposition rate may include a field deposition rate, which is the deposition rate of the material in the field of the patterned substrate; the range of the field deposition rate is From about -1 () nm/min to about +10 nm/mm, for example, the field deposition rate can range from about -3 nm/min to about +3 nm/min. The NND deposition rate may comprise a sidewall deposition rate which is the deposition rate of the material on one or more sidewalls of two or more features of the patterned soil plate, the width of the sidewall deposition rate - from about ° nm / Min to about +1° nm/min, for example, the range of the woven deposition rate is from about 0 nm/min to about +5 nm/min; the NND deposition rate may include the deposition rate of the bottom surface, which is the material in the patterned substrate. - the deposition rate on the bottom surface of two or more of the multi-feature features, the deposition rate of the bottom surface ranges from about -10 nm/min to about +10 nm/min, for example, the deposition rate of the bottom surface can range from about -5 nm/ Min to about +5 nm/min 材料 During at least a portion of the NND processing time, material can be deposited onto the patterned features (4), while no material is deposited on the field of the patterned substrate. During at least a portion of the dirty processing time, material may be deposited onto or removed from the underside of the features of the patterned substrate without substantially depositing material into the field regions of the patterned substrate. The substrate bias generator can operate at about 13.56 MHz T during at least a portion of the NND processing time, and the substrate bias power can range from about 5 〇〇w to about 1500 W. For example, the range of substrate bias power can be From about 75〇w to about 9〇〇w. During 15 1283439 _D, the substrate bias power can be adjusted to one or more values in the range greater than the sputtering threshold. For example, the controller can be used, and the substrate can be changed to optimize the process to ensure that Substantially clean deposition in the field region of the patterned substrate. , ^ The range of power can be from W to about W, for example ranging from about 450 w to about 55 G W; ICP power can range from about 2 _ about loooo w, such as target power range From about 3〇〇〇w to about 6〇卯. In addition, during at least a portion of the processing time, the process gas flowing into the process chamber may comprise an inert gas, a nitrogen-containing gas, or a metal-containing gas, or a combination thereof. The 3 milk-rolled legs and the gas-containing gas may include N2, N〇, and 3, and the oxygen-containing gas may include 〇2, (10), the inert gas may include argon, helium, neon, krypton, or xenon, or the gas may include copper. (CU), group (Ta), titanium (Ti), rice (Ru), silver (, ir3 1 (A1), silver (Ag) or platinum (pt) or a combination thereof, when we are in different processing chambers The second wafer stage of the first room of the NND system is implemented; the second process ϊϊΐ Τϊ Τϊ Τϊ 电 电 知 知 知 知 包含 包含 包含 包含 包含 包含 包含 包含 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及Executable _: human 32? chamber 1 force, processing chamber temperature, substrate temperature, process gas 3 buckle, processing cartridge speed, dry material, lcp power, substrate position or substrate bias power or a combination thereof Establish the deposition rate of the surface. 1 rate, in the example, 'deposition can be read and integrated to the Lu-f plate partial test 11 'the second substrate suspension produces H can be - the second sand brother - the first fRF generator can be 1 to the frequency range of 100 MHz to connect ^ Jie / and u surrounding n't about 13.56 mhz operation; the second plate biased to about the substrate material rate =; force 1283439 at least part of the NND During the time period, the substrate bias power can be adjusted to one or more values within the range above the sputtering threshold. For example, a controller can be used, and the second substrate bias power can be changed to the point where the process is optimized. To ensure that no net deposition occurs in the field region of the patterned substrate. "The NND deposition rate may include the field deposition rate, which is the deposition rate of the material in the field region of the patterned substrate; the field deposition rate The range is from about -1 〇 nm/min to about +10 nm/min, for example, the field deposition rate can range from about 1-5 nm/min to about +5 nm/min. The deposition rate of 丽0 can include sidewall deposition rate. , which is the deposition rate of the material on one or more sidewalls of one or more features of the patterned substrate, the sidewall sink rate ranging from about 0 nm/min to about +1 〇 nm/min, such as the side The wall deposition rate can range from about 0 nm/min to about +5 nm/min; the NND deposition rate can include a bottom deposition rate, which is one of one or more features of the patterned substrate or more The deposition rate on multiple bottom surfaces, the deposition rate of the bottom surface is from about one 1 〇 nm / mi: n to about + 10 nm / min, for example, the deposition rate of the bottom surface may range from about -5 nm / min to about +5 nm / min. In another embodiment, the deposition system may comprise a a second target, and the second power source can provide a second power to the second power supply, and the second dry power supply can be a DC power supply. In another embodiment, the second target power supply can be a single generator. It can operate in a frequency range from about 1 MHz to about 1 〇〇 MHz, and the range of the second target power can be from φ, 100 W to 1500 W. For example, the second dry material power can range from about 450. w to about 550 W. In addition, the deposition system may include a second antenna, a second dielectric window that is coupled to the second antenna to the second processing chamber wall, and a second to the second dielectric window. A deposition baffle, and a second ICP source that is bonded to the second antenna to provide a second ICP power to the mystery antenna; the wire can be configured differently. The second lcp work = can be adjusted for the LND process _ establish a high-density electricity in the second processing chamber, as can be used - controller 'and can change the second power to optimize the process' to ensure that the process is not Produce a sudden suspension. - the second 1CP source can be an RF generator and can operate from about 1 〇 MHz to about 17 1283439, for example the second ICP source can be in the range of about 13.56 MHz, for example the second Γ γρ if - 1 CP power It can range from about 2000 W to about 10000 W, and a power range of from about 3000 W to about 6000 W. In the second embodiment, the deposition system may include a second control system coupled to the second processing chamber, the second force control system may be used to establish a lion processing force at least a portion of the profitable The scope of the room service is </ br> § * / 1 1 * ^ &quot; In the example, the deposition system may also include a second gas supply system coupled to the second processing chamber for at least "partial" processing gas Flowing into the second processing chamber to process the gas. w emulsion, each nitrogen gas, oxygen-containing gas, or metal-containing gas, or a group thereof ω and tt gas may comprise N2, N0, age and title 3, and the oxygen-containing gas may comprise 〇2, ship, ; fa; ^:;^ ;f (8), silver (five) or heart)=. ), (_Step: Process ribs can be performed - the following step barrier layer., 曰 > set the 0-day layer, deposit a barrier layer; and repair a second process can include _ process or LND process. Stop Mu, decides when to stop the second process. In the decision process "Cal, tr, r will not stop the second, 3, or more, as shown in Figure 3, and can be used to decide when to stop. Plate temperature data: r processing chamber pressure data, processing room ^ ^ degree data, base X body chemical data, processing gas flow rate data, dry material 1283439 material data, ICP power data, base power data, office data f material power data, substrate deviation amount △ In some cases, the wafer can be placed in the room = material, and combined. I 'for example, we can use the optical number ^ '❿ in another room to test SEM data and / or TEM data.) Tools; in addition, we can decide when to stop when to stop the second process; or the thickness data can be applied by mtlll °; when it is decided that no additional process will be applied, the addition process can include LND process, ^H0 Ί路至355 and ended. , deposition / engraving process, cleaning process, knowing the deposition process, when the remaining time is completed; measurement data can be included in the 7 can be used to determine the steps = data, processing gas chemical data, = gas = material, negative materials, ICP power data, substrate position information, target pressure data, processing time data, or process substrate offset, for example, we can use optical digital wheel (in the 0Dj laboratory to test SEM data and / or TEM data. /, In addition, we can decide to decide when to stop the second process; or the thickness data can be used in Figure 4 to show that according to an embodiment of the present invention, Qian Yi, Shi #在,丨上再ί During the time period, the processor can be set up: Ricky: can be loaded into the processing chamber after 7!! △, and the wafer table can be set at the processing height; processing 19 1283439 in the processing chamber to increase the processing chamber pressure; The back side gas cooling can be started. The electric power is clamped on the aa5] table; the processing room, we can handle the _ private processing of the room towel, to "DC power supply; during the process, can provide the period ΐίi, / _ _ , the village provides the desired _ ΐ) Λϊ; I RF_ power can be adjusted, in the process of ⑽ by 0 ^ LNDRF the desired bias power to the dry wood, and to provide said system _ desired NND RF bias power to the targets. Gong, also

在後處理時間期間,晶圓台可設定在抽取高度 J體流動及背織體冷卻,而可令基板自晶圓台去 = ,里J理室壓力可加以歡;自晶圓台移除基板;且基 二 圖5顯示根據本發明一實施例之LND製程空間之示範圖。如 此例示實施例所示,LND製程空間可利用RF偏壓功率作為χ軸以 及沈積速率對DC功率之比值作為y軸來定義;在另一實施例中, 其他製程參數以及/或製程參數之組合可用來定義Lnd製程空間。 圖5顯示穿越諸點512之一直線510,點512表示開始餘刻 之點;圖5中亦顯示LND區域520。 LND區域顯示可施行LND製程之示範區域。 圖6顯示根據本發明一實施例之LND製程;在此例示實施例 中顯示一 LND阻P早層沈積製程,其中吾人改變各種不同之製程參 數以達到一實質上均勻之阻障層。如圖所示,吾人可開啟自電源 24至靶材25之DC電力’改變至不同位準,再於阻障層沈積 製程期間關閉電力;「DC電力」係指自電源24施加至乾材25以令 材料濺鍍之DC電力。此外,自RF產生器27至天線26之ICP電 力可於LND阻障層沈積製程期間開啟或關閉,「ICP電力」係指來 自用以形成濃密電漿之產生器27之RF感應耦合電漿;自胙偏壓 產生器28至晶圓台22之RF基板偏壓電力亦可於LNj)阻障層沈積 1283439 製程期間開啟或關閉,「RF基板偏壓電力係指 加至晶圓台22 晶圓21上產生負偏壓之抓 處理室壓力可於LND阻障層沈積製程__成各種數值。 iPVD系統可用以施行LND阻障層沈積製程。於lnd阻障層沈 ft程期間,待沈積之材料可自—來源而被雜或蒸發,接著已 分可於抵達待塗佈晶®前被轉換成正離子;複 個離^可猎由產生自真空室内之處理氣體之高密度電聚來建 一二接ί,吾人可將電磁力施加至塗佈材料之正離子,例如施加 =偏壓於晶圓上,此偏壓可令塗佈材料離子朝向晶圓加速 ,有,多分率之塗佈材料可以與晶義近垂直之角度沈積於晶圓 ^如$、,均勻之薄阻障層可沈積於晶圓表面之場區域上以及晶 Ν之咼深寬比特徵部内。LND製程提供了高深寬比特徵部之底部 及側壁之極佳包覆。 一 ° 卢· 間,晶圓21可受支撐於溫控晶圓台22之頂部 ,,處理耽體可自-來源23而供應至真空處理t 3〇 β,皇 轉於真空,並調整至LND製程之適當離&amp;匕沈 ^圍,DC電力係自電源24供應至把材25,且電源%可經開啟 ΪΓίΐ適合LND製程之功率位準;晶圓RF偏壓係藉由RF偏壓 ^士态28來供應至晶圓台22,該RF偏壓產生器沈亦可於_ 製私期間開啟並調整至一適當位準;此外,自RF產 、 線26之ICP電力可於LND製程期間開啟及調整;又,^ 力 可於LND製程_改變至各種數值。 免緣力 處理氣體可自一氣體供應系統23提供進入真空 中’真空處理室30之麗力係糊壓力控制系統29來維持於, 並調整至$合LND製程之離子化沈積範圍。 、、工 iPVD系統可包含可耦合至處理室之控制器,且該方 或參數;於至少-部分LND前處理時間期間, 期間,調整該至少-處理參數至一第二位準;以及 21 1283439 LND後處理時間期間,調整該至少一處理參數至一第三位準。 、、f半導體晶圓上之高深寬比通孔及渠溝之金屬化中,吾人要 求阻障層及種晶層須具備良好之側壁及底部包覆,阻障層須在不 其屏蔽性質下儘可能薄細;阻障層務須薄細之原“ 、ϋ通孔結構之電阻必須降至最小,阻障層須為保角且連續? is ΐί晶層材料擴散進入介電層與其他層,避免產生可靠性問 層厚颜㈣肤並則、化,尤其在通孔底 望之騎可騎互連销電阻增加㈣上非所期 ►力示,於至少—部分前處理時間期間,處理室1 於約50 ^ 〇 mT〇rT ;而於通處理時間期間,處理室塵力可大 時間期於約100 mTorr ;且於至少一部分LND後處理 ,處理室塵力可小於約2〇 mT〇rr 交二 二可小於約2°;而於至二部= 少二i : Γ/力率可大於約5000 w且小於約5_ W,·且於至 ίΐ後處理時間期間,1Cp功率可小於約20 W。、 1。二,===力r力率可小於約 W且小於約15〇(^ 广篇1 DC功率可大於約1000 &gt;率可小於約20W。於至理時間期間,%功 板偏壓功率可大於 j^ LND處理時間期間,胙基 後處至少一部分· ----- 或者可採用不同LND前處理時期。&quot;、力25移至約35秒; J時期之範圍;自大於約150秒’例如W ^ 處理時期之範圍可自自約10秒至約^ 中 22 1283439 由沈積厚度來決定。 此外,LND後處理時期可小於約5〇移、 _約25秒朗35秒;^採用i同^ 在另f實^必要條件。 來處理基板,例如可建立在一 LND ^ ^更夕LND處理時期 理條件,且可建立其H Ϊ 間,特徵部之處 之處理條件。 处寺4 d間緊猶堆疊特徵部During the post-processing time, the wafer table can be set at the extraction height J body flow and the back texture cooling, and the substrate can be removed from the wafer table, and the pressure can be added to the wafer chamber; the substrate is removed from the wafer table. And FIG. 5 shows an exemplary diagram of the LND process space according to an embodiment of the present invention. As shown in the illustrated embodiment, the LND process space can be defined using the RF bias power as the x-axis and the ratio of the deposition rate to the DC power as the y-axis; in another embodiment, other process parameters and/or combinations of process parameters. Can be used to define the Lnd process space. Figure 5 shows a line 510 crossing one of the points 512, point 512 indicating the point at which the moment begins; and LND area 520 is also shown in Figure 5. The LND area shows a demonstration area where an LND process can be performed. Figure 6 shows an LND process in accordance with an embodiment of the present invention; in this illustrative embodiment, an LND resist P early layer deposition process is shown in which a plurality of different process parameters are varied to achieve a substantially uniform barrier layer. As shown, we can turn on the DC power from the power source 24 to the target 25' to a different level, and then turn off the power during the barrier layer deposition process; "DC power" refers to the application of the power source 24 to the dry material 25 DC power that causes the material to be sputtered. In addition, the ICP power from the RF generator 27 to the antenna 26 can be turned on or off during the LND barrier layer deposition process, and the "ICP power" refers to the RF inductively coupled plasma from the generator 27 used to form the dense plasma; The RF substrate bias power from the 胙 bias generator 28 to the wafer table 22 can also be turned on or off during the LNj) barrier layer deposition process 1283439. "RF substrate bias power is applied to the wafer table 22 wafer. The processing chamber pressure that produces a negative bias on 21 can be used in the LND barrier deposition process. The iPVD system can be used to perform the LND barrier deposition process. During the lnd barrier layer, the deposition process is required. The material can be miscellaneous or evaporated from the source, and then can be converted into positive ions before reaching the crystal to be coated; the complex can be hunted by high-density electropolymerization of the processing gas generated from the vacuum chamber. Secondly, we can apply electromagnetic force to the positive ions of the coating material, such as applying = bias on the wafer, this bias can accelerate the coating material ions toward the wafer, and there are multi-component coating materials. Can be deposited on the wafer at a nearly vertical angle to the crystal $, a uniform thin barrier layer can be deposited on the field surface of the wafer surface and within the aspect ratio aspect of the wafer. The LND process provides excellent cladding of the bottom and sidewalls of the high aspect ratio feature. ° Lu, between the wafer 21 can be supported on the top of the temperature control wafer table 22, the processing body can be supplied from the source 23 to the vacuum processing t 3 〇 β, the king is transferred to the vacuum, and adjusted to the LND process The DC power is supplied from the power source 24 to the material 25, and the power source % can be turned on to suit the power level of the LND process; the wafer RF bias is biased by the RF bias. The state 28 is supplied to the wafer table 22, and the RF bias generator sink can be turned on and adjusted to an appropriate level during the OPC process; in addition, the ICP power from the RF line 26 can be turned on during the LND process. And adjustment; again, the force can be changed to various values in the LND process. The free-edge process gas can be supplied from a gas supply system 23 into the vacuum, and the Lili paste pressure control system 29 of the vacuum processing chamber 30 is maintained. And adjusted to the ionization deposition range of the LND process.,, iPVD system A controller may be coupled to the processing chamber, and the party or parameter; during at least a portion of the LND pre-processing time, during which the at least - processing parameter is adjusted to a second level; and 21 1283439 LND post-processing time period Adjusting the at least one processing parameter to a third level. In the metallization of the high aspect ratio vias and trenches on the semiconductor wafer, we require that the barrier layer and the seed layer have good sidewalls and The bottom cladding, the barrier layer must be as thin as possible without shielding properties; the barrier layer must be thin and thin; the resistance of the through-hole structure must be minimized, and the barrier layer must be conformal and continuous? Is ΐ 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶It is shown that during at least part of the pre-processing time, the processing chamber 1 is at about 50 ^ 〇mT〇rT; and during the processing time, the processing chamber dust force can be large in a period of about 100 mTorr; and after at least a part of the LND is processed. The dust in the treatment chamber may be less than about 2〇mT〇rr, and the difference between the two may be less than about 2°; and the second to the second is less than about 5,000 w and less than about 5 _ W, and The 1Cp power can be less than about 20 W during the post processing time. , 1. Second, the === force r force rate can be less than about W and less than about 15 〇 (^ Wide 1 DC power can be greater than about 1000 &gt; the rate can be less than about 20 W. During the reasonable time, the % power board bias power can be More than j^ LND processing time, at least a part of the back of the sputum · ----- or different LND pre-processing periods can be used. &quot;, force 25 moved to about 35 seconds; range of J period; since more than about 150 seconds ' For example, the range of W ^ treatment period can be determined from the thickness of deposition from about 10 seconds to about 22 1283439. In addition, the post-processing period of LND can be less than about 5 、 shift, _ about 25 seconds lang 35 seconds; ^ adopt i The same conditions can be used to process the substrate, for example, the LND processing time can be established in a LND, and the processing conditions of the H Ϊ and the features can be established. Tightly stacking features

方法ί更:系ίί之氣體供應系統;且LND 至少一部分⑽後處理時想丄 外,在不同LND處理時間期間可建立 弟j理乳體。此 理時間期間之流速可加以變化。 桃速,且在不同LND處 在一實施例中,第一處理氣體可包含一 體第二處理氣體可包含-惰性氣η:以 一含金屬氣體、或其組合;第三虚疎洛躲人3虱孔體、或 含氮氣體或其組合,例如情性氣體可包氯、m氣=一 或其組合;此外,含金屬氣體可包含mm、 上以吸引離二特徵二積:f施加至晶圓 J屬沈積時產生極少或幾乎無突懸;如此即U改善了壓且 、、、口果為阻障層金屬之理想高度保角金屬沈積。 土 如Tai^為另反則可在®阻障沈積製程期間加入例 ΊΜ,&amp;或另-反應氣體。典型上,氮氣流係為使獅系統在 23 1283439 較佳之乾材未中毒模式或金屬模式下施行;然而 由增加反應氣體流量而達到,吾人可個本發明^經 J二步地改變’以將金屬氮化物組成相當輕易地自 物之化學計量。不論吾人期望較 氮軋或反應軋體流量來控制整個沈積製程;此外, 氮化可利用沈積步驟後之Ar/沁離子電漿來控制。,、The method ί: is the gas supply system of ίί; and at least a part of the LND (10) is treated after the post-processing, and the breast can be established during the different LND processing time. The flow rate during this time period can be varied. Peach speed, and at different LNDs, in an embodiment, the first process gas may comprise an integral second process gas may comprise - an inert gas η: a metal-containing gas, or a combination thereof; The boring body, or the nitrogen-containing gas or a combination thereof, for example, the inert gas may be chlorine, m gas = one or a combination thereof; in addition, the metal-containing gas may include mm, to attract the two characteristic two products: f is applied to the crystal The circle J is deposited with little or no overhang; thus, U improves the ideal height-preserving metal deposition of the barrier metal. Soils such as Tai^ can be added during the ® barrier deposition process by adding 例, &amp; or another-reaction gas. Typically, the nitrogen flow system is such that the lion system is carried out in the preferred dry material non-poison mode or metal mode of 23 1283439; however, by increasing the flow of the reaction gas, we can change the 'two steps' of the present invention. The metal nitride composition is quite easy to measure from the stoichiometry of the material. Whether we prefer a nitrogen rolling or reactive rolling flow to control the entire deposition process; in addition, nitriding can be controlled by Ar/沁 ion plasma after the deposition step. , ,

本發明之方法在結合iPVD系統使用且以極 =子化材料(例如Ta及Cu)時特別具有優勢;本=== 30^00 mTorr南壓下均勻地沈積相同材料之優勢,此舉亦可令使 率來沈積離子化金屬;此外,本發明之製程極 易適用於不同金屬上,尤其在結合前述設備使用時。 本發财-iPVD纽,其係以高金漏子鲜以及流至 f板之大處理氣體離子通量之沈積模式來操作,其中大處理氣體 離子通量可使已沈積材料產生較小之黏滞係數(sticki= 較大之表面移動性,因此可提升圖案化晶圓之特 本發明可_- iPVD系統,其細超低沈積速率之沈積模式 刼作於圖案化基板之場區域中,且提供較佳保角,特別斑並 iPVD製程有關之侧壁包覆。 /'八 在實施例中可施行-湖製程,其施加至晶圓之偏壓功 率係升咼至即使沈積仍發生於特徵部之側壁上,然實質上並益金 f沈積於場上之程度,此種程度可利用減少至基板表面之金^通 里來達到,在此製程期間,層間介電層或前金屬化 (pre-metalized)表面並未受到蝕刻,因為藉由施加適當之晶圓 偏壓可平衡金數之沈積與蝕刻速率。 圖7顯示根據本發明一實施例之製程空間之示範圖。如 24 1283439 戶:tίΪ例所示,_製程空間可藉由以RF偏壓功率作為x軸 中,制率與電源之比值作為y軸來定義;在另一實施例 空間:他i程參數以及/或製程參數之組合可用來定義nnd製程 的點圖7顯不穿越點712的線710,點712表示蝕刻開始發生時 程之不一 NND區域720,該NND區域顯示可施行NND製 例中Γ顯8 _^峨本發明—實施例之腦製程。在所例示之實施 層其中吾人將各種不同之製程參 種曰席十接制!獲致一實質上均勻之種晶層。如圖所示,在腦Cu 改期間’吾人可開啟自電源24至把材25之DC電力, 26之ICP^^’再關閉%電力;此外’自RF產生器27至天線 自RF偏壓產生晶層沈積製程期間開啟及關閉;而 ϋ fit至晶圓台22之RF基板碰電力亦可於_ Cu 者’處議力™ 料可待沈積材 施加至塗佈材料之正離子1如1=負ϊί二C磁力 可令塗佈材料離子朝向晶圓加速,俾使2偏壓 以與晶圓幾近垂直之角声沈靜θ n f有1刀率之塗佈材料可 可沈積於晶圓表面之場‘域上以;:如此’均勻之薄阻障層 _提供了高深寬比之=寬比特徵部内。 處;處於溫幽㈣之頂部 係利用_ 29來轉域心並 25 1283439 積範圍;DC電力係自電源24供應至乾材25 ,且電源24可經開啟 並調整至適合NND製程之功率位準;晶圓RF偏壓係藉由即偏壓 產生器28而供應至晶圓台22,該RF偏壓產生器28亦可於 製程期間開啟並調整至一適當位準;此外,自即產生哭27至天 線26之ICP電力可於LND製程期間開啟並調整;又,^理 可於丽D製程期間改變至各種數值。 處理氣體可自-氣體供應系統23提供進入真空處理 中’真空處理室30之壓力係利用壓力控制系統29來維持於, 並調整至適合NND製程之離子化沈積範圍。 、二 iPVD纟統可&amp;含抑合至處理室之控彻,且财法 益數笛於至少一部分_前處理時間期間, Uif數i 一第一位準;於至少-部分nnd處理時間 如圖8所示,於至㈣ 力可小於㉟20 ιηΤοιτ ;祕_處辦^至壓 於約50 mTorr且小於約1〇〇缸:.’處理室壓力可大 時間期間,處理室壓力可小於約2〇 mT〇=至=,分_後處理 處理時間期間,ICP功率可小於約20 w;而於。二部分麵前 理時間期間’ ICP功率可大於約_ w且:於^^分_處 少-後處理時間期間,lcp功率^ 〇〇 W ’·且於至 此外,於至少一部分麵前處 、、=20 W。 則;而於至少一部分_處理時 :^DC功率可小於約 15〇〇 W ; 1〇00 於約20 W。於至少一部分_前處曰期間,DC功 壓功率可小於約丨。W ;而於至少 二間期間,RF基板偏 板偏壓功率可大於約450 W且小於約&amp;〇 w处理時間期間,即基 後處:時間期間,胙基板偏壓功率可小於約=至少-部分_ 所例示之實施例中所示,麵前處理時期可㈣約%秒且 26 1283439 時期之範如NND處理 期之範圍可自自約10秒至約i咖/另且一中時:J理時 沈積厚度來決定。 心處理時期可由測量 此外,NND後處理時期可小於約3〇 之謝自卿、蝴^ 在另單·^ND處理軸’但此並縣购之必要條件。 來處理美;^ 用—或更多不同處理條件之lnd處理時期 之条件。 麵處理時間期間緊密堆疊特徵部 法可ί包之缝編:且膽 树晴,二 纟:=:處Ϊ以工二:性,:含氮氣 -含金屬氣體、或其組合;第三處理‘體J包;戈或 輝HiS: ί rf 理氣===可 於0.1 nm/min之速率沈積至晶圓上。吾人將一極低偏壓施加至晶 27 1283439 53„特徵部之底部,由於射實f上無沈積且側壁 上實質均勻之沈積’金屬沈積時極少或無錢產生;如此即改盖 了側壁包覆,且結果為阻障層金屬之理想高度鋪金屬沈積。 hi^msNND處理紐可包細氬氣作錢鍍氣體。 為沈積如TaNx之金屬氮化物阻障層,膽處理期間亦可使用氮氣。 或另若應性製程,則可在膽製程期間加入例如TaN,N2 jI反應㈣。典型上,氮氣流係為使iPVD系統在較佳之乾材 氣屬ί式下施行;然而,中毒模式可經由增加反應 ϊ 吾人可_本發明而令氮氣流量更進-步地改 i缺物ΐ成赠輕易地自富氮金屬氮化物漸次調和 沈積步驟後之Ar/N2離子電漿來控制卜。金屬膑侧壁之鼠化可利用 均勻,且力▼使正氬離子流向晶圓上而變得較 於特徵部911 產生突懸時’種晶層914可沈積 可使用其他材mt! ’種晶層914可包含^;或者亦 内以及基板_之頂面上,t 於特徵部911 時,可沈積附加種晶層⑽,最财處層^未產生突懸 28The method of the present invention is particularly advantageous when used in combination with an iPVD system and with a polar-sub-material (such as Ta and Cu); this === 30^00 mTorr has the advantage of uniformly depositing the same material under a south pressure, which may also The rate is used to deposit ionized metal; in addition, the process of the present invention is highly adaptable to different metals, especially when used in conjunction with the aforementioned apparatus. The Fortune-iPVD New Zealand operates with a high-gold leakage and a deposition mode of large processing gas ion flux flowing to the f-plate, where the large processing gas ion flux can cause a small viscous of the deposited material. Coefficient (sticki=larger surface mobility, so the invention can be improved.) The iPVD system has a thin ultra-low deposition rate deposition mode applied to the field area of the patterned substrate and is provided. Better conformal coverage, especially for the sidewall coating of the iPVD process. / 'Eight in the embodiment - the lake process, the bias power applied to the wafer is ramped up to even if the deposition still occurs in the feature On the side wall, the thickness of the gold is deposited on the field. This degree can be achieved by reducing the amount of gold to the surface of the substrate. During this process, the interlayer dielectric layer or pre-metallization (pre- The metalized surface is not etched because the deposition and etch rate of the gold number can be balanced by applying a suitable wafer bias. Figure 7 shows an exemplary diagram of a process space in accordance with an embodiment of the invention, such as 24 1283439: tίΪ As shown in the example, _process The ratio can be defined as the y-axis by the RF bias power as the x-axis, and the ratio of the ratio to the power source; in another embodiment space: the combination of the parameters and/or the process parameters can be used to define the nnd process. Point 7 shows that the line 710 of point 712 is not crossed, and point 712 indicates that the NTD area 720 is different in the timing of the start of the etching, and the NND area shows that the NND can be implemented in the example of the invention. Process. In the illustrated implementation layer, we have a variety of different process parameters to participate in the production of a seed layer! A substantially uniform seed layer is obtained. As shown in the figure, during the brain Cu change, 'we can open from the power supply 24 To the DC power of the material 25, the ICP^^' of 26 turns off the % power; in addition, 'from the RF generator 27 to the antenna is turned on and off during the crystal layer deposition process from the RF bias; and ϋ fit to the wafer stage 22 The RF substrate can also be used to charge the positive ions of the coating material to the coating material. For example, 1 = negative ϊ 2 C magnetic force can accelerate the coating material ions toward the wafer, 俾Applying 2 biases to a nearly perpendicular angle to the wafer, the acoustic sinking θ nf has a coating rate of 1 knife Cocoa is deposited on the field of the wafer surface; such: the 'uniform thin barrier layer _ provides a high aspect ratio = width ratio feature inside. At the top of the warm (four) is the use of _ 29 to transfer the domain The core power is supplied from the power source 24 to the dry material 25, and the power source 24 can be turned on and adjusted to a power level suitable for the NND process; the wafer RF bias is by the bias generator 28 And supplied to the wafer table 22, the RF bias generator 28 can also be turned on and adjusted to an appropriate level during the process; in addition, the ICP power generated from the crying 27 to the antenna 26 can be turned on and adjusted during the LND process. In addition, it can be changed to various values during the process of Li D. The process gas can be supplied from the gas supply system 23 into the vacuum process. The pressure of the vacuum process chamber 30 is maintained by the pressure control system 29 and adjusted to the ionization deposition range suitable for the NND process. The second iPVD system can control the control room to the control room, and the financial method benefits the flute during at least part of the _ pre-processing time, the Uif number i is the first level; at least the part of the nnd processing time is as shown in the figure 8, the to (4) force can be less than 3520 ιηΤοιτ; secret _ to do ^ to pressure about 50 mTorr and less than about 1 〇〇 cylinder: . 'Process chamber pressure can be large period of time, the processing chamber pressure can be less than about 2 〇 mT 〇 = to =, minutes _ post-processing time, ICP power can be less than about 20 w; The two parts in front of the time period 'ICP power can be greater than about _ w and: less ^ _ _ less - after the processing time, lcp power ^ 〇〇 W '· and in addition, in at least a part of the front, , =20 W. And at least a portion of the processing time: ^ DC power can be less than about 15 〇〇 W; 1 〇 00 at about 20 W. The DC power can be less than about 丨 during at least a portion of the front. W; and during at least two periods, the RF substrate bias voltage may be greater than about 450 W and less than about &amp; 〇 w processing time, ie, at the base: time period, the 胙 substrate bias power may be less than about = at least - Part _ As shown in the illustrated embodiment, the front processing period may be (4) about % seconds and the period of 26 1283439 period such as the NND processing period may range from about 10 seconds to about i coffee / another one: J is determined by the thickness of the deposit. The heart treatment period can be measured. In addition, the NND post-processing period can be less than about 3 〇. Xie Ziqing, Butterfly ^ in the other ^ ND processing axis 'but the necessary conditions for county purchase. To deal with the beauty; ^ with - or more different processing conditions of the lnd processing period conditions. During the surface treatment time, the tightly stacked feature method can be stitched: and the biliary tree is fine, the second 纟:=: at work 2: sex, nitrogen-containing metal gas, or a combination thereof; third treatment Body J package; Ge or Hui HiS: ί rf qi === can be deposited onto the wafer at a rate of 0.1 nm/min. We applied a very low bias to the bottom of the crystal 27 1283439 53 „the bottom of the feature, because there is no deposition on the projection f and the deposition on the sidewall is substantially uniform. The metal deposition is very little or no money; thus the side wall package is changed. The result is the ideal height metal deposition of the barrier metal. hi^msNND treatment can be used to make fine argon gas for gas plating. For the deposition of a metal nitride barrier layer such as TaNx, nitrogen can also be used during the gallbladder treatment. Or, if it is a suitable process, for example, TaN, N2 jI reaction (4) may be added during the biliary process. Typically, the nitrogen flow system is such that the iPVD system is operated under the preferred dry gas climatic mode; however, the poisoning mode can be By increasing the reaction 吾 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The ratification of the sidewalls of the crucible can be utilized uniformly, and the force can cause the positive argon ions to flow onto the wafer to become overhang when the features 911 are formed. The seed layer 914 can be deposited and other materials can be used. 914 may contain ^; or also within and _ The top surface, t at 911, an additional seed layer may be deposited ⑽, the layer most financial feature 28 ^ overhanging does not occur

1283439 中將f一特明一實施例之另-示範製程之示意圖,其 的量#A板1η(Γ thlOUgh)區域’ _製程可控制穿透部^ 其他材料 生突i。1或者之組合時’沈積阻障層1012實質上可不產 於特禮 質上未產生突懸時,種晶層1014可沈積 ====’ ΐ:實施例中’種晶層1014可包含⑶;或者 突科ί ίίί 頂面上,當特徵部之開口處實質上未產生 H附加種晶層1G16,最後可沈積電鍍層腿。 罢,j f不根據本發明一實施例之阻障層沈積製程之示範結 Ϊ產Ϊ ί Ϊ 阻障層製程之讓結果,該結果顯示LND製程 一2齡根據本發明一實施例之種晶層沈積製程之示範結 二^、、|不(:11種晶層製程之SEM結果,該結果顯示NND製程未產 生哭懸。 雖然以上僅雜說明本發明之某些實施例,然熟悉此項技術 者將極易明瞭·在實際上不偏離本發明之新穎教示及優勢下,實 施例可進行許多修改,因此,所有此種修改均應包含於本發明之 範疇内。 【圖式簡單說明】 參照下列詳細說明,尤其在結合附圖加以考慮時,將可使本 發明之各種不同實施例之較完整評價以及其許多伴隨之優勢更形 清楚。 圖1顯示根據本發明一實施例之晶圓橫截面之簡圖; 圖2顯示根據本發明一實施例之處理系統之示範方塊圖; 29 1283439 圖3顯示根據本發明一實施例之iPVD系統操作方法之簡化流 程圖; 圖4顯示根據本發明一實施例之示範沈積製程,· 圖5顯示根據本發明一實施例之LND製程空間之示範圖; 圖6顯示根據本發明一實施例之LND阻障層沈積製程; 圖7顯示根據本發明一實施例之NND製程空間之示範圖,· 圖8顯示根據本發明一實施例之丽d種晶層沈積製程; 圖9顯示根據本發明一實施例之示範製程之示‘圖; 圖10顯示根據本發明一實施例之另一示範製^&amp;之示意圖; 圖11顯示根據本發明一實施例之LND製程空間之示g圖;’以 圖12顯示根據本發明-實施例之種晶層沈積製程之示 % ° 【主要元件符號說明】 10 金屬膜 11 通孔結構 12 晶圓 13層間介電層 14 突懸結構 15 通孔結構底部 16 側壁 18 金屬離子 21 晶圓 22 晶圓台 23氣體供應系統 24 DC電源 25 靶材 26 天線 27第一 RF源 1283439 28 RF偏壓產生器 29 壓力控制系統 30 處理室 31 介電窗 32 室壁 33 活動沈積擋板 34 永久磁鐵組 35 Z-傳動器 50 控制器 200 iPVD 系統 300 iPVD系統之操作方法 310開始 345在處理室内之晶圓台上設置圖案化基板/晶圓 320施行第一製程 325完成否? 330第二製程? 335施行第二製程 340完成否? 345附加製程 350施行附加製程 355結束 400簡化沈積製程 410 前處理時間 420處理時間 430後處理時間 710線 712蝕刻開始發生時的點 720丽D區域 910基板 31 1283439 911 特徵部 912 阻障層 914種晶層 916附加種晶層 918 電鍍層 1010基板 1011特徵部 1012阻障層 1014種晶層 1016附加種晶層 1018電鍍層1283439 A schematic diagram of another exemplary process of the embodiment of the present invention, wherein the amount #A plate 1η(Γ thlOUgh) region'_process can control the penetration portion ^ other material. 1 or a combination of the 'deposition barrier layer 1012 may not be produced on the special mass without a suspension, the seed layer 1014 may be deposited ====' ΐ: In the embodiment, the seed layer 1014 may comprise (3) Or on the top surface, when the opening of the feature portion does not substantially produce the H additional seed layer 1G16, the plated leg can be finally deposited. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Demonstration of the deposition process, ^, , | No (: SEM results of 11 kinds of crystal layer processes, the results show that the NND process does not produce crying. Although some of the embodiments of the present invention are only described above, familiar with the technology It will be readily apparent that many modifications may be made to the embodiments without departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention. The detailed description of the various embodiments of the present invention, as well as many of the attendant advantages thereof BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 shows an exemplary block diagram of a processing system in accordance with an embodiment of the present invention; 29 1283439 FIG. 3 shows a simplified flow of an iPVD system operation method in accordance with an embodiment of the present invention. Figure 4 shows an exemplary deposition process in accordance with an embodiment of the present invention. Figure 5 shows an exemplary LND process space in accordance with an embodiment of the present invention. Figure 6 shows an LND barrier layer deposition process in accordance with an embodiment of the present invention. FIG. 7 shows an exemplary diagram of a NND process space according to an embodiment of the invention, FIG. 8 shows a process for depositing a seed layer according to an embodiment of the invention; FIG. 9 shows an exemplary process according to an embodiment of the invention. FIG. 10 is a schematic view showing another exemplary embodiment of the present invention; FIG. 11 is a view showing an LND process space according to an embodiment of the present invention; - Explanation of the seed layer deposition process of the embodiment % ° [Main component symbol description] 10 Metal film 11 Via structure 12 Wafer 13 interlayer dielectric layer 14 Suspension structure 15 Via structure bottom 16 Side wall 18 Metal ion 21 crystal Circle 22 Wafer Table 23 Gas Supply System 24 DC Power Supply 25 Target 26 Antenna 27 First RF Source 1283439 28 RF Bias Generator 29 Pressure Control System 30 Process Chamber 31 Dielectric Window 32 Chamber Wall 33 Active Deposition Baffle 34 The long magnet group 35 Z-actuator 50 controller 200 iPVD system 300 iPVD system operation method 310 begins 345 setting the patterned substrate/wafer 320 on the wafer table in the processing chamber to execute the first process 325 is completed? Process 335 Performing Second Process 340 Complete No? 345 Additional Process 350 Performing Additional Process 355 End 400 Simplified Deposition Process 410 Pre-Processing Time 420 Processing Time 430 Post-Processing Time 710 Line 712 When the Etching Starts Occurred Point 720 Li D Area 910 Substrate 31 1283439 911 feature 912 barrier layer 914 seed layer 916 additional seed layer 918 plating layer 1010 substrate 1011 feature 1012 barrier layer 1014 seed layer 1016 additional seed layer 1018 plating layer

Claims (1)

1283439 十、申請專利範圍: 1· 一種沈積系統的操作方法,包含: 將圖案化基板設置於處理室内之晶圓台上· 在該處理室中建立高密度電漿,豆中兮古令 、 材料之離子及大量之處理氣體離子/、Μ、電水包含塗佈 將該圖案化基板曝露至該高密度電襞· 功率基板偏壓 包含在該圖案化基板之場區域中之超率·沈積速率 以及 將材料沈積入圖案化基板之特徵部,而實 開口產生突懸(overhang)材料。 而上不致在特徵部 專利範圍第1項之沈積系統的操作方法,其中該 ί甘^含前處理時間、LND處理時間、或⑽後處理時間、 ί二H其中該⑽前處理時間自、約0秒變化至約50秒;該LND =夺間自約10秒變化至約5〇〇秒;且LND後處理時間自約 變化至約5000秒。 nmi·如申請專利範圍第2項之沈積系統的操作方法,其中該 LND處理時間大於約150秒且小於約250秒。 33 1 如申請專利範圍第2項之沈積系統的操作方法,其中該沈 積序、、统更包含輕合至該晶圓台之基板偏壓產生器,該方法更包含: 在至少—部分該LND處理時間期間,調整該LND基板偏壓功 f至小於在—濺鍍閾值範圍中之第一值,其中該LND基板偏壓功 率之範圍係自、約0 W至約200 W。 2 / 5.如申/青專利範圍第2項之沈積系統的操作方法’其中該沈 積糸統更包含靶材、提供LND靶材電力至該靶材之靶材電源,該 1283439 方去更包含:在至少一部分該lnd處理時間期間,調整該LNI)把 材功率以達到該LND沈積速率,其中該超低沈積速率係小於約3〇 咖/min,該LND靶材功率之範圍係自約1〇 w至約2000 w。、 ^ 6·如申請專利範圍第2項之沈積系統的操作方法,其中該沈 積系統更包含一耦合至該處理室之壓力控制系統,該方法更包含: 在至少一部分該LND處理時間期間,建立一 LND處理室壓力, 其中该LND處理室壓力係小於約130 mTorr且大於約1 mTorr。 7·如申請專利範圍第2項之沈積系統的操作方法,其中該沈 積系統更包含一天線、一輕合至該天線以及該處理室壁之介電 窗、一耦合至該介電窗之活動沈積擋板、以及一耦合至該天線之 ICP源,該沈積系統的操作方法更包含: 在第一頻率下操作該ICP源;以及 調整該ICP源,以於至少一部分該LND處理時間期間提供一 LND ICP功率位準。 8·如申請專利範圍第7項之沈積系統的操作方法,其中該 LND ICP功率位準係大於約3000 W且小於約6000 W。 9·如申請專利範圍第5項之沈積系統的操作方法,其中該沈 積系統更包含一耦合至該處理室壁之靶材,一耦合至該靶材之永 久磁鐵組、以及一耦合至該靶材之DC電源,該沈積系統的操作方 法更包含: 在至少一部分該LND處理時間期間,將該DC電源之功率輸出 位準設定於第一 LND靶材功率位準,其中該第一 LND靶材功率位 準係大於約1000 W且小於約3000 W。 1〇·如申請專利範圍第2項之沈積系統的操作方法,其中該 34 1283439 NND場沈積速率之範圍係自約-10 nm/min至約+l〇 nm/min。 \6·如申請專利範圍第15項之沈積系統的操作方法,其中該 場沈積速率之範圍係自約-5 nm/min至約+5 nm/min。 ^7·如申請專利範圍第14項之沈積系統的操作方法,其中該 底*面沈積速率之範圍係自約-10 nm/min至約+1〇 nm/min。 2·如申請專利範圍第17項之沈積系統的操作方法,其中該 &amp;面沈積速率之範圍係自約—5 nm/min至約+5 nm/min。 如申請專利範圍第14項之沈積系統的操作方法,其中該 式包含丽D前處理時間、NND處理時間、或NND後處理時間、 m ^ ^0 50 # ; * 間自約。秒i=_秒;且其中該_後處理時 人· 申晴專利範圍第19項之沈積系統的操作方法,-勺 3 ·在至夕一部分該丽D處理時間期間,將其柄值厭 更匕 大於第二濺鍍閾值之箆一盤伯反偏壓功率調整至 約500 W至約1500 w。—、中絲板偏壓功率之範圍係自 其中該 其^厭利範圍第21項之沈積系統的操作方法, 基板驗功率之範圍係自約750 W至約_ W。去 更包 23·如申請專利範圍第19項之沈積系統的操作方法, 36 1283439 1薪,至少—部分該蘭D處理時間期間,將nnd靶材功率調整至 一祈數值,其中該丽D靶材功率之範圍係自約100 W至約15〇〇 w。 人:=·如申請專利範圍第19項之沈積系統的操作方法,更包 π,少—部分該NND處理時間期間,調整該ICP源以提供一 5的偷功率位準,其中該丽D DC功率位準之範圍係自約2_ W 主約 10000 W。 _ 1 *申請專利範圍冑24 J員之沈積系統的操作方法,其中該 U iCP功率位準之範圍係自約3000 W至約6000 W。 26·如申請專利範圍第19項之沈積系統的操作方法,更包 3 ·在至少一部分該NND處理時間期間,建立NND處理室壓力, 其中该NND處理室壓力小於約丨3〇 mT〇rr且大於約丨mT〇rr。 • 27·如申請專利範圍第19項之沈積系統的操作方法,更包 含·在至少一部分該丽D處理時間期間,令第二處理氣體流入該 處理室中’其中該第二處理氣體包含惰性氣體、含氮氣體、含氧 氣體、或含金屬氣體或其組合。 28·如申請專利範圍第27項之沈積系統的操作方法,其中該 惰性氣體包含氬、氦、氪、氡、或氣、或其組合。 29·如申請專利範圍第27項之沈積系統的操作方法,其中該 含金屬氣體包含鎢(W)、銅(cu)、钽(Ta)、鈦(Ti)、铷(Ru)、 銥(Ir)、鋁(A1)、銀(Ag)或鉑(pt)或其組合。 30·如申請專利範圍第14項之沈積系統的操作方法,其中該 NND製程係用以沈積種晶層。 37 1283439 31·如申請專利範圍第14項之沈積系統的操作方法,其中兮 NND製程係用以修復種晶層。 ^ &amp; 32·如申請專利範圍第14項之沈積系統的操作方法,其中兮 NND製程係用以修復阻障層。 ’、^ 33·如申請專利範圍第14項之沈積系統的操作方法,其中今 NND製程係用以沈積阻障層。 ”〜 34·如申請專利範圍第14項之沈積系統的操作方法,其中該 NND製程係用以在該圖案化基板之至少一該特徵部中建立 二 (punch through)。 ^ 、35·如申請專利範圍第丨項之沈積系統的操作方法,其 沈積系統包含一離子化物理蒸氣沈積(ipVD)處理室。^ w 36·如申請專利範圍第丄項之沈積系統的操作方法, 沈積系統包含一傳輸系統。 /、 μ H申請專利範圍第1項之沈積系統的操作方法,更包含: 整,其株材功率及基扮扁壓功率係經過調 以及在®案基板之該場區域中建立第二⑽沈積速率; 特徵===圓案化基板之特徵部’而實質上不致在 請專利範圍第1項之沈積系統的操作方法,更包含: 將_案化基板設置於第二處理室内之第二晶圓台上更w 38 Ϊ283439 施行第二LND製程,笼一釦妯#、玄β结 在該_化基板—之該顧域中力ί ,附加材料沈積至_案化基板 特徵部開口產生突懸材料。 巾只質上不致在 ,Ϊ申圍第14項之沈積系統的操作方法,更包含·· 整,D t ’其中歡材功率及基板_功率係經過調 中,該麵沈零積=及而在該麵基板之該場區域 ^ιίΐί ϊ ί1^|«;ί ™ t 40.如申請專利範圍第14項之沈積系統的操作方法,更包 將,圖案化基板設置於第二處理室内之第二晶圓台上; 整 中 施!^二NND製程,其中姆功率及基板偏塵功率係經過調 立第二膽沈積速率,而在該圖案化基板之該場區域 該丽D沈積速率約為零;以及 一 處理該®案化基板,藉此將材料沈積於該圖案化基板之 。刚壁或該B案化基板之特徵部底面或其組合上。 、 41二如申請專利範圍第1項之沈積系統的操作方法,更包含: 將该圖案化基板設置於附加處理室内之晶圓台上;及 施行一附加製程。 42二如申請專利範圍第14項之沈積系統的操作方法,更包含: 將该圖案化基板設置於附加處理室内之晶圓台上;及 施行一附加製程。 39 1283439 43· —種沈積系統的操作方法,包含: 將圖案化基板設置於處理室内之晶圓台上· 金屬其巾該高贿絲包高濃度之 ,,基板曝露至該高密度電聚; 功率或^中吾人將靶材:力率或_偏壓 包含NND場沈積速率、咖側 S$_D沈積速率 或其組合;及 /U積速率、或麵D底面沈積速率、 利用該NND製程來處 _ 圖案化基板之特徵部化基板,猎此將材料沈積於該 上,其中在_製程亥《*化基板之特徵部底面或其組合 處理氣體化學性質、處理室溫度、基板溫度、 置、歡材功率、或美杯值,體飢速、歡材材料、ICP功率、基板位 土板偏壓功率或其組合係經過調整。 44·如申請專利範圚 NND場沈積速率之範園43項之沈積糸統的操作方法,其中該 糸自約-10 nm/min 至約+1〇 nm/min。 NND場沈積^率^第44項之沈積系統的操作方法,其中該 、 礼圓係自約-5 nm/min至約+5 nm/min。 NND底面沈第43項之沈積系統的操作方法,其中該 摩已圍係自約—10 nm/min至約+1〇 nm/min。 NND底面沈第46項之沈積系統的操作方法,其中該 輕4園係自約-5 nm/min至約+5 nm/min。 48·如申請專利畫々 々 NND製程包含贿d園弟43項之沈積糸統的操作方法,其中该 月1J %理時間、NND處理時間、或NND後處理時間、 1283439 或其組合,其中該NND前處理時間自約0秒變化至約50秒;該NND 處理時間自約1〇秒變化至約500秒;且NND後處理時間自約〇秒 變化至約5000秒。 49·如申請專利範圍第48項之沈積系統的操作方法,其中該 NND處理時間大於約150秒且小於約250秒。 50.如申請專利範圍第48項之沈積系統的操作方法,其中該 沈積系統更包含耦合至該晶圓台之基板偏壓產生器,該方法更包 含: •在至少一部分該NND處理時間期間,調整該NND基板偏壓功 率至大於在一濺鍍閾值範圍中之第一值,其中該丽D基板偏壓功 率之範圍係自約500 W至約1500 W。 51·如申請專利範圍50項之沈積系統的操作方法,其中該基 板偏壓功率之範圍係自約750 W至約900 W。 52.如申請專利範圍第48項之沈積系統的操作方法,其中該 沈積系統更包含一歡材以及一乾材電源,該把材電源提供NND乾 • 材功率至該靶材,該沈積系統的操作方法更包含: 在至少一部分該NND處理時間期間,將NND靶材功率調整至 一數值,以達到該NND沈積速率,其中該NND靶材功率之範圍係 自約100 W至約1500 W。 53·如申請專利範圍第48項之沈積系統的操作方法,其中該 沈積系統更包含一耦合至該處理室壁之乾材,一揭合至該無材之 永久磁鐵組、以及一耦合至該靶材之沉電源,該沈積系統的操作 方法更包含: - 在至少一部分該NND處理時間期間,將NND靶材功率調整至 1283439 一數值,以達到該NND沈積速率, 自約100 W至約15〇〇 w。 其中該NND乾材功率之範圍係1283439 X. Patent application scope: 1. A method for operating a deposition system, comprising: placing a patterned substrate on a wafer table in a processing chamber, and establishing a high-density plasma in the processing chamber, a material in the bean, and a material The ions and a large amount of process gas ions, krypton, and electro-hydraulic water are coated to expose the patterned substrate to the high-density electrode. The power substrate biases the over-rate and deposition rate contained in the field region of the patterned substrate. And depositing material into the features of the patterned substrate, while the solid opening creates an overhang material. And the operation method of the deposition system of the first aspect of the feature patent scope, wherein the 355, the pre-treatment time, the LND treatment time, or the (10) post-processing time, the ί2H, the (10) pre-processing time, The 0 second change to about 50 seconds; the LND = the change from about 10 seconds to about 5 seconds; and the LND post-processing time varies from about to 5000 seconds. Nmi. The method of operation of the deposition system of claim 2, wherein the LND treatment time is greater than about 150 seconds and less than about 250 seconds. The working method of the deposition system of claim 2, wherein the deposition sequence further comprises a substrate bias generator coupled to the wafer stage, the method further comprising: at least a portion of the LND During the processing time, the LND substrate biasing power f is adjusted to be less than a first value in the -sputter threshold range, wherein the LND substrate bias power ranges from about 0 W to about 200 W. 2 / 5. The operation method of the deposition system according to item 2 of the Shen/Qing patent scope, wherein the deposition system further comprises a target, and the power source for supplying the LND target power to the target, the 1283439 square includes : adjusting the LNI) material power to achieve the LND deposition rate during at least a portion of the lnd processing time, wherein the ultra low deposition rate is less than about 3 Å/min, and the LND target power ranges from about 1 〇w to about 2000 w. 6. The method of operation of the deposition system of claim 2, wherein the deposition system further comprises a pressure control system coupled to the processing chamber, the method further comprising: establishing during at least a portion of the LND processing time An LND process chamber pressure, wherein the LND process chamber pressure system is less than about 130 mTorr and greater than about 1 mTorr. 7. The method of operating a deposition system of claim 2, wherein the deposition system further comprises an antenna, a dielectric window lightly coupled to the antenna and the processing chamber wall, and an activity coupled to the dielectric window a deposition baffle, and an ICP source coupled to the antenna, the method of operating the deposition system further comprising: operating the ICP source at a first frequency; and adjusting the ICP source to provide a period during at least a portion of the LND processing time LND ICP power level. 8. The method of operation of the deposition system of claim 7, wherein the LND ICP power level is greater than about 3000 W and less than about 6000 W. 9. The method of operation of the deposition system of claim 5, wherein the deposition system further comprises a target coupled to the processing chamber wall, a permanent magnet group coupled to the target, and a coupling to the target The DC power supply of the material, the operation method of the deposition system further comprises: setting a power output level of the DC power source to a first LND target power level during at least a portion of the LND processing time, wherein the first LND target The power level is greater than about 1000 W and less than about 3000 W. 1) The method of operation of the deposition system of claim 2, wherein the 34 1283439 NND field deposition rate ranges from about -10 nm/min to about +1 〇 nm/min. The method of operation of the deposition system of claim 15 wherein the field deposition rate ranges from about -5 nm/min to about +5 nm/min. The method of operation of the deposition system of claim 14, wherein the bottom surface deposition rate ranges from about -10 nm/min to about +1 〇 nm/min. 2. The method of operation of the deposition system of claim 17, wherein the &amp; surface deposition rate ranges from about -5 nm/min to about +5 nm/min. The method of operation of the deposition system of claim 14, wherein the method comprises a ray D pre-processing time, an NND processing time, or an NND post-processing time, m ^^0 50 #; Seconds i = _ seconds; and the operation method of the deposition system of the 19th item of the _ post-processing person, Shen Qing patent scope, - spoon 3 · during the part of the D D processing time, the handle value is more The 反 伯 反 reverse bias power of 匕 greater than the second sputtering threshold is adjusted to about 500 W to about 1500 watts. The range of the bias power of the middle wire plate is determined from the operation method of the deposition system of the second item, and the range of the power of the substrate is from about 750 W to about _W. Go to the package 23 · The method of operation of the deposition system of claim 19, 36 1283439 1 salary, at least - part of the blue D processing time, the nnd target power is adjusted to a value, where the D target The power range is from about 100 W to about 15 〇〇w. Person: = · The application method of the deposition system of claim 19, more π, less - part of the NND processing time, adjust the ICP source to provide a 5 steal power level, wherein the D DC The power level ranges from approximately 2 _ W main to approximately 10,000 W. _ 1 * Patent application 胄 24 J member's deposition system operation method, wherein the U iCP power level ranges from about 3000 W to about 6000 W. 26. The method of operation of the deposition system of claim 19, further comprising: • establishing an NND process chamber pressure during at least a portion of the NND processing time, wherein the NND process chamber pressure is less than about 〇3〇mT〇rr and Greater than about 丨mT〇rr. • 27. The method of operation of the deposition system of claim 19, further comprising: flowing a second process gas into the process chamber during at least a portion of the process time of the D process, wherein the second process gas comprises an inert gas , a nitrogen-containing gas, an oxygen-containing gas, or a metal-containing gas or a combination thereof. 28. The method of operation of a deposition system of claim 27, wherein the inert gas comprises argon, helium, neon, xenon, or gas, or a combination thereof. 29. The method of operating a deposition system according to claim 27, wherein the metal-containing gas comprises tungsten (W), copper (cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), iridium (Ir) ), aluminum (A1), silver (Ag) or platinum (pt) or a combination thereof. 30. The method of operating a deposition system according to claim 14, wherein the NND process is for depositing a seed layer. 37 1283439 31. The method of operation of a deposition system according to claim 14, wherein the 兮NND process is used to repair the seed layer. ^ &amp; 32. The method of operation of the deposition system of claim 14, wherein the 兮NND process is used to repair the barrier layer. The method of operation of the deposition system of claim 14, wherein the NND process is used to deposit a barrier layer. The operation method of the deposition system of claim 14, wherein the NND process is used to establish a punch through in at least one of the features of the patterned substrate. ^, 35 · Apply The method of operation of the deposition system of the scope of the third aspect of the invention, the deposition system comprising an ionized physical vapor deposition (ipVD) processing chamber. 36 36. The method of operation of the deposition system according to the scope of the patent application, the deposition system comprises a The transmission system / / μ H application method of the deposition system of the scope of the patent range, including: The entire plant power and base flat pressure power is adjusted and established in the field of the substrate The second (10) deposition rate; the characteristic === the characteristic portion of the round substrate; and the operation method of the deposition system of the first aspect of the patent scope is substantially not included, and the method further comprises: disposing the substrate in the second processing chamber On the second wafer stage, the second LND process is performed, and the second LND process is performed, and the cage is buckled, and the Xuan β junction is in the area of the substrate, and the additional material is deposited to the characteristic portion of the substrate. Produce the suspension material. The towel is only inferior in quality, and the operation method of the deposition system of the 14th item of the application, including the whole, D t 'where the power of the material and the substrate _ power are adjusted, the surface sinks Zero product=and the field area of the substrate on the surface of the substrate. The operation method of the deposition system according to claim 14 of the patent application, the package substrate is set in the first The second wafer stage in the processing chamber; the middle and middle application! ^ two NND processes, wherein the m power and the substrate dust power are adjusted by the second bile deposition rate, and the field is in the field of the patterned substrate D deposition rate is about zero; and processing the substrate, thereby depositing material on the patterned substrate. The rigid wall or the bottom surface of the feature of the B-form substrate or a combination thereof. The method for operating a deposition system of claim 1, further comprising: disposing the patterned substrate on a wafer stage in an additional processing chamber; and performing an additional process. 42. The deposition system of claim 14 Operation method, including: The patterned substrate is disposed on the wafer stage in the additional processing chamber; and an additional process is performed. 39 1283439 43. A method of operating a deposition system, comprising: placing a patterned substrate on a wafer stage in a processing chamber; The high brittleness of the high bribe, the substrate is exposed to the high density electropolymerization; the power or the target: the force rate or _ bias includes the NND field deposition rate, the coffee side S$_D deposition rate or Combining; and /U accumulation rate, or surface D bottom deposition rate, using the NND process to _ patterned substrate substrate, the material is deposited on the substrate, wherein the substrate is The bottom surface of the feature portion or a combination thereof, the gas chemistry, the temperature of the processing chamber, the temperature of the substrate, the power of the substrate, the power of the ceramic, or the value of the cup, the body hunger, the material of the material, the power of the ICP, the bias voltage of the substrate, or a combination thereof It has been adjusted. 44. For example, the method of applying the deposition method of the deposition method of the NND field deposition rate, wherein the enthalpy is from about -10 nm/min to about +1 〇 nm/min. NND field deposition rate ^ The operation method of the deposition system of item 44, wherein the ceremonial system is from about -5 nm/min to about +5 nm/min. The operation method of the deposition system of Item 43 of the bottom surface of the NND, wherein the motor has been enclosed from about 10 nm/min to about +1 〇 nm/min. The operation method of the deposition system of Item 46 of the bottom surface of the NND, wherein the light 4 is from about -5 nm/min to about +5 nm/min. 48. If the patent application 々々 NND process includes a method of depositing a deposit of 43 deposits, including the 1J% rational time, the NND processing time, or the NND post-processing time, 1283439 or a combination thereof, wherein The NND pretreatment time varies from about 0 seconds to about 50 seconds; the NND processing time varies from about 1 second to about 500 seconds; and the NND post processing time varies from about leap seconds to about 5000 seconds. 49. The method of operation of the deposition system of claim 48, wherein the NND treatment time is greater than about 150 seconds and less than about 250 seconds. 50. The method of operation of a deposition system of claim 48, wherein the deposition system further comprises a substrate bias generator coupled to the wafer stage, the method further comprising: • during at least a portion of the NND processing time, The NND substrate bias power is adjusted to be greater than a first value in a range of sputtering thresholds, wherein the radix D substrate bias power ranges from about 500 W to about 1500 W. 51. The method of operation of a deposition system of claim 50, wherein the substrate bias power ranges from about 750 W to about 900 W. 52. The method of operation of a deposition system according to claim 48, wherein the deposition system further comprises a ceramic material and a dry material power supply, the material power of the material providing NND dry material power to the target, operation of the deposition system The method further includes: adjusting the NND target power to a value to achieve the NND deposition rate during at least a portion of the NND processing time, wherein the NND target power ranges from about 100 W to about 1500 W. 53. The method of operating a deposition system of claim 48, wherein the deposition system further comprises a dry material coupled to the processing chamber wall, a bonded permanent magnet set, and a coupled to the The sinking power supply of the target, the method of operation of the deposition system further comprises: - adjusting the power of the NND target to a value of 1283439 during at least a portion of the NND processing time to achieve the NND deposition rate, from about 100 W to about 15 〇〇w. Where the range of the NND dry material power is 於約100 mTorr且大於約1 mT〇rr。 ㈣申請專利範圍第48項之沈積系統的操作方法,其中該 :、糸、、先更包含一天線、一耦合至該天線以及該處理室壁之介電 向、-輕合至該介電窗之活動沈積擔板、以及合至該天線之 ICP RF源’該沈積系統的操作方法更包含: 在第一頻率下操作該ICP RF源;以及 调整該ICP RF源,以於至少一部分該腦處理時間期間提供 一 _) ICP功率位準。 56·如申請專利範圍第55項之沈積系統的操作方法,其中該 NND Icp功率位準係大於約1000 W且小於約10000 W。 57·如申請專利範圍第56項之沈積系統的操作方法,其中該 NND ICP功率位準之範圍係自約3〇〇〇 w至約6〇〇〇 w。 、^8·如申請專利範圍第48項之沈積系統的操作方法,其中該 沈積系統更包含一耦合至該處理室之氣體供應系統,該沈積系統 的操作方法更包含: 二在至少一部分該NND處理時間期間,令一第一處理氣體流入 ,,理室中,其中該第一處理氣體包含惰性氣體、含氮氣體、含 氧氣體、或含金屬氣體或其組合。 42 1283439 59·如申請專利範圍第58項之沈積系統的操作方法,复 惰性氣體包含氬、氦、氪、氡、或氙、或其組合。 ,、中該 60·如申請專利範圍第58項之沈積系統的操作方法,复 含金屬氣體包含鎢(W)、銅(cu)、钽(Ta)、鈦(Ti)、铷(p或 銀(Ir)、鋁(A1)、銀(Ag)或鉑(Pt)或其組合。、KU)、 6L如申請專利範圍第43項之沈積系統的操作 NND製程係用以沈積阻障層。 /、中該 62·如申請專利範圍第43項之沈積系統 NND製程係用以修復阻障層。 干F乃沄其中該 63·如申請專利範圍第43項之沈積系統的操 麵製程係用以在該圖案化基板之至少一該特徵部來建立穿透2亥 二^申請專利範圍第43項之沈積系統的操作方法 將該製程自麵製程改變至低淨沈積(LND)製程 ^. =速率自_沈積逮率改變至沈積速 &lt; =該 ” _場沈積速率、L_壁沈積速率、或tNDl 率 或其組合,該LM)場沈積速率包含二二1=底面沈積速率、 超低沈積速率, ·以及、 μ圖案化基板之場區域中之 之特徵部底面或其組合i 1 _化基, 懸材料,其中處理室動、處jd部開:處不致產生突 學性質、處理氣體流速、mm板=、處理n 率、基板偏-功率或其組合係十二3功率、基板位置、輕材^ 〜^過凋整,以將該製程自該NND製 43 1283439 程改變至該LND製程。 nmi5·如申請專利範圍第64項之沈積系統的操作方法,其中該 琢’尤積速率之範圍係自約0 nm/min至約+50 nm/min。 τ Nm i6.如申請專利範圍第65項之沈積系統的操作方法,其中該 琢沈積速率之範圍係自約〇 nm/min至約+3〇 。 ^如申請專利範圍第64項之沈積系統的操作方法,其中該 底面沈積速率之範圍係自約-1G rnn/min至約 ϊ NT) 月專利範圍第67項之沈積系統的操作方法,其中該 -積速率之範圍係自約-5 nm/min至約+5 nm/min。 ί9程d專64項之沈積系統的操作方法,其中該 i盆tt Λ處1時間、LND處理時間、或⑽後處理時間、 '、中遠前處理時間自約0變化至、約50秒;該LND 至約500秒;且嶋後處理時間自約〇 二如 含上=:=:¾積=,方法,更包 整至在小於-舰間值範圍中之第 、ND基板偏壓功率調 功率之範圍係自約0 W至約1〇〇〇 w。 〃中該LND基板偏壓 其中該 72·如中請專利細第71項之沈 44 1283439 80·如申請專利範圍第78項之沈積系統的操作方法,其中該 含金屬氣體包含嫣(W)、鋼(⑸)、组(Ta)、鈇(Ti)、|ft〇 (ru)、 銥(Ir)、鋁(A1)、銀(Ag)或鉑(Pt)或其組合。 、 81·如申請專利範圍第64項之沈積系統的操作方法,其 LND製程係用以沈積種晶層。 一 μ 82·如申請專利範圍第64項之沈積系統的操作方法,其 LND製程係用以修復種晶層。 ” w 83·如申請專利範圍第65項之沈積系統的操作方法,中兮 LND製程係用以修復阻障層。 〃 μ 84·如申請專利範圍第43項之沈積系統的操作方法,其中該 沈積系統包含一離子化物理蒸氣沈積(ipVD)處理室。、〜 85·如申請專利範圍第43項之沈積系統的操作方法,其 沈積系統包含一傳輸系統。 μ 鲁 ,申請專利範圍第64項之沈積系統的操作方法,更包含·· 施行第二LND製程,其中靶材功率及基板偏壓功率係經過 、以期在该圖案化基板之該場區域中建立第二LND沈積速率; 以及 ’ 將附加材料沈積至該圖案化基板之特徵部,而實質上不致 特徵部開口產生突懸材料。 个欵在 • 8^如申請專利範圍第64項之沈積系統的操作方法,更包含: ,該圖案化基板設置於第二處理室内之第二晶圓台上; 靶行第二LND製程,其中第二靶材功率及第二基板偏壓功率 46 1283439 ϊϊί,及以期在該圖案化基板之該場區域中建立第二⑽沈 特徵案化基板之特徵部,而實質上不致在 申請專利範圍第43項之沈積系統的操作方法,更包含: tM丁第一 _製程’其中鞋材功率 整,以期建立第二NND沈積速率,而在哕羊,過凋 中,該_沈積速率約為零;以及μ圖案化基板之该場區域 特徵======化基板之 4:=¾之統 係經 該場區域巾,該_沈積速率約為零;以及“_化基板之 處理該圖案化基板,藉此_加材料 特徵部側錢_案化基板之贿部底案化基板之 範f43項之沈積系統的操作方法,更包含: 設置於附加處理室内之晶圓台上; 64項之沈積系統的操作方法,更包含: 設置於附加處理室内之晶圓台上; 圖 92. -種半導體基板之處理方法,其藉由將材料沈積至該At about 100 mTorr and greater than about 1 mT 〇rr. (4) The method for operating a deposition system of claim 48, wherein: 糸, 、, first includes an antenna, a dielectric direction coupled to the antenna and the processing chamber wall, and lightly coupled to the dielectric window The active deposition plate, and the ICP RF source coupled to the antenna, the method of operating the deposition system further comprises: operating the ICP RF source at a first frequency; and adjusting the ICP RF source to at least a portion of the brain treatment A _) ICP power level is provided during the time period. 56. The method of operating a deposition system of claim 55, wherein the NND Icp power level is greater than about 1000 W and less than about 10,000 W. 57. The method of operation of a deposition system of claim 56, wherein the NND ICP power level ranges from about 3 〇〇〇 w to about 6 〇〇〇 w. The method of operation of the deposition system of claim 48, wherein the deposition system further comprises a gas supply system coupled to the processing chamber, the method of operation of the deposition system further comprising: at least a portion of the NND During the processing time, a first process gas is flowed into the chamber, wherein the first process gas comprises an inert gas, a nitrogen-containing gas, an oxygen-containing gas, or a metal-containing gas, or a combination thereof. 42 1283439 59. The method of operation of the deposition system of claim 58 wherein the inert gas comprises argon, helium, neon, xenon, or krypton, or a combination thereof. 60. The method of operation of a deposition system according to claim 58 of the patent application, the metal-containing gas comprising tungsten (W), copper (cu), tantalum (Ta), titanium (Ti), tantalum (p or silver) (Ir), aluminum (A1), silver (Ag) or platinum (Pt) or a combination thereof, KU), 6L The operation NND process of the deposition system of claim 43 is for depositing a barrier layer. /, Zhongzhi 62. The deposition system of the 43rd patent application scope NND process is used to repair the barrier layer. The operation process of the deposition system of the 63th application of the invention is to use at least one of the features of the patterned substrate to establish a penetration of the patent application scope 43 The operation method of the deposition system changes the process from the surface process to the low net deposition (LND) process ^. = rate changes from the deposition rate to the deposition rate &lt; = the "field deposition rate, the L_wall deposition rate, Or the tNDl rate or a combination thereof, the LM) field deposition rate comprises 22 = 1 = bottom deposition rate, ultra low deposition rate, and /, the bottom surface of the feature in the field region of the patterned substrate or a combination thereof i 1 - Base, suspended material, in which the chamber is moved, where the jd portion is opened: no spoke property, processing gas flow rate, mm plate =, processing n rate, substrate bias-power or combination thereof 12 3 power, substrate position, The light material ^~^ is over-processed to change the process from the NND system to the LND process. nmi5· The method of operation of the deposition system of claim 64, wherein the 琢' Range from about 0 nm/min to about +50 nm/min τ Nm i6. The method of operation of the deposition system of claim 65, wherein the bismuth deposition rate ranges from about 〇nm/min to about +3 〇. ^Deposition system as claimed in claim 64 The method of operation, wherein the rate of deposition of the bottom surface ranges from about -1 G rnn/min to about ϊ NT). The method of operation of the deposition system of claim 67, wherein the rate of the deposition is from about -5 nm /min to about +5 nm/min. ί9 d-specific 64-item deposition system operation method, wherein the i-pot tt Λ 1 time, LND processing time, or (10) post-processing time, ', COSCO pre-treatment time from A change from about 0 to about 50 seconds; the LND is about 500 seconds; and the post-processing time is from about :2, including ===:3⁄4 product=, the method is more rounded to less than - the value of the ship value The range of the ND substrate bias power adjustment power is from about 0 W to about 1 〇〇〇 w. The LND substrate is biased in the middle, and the 72 is as disclosed in the patent item 71. The method for operating a deposition system according to claim 78, wherein the metal-containing gas comprises bismuth (W), steel ((5)), group (Ta), bismuth (Ti), |ft〇(ru), iridium (Ir), aluminum (A1), silver (Ag) or platinum (Pt) or a combination thereof. The operation method of the deposition system of the 64th item, the LND process is used for depositing the seed layer. The operation method of the deposition system of the 64th application of the patent application, the LND process is used for repairing the seed layer . w 83 · The method of operation of the deposition system of claim 65, the medium-sized LND process is used to repair the barrier layer. 〃 μ 84 · The operation method of the deposition system of claim 43 of the patent application, wherein The deposition system comprises an ionized physical vapor deposition (ipVD) processing chamber., 85. The method of operation of the deposition system according to claim 43 of the patent application, the deposition system comprising a transmission system. μ Lu, patent application scope item 64 The method of operating the deposition system further includes: performing a second LND process, wherein the target power and the substrate bias power pass through, in order to establish a second LND deposition rate in the field region of the patterned substrate; and The additional material is deposited onto the features of the patterned substrate without substantially causing the feature opening to create a protruding material. The method of operation of the deposition system of claim 64, further comprising: The substrate is disposed on the second wafer stage in the second processing chamber; the target row is a second LND process, wherein the second target power and the second substrate bias power 46 12834 39 ϊϊί, and in order to establish a feature of the second (10)-thickness-characterized substrate in the field region of the patterned substrate, and substantially not in the operation method of the deposition system of claim 43 of the patent application, further comprising: tM Ding first _ process 'where the shoe material is full, in order to establish a second NND deposition rate, and in the ram, over-dead, the _ deposition rate is about zero; and the field characteristics of the μ patterned substrate === === 4:=3⁄4 of the substrate is passed through the field area, the deposition rate is about zero; and "the substrate is processed by the patterned substrate, thereby _adding material features side money_ The method for operating the deposition system of the substrate of the bristle substrate of the substrate, further includes: the wafer table disposed in the additional processing chamber; the operation method of the deposition system of 64 items, further comprising: setting in the additional processing On the wafer table in the room; Figure 92. A method of processing a semiconductor substrate by depositing material to the
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI419280B (en) * 2009-01-16 2013-12-11 Univ Nat Taiwan Electronic device for preventing diffusion of metals

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