1283051 九、發明說明： 【發明所屬之技術領域】 本發明係一種堆疊構裝結構及其製造方法，尤指一種 系統化封裝構件中運用一中間基板作為堆疊構裝之中介 層，以提升立體堆疊構裝的銲接品質及產品可靠度試驗等 級0 【先前技術】 電子產品層次與功能提升的趨向可歸納為多功能、高 _ 速化、大容量化、高密度化、輕量化，為達成這些需求， 除積體電路製程技術進步的推動外，許多新的組合式結構 亦不斷被開發出來。而現今電子工程發展走向，係由傳統 的一個半導體元件的開發，進入到集結多個半導體元件組 成系統的開發階段，在此發展方向的引導下，便形成一個 包含邏輯元件、記憶體元件及被動元件的系統，整合於一 個單位之中的技術，即所謂系統化封裝（System in a Package, SiP ) o 一般而言，系統化封裝並無一定型態，就半導體晶片 ^ 排列方式可以是二維平面的擴展封裝，更可再進一步組合 ® 成三維立體的堆疊封裝。而不同的晶片排列方式與不同的 内部接合技術互相搭配之下，使系統化封裝型態產生多樣 化的組合，並可依實際之需要加以彈性生產。 - 請參閱第1圖，習知系統化構裝件之堆疊構裝製程。 在第1圖（a)中，首先提供一預先運用表面黏著技術封裝 而成的一第一封裝體pl〇，將該第一封裝體pl〇之複數個 銲球pl2朝上，再如第1圖（b)中所示，在該載板pl3上 塗佈助銲劑pll後，再如第1圖（c)中所示，另提供一 上、下表面各配置有複數個銲球p31，p32之基板p30，在 該基板p30表面塗上助銲劑p40後，以該些銲球p31對正 1283051 該第一封裝體pio之該些銲球pl2後作黏合，同時，以表 ' 面黏著技術封裝而成的第二封裝體p20以其該些銲球p21 對正該基板p30之該些銲球p32後黏合，再如第1圖（d) 所示，之後以迴銲、烘烤製程將該些銲球pl2與p31、 p32與p21做電性接合，再接著以一清除助銲劑製程，將 該些助銲劑pll、p40予以清除，以形成一疊堆式的系統 化封裝單位。 惟，上述製程中，如第1圖（b)、（c)所示，塗佈之 助銲劑pll、p40於該第一封裝體plO表面及該基板p30 表面時，因該助銲劑pll、p40為液態之特性，因其表面 籲 張力作用而形成弧狀表面，導致該些最外圍的銲球pl2、 p32之外側B處無法受液態的助銲劑pi 1、p40的潤溼， 而在後續迴銲接合製程後形成虛銲（cold join)的不良銲 接。而為使上述之外圍該些銲球pll受該助銲劑pll、 p40之潤溼，亦有將該助銲劑pll、p40之塗佈量增加， 但這又會造成過量的助銲劑pll、p40在接合第一封裝體 plO及第二封裝體p20後溢出，造成污染。 又，如第1圖（e)所示，在對正基板p30與第一封裝 體plO或第二封裝體p20與基板p30時，由於該些銲球 φ pl2、p31或p32、p21間之對位並未有可供作為基準之 結構，再加上該些銲球pl2、p31或p32、p21係為球 面，使中心點對中心點之掌握不易，導致無法確實對正而 互相交錯如第1圖（e)之A處。 再者，上述之習知技術中，堆疊結構之高度完全由該 些銲球pl2、p31或p32、p21所堆疊形成，該些銲球 pl2、p31或p32、p21於迴銲製程時所造成的熔融狀態 將改變其接合高度，且其所改變之高度不易控制，形成最 終封裝體之總高度無法預期之窘境。 且，如同上述之習知技術中，堆疊結構之高度完全由 !283〇5l ，些銲球Pl2、P31或P32、P21所堆聂报占道從 間之基板四周形成懸空狀態，因而造处位於 :ϊ择f而無法通過摔掉測試之可靠度試驗；另ί 心造接合硬化時應力上; 【發明内容】 能確目的除可精準控制銲接之助銲_量外，並 ;也可以堆疊各封裝體時有-對正機ΐ :; 來位站合，另可精準地控制整體封裝高度及避免產: 驗曲’更可增強整個封震製品之強度，提升可靠度; 構成ΐ述目的，本發明提供—具有中間基板之堆疊 :—具有载板、半導體晶片，及複數個銲 妒.va封衣體，一具有載板’半導體晶片之第二封裝 ί恭ί 介於該第一封裝體之該載板與該第二封裝體之 =之，的中間基板’且該中間基板設有一中空部 體之該些銲球位置之複數個穿孔，以提供堆 t明提供另-目的係提供—上述結構之製造方法， :,1、^" ^含步驟有：提供該第一封裝體，其具有一載板、 - 導體晶片及複數赠球。黏合該巾間基板於該第 一^衣體之該載板上，該中間基板設有一第一表面、一第 二=，:開口 ’且對應該第—封裝體之該些銲球位置設 ίϊ數孔，該些穿孔對正並套入該第-封裝體之該些 ϊί^ιΐ助銲劑於該中間基板之該些穿孔内，以潤渔 Μ二鈈球。提供一第二封襞體，該第二封裝體配置至少一 1283051 半導體晶片及複數個銲球，該半導體晶片 基板之開口内，且該第二封裝體以該球置於該中間 基板之該些穿孔後，堆疊配置於該第二封2正於該中間 銲及，烤製程以電性接合該第一封褒體與J體進行迴 飼本發明功效為： 一封衣體。 1·改善習知技術在塗佈助銲劑難以準 產生銲接接點虛銲的問題，本發明利用 =|用量導致 定好的容置第一封裝體及第二封裝體 j基板之預先設 液恶的助銲劑，並可充分潤溼容置於j：二二，牙孔來盛裝 高品質的銲接接點。 ’、θ各銲球，保持 2·改善習知技術之各個封裝體對正自 的問題，本發明利用中間基板之預先 ^產生歪斜 第-封裝體及第二封裝體之銲球，、使二2穿孔來容置 =封裝體的定位功能’確保每個堆“以=2 ii個封裝體間形成實趙的強化層 二 本發體高度不易控制的缺失， 際高度，擺脫封裳產品的實 易掌握的缺點。 一、干表鋅接之咼度在迴銲製程後不 【實施方式】 表Ξίίΐ式ίί發明較佳實施例詳細說明如下。 構。复中勺括圖it15明之具有中間基板之堆疊構裝結 接合於其S之中；裝體10、-第二封裝體20以及- 1283051 該第一封裝體10具有一載板π供至少一半導體晶片12 ' 承載於其表面，而在該載板11的另一表面上則配置有複數 、 個銲球13，並以一封膠體14將該半導體晶片12予以密封。 當然，在此載板11的表面除配置其半導體晶片12之外，亦 可再配置其他的半導體元件，如配置有至少一被動元件 等。 該第二封裝體20同樣具有一載板21，以供至少一半導 體晶片22承載於其表面上，而該載板11另一表面則配置有 複數個銲球23，並以一封膠體24將該半導體晶片12密封。 m 該中間基板30係一介於該第一封裝體10的該載板11與 • 該第二封裝體20的該載板21之間，該中間基板30可使用如 FR-4樹酯（FR-4 Epoxy )或BT樹酯（Bismaleimide Triazine，三氮雜苯雙馬來醯亞胺）材料。又，該中間基 板30對應該第二封裝體2〇的該半導體晶片22位置，配合開 設有一中空部31，以避開堆疊該第二封裝體20時，該半導 體晶片22的位置，形成一容置空間。另外在該中間基板3〇 的對應該第一封裝體之該些銲球位置設有對應之複數個穿 孔32。 續請參閱第3圖之製造流程示意圖。根據上述結構之 Φ 製造方法至少包含下列步驟： 如第3圖（a)所示，提供一第一封裝體1〇，該第一封 裝體10具有一載板11、至少一半導體晶片12及複數個銲球 13 (步驟S10)，本步驟中更可在該半導體晶片12上再以 一封膠體14密封之，以形成更佳之保護。此步驟中，载板 11的表面除配置其半導體晶片12之外，亦可同樣利用表面 黏著技術再配置除半導體晶片12之外的半導體元件，如配 置有至少一被動元件等。 如第3圖（b)所示，在該中間基板30之第一表面33塗 佈一黏著膠35以黏合該中間基板30於該第一封裝體1〇之^ 1283051 .. 載板11上，該中間基板10設有一第一表面33、一第二表面 34與一開口，且對應該第一封裝體10之該些銲球13位置設 有複數個穿孔32，利用該些穿孔32自然形成的對位功能， 予以對正並套入該第一封裝體1〇之該些銲球13 (步驟 S20 )，上述該黏著膠35可使用UV黏膠351(uli：ravi〇let紫 外光黏膠）或熱塑性黏膠352，以運用照射紫外光或加熱 的方式來進行黏貼。 如第3圖(c)所示，塗佈一助銲劑40於該中間基板30 之該些穿孔32内，以潤溼該些銲球13 (步驟S30 )，談助 銲劑40可流入該些穿孔32中，並充滿該些穿孔32形成若干 攀 助銲劑40池，如此，除可提供位於該些銲球13之潤溼之 外，同時可供後續套入之該第二封裝體2〇之該些銲球23的 >父泡潤渔之用，另在該中間基板30之第二表面34塗佈一黏 著膠35以利後續之黏合該中間基板30與該第二封裝體2〇。 如第3圖（d)所示，提供一第二封裝體2〇，該第二封 裝體20配置至少一半導體晶片22及複數個銲球23，更可在 該半導體晶片22上再以一封膠體24密封之，以形成更佳之 保護，該半導體晶片22係容置於該中間基板3〇之中空部& 内，且該弟一封裝體20以該些鲜球23對正於該中間基板3〇 φ 之該些穿孔犯後，堆豐配置於該第一封裝體1〇之上（步驟 S40 )，使該些銲球13、23互相對正黏合。 如第3圖（e)及第3圖（f)所示，進行迴銲及烘烤萝 程以電性接合該第一封裝體10與第二封裝體2〇之該^ ^ 13、23 (步驟 S50 )。 一 嗣由上述之製造方法可利用該中間基板3〇之預先設定 好的該些穿孔32來盛裝液態的助銲劑4〇，並可充分潤^容 置於其間之各銲球13, 23，保持高品質的銲接接點，· 該中間基板30之預先設定好的該些穿孔32來容置第一封牡 體10及第二封裝體20之該些銲球13,23的諸穿孔犯，使^ 1283051 _形成一對正各個堆疊的封裝體的功能，確保每個堆聂 裝體的正確位置；利用該中間基板3〇與各個封裝體ς载板 11，21互相黏合，在各個封裝體間形成實體的強化層， 止翹曲變形的發生；以及利用該申間基板30的實體^产 控制堆疊封裝產品的實際高度，以改善習知技術在塗佈助 銲劑用量難以準確控制導致產生銲接接點虛銲的問題、各 個封裝體對正不良而易產生歪斜的問題、堆疊封裝體產品 四周易產生翹曲的缺失以及堆疊的封裝體產品高度不易控 制的問題。 續請參照第4圖所示，上述該中間基板3〇之該些穿孔 32的截面形狀，除可為柱狀如第4圖（a)之外，亦可為錐 型如第4圖（b) ’以形成一引導面，使該第二封裝體2〇之 該銲球23易於置^ ’甚或使該些穿孔32截面形成沙漏狀， 如第4圖（c)所示，以利上、下之該些銲球23,13的對位 並引導其容置。再者’上述之該些穿孔32孔壁上可更進一 步地鍍一金屬廣’以提高容置於其中之該些銲球23，13的 電性傳導效能。“ 綜上所述，當知本發明之堆疊構裝製程已具有產業 性、新穎性與進步性，符合發明專利要件。惟以上所述 者，僅為本發明之一較佳實施例而已，並非用來限定本發 明實施之範圍。即凡依本發明申請專利範圍所做的均等變 化與修飾，皆為本發明專利範圍所涵蓋。 11 1283051 【圖式簡單說明】1283051 IX. Description of the Invention: [Technical Field] The present invention relates to a stacked structure and a manufacturing method thereof, and more particularly to a systemized package member using an intermediate substrate as an interposer for stacking to enhance three-dimensional stacking Welding quality and product reliability test level 0 [Previous technology] The trend of electronic product hierarchy and function improvement can be summarized as multi-functional, high-speed, high-capacity, high-density, and lightweight. In addition to the advancement of integrated circuit process technology, many new modular structures have been continuously developed. Nowadays, the development trend of electronic engineering is from the development of a traditional semiconductor component, to the development stage of assembling a system of multiple semiconductor components. Under the guidance of this development direction, a logic component, a memory component and a passive component are formed. The system of components, the technology integrated in one unit, the so-called System in a Package (SiP) o In general, the systemized package does not have a certain type, and the semiconductor wafer can be arranged in two dimensions. The planar expansion package can be further combined into a three-dimensional stacked package. Different wafer arrangements and different internal bonding techniques are combined to create a diverse combination of systemized package types and can be flexibly produced according to actual needs. - Please refer to Figure 1, a conventional stacking process for systematic components. In Fig. 1(a), a first package pl〇 packaged by a surface adhesion technique is first provided, and the plurality of solder balls pl2 of the first package pl〇 are facing upward, and then the first As shown in (b), after the flux p11 is applied to the carrier pl3, as shown in FIG. 1(c), a plurality of solder balls p31, p32 are disposed on each of the upper and lower surfaces. The substrate p30 is coated with the flux p40 on the surface of the substrate p30, and the solder balls p1 are aligned with the solder balls p31 to bond the solder balls pl2 of the first package pio, and are packaged by the surface adhesion technology. The second package p20 is bonded to the solder balls p32 of the substrate p30 by the solder balls p21, and then as shown in FIG. 1(d), and then the soldering and baking process is performed. The solder balls pl2 and p31, p32 and p21 are electrically joined, and then the fluxes pll and p40 are removed by a flux removal process to form a stacked systemized package unit. However, in the above process, as shown in FIGS. 1(b) and (c), when the applied fluxes p11 and p40 are on the surface of the first package plO and the surface of the substrate p30, the fluxes p11 and p40 are used. It is a liquid property, and the surface of the outer surface of the solder balls pl2 and p32 cannot be wetted by the liquid fluxes pi 1 and p40 due to the surface tension. A poor soldering of a cold join is formed after the welding process. In order to wet the solder balls p11 and p40 in the periphery, the amount of the fluxes p11 and p40 is increased, but this causes excessive fluxes p11 and p40. After the first package plO and the second package p20 are joined, they overflow and cause contamination. Further, as shown in FIG. 1(e), when the alignment substrate p30 and the first package p10 or the second package p20 and the substrate p30 are aligned, the pair of solder balls φ pl2, p31 or p32 and p21 are The position does not have a structure that can be used as a reference. In addition, the solder balls pl2, p31, or p32, and p21 are spherical, so that the center point is difficult to grasp the center point, and the alignment is not correct. At point A of Figure (e). Furthermore, in the above-mentioned prior art, the height of the stacked structure is completely formed by stacking the solder balls pl2, p31 or p32, p21, and the solder balls pl2, p31 or p32, p21 are caused by the reflow process. The molten state will change its joint height, and its altered height is not easily controlled, forming an unpredictable dilemma in the overall height of the final package. Moreover, as in the above-mentioned prior art, the height of the stacked structure is completely from !283〇5l, and some of the solder balls Pl2, P31 or P32, P21 are stacked to form a suspended state from the periphery of the substrate, and thus the location is located. : The choice of f can not pass the test of the reliability of the test; the other is the stress on the joint hardening; [Summary of the invention] In addition to the precision of the welding can be precisely controlled, and can also be stacked When there is a package, there is a - aligning machine: : The position is integrated, and the overall package height can be accurately controlled and the production can be avoided: The test can enhance the strength of the entire sealed product and improve the reliability; The present invention provides a stack having an intermediate substrate: a carrier substrate, a semiconductor wafer, and a plurality of solder fillet va seal bodies, and a second package having a carrier substrate 'semiconductor wafer ί 介于 介于The intermediate substrate of the carrier plate and the second package body, and the intermediate substrate is provided with a plurality of perforations of the solder ball positions of the hollow portion to provide a stack. Manufacturing method of the above structure, :, 1, ^" The method includes the steps of: providing the first package, which has a carrier, a conductor wafer, and a plurality of balls. Bonding the inter-sheet substrate to the carrier of the first body, the intermediate substrate is provided with a first surface, a second surface, an opening, and corresponding to the solder ball positions of the first package And the plurality of holes are aligned and inserted into the perforations of the intermediate substrate of the first package to lubricate the ball. Providing a second package body, the second package body is configured with at least one 1283051 semiconductor wafer and a plurality of solder balls, the openings of the semiconductor package substrate, and the second package body is disposed on the intermediate substrate by the ball After the perforation, the stacking is disposed in the second seal 2 in the middle welding, and the baking process electrically joins the first sealing body and the J body for feeding back. The effect of the invention is: a clothing body. 1·Improving the problem that the soldering agent is difficult to produce solder joints in the solder joint, and the present invention utilizes the use of the =| the amount of the pre-set liquid of the first package and the second package j. Flux, and fully wetted to accommodate j: 22, the hole to hold high quality solder joints. ', θ each solder ball, hold 2 · improve the problem of the self-contained package of the conventional technology, the present invention utilizes the intermediate substrate to pre-produce the solder ball of the skewed first package and the second package, and 2 perforation to accommodate = the positioning function of the package 'ensure each pile' to form a solid layer of the reinforced layer between the = 2 ii package, the height of the hair is not easy to control, the height, get rid of the product Disadvantages that are easy to grasp. 1. The dryness of the zinc in the dry table is not after the reflow process. [Embodiment] The preferred embodiment of the invention is described in detail below. The structure is shown in Fig. 15 and has an intermediate substrate. The stacked package is bonded to the S; the package 10, the second package 20, and the -1283051 the first package 10 has a carrier π for carrying at least one semiconductor wafer 12' on its surface, and On the other surface of the carrier 11, a plurality of solder balls 13 are disposed, and the semiconductor wafer 12 is sealed with a glue 14. Of course, the surface of the carrier 11 is disposed except for the semiconductor wafer 12 thereof. Other semiconductor components can be configured If at least one passive component is disposed, the second package 20 also has a carrier 21 for carrying at least one semiconductor wafer 22 on its surface, and the other surface of the carrier 11 is provided with a plurality of soldering. The ball 23 is sealed with a glue 24. The intermediate substrate 30 is interposed between the carrier 11 of the first package 10 and the carrier 21 of the second package 20. The intermediate substrate 30 may be made of a material such as FR-4 Epoxy or BT resin (Bismaleimide Triazine). Further, the intermediate substrate 30 corresponds to the second. The semiconductor wafer 22 of the package 2 is disposed with a hollow portion 31 to avoid the position of the semiconductor wafer 22 when the second package 20 is stacked to form an accommodating space. In addition, the intermediate substrate 3 〇 Corresponding to the plurality of perforations 32 corresponding to the solder ball positions of the first package. Please refer to the manufacturing flow diagram of Fig. 3. The Φ manufacturing method according to the above structure includes at least the following steps: a), providing a first package 1 The first package 10 has a carrier 11 , at least one semiconductor wafer 12 , and a plurality of solder balls 13 (step S10 ). In this step, the semiconductor wafer 12 is further sealed with a glue 14 to In this step, in addition to the semiconductor wafer 12 disposed on the surface of the carrier 11, the semiconductor components other than the semiconductor wafer 12 may be reconfigured by surface adhesion techniques, such as at least one passive component. As shown in FIG. 3(b), an adhesive 35 is applied on the first surface 33 of the intermediate substrate 30 to bond the intermediate substrate 30 to the first package 1 128 1281301 .. carrier 11 The intermediate substrate 10 is provided with a first surface 33, a second surface 34 and an opening, and a plurality of through holes 32 are formed at positions of the solder balls 13 corresponding to the first package 10, and the through holes 32 are naturally formed. The alignment function is aligned and inserted into the solder balls 13 of the first package 1 (step S20), and the adhesive 35 can be used with UV adhesive 351 (uli: ravi〇let ultraviolet adhesive) ) or thermoplastic adhesive 352 to apply ultraviolet light or heat Way to paste. As shown in FIG. 3(c), a flux 40 is applied to the through holes 32 of the intermediate substrate 30 to wet the solder balls 13 (step S30), and the flux 40 can flow into the through holes 32. And filling the perforations 32 to form a plurality of pools of climbing flux 40, such that, in addition to providing wetting of the solder balls 13, the second package 2 can be subsequently inserted The adhesive ball 23 is coated with an adhesive 35 on the second surface 34 of the intermediate substrate 30 to facilitate subsequent bonding of the intermediate substrate 30 and the second package 2 . As shown in FIG. 3(d), a second package body 2 is provided. The second package body 20 is provided with at least one semiconductor wafer 22 and a plurality of solder balls 23, and further a semiconductor chip 22 is provided. The colloid 24 is sealed to provide better protection. The semiconductor wafer 22 is housed in the hollow portion of the intermediate substrate 3, and the package 20 is aligned with the fresh ball 23 to the intermediate substrate. After the punching of the 3〇φ, the stacking is disposed on the first package body 1 (step S40), and the solder balls 13, 23 are aligned to each other. As shown in FIG. 3(e) and FIG. 3(f), reflowing and baking are performed to electrically bond the first package 10 and the second package 2 to the ^^13, 23 ( Step S50). The above-mentioned manufacturing method can utilize the predetermined through holes 32 of the intermediate substrate 3 to hold the liquid flux 4 〇, and can fully fill the solder balls 13 and 23 placed therebetween. The high-quality solder joints, the pre-set holes 32 of the intermediate substrate 30 accommodate the perforations of the solder balls 13, 23 of the first block 10 and the second package 20, so that ^ 1283051 _The function of forming a pair of positively stacked packages ensures the correct position of each stack of horns; and the intermediate substrate 3 〇 and the respective package ς carriers 11, 21 are bonded to each other between the packages Forming a solid strengthening layer to prevent the occurrence of warping deformation; and controlling the actual height of the stacked package product by using the physical properties of the inter-substrate substrate 30 to improve the conventional technology, it is difficult to accurately control the amount of coating flux, resulting in solder joint The problem of spot soldering, the problem that each package is misaligned and prone to skew, the lack of warpage around the packaged product, and the difficulty in controlling the height of the stacked package products. Continuing to refer to FIG. 4, the cross-sectional shape of the through-holes 32 of the intermediate substrate 3 may be a columnar shape as shown in FIG. 4(a) or a tapered shape as shown in FIG. 4(b). 'To form a guiding surface, the solder ball 23 of the second package 2 is easily disposed, or even the cross section of the through holes 32 is formed into an hourglass shape, as shown in FIG. 4(c), for the purpose of The solder balls 23, 13 are aligned and guided to accommodate them. Further, the above-mentioned perforated 32-hole walls may be further plated with a metal to improve the electrical conductivity of the solder balls 23, 13 accommodated therein. In summary, it is known that the stacking process of the present invention is industrial, novel, and progressive, and meets the requirements of the invention patent. However, the above description is only a preferred embodiment of the present invention, and is not It is intended to limit the scope of the invention, that is, the equivalent changes and modifications made by the scope of the invention are covered by the scope of the invention. 11 1283051 [Simple description]
第1圖 第2圖 第3圖 第4圖 係第2圖之製造流程示意圖。 ^本發日狀中·板穿孔之實施 【主要元件符號說明】 [習知] pl〇第一封裝體Fig. 1 Fig. 2 Fig. 3 Fig. 4 is a schematic diagram of the manufacturing process of Fig. 2. ^Implementation of the shape of the plate and the perforation of the plate [Description of the main components] [Practical] pl〇 first package
Pll助銲劑 銲球 1)13载板 P20第二封裝體 P21銲球 P30基板Pll flux solder ball 1) 13 carrier plate P20 second package P21 solder ball P30 substrate
p3l銲球 P32銲球 P40助銲劑 [本發明] 10第一封裝體 11载板 12半導體晶片 13銲球 14封膠體 20第二封裝體 2ι載板 22半導體晶片 12 1283051 23銲球 〜 24封膠體 ' 30中間基板 31中空部 32穿孔 33第一表面 34第二表面 35黏著劑 351UV黏膠 352熱塑性黏膠 ® 40助銲劑 步驟S10提供一第一封裝體，該第一封裝體具有一 載板、至少一半導體晶片及複數個銲球。 步驟S20黏合一中間基板於該第一封裝體之該載板 上，該中間基板設有一第一表面、一第二 表面與一開口，且對應該第一封裝體之該 些銲球位置設有複數個穿孔，該些穿孔對 正並套入該第一封裝體之該些銲球。 步驟S30塗佈一助銲劑於該中間基板之該些穿孔 φ 内，以潤溼該些銲球。 步驟S40提供一第二封裝體，該第二封裝體配置至 少一半導體晶片及複數個銲球，該半導體 晶片係容置於該中間基板之開口内，且該 第二封裝體以該些銲球對正於該中間基板 之該些穿孔後，堆疊配置於該第一封裝體 上。 步驟S50進行迴銲及烘烤製程以電性接合該第一封 裝體與第二封裝體。 13P3l solder ball P32 solder ball P40 flux [Invention] 10 first package body 11 carrier board 12 semiconductor wafer 13 solder ball 14 sealant 20 second package body 2ι carrier plate 22 semiconductor wafer 12 1283051 23 solder ball ~ 24 sealant ' 30 intermediate substrate 31 hollow portion 32 perforation 33 first surface 34 second surface 35 adhesive 351 UV adhesive 352 thermoplastic adhesive ® 40 flux step S10 provides a first package, the first package has a carrier, At least one semiconductor wafer and a plurality of solder balls. In the step S20, an intermediate substrate is bonded to the carrier of the first package. The intermediate substrate is provided with a first surface, a second surface and an opening, and the solder balls corresponding to the first package are disposed. a plurality of perforations that are aligned and nested into the solder balls of the first package. Step S30 applies a flux to the through holes φ of the intermediate substrate to wet the solder balls. Step S40, a second package is disposed, the second package is configured with at least one semiconductor wafer and a plurality of solder balls, the semiconductor chip is disposed in the opening of the intermediate substrate, and the second package is formed by the solder balls After being aligned with the through holes of the intermediate substrate, the stack is disposed on the first package. Step S50 performs a reflow and baking process to electrically bond the first package and the second package. 13