TWI283014B - Barrier enhancement process for copper interconnects - Google Patents

Abstract

A damascene process for introducing copper into metallization layers in microelectronic structures includes a step of forming an enhancement layer of a metal alloy, such as a copper alloy or Co-W-P, over the barrier layer, using PVD, CVD or electrochemical deposition prior to electrochemically depositing copper metallization. The enhancement layer has a thickness from 10 Å to 100 Å and conformally covers the discontinuities, seams and grain boundary defects in the barrier layer. The enhancement layer provides a conductive surface onto which a metal layer, such as copper metallization, may be applied with electrochemical deposition. Alternatively, a seed layer may be deposited over the enhancement layer prior to copper metallization.

Description

1283014 V. INSTRUCTIONS (1) [Field of the Invention] The present invention relates to an electro-chemical treatment on an ultra-thin barrier layer, in particular, a method suitable for sinking and strengthening its barrier properties, Repairing the defect of the barrier layer and the seed layer of the subsequent copper key process: the film reinforcement layer can be used as the barrier layer [Background of the invention] The components of the open 4 需要 need to be connected by the inner wiring of the metal cloth pattern to For high-performance ultra-large integrated wafers, usually === belongs to the industry, and the reduction of component size will increase. 'The performance of the 'metal layer' pre-integrated circuit chip on the stacking chip Will be limited by the propagation delay of the signal in the connection, that is, the so-called "resistance" delay, in order to improve the speed of the circuit, reduce the Thunder of the relevant interconnect and it is important to block the two girls and Bao Guzhen . Recently, on integrated power, copper-metallization processes have been used to replace the metallization process because of the lower resistance and higher current carrying capacity of copper compared to aluminum. ^The manufacturing process required for copper to be a private product is different from the aluminum metallization process. The copper metal interconnect is usually made by using the inlay process instead of using a metal layer first when forming the aluminum interconnect. Then define the shape of the graphic. In the damascene process, the pattern of the wire is first etched onto the dielectric material, and the etched pattern is then filled with copper, and excess copper is removed by a chemical mechanical polishing step. In the integrated circuit chip, different metal layers are connected by window holes. If the pattern of the wires and the pattern of the window holes are respectively the paper size, the Chinese standard is used. The A4 specification (210X297 mm) (please read first) Note on the back and fill in the pages of this page. Binding 1283014 V. Invention Description (2) Filling and grinding, the graphics and window holes of this line are ^, , 'single inlay' process, if the guide is inlaid "Process. " Temple fill, this process is called, the dual-inlaid damascene process is ^ before the surface of the electric layer is deposited a 7-copper layer, first spread the well-distributed copper to the component area Required. The seed layer, the barrier layer is a preventive operation, usually with a thin resistance: when it is completely, it will destroy the typical barrier layer material of the broken component (4) or metal nitride as a barrier layer, phlegm. Sound β Α σ gas reduction, tungsten, tungsten nitride, niobium and nitrogen ♦ * (3) 疋 in order to provide the electrical conductivity of the electrochemical deposition reaction, while the 疋 疋 后续 后续 后续 后续 后续 后续 后续 后续 ; ; ; ; Depositing a layer of copper on the barrier layer as a seed layer The hard layer copper inlay process must have the most necessary chrome tanning and copper to fill the line. The line must be the ratio of the deposition ratio (n-person, small size, high-depth ice, divided by width) or Ditches and holes. One = 读 read (4) deposited copper is better than this process compared with physical vapor deposition or chemical vapor deposition (CVD): cover: 'due to electrochemical copper deposition process It is possible to deposit a relatively large amount of copper in the small trench, and the electrochemical copper deposition process is often referred to as J Xing. The physical vapor deposition technique includes various vapor deposition and sputtering techniques, such as DC or RF plasma sputtering. , bias sputtering, magnetron sputtering, ion plating or cesium ionized metal plasma sputtering. Physical vapor deposition processes are generally non-conservative deposits due to their non-, directional, and directional properties: Chemical vapor deposition technology includes thermal chemical vapor deposition, plasma enhanced chemical vapor phase precipitation I ^ 5 This paper scale applies to China National Standard (CNS) A4 specifications (21Gx297 public) installed--------- -------- (Please read the note on the back first Item: Fill in the columns of this page) Line! 1283014 V. Invention Description (product, low pressure chemical vapor deposition, high pressure chemical vapor deposition and metal organic chemical vapor deposition. Chemical vapor deposition process is most commonly used to make conformal Deposition, that is, the entire thickness of the deposition surface, including the upper portion of the field and the bottom and sides of the opening, has a uniform thickness. Currently, the barrier layer and the seed layer are mainly formed by a physical vapor deposition process, such as sputtering and Ionization sputtering, while the barrier layer and the seed layer are often deposited continuously in two different chambers of the crucible without breaking open to avoid surface contamination. The most critical element of this deposition process is in the etching pattern. Deposit <film thickness, especially at the sides and bottom of the etched lines or trenches and vias. Physical vapor deposition processes typically deposit thinner film layers over the entire flat field in the contact pattern of these dielectric materials, and step coverage has become a problem. The film must be continuous and defect-free. If there are holes or defects in the barrier layer, it will affect the integrity of the component. If there are holes or defects in the seed layer, it will cause holes in the copper film. Or defects are formed. In order to improve the step coverage ability, the chemical vapor deposition process has been used to deposit the barrier layer and the seed layer. However, the chemical vapor deposition process has not yet made a better result than the vapor phase deposition process, and its cost is more It is expensive. The copper seed layer deposited by the A phase "L product is usually poorly attached, the impurity amount is high, and the crystal orientation is poor. When copper is electrochemically deposited on the seed layer: there will be problems. produce. Sometimes the physical vapor deposition is carried out together with the chemical, which is deposited on the copper seed layer deposited by chemical vapor deposition to deposit a layer of copper deposited by physical vapor deposition, but this is only an increase. The cost of chemical vapor deposition. Therefore, the physical vapor deposition process comes to this paper scale suitable for the country (2H) X2697 public order

Install the line! (Please read the notes on the back and then fill out the palms on this page) -----Order------- 1283014 A7 B7 V. Description of the invention (The barrier layer and seed layer of the deposited copper wire are still A better choice, although it has the aforementioned step coverage problem. The improvement of physical vapor deposition technology is not enough to solve the film coverage problem encountered when physical vapor deposition deposits the barrier layer and the seed layer. Moreover, as the component size continues to decrease, the thickness of the barrier film layer on the side of the trench will be less than ten nanometers in the future, which will require a combination of various technologies to meet the more stringent requirements. 6,1, 3,707 discloses a method of combining a first copper seed layer and a second copper seed layer, wherein the first copper seed layer is formed by chemical vapor deposition, and the second copper seed layer is formed by physical vapor. A method of combining a first copper seed layer and a second copper matte layer, wherein the first copper seed layer is an alkaline layer, is disclosed in US Pat. No. 6,97,1,81. The electroplating solution is electrolytically deposited, and the second copper seed layer is also physically vaporized. Both methods require more process steps to obtain a copper η seed layer with good adhesion. How does the method disclosed in these patents solve the defect problem of the barrier layer? Or the problem of poor interface between the barrier layer and the copper seed layer. Therefore, the industry has been looking for a better electrochemical deposition method to deposit copper into high aspect ratio holes and trenches. [Overview of the present invention 】 = hair = contains - a method of applying metal to microelectronic workpieces. The surface of the electronic workpiece is covered with a wall structure. Generally, the above microelectronic workpiece is a semiconductor wafer, such as 夕 (cns) (please Read the precautions on the back and fill in the fields on this page. ---------Book--------Line! V. Invention Description (5) Interlayer holes or other semiconductor wafers. The metal is preferably copper to form a metal layer of the trench or void structure in the semiconductor wafer failure or dual damascene process. The method according to the invention comprises the steps of: (a) in the electronic workpiece gentry jrr rr / ι . 仟 $ surface forms a barrier layer, The middle layer also forms a barrier layer on the inner wall of the ruined wall structure; a reinforcing layer is formed on the barrier layer, wherein the alloy is formed by the alloy; and the f field structure is formed. (4) The electric money-metal is in the reinforcing layer Preferably, the reinforcing layer has a thickness of 1 (10) angstroms (A) or less, more preferably angstroms to 100 angstroms, and is formed by an electrochemical deposition process, such as two clocks. Or: plating process, in addition, the reinforcement layer can also be chemically synthesized: the vapor phase deposition process is formed. In the invention, the waste layer is synthesized by _ steel, such as copper-ming, dance j_magnesium and/or Or copper_zinc-' or 疋一& to a composition, such as lead-tungsten-phosphorus.

Even if the resistive P single layer has cracks, discontinuities, or grain boundary defects, A can be covered with a conformal layer; The pair of Jane Semiconductors Plus & layers may be titanium, titanium nitride or other conventional barrier materials. Q, the barrier has sufficient conductivity to allow a metal (preferably = strong layer. After that, too much metal will be removed from the surface of the field, except for, for example, chemical chemistry, invention (6) mechanical grinding The method still exists in the presence of a deposited metal within the microelectronic structure to the interconnect or metal layer. / In another embodiment, the process steps include: ft - (1 forming a barrier layer on the surface of the U-bump workpiece, #中中 Also includes a barrier layer formed on the inner wall of the faux-wall structure; (b) forming a reinforcing layer of a metal alloy on the barrier layer (Ο forming a seed layer on the reinforcing layer; and constructing (4) an electric clock - a metal over the reinforcement layer to fill the micro-embedded junction. In this embodiment, the seed layer may further comprise a "metal alloy layer or": the metal of the metal layer is a metal to be deposited onto the microelectronic structure Since the 1' seed layer may be a copper alloy, a double alloy such as cobalt-phosphorus is a second:: such as cobalt winter phosphorus, and the thickness of the seed layer is preferably between 5. angstrom; the damascene process can be A production line comprising various manufacturing microelectronic circuits: the preparation is completed, wherein the above devices have - or =. = surface of the part, the metal interconnected silicon wafer is fabricated by the damascene process, and the semiconductor wafer is formed on the surface; ^, the workpiece is preferably cut or η, ^ is formed into a hole, a ditch or a medium Metallizing and forming microelectronic circuit components or parts. [1] One or more devices include: a 7:: sink process to form a barrier layer on a micro-package surface device, wherein the barrier The layers are all chemically deposited with metal interconnects; and, for a large number of paper grades, the Chinese national standard RnS is applied. A4 specification 9 10 1283014 V. Invention description (7) A second deposition process is used, and a reinforcement layer is used. Formed on the barrier layer upper device, wherein the reinforcing layer is formed by a human anvil and a human alpha from the mouth, and is generally used for subsequent electrochemical formation - the pre-existing system is a metal interconnect a body portion; and a device for electrochemically depositing a metal on the reinforcing layer. The device for forming the reinforcing layer is preferably an electrochemical deposition device such as an electroless plating or electroplating process. strengthen The device of the layer is capable of depositing a reinforcing layer on the barrier layer, and the thickness of the reinforcing layer is 100 angstroms or more, preferably 1 angstrom to 1 angstrom. The material of the reinforcing layer is preferably 2 genus alloys, such as copper alloys, such as copper such as copper, magnesium and/or copper - rendezvous to 'double alloys, such as Ming-Phosphorus; or three alloys, such as the start-heel-scale, or the earth may be the above alloy A mixture of electrochemical deposition - metal on the reinforcement layer (4) is a device that can use steel metal in (4). If copper is used as a metal layer or a microelectronic structure, a part of copper must be provided from the surface of the microelectronic workpiece. The device to be removed is preferably a chemical mechanical polishing device. The device may further comprise a first chamber forming a barrier layer and a first chamber ▲ forming a drag. In addition, the optional additional seed layer and copper metal layer may also be deposited on the workpiece while the workpiece is in the second chamber forming the reinforcement layer. In this way, the electrochemically deposited reinforcement layer, the selective seed layer and the copper metal layer can be completed in the same chamber of the apparatus. [Simple description of the drawings] This paper standard (CNS) A4g (2 songs 297 mm) Pack---------Book---- (Please read the notes on the back and fill in the palm of this page. ) Line! 12 trench 14 barrier layer 18 joint 20 crack 24 barrier reinforcement layer 28 seed layer 1283014 V. Description of the invention (8) Figure 1A is a cross-sectional view of a semiconductor wafer, which has been etched to form a dielectric Electrical drain pattern. Figure 1B is a cross-sectional view of a semiconductor germanium wafer having a trench in which a thin barrier layer, such as tantalum or tantalum nitride, has been uniformly deposited on its surface. Figure 2 is a cross-sectional view of a semiconductor germanium wafer having a trench that has been covered with a thin barrier layer and that surface defects are most often formed in a thin barrier layer. Fig. 2A is an enlarged cross-sectional view showing the semiconductor wafer trench of the covered film in Fig. 2. Fig. 3 is a cross-sectional view of a semiconductor wafer having a trench, and a thin barrier layer is deposited in accordance with the present invention, and a barrier reinforcing layer is deposited. " Figure 4 is a cross-sectional view of the semiconductor germanium wafer of Figure 3, which has been filled with copper by electrochemical deposition. Figure 5 is a cross-sectional view of the semiconductor wafer surface of Figure 4 after grinding and removing excess copper to obtain a complete conductor mosaic pattern. Figure 6 is a cross-sectional view of another embodiment of a semiconductor germanium wafer having a complete conductor mosaic pattern and, prior to filling the trench with copper, a sink: a seed layer over the barrier reinforcement layer. ' — Figure 7 is at 75. (: Next, deposit the wrong tungsten-scale alloy barrier layer on the barrier layer < Deposit thickness (in angstroms) versus time (in minutes). [Illustration] 10 Dielectric material 16 Barrier Layer 2 2 Grain Boundary This paper scale is applicable to the towel A4 specification (21GX^7 mm) _ (please read the notes on the back and fill in the pages on this page) Pack--------- Order --------line* · A7 B7 1283014 V. Description of the invention (9) [Detailed description of the specific embodiment of the company] 凊 See Figure 1A first, for the dielectric constituting the semiconductor wafer A partially enlarged cross-sectional view of the material 10, such as cerium oxide, a trench 12 is formed in the dielectric material 10. The surface of the dielectric material 10 is covered with a thin barrier layer ,4, and the thin barrier layer 14 can be The chemical vapor deposition process is preferably performed using a physical vapor deposition process. The barrier layer can generally be a thin refractory metal or a metal nitride, and the representative barrier layer material includes a package, a light nitride, and a nitride nitride. Light, crane, nitrided crane, nitrided tungsten, Qin, titanium nitride and t-money, and other tertiary compounds. As shown in Fig. 1A, the barrier layer 14 is a continuous film without cracks or surface defects, which is an ideal layer surface coverage. The thickness of the barrier layer is usually in the field area and the flat bottom surface of the trench. Between 1 〇〇 and 5 〇〇, the thickness of the sidewall of the trench depends on the aspect ratio and the size of the opening, usually below angstrom or below. For trenches with smaller openings and deeper depths, deposited on the sidewalls The film thickness may be too thin to cause cracks or surface defects. Next, referring to Figures 2 and 2A, the barrier layer 16' formed on the dielectric material 1' has a surface covering defect in the trench 12, such as the first It is shown that the barrier layer 16 does not smoothly cover the sidewalls and the flat bottom surface of the trench. The barrier layer at the bottom corner does not completely cover the dielectric material, but forms the seam 18' and the crack 2G is the sidewall of the cover film. Cracks. Grain boundaries such as the National Standard (CNS) A-4 specifications (2 songs C, please read the back of the notes and then fill out the various pages) Binding ----- Line! 1283014 V. Inventions ( 10), inhibiting the copper seed layer from properly adhering to the barrier Barrier defects are related to the diffusion of steel at grain boundaries, because the diffusion of the boundary is much faster than that of the diffusion through the day. Therefore, the grain boundary is improved by filling the grain boundaries. The early nature of the defect. For example, the titanium nitride barrier layer often uses oxygen to fill the grain boundary with oxygen atoms. Another method to reduce grain edge defects and fl is in the original Adding other materials to the barrier metal to form: gold, the added materials usually gather at the grain boundaries (also known as separation), and can be integrated into gold to meet different needs, such as copper alloys, such as 2 tin-copper. Zinc, copper-magnesium or copper_Ming, can be used as a diffusion barrier for copper. The metal added to the alloy usually collects on the grain boundary surface or on the free surface to prevent copper atoms from escaping. Copper-tin and copper-zinc are conventional ways to prevent the diffusion of oxygen atoms to slow the annihilation of copper in the air. Recently, copper _ aluminum has been studied as a diffusion barrier for copper because aluminum tends to separate at the grain boundaries and surfaces. One of the difficulties encountered in depositing a seed layer on the barrier layer is how to have good adhesion between the seed layer and the barrier layer, and the case where the electroplated copper adheres to the surface of the barrier layer is poor. Why is the reason why the described seed reinforcement layer is not deposited directly on the barrier layer and is deposited on the copper seed layer deposited by physical vapor deposition in the US Patent No. 97,181; The copper seed layer deposited by phase deposition has poor adhesion to the barrier layer. Therefore, the copper seed layer deposited by physical vapor deposition is usually used to improve the adhesion of the copper seed layer deposited by chemical vapor deposition. . 13

(Please read the notes on the back and then fill in the columns on this page) -----, one-------- line! n n n · installed 1283014

V. Description of the Invention (11) As shown in Fig. 3, the barrier reinforcing drawer of the present invention is above the barrier layer 16, which can be deposited by deposition/preservation... + fly phase deposition process, physical vapor phase Read the precautions of the back and fill the nest. This page is divided into a private chemical process or a chemical vapor phase. It is better for electrochemical processes, such as electrodeless and electroplating processes. The thickness of the barrier layer is between Covered between 1 〇 and 1 〇〇, such as the seam 18 in the barrier layer 16 , the vacancy 7 祛, , 18 , the crack 2 〇 and the grain boundary and the early strengthening layer It has good step coverage. The barrier reinforcement layer 2R is used to strengthen the diffusion barrier layer and serves as a seed layer for the copper plating process. Therefore, depositing the barrier reinforcement layer can reduce the need for another copper seed layer. The barrier reinforcement layer is formed of a conductive metal which can be attached to the barrier layer or can be subsequently plated with copper. Preferably, the barrier reinforcement layer is formed of a double or triple metal alloy material. And may be selected from any of the following: cobalt-phosphorus or cobalt-tungsten-phosphorus, It is formed of a copper alloy such as copper-aluminum, copper-magnesium, copper-zinc or copper-tin, or any possible mixture of such alloys. As an alloy material for the early strengthening layer, it is preferably a _he_ Scales, the electrochemical deposition process of which is described in detail in U.S. Patent No. 5,695,810, the disclosure of which is incorporated herein by reference. At 9 〇 °c, the amount of liquid electrolytic solution lost due to evaporation will be excessive, so a lower temperature, such as 75 ° C is preferred. The deposition thickness of lead · chicken-scale alloy can be determined by a certain sedimentary reactant The deposition time and temperature are controlled. As shown in Fig. 6, the cobalt-tungsten-phosphorus alloy is applied to the Chinese national standard (CNS) A4 specification (210X297 GM) at 75 °C at 175 mm. A7 B7 V. INSTRUCTIONS (12) '' The rate at which the pen-based deposition process is deposited on the tantalum nitride-resistant layer is about 100 to 200 angstroms per minute. The electrochemical deposition process is preferably used. Depositing a barrier reinforcement layer, and this process and standard copper plating process and equipment for making copper interconnects Compatible. Therefore, a new process chamber ▲ can be set up in the existing system, that is, a new electrochemical deposition process for depositing the barrier reinforcement layer is directly integrated into the existing plating tool. A proper integration The tool structure, as shown in U.S. Patent No. 6, 127, 437, Figure 12, has an integrated tool structure that reduces tooling costs and has a simple wafer fabrication process. After depositing the barrier reinforcement layer, the wafer can Directly transferred into the copper plating module to complete the plating process without leaving the plating tool. After the barrier reinforcement layer 24 is completely covered by the barrier layer 丨6, the pattern carved out by the copper clock is filled up. As shown in Figure 4. Thereafter, the surface of the field is re-ground to remove excess copper, preferably by chemical mechanical polishing. After the chemical mechanical polishing is completed, the completed conductor mosaic pattern is obtained, as shown in Figure 5. In another embodiment, two layers of film can be deposited on the barrier layer, as shown in Fig. 6 is a cross-sectional enlarged view of the wafer dielectric material 形成 formed with the trenches 2. A barrier layer 16 is deposited on the flat bottom and sidewall surfaces of the trench, and as described above, has grain boundaries, seams, and cracks. The barrier reinforcement layer 24 is again overlaid on the barrier layer 16, after which the seed layer is "formed over the barrier reinforcement layer 24, and the seed layer 28 can likewise be formed of an alloy, as if a barrier is formed. Like layer 24, copper metal can also be used. Although the seed layer can be chemical vapor deposition, physical vapor deposition or electrochemistry (please read the back of the note before filling in the columns on this page) __^__T__ 15 1283014 , the invention description (13) ^ deposition process to deposit, the preferred way is electrochemical deposition • privately using a compatible deposition process to deposit barrier reinforcement layer and seed layer is more economical, and It is preferred to use the same tool. Example 1. Depositing a barrier-reinforcing layer on a titanium nitride barrier layer. The titanium nitride barrier is first plated on the oxidized dielectric material and then blocked by a tantalum nitride. The surface of the barrier layer is cleaned and rinsed, and a lead-prepared phosphor film is deposited on the titanium nitride barrier layer by electrodes. The composition of the electrolytic solution used for deposition is:

CoC1x6H20 30 g / liter (NH4) 2W04 1 gram / liter

Na3C6H5〇7xH2〇 80 g/L

NaH2P02xH20 20 g / liter KOH added to pH 9.5 9.5 deposition temperature of 75 ° C, deposition time of about i minutes, the deposited film (, '. 100 angstroms) has good diffusion properties, and successfully The seed layer of the subsequent copper electric clock. Example 2 / Sputtering a button barrier layer on a cerium oxide dielectric substrate, because the cobalt-tungsten-phosphorus directly deposited on the substrate has a low degree of adhesion, and the smelting of a layer of cobalt film (about 100 angstroms) ) on the surface of the button, then at 75.钴Cobalt-tungsten-phosphorus film is deposited on the surface of the cobalt for about 丨 minutes by electrodeless deposition. The combined film (about 200 angstroms) has satisfactory adhesion, and then the copper is directly plated on the cobalt. On the tungsten-phosphorus film. In this embodiment, the cobalt thin film is a barrier reinforcing layer, and the cobalt-tungsten-phosphorus thin film is a seed layer of copper plating. 1283014

V. INSTRUCTION OF THE INVENTION (14) This example is based on Example 2 of the present invention, ("different two layers of barrier reinforcing layer and seed layer can be used; and (7) deposition of barrier reinforcing layer and seed crystal The present invention has been described in detail with reference to the preferred embodiments of the present invention, and various modifications in form and detail of those skilled in the art will be included. Therefore, the present invention must be made in the scope of the patent application, and not only the description of the preferred embodiment. (Please read the notes on the back and then fill in the pages of this page.) Binding €-17 This paper size applies. China National Standard (CNS) A4 specification (210X297 mm)

Claims (1)

1283014 Sixth, the scope of application for patents Ministry of Economic Affairs Intellectual Property Bureau employees consumption cooperatives printed 8 · a variety of metals applied to microelectronics ^ ^ L. y. Dry process, the microelectronic workpiece includes a cloth with one or more micro-embedded The wall includes: a surface of the structure, the process package (a) forming an inner wall of the wall structure on the surface of the microelectronic workpiece; and an early layer, the micro-embedded (8) forming a reinforcing layer on the surface of the layer a cobalt-phosphorus alloy or a cobalt-tungsten-phosphorus alloy; /, a seed layer formed on the strong layer, wherein the seed layer is composed of copper = and copper such as copper zinc, copper tin or the like Made up of a mixture; (4) electroplating a metal on the seed layer to fill the micro-embedded junction. 9. The process of claim 8, wherein the reinforcement layer is formed using an electrochemical deposition process. 10. The process of claim 9, wherein the electrical deposition process is selected from the group consisting of electrodeless and electric ore processes. 11. The process of claim 8, wherein the reinforcement layer is formed using a chemical vapor deposition process (CVD). 12 · The process described in item 8 of the patent application is formed using a physical vapor deposition process (p VD ). 13 The process described in item 8 of the patent application range is between 10 angstroms and 1 angstrom. between. 14. The process of claim 8, wherein the process has a seam, a crack or a grain boundary defect, and the reinforcing layer has a conformal layer above the barrier layer. 10 15 20 The paper size is applicable to China's country ^#F(CNS)A4 mU210 x 297 ^ where the reinforcement is the reinforcement where the resistance PI Α8 Β8 C8 D8 Patent Application No. 1283014 5. The process of claim 8, wherein the metal that is electro-mineralized on the seed layer is copper. 16. The process of claim 8 further comprising the step (e) removing a portion of the metal from the surface of the microelectronic workpiece. 5 ί7. The process of claim 16, wherein the removal is performed by chemical mechanical polishing. 18. The process of claim 8 wherein the microelectronic workpiece is a germanium or gallium arsenide semiconductor wafer. 19. A metal layer formed on a 10 microelectronic workpiece in accordance with the process described in claim 8 of the scope of the patent application. 20. A production line comprising a variety of apparatus for fabricating microelectronic circuit components or components, one or more of which are used to form a metal interconnect in a damascene process on a surface of a microelectronic workpiece to form the micro An electronic circuit component or component, the one or more devices comprising: 15 means for forming a barrier layer on a surface of the microelectronic workpiece using a first deposition process, wherein the barrier layer is generally unsuitable for mass electrification Depositing the metal interconnect; a device for forming a reinforcement layer on the barrier layer using a second deposition process, wherein the reinforcement layer is composed of a cobalt-phosphorus or a cobalt-tungsten-phosphorus 20 a device comprising a third process for forming a seed layer on the reinforcing layer, wherein the seed layer is composed of copper-aluminum, copper-magnesium, copper-copper, copper-tin, cobalt Phosphorus, cobalt, tungsten-phosphorus or a mixture of such alloys; and a device 25 for electrochemically forming the metal on the reinforcing layer. This paper scale applies to China National Standard (CNS) A4 specifications ---:----- (Please read the notes on the back and then fill out this page) Order-----1---Line j Ministry of Economics intellectual property Bureau employee consumption cooperative printed 1283014 A8 B8 C8 D8 5 10 Ministry of Economic Affairs Zhici Financial Bureau Member X Consumer Cooperatives Printing 20 Patent Application Scope 21 The production line described in claim 2, wherein the device forming the reinforcing layer is an electrochemical deposition device. The production line of claim 21, wherein the means for forming the reinforcement layer performs an electrochemical deposition process selected from the group consisting of electrodeless and electroplating processes. 23. The production line of claim 2, wherein the means for forming the reinforcement layer is a chemical vapor deposition process (CVD) apparatus. 24. The production line of claim 2, wherein the device forming the 5 reinforced layer is a physical vapor deposition process (PVD) device. The production line of claim 20, wherein the means for forming the reinforcing layer is conformally formed on the barrier layer to form the reinforcing layer having a thickness of 100 angstroms or less. 26. The production line of claim 2, wherein the means for electrochemically forming the metal on the seed layer can be made of copper. </ RTI> 27. The production line of claim 2, further comprising a means for removing a portion of the metal from the surface of the microelectronic workpiece. 28. The production line of claim 27, wherein the means for removing the portion of the metal comprises a chemical mechanical polishing apparatus. 29. The production line of claim 20, wherein the microelectronic workpiece is a germanium or gallium arsenide semiconductor wafer. CPlease read the notes on the back and fill in the page. 297 secret)