丨 8twf.doc/g 九、發明說明： 【發明所屬之技術領域] 本發明疋有關於-種晝素結構（pixdstructure)，且 ~別疋有關於—種能有$文地提昇開啟/關閉電流比 (Ion/Ioff)之畫素結構。 【先前技術】 ” 現今社會多媒體技術相當發達，多半受惠於半導體元 件或顯示裝置的進步。就顯示褒置而言，具有高畫質、空 間利用效率佳、低、;肖耗功率、絲射料輔性之薄膜電 晶體液晶顯示器（Thin Film Transist〇r Uquid Crystal丨8twf.doc/g IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a pixd structure, and there is a need to increase the on/off current. The pixel structure of (Ion/Ioff). [Prior Art] Today's social multimedia technology is quite developed, and most of them benefit from the advancement of semiconductor components or display devices. In terms of display devices, it has high image quality, good space utilization efficiency, low, and power consumption. Thin film transistor liquid crystal display (Thin Film Transist〇r Uquid Crystal)
Display，TFT-LCD)已逐漸成為市場之主流。 一般的薄膜電晶體液晶顯示器主要是由一薄膜電晶 體陣列基板（Thin Film Transistor array substrate, TFT array substrate)、一彩色濾光基板（c〇i〇r Fiiter substrate)以及 一設置於上述二基板之間的液晶層（Uquid Cry stall ay er ) 所構成。其中，薄膜電晶體陣列基板主要是由基板、陣列 排列於基板上之薄膜電晶體與畫素電極（pixd electrode)， 以及掃描線(scan line)與資料線(data line)所構成。一般而 言’掃描線與資料線可將訊號傳輸至對應之薄膜電晶體， 以達到顯示之目的。 在高解析度（high resolution )與高垂直掃瞄頻率 (vertical scan frequency )的液晶顯示器中，薄膜電晶體陣 列（TFT array )需滿足較大的開啟/關閉電流比（i〇n/i〇ff)。 一般而言，當開啟/關閉電流比（Ion/Ioff)大於等於五個級 6 1282175 8twf.doc/g 數（105 )時，才能使薄膜電晶體液晶顯示器提供較佳的顯 品^[立。 - 承上述，在習知技術中提高開啟/關閉電流比 (Ion/Ioff)的方式有兩種：（1)增加開啟電流（I〇n)。 (2)降低關閉電流（Ioff)。其中，第一種方式是利用調 • 整薄膜電晶體的通道寬長比（W/L of channel)而設定其開 . 啟電流。但是，若一味的加大薄膜電晶體的通道寬度（width of channel)，將會造成較大的閘汲寄生電容（cgd)與回 鲁 踢電壓值（kick-back voltage )。因此，將導致閃燦（flicker) 的問題並影響顯示品位。 然而，第二種方式是透過降低關閉電流，其不具有上 述之缺點。意即，其能減少薄膜電晶體中所產生的漏電流 現象’並有效地提昇開啟/關閉電流比（I〇n/I〇ff)，卻不會 造成較大的閘汲寄生電容（Cgd )與回踢電壓值（kick七ack voltage)。值得一提的是，上述漏電流的現象主要是由半 導體層中未蝕刻完全的歐姆接觸層所引起的。 • 人—圖1繪不為習知一種畫素結構的俯視示意圖。圖1A 、’、曰示為&圖1中的A-A’線的剖面示意圖。請共同參照圖j 與圖1A’此晝素結構3〇〇包括薄膜電晶體1〇〇與畫素電極 200 ’並利用基板16〇上的掃瞄線17〇與資料線18〇驅動薄 膜電晶體100。其中，薄膜電晶體1〇〇包括閉極11〇、問絕 、、彖層120、半導體層、源極i4〇a、汲極i4〇b與保護層 150閘極11〇是與掃瞄線170電性連接。閘絕緣層12〇 覆蓋閑極110與掃瞒線170。半導體層13〇配置於閘極π〇 7 12821¾ 8twf.doc/g 上方之閘絕緣層12G上，其是由通道層施與歐姆接觸層 130b所組成。源極i4〇a與汲極i4〇b配置於半導體層1卯 上，而源極140a與資料、線180電性連接。保護層15〇曰覆蓋 源極H〇a與没極140b，而保護層15〇中設置有接觸窗開 口 150a暴露出沒極丨働。而晝素電極·則是與薄膜· 晶體100的汲極140b電性連接。 、％ …請再參照圖1A，在-般的薄膜電晶體製程中會利用 光阻層（未!會示）以及源極14〇&與汲極·作為触刻罩 幕，匕將閘極110上方的歐姆接觸層！ 3 〇 b移除，也就是會進 ::Back channd Etching，bce )而完成薄膜電 曰曰體100的製作。然而，此種方式在大面積面板的製作中， 由於整體的_速料句度會有所差異，所以在如圖！或 圖1A所繪示的區域J9〇附近將殘留有部分的歐姆接觸層 上由於^姆接觸層13Gb具有良好的導電性 電流將沿著圖1中所緣示的路徑A發生。因此，晝素電^ 2〇〇將無法保持施加在其上的資料電壓（紙讀喂）， 而產生閃蝶（flieker)和串影（_s滅）等顯示不良的 現象。 、，知減少上述漏電流現象的作法有以下三種。第一種 方式是增加半導體層13〇以及源極14加 的層間距離。往夂日力同〇 Μ 一你七間 、 明 圖2 ’弟一種方式疋增加源極140a與 f極14%之間的半導體層130的缺ϋ 195的寬度w，使漏 f流不易在路徑Β内流通。但是，上述兩種方法會增加使 、泉路的負載電容（l°ad capacitance)以及減少畫素結構3〇〇 '8twf.doc/g 的開口率（aperture ratio)，所以會造成驅動訊號的失真和 閃爍等現象。 請參照圖3,第三種方法是增加源極i40a與汲極140b 在邊緣位置的距離，其揭露在美國專利公開號 US2005/0041169A1中。如圖3所繪示，源極H〇a與汲極 140b之間的距離為L1 (即通道長度），且源極M〇a與汲 極140b的邊緣之間距離為L2。也就是說，源極M〇a與汲 極140b之間在邊緣位置的距離增加了 Δί、寬度變化了 此’在不減少開啟電流的情況下，此設計將可以減 v漏包*的產生。但是此設計不能減少因歐姆接觸層· 餘刻不均勻所引起之漏電流現象，並且其開啟/關閉電 /，广I〇n/I〇ff)也未能提昇到所需 【發明内容】 干 因歐妞疋提供—種畫素結構，可以有效地減少 其開啟/關閉^電流所引起之漏電流，進而提昇 本發明之另一日3 i 板’其且有上述之蚩1疋楗供一種薄膜電晶體陣列基 觸層的乾钕刻不均構’而能夠有效地減少因歐姆接 關閉電流比（i〇n/lGff)。起之漏電流’進而提昇其開啟/ 本發明的又一目的e 上述之薄膜電晶體陣、種液晶顯示面板，其具有 和串影』基板，而能夠減少閃爍（flicker) 現象。 ”也目的，本發明提出一種畫素結構， 9 12821775 8twf.doc/g ίΐ:=ΐ!:Γ與資料線而驅動，畫素結構包括 = 賴電晶體包括_ m 1 +¥體層、源極與汲極、以及第二介電層 1 田己連接。第—介電層覆蓋閘極與掃瞒線。半導體芦 至少一延伸部。== 2;上’而源極與資料線電性連接，並且延伸部自位 核Γ 極之間的主體部邊緣突出。第二介電層覆苗源 二/、沒極，而第二介電層中設置有 皿異、 J出延伸部娜。晝素電極與薄膜電晶體= 體陣:多 個金絲m W / 線與多條資料線與多 ^4。其中，掃猫線與f料線配置 :構與對應之掃瞒線與資料線電性連接，且每 電晶體與畫素電極。此薄膜電晶體包括開極:第 朽2广、半導體層、源極與汲極、以及第二介電声。門 :體層配置於間極上方之第一介電層上，其中:匕： 有主體部以及與主體部連接的至少 ：體層具 配置於丰導髀爲μ ^ . t ^ /原極與汲極 二、Η上，I雜與㈣線紐連接，並且 於源極與汲極之_主體部邊緣突出。第二介電展 第f介電層中設置有至少-接觸窗二 “蚊伸#汲極。畫素電極與_電晶體的汲極 12821775 8tvvf.doc/g 電性連接。 為達上述或是其他目的，本發明又提出一種 面板，包括-上述之薄膜電晶體陣板、—彩色濾光基 板以及-液晶層。而液晶層位於薄膜電晶體陣列基板 色濾光基板之間。 〃 山在一實施例巾，上述之接觸·窗口暴露出延伸部的末 部的末端中的第—介電層、半導體層與第二 ;丨笔層疋透過接觸窗開口而移除。 f μ〜例中’上述之接觸窗開σ暴露出延伸部的中 間口亚且延伸部的中間部分中的第—介電層、半導體 層與第二介電層是透過接觸窗開cr而移除。 、豆 亩，’上述之延伸部的延伸方向與掃瞒線垂 直，且L伸邛大出於掃瞄線外。 延伸例：’上述之延伸部包括第-延伸部與第二 =第二申 m邊-士人出知線外。弟二延伸部往垂直於掃 上：：伸，且第二延伸部突出掃瞄線外。 姆接觸> m’上叙半導體層包括—通道層與一歐 姆接觸層’而歐姆接觸層位於通道層上。 部，^構巾的半導體層具有主體部與延伸 第二介出掃晦線外。再加上於延伸部上方的 1=接觸層、通道層與第-介電層。因此，可以有效地 減少因歐姆接觸層的乾_不均㈣ •8twf.doc/g 提昇畫素結構的開啟/關閉電流比（I〇n/1〇ff)。並且，將此 晝素結構應用於薄膜電晶體陣列基板與液晶顯示面板中， 將可以提昇其解析度與垂直掃目㈣率，並減少液晶顯示面 板的閃爍和串影等顯示不良的現象。 >為毒本發明之上述和其他目的、特徵和優點能更明顯 易懂，下域舉較佳實施例，並配合所關式，作詳細說 明如下。 【實施方式】 圖4繪不為本發明較佳實施例中一種畫素結構的示音 圖。圖4A繪示為沿圖4中的㈣，線之剖面示意圖。圖^ 與圖4C繪示為沿圖4中的c_c，線的剖面示意圖。 請先共同參照圖4與圖4A，此畫素結構_適於由 基板460上的掃瞄線470與資料線48〇而驅動，此晝素结 構600包括薄膜電晶體4〇〇與晝素電極5〇〇。❿此薄膜^ 晶體400包括閘極41〇、第一介電層42〇、半導體層43〇、 源極440a與汲極440b、以及第二介電層45〇。 閘極410與掃瞄線470電性連接。第一介電層42〇覆 蓋閘極=1G與㈣線47G。半導體層配置於閘極41〇 上方之介電層42〇上，其中半導體層·具有主體部 432以及與主體部432連接的至少一延伸部434a、43仆。 源極440a與汲極440b配置於半導體層43〇上，而源極44如 與貧料線480電性連接，並且延伸部434a、434b自位於源 極440a與汲極440b之間的主體部432邊緣突出。第二介 電層450覆盍源極440a與汲極44〇b，而第二介電層450 12 8twf.doc/g 中没置有至少一接觸窗開口 4% t 4；)Ua暴露出延伸部434a、 434b與汲極440b。畫素電極5〇〇與薄 440b電性連接。 …專膜電晶體400的汲極 在一實施例中，可以利用掃瞒線470本身作為閘極 410^ , 在=-貝_中，也可以另外製作—間極圖案（未繪示）， 而在閘極圖案上製作薄膜電晶體（未繪示），豆中，閘極Display, TFT-LCD has gradually become the mainstream of the market. A thin film transistor liquid crystal display device is mainly composed of a thin film transistor array substrate (TFT array substrate), a color filter substrate (c〇i〇r Fiiter substrate), and a second substrate. The liquid crystal layer (Uquid Cry stall ay er) is formed. The thin film transistor array substrate is mainly composed of a substrate, a thin film transistor and a pixd electrode arranged on the substrate, and a scan line and a data line. In general, the scan line and the data line can transmit signals to the corresponding thin film transistors for display purposes. In liquid crystal displays with high resolution and high vertical scan frequency, the TFT array needs to meet a large on/off current ratio (i〇n/i〇ff). ). In general, when the on/off current ratio (Ion/Ioff) is greater than or equal to five levels of 6 1282175 8twf.doc/g (105), the thin film transistor liquid crystal display can provide a better display. - In view of the above, there are two ways to increase the on/off current ratio (Ion/Ioff) in the prior art: (1) increase the turn-on current (I〇n). (2) Reduce the off current (Ioff). Among them, the first method is to set the on/off current by adjusting the channel width to length ratio (W/L of channel) of the thin film transistor. However, if the width of the channel of the thin film transistor is increased, a large gate parasitic capacitance (cgd) and a kick-back voltage will be caused. Therefore, it will cause problems with flickers and affect the display quality. However, the second way is by reducing the off current, which does not have the above disadvantages. That is, it can reduce the leakage current generated in the thin film transistor and effectively increase the on/off current ratio (I〇n/I〇ff) without causing a large gate parasitic capacitance (Cgd). With kickback voltage value (kick seven ack voltage). It is worth mentioning that the above leakage current phenomenon is mainly caused by the unetched ohmic contact layer in the semiconductor layer. • Person—Figure 1 depicts a top view of a conventional pixel structure. 1A, ′, and 曰 are schematic cross-sectional views of the line A-A' in Fig. 1. Referring to FIG. 1 and FIG. 1A together, the pixel structure 3 includes a thin film transistor 1 and a pixel electrode 200' and drives a thin film transistor by using a scan line 17A on the substrate 16 and a data line 18? 100. Wherein, the thin film transistor 1 〇〇 includes a closed-end 11 〇, a 、, a 彖 layer 120, a semiconductor layer, a source i4〇a, a drain i4〇b, and a protective layer 150 gate 11〇 and a scan line 170 Electrical connection. The gate insulating layer 12A covers the idler 110 and the broom line 170. The semiconductor layer 13 is disposed on the gate insulating layer 12G above the gate π 〇 7 128213⁄4 8 twf.doc/g, which is composed of the channel layer and the ohmic contact layer 130b. The source i4〇a and the drain electrode i4〇b are disposed on the semiconductor layer 1卯, and the source 140a is electrically connected to the material and the line 180. The protective layer 15 〇曰 covers the source H 〇 a and the immersion 140 b, and the protective layer 15 设置 is provided with a contact opening 150 a to expose the immersion. The halogen electrode is electrically connected to the drain 140b of the film/crystal 100. %, please refer to Figure 1A again. In the general thin film transistor process, the photoresist layer (not shown) and the source 14〇& and the drain electrode are used as the touch mask, and the gate is used. Ohmic contact layer above 110! 3 〇 b is removed, that is, it will enter ::Back channd Etching, bce ) to complete the fabrication of the thin film electrode 100. However, in this way, in the production of large-area panels, the overall _ fast material sentence will be different, so in the figure! Or a portion of the ohmic contact layer remaining in the vicinity of the region J9 图 shown in Fig. 1A has a good conductivity current due to the ohmic contact layer 13Gb, which will occur along the path A shown in Fig. 1. Therefore, the halogen electrode will not be able to maintain the data voltage applied to it (paper feed), resulting in poor display such as flieker and crosstalk (_s off). There are three ways to reduce the above leakage current phenomenon. The first way is to increase the interlayer distance of the semiconductor layer 13 and the source 14 plus.夂 力 力 〇Μ 〇Μ 〇Μ 你 你 你 你 你 你 你 你 你 你 你 你 你 你 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Circulation inside. However, the above two methods increase the load capacitance (l°ad capacitance) of the spring path and the aperture ratio of the pixel structure 3〇〇'8twf.doc/g, so the distortion of the drive signal is caused. And flashing and other phenomena. Referring to Fig. 3, a third method is to increase the distance between the source i40a and the drain 140b at the edge position, which is disclosed in U.S. Patent Publication No. US2005/0041169A1. As shown in Fig. 3, the distance between the source H〇a and the drain 140b is L1 (i.e., the channel length), and the distance between the source M〇a and the edge of the drain 140b is L2. That is to say, the distance between the source M〇a and the drain 140b at the edge position is increased by Δί, and the width is changed. This design can reduce the occurrence of the leaky packet* without reducing the turn-on current. However, this design can not reduce the leakage current caused by the ohmic contact layer and the unevenness of the residual, and its on/off power/, wide I〇n/I〇ff) is not improved to the required content. Because Ou Niu provides a pixel structure, it can effectively reduce the leakage current caused by its on/off current, and thus enhance the other day of the present invention. The dry etching unevenness of the base layer of the thin film transistor array can effectively reduce the off current ratio (i〇n/lGW) due to the ohmic connection. The leakage current □ further enhances its opening. According to still another object of the present invention, the above-mentioned thin film transistor array and liquid crystal display panel have a crosstalk substrate, and the flicker phenomenon can be reduced. Also, the present invention proposes a pixel structure, 9 12821775 8twf.doc/g ίΐ:=ΐ!:Γ and the data line are driven, the pixel structure includes = 赖电晶 including _ m 1 +¥ body layer, source Connected to the drain and the second dielectric layer 1 . The first dielectric layer covers the gate and the broom line. The semiconductor reed has at least one extension. == 2; the upper and the source are electrically connected to the data line. And the extension portion protrudes from the edge of the main body portion between the nucleus of the nucleus. The second dielectric layer covers the seed source source 2/, the pole is not, and the second dielectric layer is provided with the dish and the J extension portion. Electrode and thin film transistor = body array: multiple gold wires m W / line and multiple data lines and more ^ 4. Among them, sweep cat line and f material line configuration: structure and corresponding broom line and data line electrical Connected, and each transistor and pixel electrode. The thin film transistor includes an open electrode: a second layer, a semiconductor layer, a source and a drain, and a second dielectric sound. The gate: the body layer is disposed above the interpole On a dielectric layer, wherein: 匕: has a main body portion and at least a body layer connected to the main body portion, and the body layer is disposed at a thickness of μ ^ . t ^ / original pole and 汲On the second pole, the upper side, the I and the (4) line are connected, and protrude from the edge of the main body of the source and the bungee. The second dielectric display is provided with at least a contact window in the f dielectric layer. Bungee jumping. The pixel electrode is electrically connected to the drain of the transistor 12821775 8tvvf.doc/g. To achieve the above or other objects, the present invention further provides a panel comprising - the above-described thin film transistor array, a color filter substrate, and a liquid crystal layer. The liquid crystal layer is located between the thin film transistor array substrate color filter substrates. In an embodiment of the invention, the contact/window exposes a first dielectric layer, a semiconductor layer and a second layer in the end of the end portion of the extension; the 疋P layer is removed through the contact opening. f μ~ In the example, the above contact opening σ exposes the intermediate portion of the extension and the first dielectric layer, the semiconductor layer and the second dielectric layer in the middle portion of the extension are moved through the contact window except. Bean acres, the extension of the above-mentioned extension is perpendicular to the broom line, and the extension of the L is large outside the scanning line. Extension example: 'The above extension includes the first extension and the second = second margin - the scholar outside the line. The second extension extends perpendicular to the sweep:: and the second extension protrudes beyond the scan line. The m-contact > m' semiconductor layer includes a channel layer and an ohmic contact layer, and the ohmic contact layer is on the channel layer. The semiconductor layer of the structure has a body portion and an extension of the second delivery broom line. In addition, 1 = contact layer, channel layer and dielectric layer above the extension. Therefore, it is possible to effectively reduce the on/off current ratio (I〇n/1〇ff) of the pixel structure due to the dry_unevenness of the ohmic contact layer (4) • 8twf.doc/g. Moreover, applying the halogen structure to the thin film transistor array substrate and the liquid crystal display panel can improve the resolution and the vertical scanning (four) rate, and reduce the display defects such as flicker and crosstalk of the liquid crystal display panel. The above and other objects, features, and advantages of the present invention will become more apparent from the <RTIgt; [Embodiment] FIG. 4 is a diagram showing a pixel structure which is not a preferred embodiment of the present invention. 4A is a cross-sectional view of the line taken along line (4) of FIG. 4. Figure 4 and Figure 4C are schematic cross-sectional views along line c_c in Figure 4. Referring to FIG. 4 and FIG. 4A together, the pixel structure _ is adapted to be driven by a scan line 470 on the substrate 460 and a data line 48, which includes a thin film transistor 4 and a pixel electrode. 5〇〇. The film 400 includes a gate 41, a first dielectric layer 42, a semiconductor layer 43, a source 440a and a drain 440b, and a second dielectric layer 45A. The gate 410 is electrically connected to the scan line 470. The first dielectric layer 42 is covered by the gate 1G and the (4) line 47G. The semiconductor layer is disposed on the dielectric layer 42A above the gate 41A, wherein the semiconductor layer has a body portion 432 and at least one extension portion 434a, 43 connected to the body portion 432. The source 440a and the drain 440b are disposed on the semiconductor layer 43A, and the source 44 is electrically connected to the lean line 480, and the extensions 434a, 434b are from the body portion 432 between the source 440a and the drain 440b. The edges are prominent. The second dielectric layer 450 covers the source 440a and the drain 44〇b, and the second dielectric layer 450 12 8twf.doc/g is not provided with at least one contact opening 4% t 4 ;) Ua exposes the extension Portions 434a, 434b and drain 440b. The pixel electrode 5 is electrically connected to the thin 440b. In an embodiment, the bucking wire of the special film transistor 400 can be used as the gate 410^ by using the broom line 470 itself, and the interpole pattern (not shown) can be additionally produced in the =-be. Making a thin film transistor (not shown) on the gate pattern, in the bean, gate
圖案，，《線47。是彼此電性連接。❿閘極彻與掃目苗線 470疋弟一金屬層（metal 1)。 而第-介電層420覆蓋閘極彻與掃猫線47()。第一 介電層42^的材質可以是氧切、氮切魏氧化石夕，並 且’形成第-介電| 420❸方法例如是化學氣相沈積法 (Chemical Vapor Deposition，CVD )。 半導體層430可以是由一通道層43〇a與一歐姆接觸 層430b所組成的膜層，而歐姆接觸層43此位於通道層 430a上。其中，通道層43〇a之材質可以是非晶矽（他）， 而歐姆接觸層430b之材質可以是經摻雜的非晶矽 (n aSi)。特別是，半導體層43〇例如是具有主體部432 與至少一延伸部434a、434b的圖案，而延伸部434a、434b 的延伸方向與掃瞄線470垂直，且延伸部434a、434b突出 於掃瞄線470外。 更詳細而言，如圖4所繪示之兩個延伸部包括第一延 伸部434a與第二延伸部434b，其中，第一延伸部434a往 垂直於掃瞄線470的第一方向+Y延伸，且第一延伸部434a f.doc/g 突出掃瞄線470外。而第二延伸部434b往垂直於掃瞄線 470的第二方向-γ延伸，且第二延伸部434b突出掃瞄線 470外。關於設置延伸部的優點，將在後續再說明。 源極440a與汲極440b是設置在半導體層43〇的主體 部432上，而源極440a、汲極440b與資料線480是第二 金屬層（metal 2)。晝素電極5〇〇與薄膜電晶體4〇〇的汲 極440b電性連接。在一實施例中，晝素電極5〇〇的材質可 以疋透明導電材質，其例如是銦錫氧化物（Indium Tin Oxide，IT0)或銦鋅氧化物(in(jium Zinc 〇xide，IZ〇)。 ，以下將說明設置延伸部的優點。請參照圖4與圖4A， 备掃目田線470對薄膜電晶體4〇〇施予一適當電壓時，薄膜 電晶體400會被開啟，而使得資料、線_施加在源極 上的資料電壓（data voltage )能夠傳遞到畫素電極5〇〇上。 然而，由於半導體層的週邊具有未_完全的歐姆接 觸層430b，所以將使得施加在畫素電極5〇〇上的資料電潭 無法維持穩定，而沿著路徑c或路徑D產生漏流。土 因此，本發明藉由上述之延伸部434a、434b，再利用 蝕刻製程（etching precess)移除延伸部43如、幻仆末浐 或中間部分的歐姆接觸層43%，如此，將可以減少薄膜: 晶體400中所發生的漏電流現象。 、 請共同參照圖4、圖犯與圖4C，在延伸部你心傷 =上方設置了至少-個接觸窗開σ 45〇a。在一實施 接觸窗開口 450a暴露出延伸部434a、 末Pattern, "Line 47. They are electrically connected to each other. The ❿ gate is very thorough with the sweeping line 470 brothers a metal layer (metal 1). The first dielectric layer 420 covers the gate and the whisk line 47 (). The material of the first dielectric layer 42 may be oxygen-cut, nitrogen-cut oxidized oxide, and the method of forming a first-dielectric| 420 例如 is, for example, a chemical vapor deposition (CVD). The semiconductor layer 430 may be a film layer composed of a channel layer 43A and an ohmic contact layer 430b, and the ohmic contact layer 43 is located on the channel layer 430a. The material of the channel layer 43A may be amorphous germanium, and the material of the ohmic contact layer 430b may be doped amorphous germanium (n aSi). In particular, the semiconductor layer 43 is, for example, a pattern having a body portion 432 and at least one extension portion 434a, 434b, and the extension portions 434a, 434b extend in a direction perpendicular to the scan line 470, and the extension portions 434a, 434b protrude from the scan. Line 470 outside. In more detail, the two extensions as shown in FIG. 4 include a first extension 434a and a second extension 434b, wherein the first extension 434a extends in a first direction +Y perpendicular to the scan line 470. And the first extension portion 434a f.doc/g protrudes beyond the scan line 470. The second extension 434b extends in a second direction - γ perpendicular to the scan line 470, and the second extension 434b protrudes beyond the scan line 470. The advantages of setting the extension will be described later. The source 440a and the drain 440b are disposed on the body portion 432 of the semiconductor layer 43B, and the source 440a, the drain 440b, and the data line 480 are the second metal layer (metal 2). The halogen electrode 5〇〇 is electrically connected to the anode 440b of the thin film transistor 4〇〇. In one embodiment, the material of the halogen electrode 5〇〇 may be a transparent conductive material, such as Indium Tin Oxide (IT0) or indium zinc oxide (in (jium Zinc 〇xide, IZ〇)). The advantages of providing the extension portion will be described below. Referring to FIG. 4 and FIG. 4A, when the scanning field line 470 applies an appropriate voltage to the thin film transistor 4, the thin film transistor 400 is turned on, and the data is made. The line_data voltage applied to the source can be transferred to the pixel electrode 5〇〇. However, since the periphery of the semiconductor layer has a non-complete ohmic contact layer 430b, it will be applied to the pixel electrode. The information pool on the 5th is unable to maintain stability, and the leakage flow is generated along the path c or the path D. Therefore, the present invention removes the extension by the etching process by the above-mentioned extensions 434a, 434b. For example, the ohmic contact layer of the portion 43 or the intermediate portion is 43%, so that the leakage current phenomenon occurring in the film: crystal 400 can be reduced. Please refer to FIG. 4, FIG. 4, and FIG. 4C together. Department of your heart injury = above A set of at least - a contact window opening σ 45〇a In one embodiment exposes contact opening 450a extending portion 434a, the end.
延伸部的末端中的第—介電層42G 12821¾ 8twf.doc/g 430與第二介電層彻是透過接觸窗開口娜而移除。 在另-實施例中，接觸窗開口 45〇a暴露 434a、434b的中間部分（未緣示），並且延伸部伽、 的中間部分中的第-介電層420、半導體層43_第 電層450是透過接觸窗開口 45〇a而移除。 更詳細而言’在-實施例中，可利用如圖4 的光阻層490與侧製程495來移除部分第二介電層曰45〇 而形成如圖4C所繪示之接觸窗開口 45〇a，同時，^一 移除接觸窗開口 45Ga所暴露的歐姆接觸層侧盘诵道芦 =a。因此’位於延伸部434a、434b的末端或中間：歐ς f層43Gb就相被完全移除。也就是說，由歐姆接觸層 f〇b所引起的沿著c路徑與D路徑的漏電流，即可以^ ，置有接觸窗開口 450a的位置而被阻斷。如此一來，即使 薄膜電晶體400的兩側或週邊仍存在有歐姆接觸層4鳥， 也不冒造成漏電流過大的情形。因此，此薄膜電晶俨彻 能夠有效地降低關閉電流（lGff)，並提高開啟/關^ 比（Ion/Ioff)。 在一實施例中，蝕刻製程495所使用的氣體是選自於 、CH4的混合氣體，其對於非晶矽/氮化矽（a_Si/SiN ) 白口Η虫刻選擇比是大於等於j : 3〜i : 5。因此，飾刻製程州 可以有效地移除歐姆接觸層430b與通道層430a。 另外，由於延伸部434a、434b並不是設置 或是資料線上，所以，線路的負載電容並不會^ 力並且，延伸部434a、434b的設置也不會影響到晝素結 ；twf.doc/g 構600的開口率，而使光線能夠有效地穿透畫素結構6〇〇。 此外，利用形成接觸窗開口 450a而同時移除歐姆接觸層 430b的製程也十分簡單並不會增加額外的成本。 紅上所述，本發明的晝素結構6〇〇可以在不增加線路 的負載電谷和晝素開口率的情況下’減少由歐姆接觸層 430b所造成之沿著路徑C或路徑D的漏電流現象。結果 是，此晝素結構600可以有效地降低其關閉電流（l〇ff) 與提昇其開啟/關閉電流比（Ion/Ioff)。 圖5繪示為本發明較佳實施例中一種薄膜電晶體陣列 基板的示意圖。請參照圖5，此薄膜電晶體陣列基板7〇〇 包括基板谓、多條掃猫線，與多條資料線73〇與多個 晝素結構740。其中，掃瞒線72〇與資料、線73〇配置於基 板710上。晝素結構74〇與對應之掃瞄線72〇鱼資料 電性連接。 /'、、 值得注意的是，每一晝素結構74〇的各個構件盥上述 ，晝素結構6 0 0的各個構件相同，在此不予以重述。、由於 =電晶體74Ga中的半導體層（未繪示）具有延伸部（未 二不，並將延伸部末端或中間的歐姆接觸層（未繪示） 以形成接觸窗開口（未繪示）時—併以_方式去除。所 的、、=可以有效地減少因為歐姆接觸層未_完全而引起 曰甘屯机現象，進而能有效地降低關閉電流汗）與提 =開啟/關閉電流比（I〇n滅）。所以，畫素電極7儀 上的肓料電壓可以維持穩定。 圖6繪示為本發明健實關巾—魏晶顯示面板的 16 1282175 8twf.doc/g 立體示意圖。此液晶顯示面板1〇〇〇包括一上述之薄膜電晶 體陣列基板700、一彩色濾光基板8〇〇以及一液晶層9〇〇， 而液晶層900是位於薄膜電晶體陣列基板7〇〇與彩色濾光 基板800之間。由於此液晶顯示面板1〇〇〇具有上述之開啟 /關閉電流比（Ιοη/Ioff)較高的薄膜電晶體陣列基板7〇〇， ，以其將能夠減少閃爍（flicker)和串影（cr〇ss癒）等 頒示不良的現象，並提昇顯示品質。 、綜上所述，本發明之晝素結構、薄膜電晶體陣列基板 與液晶顯示面板具有下列優點： (1)本發明之晝素結構可以有效地減少由歐姆接觸 層所造成之漏電流現象。所以，可以降低關電流（Ioff) 進而大幅度地提昇畫素結構的開啟/關電流比（〖on/·)。 、（2 )本發明利用光罩上的配置設計（layout of mask) 即可以喊具社體部與延伸部的半導體層。並利用形成 接觸窗開口的同時_併移除延伸部中的歐姆接觸層。如 此，即可降低漏電流現象。因此，本發明的製程十分簡單。 (3)將具有較高的開啟/關閉電流比（Ion/I〇ff)的圭 素結構應用在薄膜電晶體_基板與液晶顯示面板中，ί 可=提昇_電晶體陣列基板的解析度與垂直掃猫頻率， 亚減>、液晶顯示面板的閃燦和串影等顯示不良的現象。 限〜Γ ί ΐ發明6崎佳實施賴露如上，然其並非用以 二ίριΓ丄任何熟習此技藝者，在不脫離本發明之精神 # =内’备可作些許之更動與潤飾，因此本發明之保護 軏圍當視後附之申請專利範騎界定者為準。 Ί !twf.doc/g 【圖式簡單說明】 示為習知1晝素結構的俯視示意圖。 圖1A繪示為沿圖1中 - v中的A-A，線的剖面示意圖。 圖2不為習知另—接| ^ m 3給一么羽a 種旦素結構的俯視示意圖。 、圖 3、、、胃不為-白知—^ F, β,Λ 圖 4綠示為本發明較佳： 圖4Α緣示為沿圖4中沾 甲的Β-Β線之剖面示音、圖。 圖4β與圖4C繪示 為>口圖4中的C-C，線的剖面示意 圖。 圖5緣示為本發明較祛 故“aa -立门 平Λ1土汽施例中一種薄膜電晶體陣列 基板的不意圖。 圖6繪示為本發明較佳徐 ^ ^ ^ π 1土汽施例中一種液晶顯示面板的 立體不思圖。 【主要元件符號說明】 100、400、740a :薄膜電晶體 110、410 :閘極 120、420 ·閘絕緣層 130、430 :半導體層 130a、430a :通道層 130b、430b :歐姆接觸層 140a、440a :源極 140b、440b :;：及極 150、450 :保護層 丨 8twf.doc/g 150a、450a :接觸窗開口 — 160、460、710 :基板 - 170、470、720 :掃瞄線 180、480、730 :資料線 190 :區域 195 :缺口 . 200、500、740b :晝素電極 300、600、740 :畫素結構 • 432 :主體部 434a :第一延伸部 434b :第二延伸部 490 :光阻層 495 ··蝕刻製程 700 :薄膜電晶體陣列基板 800 :彩色濾光基板 900 :液晶層 • 1000 :液晶顯示面板 A、B、C、D :路徑 A-A’、B-B’、C-C’ ：剖面線 U、L2、AL :距離 w :寬度 Aw :寬度變化 +Y :第一方向 -Y :第二方向 19The first dielectric layer 42G 128213⁄4 8twf.doc/g 430 and the second dielectric layer in the end of the extension are removed through the contact opening. In another embodiment, the contact opening 45〇a exposes an intermediate portion of 434a, 434b (not shown), and the first dielectric layer 420, the semiconductor layer 43_the electrical layer in the intermediate portion of the extension portion 450 is removed through the contact opening 45〇a. In more detail, in the embodiment, the photoresist layer 490 and the side process 495 of FIG. 4 can be used to remove a portion of the second dielectric layer 曰45〇 to form the contact opening 45 as shown in FIG. 4C. 〇a, at the same time, the ohmic contact layer side disk sill reed exposed by the contact window opening 45Ga is removed. Thus, the end or middle of the extensions 434a, 434b: the ς f layer 43Gb is completely removed. That is, the leakage current along the c-path and the D-path caused by the ohmic contact layer f〇b can be blocked by the position where the contact opening 450a is placed. As a result, even if the ohmic contact layer 4 is present on both sides or the periphery of the thin film transistor 400, the leakage current is not excessively generated. Therefore, the thin film transistor can effectively reduce the off current (lGff) and increase the on/off ratio (Ion/Ioff). In one embodiment, the gas used in the etching process 495 is a mixed gas selected from the group consisting of CH4, and the ratio of the amorphous yttrium/niobium nitride (a_Si/SiN) white mites is greater than or equal to j:3. ~i: 5. Therefore, the etched process state can effectively remove the ohmic contact layer 430b and the channel layer 430a. In addition, since the extensions 434a, 434b are not disposed or on the data line, the load capacitance of the line does not force and the arrangement of the extensions 434a, 434b does not affect the elementary junction; twf.doc/g The aperture ratio of the structure 600 is such that the light can effectively penetrate the pixel structure 6〇〇. In addition, the process of forming the contact opening 450a while removing the ohmic contact layer 430b is also simple and does not add additional cost. As described above, the halogen structure 6〇〇 of the present invention can reduce the leakage along the path C or the path D caused by the ohmic contact layer 430b without increasing the load cell valley and the aperture ratio of the line. Current phenomenon. As a result, the halogen structure 600 can effectively reduce its off current (l〇ff) and increase its on/off current ratio (Ion/Ioff). FIG. 5 is a schematic diagram of a thin film transistor array substrate in accordance with a preferred embodiment of the present invention. Referring to FIG. 5, the thin film transistor array substrate 7 includes a substrate, a plurality of sweeping cat lines, and a plurality of data lines 73 and a plurality of halogen structures 740. The broom line 72A and the data line 73 are disposed on the substrate 710. The halogen structure 74〇 is electrically connected to the corresponding scan line 72 squid data. /', It is worth noting that each component of each of the unitary structures 74A is the same as the above, and the components of the unitary structure 600 are the same and will not be repeated here. Since the semiconductor layer (not shown) in the transistor 74Ga has an extension (none, and an ohmic contact layer (not shown) at the end or the middle of the extension to form a contact opening (not shown) - and removed by _. The =, can effectively reduce the 曰 接触 因为 因为 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 , , , , , , 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆 欧姆〇n off). Therefore, the dip voltage on the pixel electrode 7 can be kept stable. 6 is a perspective view of the 16 1282175 8twf.doc/g of the Weijing display panel of the present invention. The liquid crystal display panel 1 includes a thin film transistor array substrate 700, a color filter substrate 8A, and a liquid crystal layer 9〇〇, and the liquid crystal layer 900 is located on the thin film transistor array substrate 7 Between the color filter substrates 800. Since the liquid crystal display panel 1 has the above-described thin film transistor array substrate 7 having a high on/off current ratio (Ιοη/Ioff), it is possible to reduce flicker and crosstalk (cr〇). Ss (such as more) issued poor performance and improved display quality. As described above, the halogen structure, the thin film transistor array substrate and the liquid crystal display panel of the present invention have the following advantages: (1) The halogen structure of the present invention can effectively reduce the leakage current caused by the ohmic contact layer. Therefore, the off current (Ioff) can be lowered to greatly increase the on/off current ratio of the pixel structure (〖on/·). (2) The present invention utilizes a layout of a mask to scream a semiconductor layer having a body portion and an extension portion. And taking advantage of the formation of the contact opening while removing the ohmic contact layer in the extension. In this way, the leakage current can be reduced. Therefore, the process of the present invention is very simple. (3) Applying a high-level on/off current ratio (Ion/I〇ff) to the thin film transistor _substrate and liquid crystal display panel, ί can be used to improve the resolution of the OLED array substrate. Vertical sweeping cat frequency, sub-subtraction, liquid crystal display panel flashing and cross-talking, etc., show poor performance. Limit ~Γ ί ΐInvention 6 is to implement Lai Lu as above, but it is not used by anyone who is familiar with this skill, without departing from the spirit of the present invention #=内' The protection of the invention shall be subject to the definition of the patent application. Ί !twf.doc/g [Simple description of the diagram] It is shown as a top view of the conventional monolithic structure. 1A is a schematic cross-sectional view taken along line A-A of FIG. Figure 2 is not a schematic view of a conventional structure of ^ a 3 m. Fig. 3, ,, stomach is not - Baizhi - ^ F, β, Λ Figure 4 Green is preferred for the present invention: Figure 4 shows the edge of the Β-Β line along the 沾Figure. Fig. 4β and Fig. 4C are schematic cross-sectional views of the line C-C in Fig. 4; Figure 5 is a schematic view of a thin film transistor array substrate in the "aa-立门平Λ1 soil vapor application" of the present invention. Figure 6 is a view of the preferred embodiment of the present invention. In the example, a liquid crystal display panel is not considered. [Main element symbol description] 100, 400, 740a: thin film transistor 110, 410: gate 120, 420 · gate insulating layer 130, 430: semiconductor layer 130a, 430a: Channel layers 130b, 430b: ohmic contact layers 140a, 440a: source 140b, 440b:; and poles 150, 450: protective layer 丨 8twf.doc / g 150a, 450a: contact window opening - 160, 460, 710: substrate - 170, 470, 720: scan lines 180, 480, 730: data line 190: area 195: notch. 200, 500, 740b: halogen electrodes 300, 600, 740: pixel structure • 432: body portion 434a: First extension portion 434b: second extension portion 490: photoresist layer 495 · etching process 700: thin film transistor array substrate 800: color filter substrate 900: liquid crystal layer • 1000: liquid crystal display panel A, B, C, D : Paths A-A', B-B', C-C': section lines U, L2, AL: distance w: width Aw: width change + Y: The direction of -Y: second direction 19