TWI281192B - Power semiconductor structure capable of reducing on-state resistance and method of manufacturing the same - Google Patents

Abstract

The present invention provides a power semiconductor (DMOS) structure capable of reducing on-state resistance (Ron) and method of manufacturing the same, which mainly employ an ion implantation means having a slanted implantation angle and enabling to select adequate implantation depth to directly implant impurity in a first conduction state into an epitaxial region affected by a junction field effect transistor (JFET) after completing etch of a polysilicon structure. The impurity in the first conduction state is blocked by the polysilicon structure and won't be directly implanted in a channel region; the channel region is immune to the influence of the increase amount of the impurity, and under the condition of a constant starting voltage, the length of the channel region can be shortened to reduce the resistance of the channel region; after increasing the amount of the impurity, the resistance on top of the epitaxial region can be further reduced.

Description

</ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; method. [Prior Art] In the semiconductor industry, a MOS field effect φ tmnS1 St〇r 'MOSS is a known power semiconductor device, and one of the types of the MOS field-effect transistor is Is a double diffused field effect transistor 'also known as double diffused metal oxide semiconductor (D〇uble Diffused Metal

Oxide Semiconductor (DMOS) structure (hereinafter referred to as DMOS structure), wherein the DMOS structure includes a DMOS structure of an n-type channel and a DMOS structure of a p-type pass, and the other is similar to the power of the MOS half-effect transistor. The body is called 'Insulate (j Gate • BlPolar Transistor, IGBT) (hereinafter referred to as: IGBT structure), the main advantage is that the electric power consumed by it is very small, so most of them do not need to be added. The heat sink can be miniaturized, which meets the basic requirements of modern electronic products, which are becoming lighter, thinner and shorter. However, due to the rapid changes in electronic products today and the stricter requirements for low power consumption and frequency, how to effectively Improving the power semiconductor device to have ultra-low on-resistance has become a key development direction in the field of technology. As shown in the first figure, it is a general structure of the DM 〇s structure of the n-type channel 51281192. The DMOS structure includes an n-type drain region 1 〇a (矽 wafer substrate), and an n-type epitaxial region (layer) formed at the upper end of the drain region 1 〇a (n-type epitaxial la) Yer) 20 a, a p-type body formed at the top of the epitaxial region 2 〇a 3 0 a, a source region formed at the top of the body region 3 0 a (source regi〇ns) 4 〇a, and a gate region 5〇a (which includes an insulating layer and a polysilicon structure) formed at an upper end of the epitaxial region 20 a; wherein a lower portion of the gate region 5 〇a partially overlaps the source a region 40a extending over a portion of the surface of the body region 3a. Further, a surface of the body region 3a at the lower end of the gate region 5a can be defined as a channel region 3: [a, and The surface area at the top of the epitaxial region 2 〇a is generally referred to as a Junctified Field Effect Transistor (JFET) region (hereinafter referred to as the JFET region). Further, the source region of the DMOS structure 4 The impedance between 〇a and the drain region 1 〇a is called the on-resistance (〇n_state resistance, R〇n). The on-resistance mainly includes: the resistor R1 of the channel region 3丄a, the resistor R2 of the JFET region, and the epitaxial layer. a resistor R3 of the region 2 〇a, and a resistor R4 of the drain region (substrate) region 10 a; The most influential impedance of the overall on-resistance (Ron) of the j) MOS structure is the resistance at the top of the epitaxial region (i.e., the resistance of the JFET region or the channel region). As shown in the second figure, it is a conventional manufacturing method developed to reduce the resistance of the JFET region, that is, mainly by using ion implantation or other diffusion before forming the gate region 5 6 1281192 0 a. In a manner, the impurity is implanted vertically downward to the JFET region or the channel region at the top of the epitaxial region to increase the n-type dopant concentration of the JFET region, and reduce the electrical resistance R2' of the jfeT region and reach The purpose of reducing the on-resistance of the DMOS structure. • Only by using the above method, although the resistance of the JFET region can be reduced, the n-type impurity of the south agent will simultaneously neutralize the p _ type impurity at the top of the body region 3 〇a, and then lower the body region 3 〇a The p-type dopant concentration at the top, that is, because the n-type impurity is directly implanted in the position of the channel region 31a, such that the outer edge of the region 3p is pushed-inwardly (pushing_in) the body region 30a (eg As shown in part j of the second figure; however, as the dose of the impurity increases, the concentration of the channel region 3 1 a will gradually fade, and at the same time, the threshold voltage (Vt) will be lowered, and the The structure is more susceptible to the punch-through effect and causes a breakdown of the Breakdown Voltage. Therefore, the above method will be limited by the amount of ion implantation dopant or impurity (D0se) in the JFET region, so that the drop in the resistance of the JFET region is limited, so how to reduce the DM〇s more effectively. The on-resistance of the structure is one of the issues that have been faced and solved for a long time. In view of the fact, the inventors are missing from the "method of manufacturing the on-resistance (R〇n) of the conventional mDMOS structure, and are based on the influence of the increase in the ion implantation dopant (Dose) of the JFET region. Under the premise, and the accumulation of 7 1281192 years of trial production and implementation, we can finally develop an innovative "can reduce the conduction and resistance of the double-diffused metal oxide semiconductor manufacturing method", in order to solve the above, the missing. SUMMARY OF THE INVENTION An object of the present invention is to provide a power semiconductor structure capable of reducing on-resistance (R0n) 10 and a method of fabricating the same, which are mainly for reducing ion implantation in a muscle region (hereinafter referred to as: Jfet IMP) affects the collapse/beauty voltage and the starting voltage (Vt), which in turn increases

JFET IMP's amount of domicile or impurity (Dose), and achieve the purpose of reducing the conduction resistance of the DM〇s structure. The manufacturing method of the present invention mainly uses the ion implantation method with an oblique angle after the completion of the multiple (four) (p. (four) plane) structure (eteh), and the φ 肸 first transmission type 恶 (wherein the n-type channel) In DM〇s, the first conduction is η-type, the first-conductivity type is p-type, and in the reading of p-type channel (10), the di-conductive type is p-type, and the second conduction type is impurely inclined. Into the top of the wormhole region; the FET region, at which time the impurity of the first conductivity type can be selected to appropriately implant depth, and directly implant (or diffuse into) the stray region affected by the JFET, and the first The impurity of the conduction type will be blocked by the gate region and will not directly implant the low-concentration body region of the second conductivity type (ie, the channel region), so that the original starting voltage can be maintained (Vt/8). 1281192 does not cause a breakdown of the breakdown voltage due to the effect of the punch-through effect. / Further, a power semiconductor structure formed by the manufacturing method of the present invention can be applied to DMOS structure or IGBT structure, including one a substrate; a conductivity-type sorrowful crystal region is formed at an upper end of the substrate; a free region is formed at an upper end of the epitaxial region; and one or a plurality of second-passed-type regions Formed on top of the epitaxial region; a plurality of source regions are formed on top of the body region; wherein the upper surface of the body region is provided with a channel region, the channel region being shielded from the gate region The lower end; and the concentration epitaxial region of the first conductivity type are formed by the interfacial field effect transistor (JFET) by using an ion implantation method with an oblique implantation angle and a selectable implantation depth. In the stray area, the channel area will not be affected by the jFET IMP's dopant or impurity _J曰 Gary, and the breakdown voltage and the starting voltage (Vt) will not change. The length of the channel region is shortened, thereby reducing the resistance of the channel region, and when the amount of dopant or impurity of the JFET IMp is increased, the resistance of the JFET region at the top of the epitaxial region is also reduced. The present invention is a DMOS structure of an n-type channel (i.e., using a substrate of a first conductivity type 9 1281192 _ complaint, wherein the first conductivity type is a p-type of the second conductivity type) is one of the modes. The present invention is also applicable to the DMOS structure of the p-type equivalent of the equivalent structural change (that is, the substrate using the first conductivity type, wherein the first conduction type is P type, and the second conduction type is ^ type), And the IGBt structure: (ie, different from the DMOS structure, only the substrate of the second conductivity type is used.) _ Please refer to the third to third E diagrams, which are double diffusion metal oxide semiconductors (DMOS) of the present invention. The manufacturing method is described as follows according to the manufacturing steps: As shown in FIG. 2A, a germanium wafer (ie, a substrate) is first provided, which is doped to form a high conductivity germanium region of a first conductivity type (n-type).丄〇; using a reaction gas (produced by a chemical reaction between trichlorosilane and hydrogen), ', I the surface of the substrate to form a boundary layer; then, the reaction gas will diffuse through the boundary layer, That is, using the m formula, the 7th floor of the day is grown in the day. _ The upper end of the substrate to form a low concentration insect crystal region 20 of a first conductivity type (n-type). Furthermore, as shown in the third figure, at least one gate region 5 is formed on the upper end of the low-concentration epitaxial region 2 利用 by a thin film, a lithography, and an etching process; "the gate region 5 includes a polycrystalline germanium (p〇lysilic) structure 5 1 and an insulating layer 5 2 . As shown in the third C diagram, the second pass &amp; type sad (P type) impurity is used by ion implantation or other means. Implanted in the top end of 10 -1281192 of the low-concentration epitaxial region 2 以 to form a p-type body region 3〇 (which includes two adjacent concentration regions and a low-length body region). The second conductivity type (n-type) impurity is implanted on the top of the p-type body region 30 to form at least two, as in the case of the second image, or by other methods. Η-type high-concentration source region 4 〇, wherein 'the upper surface of the body region 30 of the Ρ-type, and a channel region is formed in the high-concentration source region 40 and the edge of the body region 30 3 1, the length of which is a mountain, wherein the channel region 3 1 is shielded at the lower end of the gate region 5 。. Further, the present invention The main technical means, as shown in the third figure, is to perform ion implantation in the JFET region (i〇I1 impiantati〇11) (hereinafter referred to as JFET IMP), that is, using an inclined implantation angle and selecting an appropriate implantation depth. In the ion implantation mode, the impurity of the first conductivity type (n-type) is obliquely implanted on the surface of the φ DM0S structure, and the n-type impurity is blocked by the polysilicon structure 51, and is not directly implanted. The low concentration body region (ie, the channel region 3 1 ), that is, the JFET region-domain (ie, the epitaxial region affected by the JFET) directly entering the top of the epitaxial region 20 to form a first conduction type (η) Type) Medium/Changing Insect Crystal Area 6 〇 (as shown in the fourth figure). By this, the original starting voltage (Vt) can be maintained without being affected by the pUnch-through effect. And the phenomenon that the breakdown voltage is reduced. 11 1281192 The length of the channel region 3 1 can be shortened to d2 to reduce the resistance of the wanted region 3; and when the crystal region affected by the JFET is increased 2 When the mass of the top of the 〇 is increased (gp increases the n of the JFET region) In addition, the JFET region of Leiyang Jieyumen, +mu y and P can also be low, so the resistance through the channel region 3 1 or the JFET region + + $ $ can be reduced, and can be reduced The DM〇S structure leads to the general ("), 俾 细则 细则 细则 细则 细则 细则 quot quot quot quot quot quot quot quot quot 综 综 综 综 综 综 综 综 综 综 综 综 综 综 综 综 综 综 综 本 本 本 本 本 本 本 本 本The method is effective to make the shadow of the parental JFET IMP doping quality of the channel region be that the mountain is in the condition that the phase collapse fM and the initiation power &amp; not change, and the length of the (four) channel region can be reduced. ^ The resistance of the low-pass region is increasing, and the doping amount of the FET trace can also reduce the resistance of the lung τ region at the top of the worm region; therefore, it can be used for a large amount of %. /, 'Please ask for a piece of paper, according to the patent law, and apply for a patent to protect the rights of the creator. Wood seeks profit, but only the above-mentioned materials are only applicable to the scope of patents of the present invention. Therefore, the application of the invention and the internal structure of the macro to the equivalent structure change are the same. All are included in the scope of the present invention, and 1281192 [Simplified description of the drawings] The first figure is a general structure diagram of a conventional double-diffused metal oxide semiconductor (DMOS) structure; 'Second figure: is a conventional Schematic diagram of the channel region concentration being changed by the influence of JEFT IMP; FIG. A to FIG. 2E: manufacturing order of reducing the on-resistance of double-diffused metal oxide semiconductor (DMOS) according to the manufacturing method of the present invention FIG. 4 is a double-diffused metal oxide semiconductor structure fabricated by using the third to third E-graphs to reduce the on-resistance. [Main component symbol description]

Bungee area

Insect crystal region

4〇a body area

Source region gate region

Osmotic region body region source region 4 0 polycrystalline stone structure

Insect crystal region channel region gate region insulation layer

13 1281192 medium concentration epitaxial region

Claims (1)

1281192 X. Patent Application Range: 1. A method for fabricating a power semiconductor structure capable of reducing on-resistance, comprising the steps of: 'providing a substrate; forming an epitaxial region of a first conductivity type at an upper end of the substrate; • forming a gate region at an upper end of the epitaxial region; • forming a body region of one or more second conductivity types at the top of the epitaxial region; forming a plurality of source regions at the top of the body region; The upper surface of the body region is provided with a channel region which is shielded at the lower end of the gate region; and the first conductivity type is utilized by an ion implantation method with an oblique implantation angle and a selectable implant depth The impurity is obliquely implanted (or diffused) into the area of the insect crystal affected by the field effector crystal (JFET) to form a first conduction type of medium concentration concentration crystallite region, and the impurity will be subjected to the gate Blocking of the pole region, and not directly implanting the channel region; - Turning this channel region will not be affected by the increase in the impurity, and the starting voltage will not Under varying conditions, and can shorten the length of the channel region, and the concentration at the top of the Yak force u stupid crystal region. 2. The method for manufacturing a half-body structure capable of reducing on-resistance as described in claim 1, wherein the power semiconductor structure is a double-diffused metal oxide semiconductor (DMQS) structure of an n-type 15 1281192 channel, And the reading plate is a high-concentration secret region of the first-conducting type, the first-conducting is: ^, and the second conducting type is p-type. 3. The manufacturing method for reducing the conduction of a semiconductor structure as described in the item i of the patent scope, wherein the power semiconductor structure (4) is a double-diffused metal oxide semiconductor (DMqS) structure, _ = a high-density type of conduction type In the polar region, the first conduction type is; type: the far two conductivity type is η type.泡 Bubble 2, such as the towel, please refer to the manufacturing method of the structure of the first half of the patent, which can reduce the on-resistance, and the middle 隹μ + · , the middle force 4 + Lai structure is the insulation gate Polar transistor (IGB) structure, high concentration immersion region. And the county board is the second conductivity type of the second, a power semiconductor structure that can reduce the on-resistance, including: a substrate; an ang-conductive type of suspended crystal region formed on the upper end of the substrate; Formed in the upper end of the epitaxial region; a body region of one or a plurality of second conductive faces is formed in the smectic portion of the telecrystalline region; and a plurality of source regions are formed in the body a top portion of the region; wherein the upper surface of the body is a $way region, the channel region is shielded at a lower end of the idler region; and 16