TWI279920B - Thin film transistor array substrate and liquid crystal display panel - Google Patents

Abstract

A thin film transistor array substrate, including a substrate, a plurality of scan lines and data lines, a plurality of pixel units, a plurality of scan bonding pads and data bonding pads, and a plurality of first and second switching devices. The substrate has a display region and a peripheral circuit region. The scan lines and data lines are disposed on the substrate, and the display region is divided into a plurality of pixel areas by thereof. Each pixel unit is disposed in one of the pixel areas, and is driven by the scan lines and data lines. The scan bonding pads and the data bonding pads are disposed in the peripheral circuit region. The scan bonding pads are electrically connected with the scan lines. The data bonding pads are electrically connected with the data lines. The first and the second switching devices are disposed in the peripheral circuit region, wherein at least one of the first switching devices is disposed between two adjacent scan bonding pads, and is electrically connected with thereof. And at least one of the second switching devices is disposed between two adjacent data bonding pads, and is electrically connected with thereof.

Description

Mm doc/y IX. Description of the Invention: [Technical Field] The present invention relates to a device array substrate and a display panel, and more particularly to an electrostatic protection function (anti -Thin Film Transistor Array Substrate (TFT Array Substrate) and Liquid Crystal Display Panel (LCD Panel). [Prior Art] In recent years, due to the maturity of optoelectronic technology and semiconductor manufacturing technology, the flat panel display has been flourishing, and the Thin Film Transistor Liquid Crystal Display 'TFT-LCD based on it Low voltage operation, fast operation speed, light weight and small size have gradually become the mainstream of display products. The thin film transistor liquid crystal display mainly comprises a liquid crystal display panel and a backlight module, wherein the liquid crystal display panel comprises a color filter substrate (C/F) and a thin film transistor array substrate (Thm Film). The TFT array substrate and the liquid crystal layer disposed between the two substrates, and the moonlight group is used to provide a surface light source required for the liquid crystal display panel, so that the liquid crystal display can be displayed. Effect. The main figure 1 is not a schematic view of a conventional thin film transistor array substrate. Referring to FIG. 1, the thin film transistor array substrate 100 includes a substrate 110, a plurality of scan lines 120 and data lines 13A, a pixel unit 15A, a scan pad 16A, a 6 uim doc/y data, and a dry pad. 170. An internal static protection ring i92 (inner guard ring) and an external static protection ring 丨94. The substrate 11A has a display region 112 and a peripheral circuit region 114. The Sweep line 120 and the tribute line 130 are disposed on the substrate 11A, wherein the scan line 12A and the data line 130 divide the display area 112 into a plurality of halogen regions 14A. The halogen elements 150 are respectively disposed in one of the halogen regions 14 , and are driven by the scan line 120 and the data line 13 , which is composed of a thin moon crystal 152 and A unitary electrode 154 is formed. 4 Continuing to refer to FIG. 1 , the scan pad 16 is disposed in the peripheral line region 114 , and the scan pad 160 is electrically connected to the scan line 120 . The data pad 17 is disposed in the peripheral line region 114, and the data pad 17 is electrically connected to the data line 130. The internal static protection ring 192 is disposed in the peripheral circuit area ι 4, and is located between the scanning switch 16G and the display area 112, and between the data soldering and display area 112, and the internal static protection ring 192 is electrically connected. Miao line (10) and data line 13G. The internal static protection ring 19 is a switch circuit for X (such as a thin film transistor or a diode) * an electrostatic protection circuit composed of an I line 12G and a data line 13G. In addition, the II 砰 砰 guard 194 is disposed in the peripheral line area (1) material r (four) between the pad 16G and the outer edge of the substrate 11G and between the outer edge of the G and the substrate 11G, and external electrostatic protection Ring 194 knives are connected to the sweeping mm and the (four) wires = partial electrostatic protection _ is formed by the active switching component core or 疋 diode) and the surrounding broom wire 12 〇 and the data line 13 7 7 i279920w , 〇c/y electrostatic protection circuit. The composite crystal array substrate is typically 1% in the process of fabrication. In this way, when the electric charge is accumulated to a constant number of 100, the electrostatic discharge causes the thin film transistor array substrate body 152 to be called the anti-view 192 and the external static protection ring 194, so that the entire substrate, the display area m In the case of the elemental unit 15G or the line 嶋4 partial # 194: ^ = internal static protection ring 192 or external static protection % 194 疋 through the active switching element (not edge: = 3::; r when sweeping _. With the information please = electrician, etc. Lei Ba &#屯 more than 1 when, you can open the wire _ components and put the 砰 electric knife on the internal static anti-reliance 19 194, - _ material Lai Wei. By using the above-mentioned internal electrostatic protection ring 192 and the design of the external static electricity m, there is still a possibility that static f damage may occur, which is the position of the scanning pad 16G and the data pad 17G, because the two are large and accumulate A large amount of static electricity. Therefore, the static electricity is destroyed by the circuit or the thin film transistor on the thin film transistor array substrate (10). Still & [Invention] In view of the above, the object of the present invention is to provide Thin array substrate, a large amount of static electricity accumulated on the microscopic board , I27ma.-/y, the electrostatic breakdown phenomenon generated on the substrate. Further, it is still another object of the present invention to provide a liquid crystal display surface, the above-mentioned thin film transistor array substrate, and the liquid crystal display And good electrostatic protection ability. The board has a purpose based on the above purpose or other purposes, the present invention proposes a scorpion array: positive, including the substrate, a plurality of sweeping cat lines and a plurality of data lines, two pixels single 7G, more a scanning pad, a plurality of data pads, a plurality of second switching elements, and a plurality of second switching elements. The substrate has a display area and a line area. The broom line and the data line are disposed on the substrate, wherein the display area is divided into a plurality of pictures. The pixel region is respectively arranged in the Wei domain, where H is disposed in the peripheral circuit area by the sweeping cat line and the f ^ broom pad, and the shovel is in the 2 mesh line. The data pad is disposed in the periphery. In the line area, and ^^ is connected to the data line. The first-switching element is arranged in the peripheral circuit area,] at least one first-switching element is arranged between the pads: the first piece will be scanned with the two sides瞒 solder pads are electrically connected. The pieces will be on both sides Among them, "the two switching elements are =: first! Parallel mode ridges, and the two first-off components are a switch series of 虿雨弟弟, and the two second switching elements are 9 127· 丨twf .doc/y In one embodiment of the invention, the per-first-switching element package includes a net gate, a gate insulating layer, a semiconductor layer, and a source-level electrode. The floating gate diode configuration On the substrate, the gate insulating layer covers the floating gate, and the semiconductor layer is disposed on the gate and the pad edge layer above the floating gate. The source/drain is disposed on the semiconductor layer, wherein the source/drain is combined with The scan pads on both sides are electrically connected. In addition, the source/drain electrodes described above are asymmetrically disposed or symmetrically disposed. In one embodiment of the present invention, each of the second and second switching elements includes a gate, a gate insulating layer, a semiconductor layer, and a source/drain. The floating gate is disposed on the substrate. The layer covers the floating gate. The semiconductor layer is disposed on the gate insulating layer above the floating gate. The source/drain is disposed on the semiconductor layer, wherein the source/drain is electrically connected to the data pads on both sides thereof In addition, the above-mentioned source/drain electrodes are asymmetrically disposed or symmetrically disposed. + "In one embodiment of the present invention, each of the above-described pixel units includes a thin germanium transistor and a halogen electrode. The thin film transistor is disposed in one of the halogen regions. The halogen electrode is disposed in one of the halogen regions and electrically connected to the film body. In an embodiment of the present invention, the thin film transistor array substrate further includes a plurality of internal inner guard rings disposed in the peripheral circuit region and located in the scan pad and the display region. Between the poor solder pad and the display area, and the internal static protection ring is electrically connected - to the scan line and the data line. In an embodiment of the invention, the thin film transistor array substrate ′ further includes a plurality of external 静电 guard rings, which are disposed in the peripheral circuit area, located at ίο 1279920 17320 twf.doc/y. The data soldering and the outer edge of the substrate = 晦 ^ and the outer edge of the substrate are connected to the broom line and the data line.曰1' and the external electrostatic protection ring are electrically based on the above-mentioned purpose, and the liquid crystal display layer is further proposed. This _ electric day and day _ transistor array substrate and liquid array substrate, "Layer 3 = between the thin film electro-crystalline array substrate as described above. 9 · D color filter substrate and thin film transistor eight wood The first switching element and the second switching element, and the pot: the pad and the adjacent two power transmissions can be statically turned into an effect when the i-th or the data is soldered, and the charge is generated on the piece. Electrostatic Disruption Occurred on Adjacent Wipe Lines or Adjacent Hetero Crystal Array Substrates 2 "Every of the above and other objects, advantages and advantages are readily understood. The preferred embodiments are described below and in conjunction with the drawings. The formula is as follows.实施 Embodiments Fig. 2 is a schematic view showing a thin film transistor array substrate which is not a preferred embodiment of the present invention. Referring to FIG. 2, the thin film transistor array substrate 2 includes a substrate 210, a plurality of scan lines 22 and data lines 23, a plurality of pixel units 250, a plurality of scan pads 260, and data pads 270. a plurality of first switching elements 280a and a plurality of second switching elements 28〇b. 1279920 17320twf.doc/y

The substrate 210 has a display area 212 and a peripheral line area 214. The brush line 220 and the data line 23 are placed on the substrate 21, wherein the cat line 220 and the lean line 230 divide the display area 212 into a plurality of halogen regions 24A. Each of the pixel units 250 is disposed in one of the halogen regions 24, and is driven by the broom line 220 and the data line 23A. The wiper solder fillet is disposed in the peripheral under-line region 214, and the sweeping wire is electrically connected to the broom wire 220. The bead solder 270 g has been placed in the peripheral line area 214 0, and the data solder 270 is electrically connected to the cultivating line 23 (). The first switching element 2 is disposed in the peripheral circuit region, wherein at least one of the first and second closing elements is disposed between the adjacent two scanning brush pads (a two are shown in FIG. 2), and each of the switches The component 28Ga is electrically connected to the trace pads on both sides thereof. The second switching element 280b is disposed in the peripheral circuit region 214, and at least one second switching element 280b (two in FIG. 2) is disposed between the adjacent two data pads 27G, wherein each of the second switching elements The device is electrically connected to the data pads 270 located on both sides thereof. Referring to Figure 2, in one embodiment of the invention, each of the pixel units 250 includes a thin film transistor 252 and a halogen electrode. The thin film transistor 252 is disposed in the -pixel region 24A. The halogen electrode b is disposed in the halogen region 240 and electrically connected to the thin film transistor 252. In addition, as shown in FIG. 2, the thin film transistor array substrate 200 further includes a multi-send electrostatic protection ring 292, which is disposed in the peripheral circuit region 2! 4, and is located in the scanning pad 260 and the display region. Between 214 and between the pad 270 and the display area 214, and the internal static protection ring 292 is electrically connected to the broom wire 220 and the data line 23A. And, thin film transistor array

1279920 17320twf.doc/y The substrate 200, for example, further includes a plurality of external static protection rings 294 disposed within the peripheral line region 214 and located between the broom pads and the substrate (10) and on the data pads 27. Between the outer edges of the slanted substrate 21Q, the sb=electrostatic protection ring 294 is electrically connected to the squirrel line 220 and the data line 23= pings finely, 'the internal static protection ring 292 or the outer ring is through the active switching element ( Unexpectedly, the circuit structure of the smashing line 22=the lean line 230 is activated. When the static electricity on the scanning line 220 and the data line 230 or the thin plate transistor 252 is accumulated, the active switching element is turned on. The electricity is dispersed to the internal static protection ring M2 and/or the external static protection ring 294 to achieve the function of electrostatic protection. However, it is still possible to generate a large amount of static electricity accumulation in the area of 60 or the data pad. Therefore, in the present invention, the first switching element county and the switching element 280b are disposed between the adjacent two broom pads 26A and the adjacent two poor pad 270. In one embodiment of the invention, two first switching elements 28〇a are disposed between adjacent two scanning pads, and two first switching elements 〇a疋 are disposed in parallel. In addition, between the two adjacent data pads 270, for example, two second switching elements 28〇b are disposed, and the two second switching elements 28〇b疋 are disposed in parallel, so that the static electricity can be transmitted through the two-way transmission. (two_way conducting) way to conduct. Figure 3 is a schematic plan view of the scanning pad of Figure 2 in the A area. Figure 3A is a cross-sectional view along line A_A in Figure 3, and Figure 3B is a cross-sectional view along line BB in Figure 3. , the schematic diagram of the line. Referring to FIG. 3 and FIG. 3A together, in one embodiment of the present invention, the 13 I27m.y per-first-off element 28Ga includes a floating gate 2δ2 284, a semiconductor layer inspection, and a source-polarization configuration on the substrate. . The closed insulating layer 284 covers the floating idler. The semiconductor layer 286a is disposed on the gate insulating layer of the floating gate. The source/dot pole 288a is placed on the semiconductor layer, and the potless pole 288a is connected to the sweeping solder joints on both sides. ', the conventional process of forming a halogen array is to form wires on the substrate training (for example, sweeping wire, data line), thin film transistor and bismuth electrode, etc. This process can be used in five fresh processes, Four fresh processes or any known halogen array process. Please refer to FIG. 3, FIG. 3A and FIG. 3B simultaneously, taking a five-mask process as an example, as shown in FIG. 3, the sweeping wire (10), the sweeping pad 260, and the floating gate of the first switching element 28, for example. 282 & is made by the first mask process (Metal 1), which is directly disposed on the substrate 210^1. Then, on the substrate 21, the gate insulating layer 28^ is further formed to cover the cat, the wire 220, the sweeping wire 26 〇 and the floating gate 282 & Next, a semiconductor layer 286a is formed on the floating gate 2 82a by a second mask process. Then, the source/drain 288 & amp layer (MetaU) is fabricated in a third mask process. Thereafter, the protective layer 300 is completely covered on the substrate, and the opening 3 is defined by the fourth mask process, for example, with the opening 3〇〇b, that is, the position of the protective layer 3〇〇 above the scanning line 220. Opening 300a, the opening 3〇〇a exposes the metal layer of the source/drain 288a (as shown in FIG. 3A), and the opening 3 is formed in the gate insulating layer 284 and the protective layer 300 above the scanning pad 26? 〇〇b' exposes the scanning pad 26〇 (as shown in Fig. 3B). Next, a conductive layer 31G (for example, an indium tin oxide layer, -IT〇) is formed on the scan pad 26〇 14 1279920 17320 twf.doc/y and the sweep line 220 by a fifth mask process. It should be noted that the conductive layer 310 as shown in FIG. 3, FIG. 3A and FIG. 3B can pass through the opening 3〇〇a and the opening 3_, so that the source/drain 288a and the scanning pad 260 Electrically connected to each other. That is, when one of the scan pads 26 () is accumulated with a large amount of static electricity, the static electricity can be conducted from the scan pad 26 to the source/drain in the "" switching element 280a. 288a. Then, a charge-coupling effect is generated between the source/no-pole and the floating gate 282a, and the first-switching element 2 8 G a is turned on. As a result, the static electricity accumulated on one of the broom pads 260 can be conducted through the first-off component, the semiconductor layer 286a, to the adjacent daughter-in-law line 22(). Therefore, static electricity does not locally accumulate on the surface of the squeegee 26, and electrostatic breakdown in the vicinity of the scanning pad 260 can be avoided. In addition, it is worth noting that the source/deuterium in the first switching element 280a may be non-aligned or symmetrically disposed. Please refer to Fig. 3 'In the implementation of the 'transmission' of the first switching element · a miscellaneous / 汲 购 # 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如 例如The pole 288a has a good ability to collect static electricity and can improve the charge surface effect between the source/drain and the floating gate 282a. In more detail, the length of the source (or the pole) of the first-switching member 28Ga is U, and the length of the other-side drain (or source) is 'L2' and the length of L2 is greater than The length of L1. Since L2 is long, the drain with L2 length will have a larger space to collect static electricity, thus making the drain between the drain and its lower gate 282a more. (4) The charge is light 15 -I27^fidoc /y combined effect. As a result, when static electricity is accumulated, the first switching element 280a will be more easily turned on, and the static electricity will be transferred from one side of the drain having the length L2 to one side of the source having the length of L1. In addition, please continue to refer to FIG. 3. When two first switching elements 28a, 28a are disposed between two adjacent scanning pads 26A, the other first switch τ 280a' is preferably Asymmetric settings are also used. In particular, the source/drain 288a disposed above the floating gate 282a of the first switching element 280a at this time has a length opposite to that described above. That is to say, as shown in FIG. 3, another first-switching element 28〇a, one of its source (or no-pole) has a length L3 and the other has a drain (or source). The length is L4' and the length of L3 is greater than the length of L4. As a result, static electricity can be conducted from one side of the source (or drain) having a length of L3 to one side of the drain (or source) having a length of L4. In summary, when two parallel switching elements 28〇a, 28〇a are disposed between the scanning pads, and the source/drain 288a is asymmetrically disposed, except for the first switching element. The opening of 28〇a, 28, for example can be faster, and the direction of conduction of static electricity can also be performed by means of two-way conducting. 4 is an enlarged plan view of the scanning pad of FIG. 2 in a region of 3, FIG. 4A is a cross-sectional view taken along line CC of FIG. 4, and FIG. 4B is a cross-sectional view taken along line DD of FIG. A schematic view of the line. - Referring collectively to Figures 4 and 4A, in one embodiment of the invention, ^ each of the second switching elements 280b includes a floating gate 282b, a gate insulating layer 284, a semiconductor layer 286b, and a source/drain 288b. The floating gate 282b is disposed on the substrate 210. The gate insulating layer 284 covers the floating gate 282b. The half 16 I2Hy conductor layer 286b is disposed on the tearing of the insulating layer above the floating gate 282b. The source/drain 288b is disposed on the semiconductor layer 286b, wherein the source/drain 288b is electrically connected to the data pads 27 on both sides thereof. Similarly, in the fabrication of the above components, the process used can be a five-mask process, a four-mask process, or any known halogen array process. ^ Five mask process as an example, and please refer to FIG. 4, FIG. 4A and FIG. 4B at the same time, the floating gate 28 of the second switching element 28〇b is made by the first mask process (Metal 1) It is directly fabricated on the substrate 21〇. Then, a closed insulating layer is further formed on the substrate 210 to cover the outer gate 282b. Next, a semiconductor layer 28 is formed on the floating interpole 2 by a second mask process. Further, the third mask process is used to fabricate the data line 230, the data pad 270, and the source/drain metal layer (Metal 2), which is a homo-layer metal layer. Then, on the substrate 2i, the surface is covered with the layer, and then the opening 〇c is defined by the fourth mask process, that is, the gate insulating layer 2 and the protection 2 300 are disposed above the poor solder pad 27〇. Make an opening 3〇〇c and expose the information to Tan. A fifth photomask process is then applied to the poor solder fillet 270 and the data line 230 to form a conductive layer 31G (e.g., an oxide layer, ίτ〇). It is worth noting that the source/dot 2' tan pad shown in Figure 4, Figure 4 and Figure 4β is the same metal layer, so the source/drain and the pad 270 are electrically connected to each other. of. = In particular, 'When one of the data pads shown in Figure 4 is accumulated, this static electricity can be transferred from the (four) pad (10) to the source/drain 2 in the second sweat 280b. Then, the source /Coupling 1279920 17320twf.doc / y and the floating gate 282b can generate charge coupling effect, and the second switching element 28 〇 b is turned on. As a result, the static electricity accumulated on one of the data pads 27 can be conducted to the adjacent data line 23 through the semiconductor layer 286b of the second switching element 280b, so that static electricity does not accumulate in The data pad 270 is placed to avoid electrostatic damage in the vicinity of the data pad 270. Further, the source/drain 288b in the second switching element 280b may be disposed asymmetrically or symmetrically. The purpose, method, and effect of this setting have been described in the above description of the first switching element and will not be described in detail herein. In short, #=the second switching element 28Gb is disposed between the data pads 27c), and the source/poleless lion is asymmetrically arranged, except that the opening of the first switching element 280b can be faster, the conduction direction of the static electricity It can also be carried out by means of two-way circulation. In summary, the arrangement of the first switching element and the second switching element can be formed by the five masks (4) so that no additional step is required. In addition, the first switch tree and the second switch element are respectively disposed between two adjacent smatter pads and two adjacent f pads to accumulate static electricity on the pad or the data pad. The charge coupling effect occurring on the member and the 'or second switching element=, and the switching element and/or the second switching element are turned on. In this way, the reduction of electricity is excessively accumulated on the local broom pads and the data pads, thereby reducing electrostatic breakdown. The crystal array substrate is applied to a liquid crystal display 'μ has a better static protection effect · crystal difficulty = 4' will be obtained with 18 I27^m〇c/y. FIG. 5 illustrates a liquid crystal display according to a preferred embodiment of the present invention. Schematic diagram of the panel. This liquid crystal display panel 400 includes a color filter substrate 410, a thin film transistor array substrate 420, and a liquid crystal layer 430. The thin film transistor array substrate 420 is, for example, a thin film transistor array substrate 200' as shown in FIG. 2, and the liquid crystal layer 430 is disposed between the color filter substrate 41A and the thin film transistor array substrate 420. A common electrode is disposed on the color filter substrate 410 (c〇mm〇n

Electrode) (not shown) and a color filter array layer (not shown), between the common electrode and the thin film transistor substrate 42 (not shown) An electric field is formed to rotate the liquid crystal molecules between the color filter substrate 410 and the thin film transistor array substrate 42, thereby changing the intensity of the human light. In addition, the color light-emitting array layer enables the liquid crystal display panel to be fully colored. Moreover, since the thin film transistor array substrate 2 as shown in Fig. 2 can be used, the liquid crystal display panel 400 of the present invention will have good electrostatic protection capability. '

In summary, the thin film display panel of the present invention has the following advantages: a crystal array substrate and a liquid crystal display

The two components are respectively disposed between the adjacent two broom pads and the adjacent first switch element and the second switch element, so that Γ 1 accumulates in the sweeping pad or the data pad, The first -PH and / or second switching element will be turned on. In this way, static: Second, the line between the seedlings or adjacent data lines, and eliminate the static damage caused by the accumulation of most areas. "s" bureau (7) in a limited space, the first - switching element and the second switching element 19

*1279920 17320twf.doc/y The source/drain is set asymmetrically, so when the pad or the data pad is on, the U-off component and == are turned on at a faster speed, so that the static conduction is Adjacent sweeping cat line or data line. (3) The use of two parallel-connected first switching elements or two parallel-connected second switching elements S will allow the conduction direction of the static electricity to flow in both directions. (4) The first switching element and the second switching element can be fabricated by a conventional five-mask process, and therefore, no additional process steps are required. (5) When a thin film transistor array substrate having electrostatic protection capability is applied to a liquid crystal display panel, electrostatic breakdown caused by static electricity accumulation can be improved, and the liquid crystal display panel has good operational performance. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional thin film transistor array substrate. 2 is a schematic view of a thin film transistor array substrate in accordance with a preferred embodiment of the present invention. 3 is an enlarged plan view showing the scanning pad of FIG. 2 in the area A. 3A is a schematic cross-sectional view taken along line A-A of FIG. 3. 3B is a cross-sectional view taken along line B-B of FIG. 3. 20 127 doc/y Figure 4 shows an enlarged plan view of the scanning pad of Figure 2 in the B region. 4A is a cross-sectional view taken along line C-C' of FIG. 4. 4B is a cross-sectional view taken along line D-D' of FIG. 4. FIG. 5 is a schematic diagram of a liquid crystal display panel according to a preferred embodiment of the present invention. [Description of main component symbols] 100, 200: thin film transistor array substrate • 110, 210: substrate 112, 212: display area 114, 214: peripheral line area 120, 220: scan line 130, 230: data line 140, 240 : halogen region 150, 250: halogen unit 152, 252: thin film transistor φ 154, 254 · 昼 electrode 160, 260 · scan pad 170, 270: data pad 192, 292: internal static protection Rings 194, 294: external static protection rings 280a, 280a': first switching element < 280b: second switching element ^ 282a, 282b · floating gate 21 1279920 17320twf.doc / y 284: gate insulating layer 286a, 286b: semiconductor layers 288a, 288b: source/drain electrodes 300a, 300b, 300c: opening 310: conductive layer 400. liquid crystal display panel 410: color filter substrate 420: thin film transistor array substrate 430: liquid crystal layer A, B : Area A-A', BB, CC, DD, · · Section line U, L2, L3, L4 · · Contact length

twenty two

Claims (1)

127 views _ 10, the scope of application for patents: h a thin film transistor array substrate, including · has a display area and a peripheral line area; eve number of lines and a number of data lines, with the broom line and These data lines are divided into: 'the prime area; ', ', 'members are not divided into a number of most of the pixel units, respectively, configured in these The scanning lines and the data lines are provided by: the driving::--the plurality of scanning pads are arranged at the periphery, and the soldering pads are electrically connected to the scanning lines of the sweeping cat lines. And scanning the plurality of data soldering holes, the material soldering pads disposed in the peripheral circuit area are electrically connected to the data lines; and the second switching element is disposed in the peripheral circuit area Between the aiming pads, at least one of the two switching elements will be arranged with the scanning materials on both sides of the welding pad = A plurality of second switching elements are disposed in the peripheral circuit region, and: phase: 2 λ data pads are disposed with at least one second switching element, and each of the switching elements is disposed on both sides thereof These materials are electrically connected. 2. The thin film transistor array substrate of claim 2, wherein two first switching elements are disposed between adjacent ones of the scanning pads. 3. The thin film transistor array substrate according to claim 2, wherein the two first switching elements are disposed in parallel. 4. The thin film transistor array substrate according to claim 1, wherein two second switching elements are disposed between adjacent data pads. 5. The thin film transistor array substrate of claim 4, wherein the two second switching elements are disposed in parallel. 6. The thin film transistor array substrate of claim 1, wherein each of the first switching elements comprises: B - a floating gate disposed on the substrate; a gate insulating layer covering the floating gate a semiconductor layer disposed on the gate insulating layer above the floating gate; and a source/drain disposed on the semiconductor layer, wherein the source/drain is disposed on both sides thereof The sweeping cat pads are electrically connected. 7. The thin film transistor array substrate of claim 6, wherein the source/drain is asymmetrically disposed. 8. The thin film transistor array substrate of claim 6, wherein the source/drain electrodes are symmetrically disposed. 9. The thin film transistor array substrate of claim 1, wherein each of the second switching elements comprises: a floating gate disposed on the substrate, a gate insulating layer covering the floating gate a semiconductor layer disposed on the gate insulating layer above the floating gate; and 24 1279920 17320 twf.doc/y a source/:: and a pole disposed on the semiconductor layer, wherein the source/汲: The pole will be electrically connected to the data pads on both sides of the pole. The thin film transistor array substrate of claim 9, wherein the source/drain is asymmetrically disposed. U. The thin film transistor array substrate of claim 9, wherein the source/drain is symmetrically disposed. 12. The thin film transistor array substrate according to claim 1, wherein each of the pixel units comprises a thin film transistor disposed in one of the halogen regions; and the a-electrode is disposed on In one of the pixel regions, and electrically connected to the thin film transistor. 13. The thin film transistor array base according to claim 1 further includes a plurality of internal electrostatic protection rings (inner guards, placed in the peripheral circuit area of the 4, and located in the scanning pads and The display area ft is located between the data pads and the display area, and the internal static 甩 甩 濩 is electrically connected to the scan lines and the data lines. The thin film transistor array of the above 1 includes a plurality of external electrostatic protection rings (outguardring) in the two peripheral circuit regions, and is located on the outer surface of the scanning pad and the outer edge of the substrate and the outer edge of the substrate. A pair of outer side garments are electrically connected to the scan lines and the data lines. • A liquid crystal display panel, including: a color filter substrate; a diaphragm film array substrate, which is applied as Patented at item 25; and a liquid crystal layer disposed between the column substrates. The color filter, the optical substrate, and the _ transistor array