JP2007123793A - Thin film transistor array substrate and liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a TFT substrate which is suitable for reducing damage due to an electrostatic charge. <P>SOLUTION: A thin film transistor array substrate includes a substrate, a plurality of scanning lines and data lines, a plurality of pixel units, a plurality of scanning bonding pads and a plurality of data bonding pads, and a plurality of first and second switching elements. The scanning lines and data lines which divide a display area into a plurality of pixel areas are located on the substrate. The scanning bonding pads are electrically connected to the scanning lines. The data bonding pads are electrically connected to the data lines. The first and second switching elements are located on peripheral circuit regions. At least one of the first switching elements is located between two adjacent scanning bonding pads, and is electrically connected thereto. At least one of the second switching elements is located between two adjacent data bonding pads, and is electrically connected thereto. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates generally to an element array substrate and a display panel, and more specifically to a thin film transistor (TFT) array substrate and a liquid crystal display (LCD) panel having antistatic performance.

  With the rapid progress of electro-optic technology and semiconductor manufacturing technology in recent years, the development of flat display panels has progressed rapidly. Among flat display panels, the thin film transistor liquid crystal display panel (TFT-LCD) type has become mainstream due to low voltage operation, high speed operation, light weight and reduced space requirements.

  The thin film transistor LCD mainly includes an LCD panel and a backlight module, and the LCD panel includes a color filter (C / F), a thin film transistor array substrate (TFT array substrate), and a liquid crystal layer disposed between the filter and the substrate. The backlight module serves to provide a planar light source necessary for the LCD panel to display an image.

  FIG. 1 illustrates a substrate 110, a plurality of scanning lines 120, a plurality of data lines 130, a plurality of pixel units 150, a plurality of scanning bonding pads 160, a plurality of data bonding pads 170, a plurality of inner antistatic protective rings 192, and a plurality of 1 shows a conventional TFT array substrate 100 with an outer antistatic protective ring 194 of FIG.

  The substrate 110 includes a display area 112 and a peripheral circuit area 114. The scanning lines 120 and the data lines 130 are disposed on the substrate 110, and the scanning lines 120 and the data lines 130 divide the display area 112 into a plurality of pixel areas 140. Each pixel unit 150 is disposed in one of the pixel regions 140 and is driven by the scanning line 120 and the data line 130. The pixel unit 150 includes a TFT 152 and a pixel electrode 154.

  In FIG. 1, the scan bonding pad 160 is disposed in the peripheral circuit region 114 and is electrically connected to the scan line 120. The data bonding pad 170 is disposed in the peripheral circuit region 114 and is electrically connected to the data line 130. The inner antistatic protective ring 192 is similarly disposed in the peripheral circuit region 114 between the scanning bonding pad 160 and the display region 112 and between the data bonding pad 170 and the display region 112. The inner antistatic protective ring 192 is electrically connected to the scanning line 120 and the data line 130 and includes an active switch element (for example, a TFT or a diode), and the scanning line 120 and the data line 130 surrounding the active switch element. This is a charge protection circuit. Further, the outer antistatic protective ring 194 is disposed in the peripheral circuit region 114 and is located between the scanning bonding pad 160 and the outside of the substrate 110 and between the data bonding pad 170 and the outside of the substrate 110. Similarly, the outer antistatic protection ring 194 is electrically connected to the scan line 120 and the data line 130, and is composed of an active switch element (eg, TFT or diode) and a scan line and a data line surrounding the active switch element. It is a protection circuit.

  The TFT substrate 100 tends to accumulate static charges due to external factors such as transportation during manufacturing of the TFT substrate or environmental changes. Therefore, if the static charge is accumulated to a certain level, the circuit disposed on the TFT substrate 100 and the TFT 152 may be damaged due to the static charge. Accordingly, the inner anti-static protective ring 192 and the outer anti-static protective ring 194 allow the static charge to be transferred to the TFT so as to avoid locally accumulated static charges from damaging the circuit in the display area 112 or the pixel unit 150. Used to prevent leakage to the entire substrate 100.

  Specifically, the inner antistatic protective ring 192 and the outer antistatic protective ring 194 are connected to the scanning line 120 and the data line 130 via an active switch element (not shown). Therefore, when the electrostatic charge on the scanning line 120, the data line 130, or the TFT 152 is overloaded, the active switch element is turned on to dissipate the electrostatic charge to the inner antistatic protective ring 192 and / or the outer antistatic protective ring 194. The antistatic function is executed.

  However, in the design of the inner antistatic protective ring and the outer antistatic protective ring 194, the static charge damage is caused particularly in the area of the scanning bonding pad 160 and the data bonding pad 170 because of the large area and the ease of electrostatic charge accumulation. It can still happen. Therefore, when the static charge cannot be dissipated, damage to the circuit disposed on the TFT substrate 100 and the TFT 152 due to the static charge occurs.

  Therefore, the present invention is directed to providing a TFT substrate suitable for further reducing damage caused by electrostatic charges by dissipating a large amount of electrostatic charges accumulated in the TFT substrate.

  Therefore, the present invention is directed to an LCD panel using the above-described TFT substrate so that the LCD panel can have an antistatic protective performance.

  Based on the above object or other objects, the present invention includes a substrate, a plurality of scanning lines and data lines, a plurality of pixel units, a plurality of scanning bonding pads and data bonding pads, and a plurality of first and second switching elements. A TFT array substrate is provided. The substrate includes a display area and a peripheral circuit area. On the substrate, scanning lines and data lines for dividing the display area into a plurality of pixel areas are arranged. Each pixel unit is disposed in one of the pixel regions and is driven by a scanning line and a data line. The scanning bonding pad is disposed in the peripheral circuit region and is electrically connected to the scanning line. The data bonding pad is disposed in the peripheral circuit region and is electrically connected to the data line. The first switching element is disposed in the peripheral circuit region. At least one of the first switching elements is disposed between and electrically connected to two adjacent scan bonding pads. The second switching element is disposed in the peripheral circuit region. At least one of the second switching elements is disposed between and electrically connected to two adjacent data bonding pads.

  In one embodiment of the present invention, two first switching elements connected in parallel are disposed between two adjacent scanning bond pads.

  In one embodiment of the present invention, two second switching elements connected in parallel are disposed between two adjacent scanning bond pads.

  In one embodiment of the present invention, each of the first switching elements includes a floating gate, a gate insulating layer, a semiconductor layer, a source, and a drain. The floating gate is disposed on the substrate and covered with a gate insulating layer. The semiconductor layer is disposed on a gate insulating layer on the floating gate. The source and drain are disposed on the semiconductor layer and electrically connected to scan bonding pads disposed on the two side surfaces thereof. Further, the source and the drain are arranged asymmetrically or symmetrically.

  In one embodiment of the present invention, each of the second switching elements includes a floating gate, a gate insulating layer, a semiconductor layer, a source, and a drain. The floating gate is disposed on the substrate and covered with a gate insulating layer. The semiconductor layer is disposed on a gate insulating layer on the floating gate. The source and drain are disposed on the semiconductor layer and electrically connected to data bonding pads disposed on their two sides (source and drain). Further, the source and the drain are arranged asymmetrically or symmetrically.

  In one embodiment of the present invention, each of the pixel units includes a TFT and a pixel electrode. The TFT is disposed in one of the pixel areas. The pixel electrode is disposed in one of the pixel regions and is electrically connected to the TFT.

  In one embodiment of the present invention, the TFT array substrate further includes a plurality of inner protection rings disposed in the peripheral circuit region and positioned between the scanning bonding pad and the display region and between the data bonding pad and the display region. . The inner guard ring is electrically connected to the scan line and the data line.

  In one embodiment of the present invention, the TFT array substrate is disposed in the peripheral circuit region, and includes a plurality of outer protection rings positioned between the scanning bonding pad and the outside of the substrate and between the data bonding pad and the outside of the substrate. Further prepare. The outer protection ring is electrically connected to the scan line and the data line.

  In order to achieve these and other advantages, in accordance with the objectives of the present invention, as embodied and broadly described herein, the present invention provides a liquid crystal display comprising a color filter substrate, a TFT array substrate, and a liquid crystal layer. Provide a panel. The TFT array substrate may be, for example, the TFT array substrate, and the liquid crystal layer is disposed between the color filter substrate and the TFT array substrate.

  The present invention utilizes first and second switching elements disposed between two adjacent scan bond pads and between two adjacent data bond pads, respectively. When a large amount of electrostatic charge is accumulated on the scan bonding pad or the data bonding pad, the first and second switching elements are turned on by the accumulated electrostatic charge so that the first switching element and the second switching element are switched on. The charge coupling effect occurs on the switching elements. Accordingly, the accumulated electrostatic charge moves between adjacent scanning bonding pads or adjacent data bonding pads, thereby reducing damage to the TFT array substrate caused by the accumulated electrostatic charge.

  The invention will now be described in detail, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

  FIG. 2 shows a TFT array substrate according to an embodiment of the present invention. The TFT array substrate 200 includes a substrate 210, a plurality of scanning lines 220 and data lines 230, a plurality of pixel units 250, a plurality of scanning bonding pads 260 and a data bonding pad 270, a plurality of first switching elements 280a and a second switching. An element 280b is provided.

  The substrate 210 has a display area 212 and a peripheral circuit area 214. Scan lines 220 and data lines 230 that divide the display area 212 into a plurality of pixel areas 240 are disposed on the substrate 210. Each pixel unit 250 is disposed in one of the pixel regions 240 and is driven by the scanning line 220 and the data line 230. The scan bonding pad 260 is disposed in the peripheral circuit region 214 and is electrically connected to the scan line 220. The data bonding pad 270 is disposed in the peripheral circuit region 214 and is electrically connected to the data line 230. The first switching element 280a and the second switching element 280b are disposed in the peripheral circuit region 214. At least one of the first switching elements 280a (two second switching elements are shown in FIG. 2) is disposed between and electrically connected to two adjacent scan bonding pads 260. At least one of the second switching elements 280b (two second switching elements are shown in FIG. 2) is disposed between and electrically connected to two adjacent data bonding pads 270.

  FIG. 2 is an embodiment of the present invention. Each of the pixel units includes a TFT 252 and a pixel electrode 254. The TFT 252 is disposed in one of the pixel regions 240. The pixel electrode 254 is disposed in one of the pixel regions 240 and is electrically connected to the TFT 252.

  As shown in FIG. 2, the TFT array substrate 200 includes a plurality of TFTs arranged between the scanning bonding pad 260 and the display region 212 and between the data bonding pad 270 and the display region 212 in the peripheral circuit region 214, for example. An inner protective ring 292 is further provided. The inner protection ring 292 is electrically connected to the scan line 220 and the data line 230. The TFT array substrate 200 further includes a plurality of outer protective rings 294 disposed between the scanning bonding pad 260 and the outside of the substrate 210 and between the data bonding pad 270 and the outside of the substrate 210 in the peripheral circuit region 214, for example. The outer protection ring 294 is electrically connected to the scan line 220 and the data line 230.

  Specifically, the inner antistatic protective ring 292 or the outer antistatic protective ring 294 is connected to the scanning line 220 and the data line 230 via an active switch element (not shown). Therefore, when the electrostatic charge on the scanning line 220, the data line 230, or the TFT 252 is overloaded, the active switch element is switched on to dissipate the electrostatic charge to the inner antistatic protective ring 292 and / or the outer antistatic protective ring 294. To achieve an antistatic effect. However, a large amount of static charge is still accumulated in the areas of the scan bonding pad 260 and the data bonding pad 270. Therefore, in the present invention, the first switching element 280a and the second switching element 280b are disposed between two adjacent scanning bonding pads 260 and two adjacent data bonding pads 270, respectively. In one embodiment of the present invention, two first switching elements 280a connected in parallel are disposed between two adjacent scanning bonding pads 260. In one embodiment of the present invention, two second switching elements 280b connected in parallel are disposed between two adjacent data bonding pads 270, so that electrostatic charges can be discharged by bidirectional conduction.

  FIG. 3 is an enlarged top view of the scanning bonding pad disposed at the position A shown in FIG. 3A is a cross-sectional view taken along line A-A ′ of FIG. 3, and FIG. 3B is a cross-sectional view taken along line B-B ′ of FIG. 3.

  3 and 3A of one embodiment of the present invention, each of the first switching elements 280a includes a floating gate 282a, a gate insulating layer 284, a semiconductor layer 286a, and a source and drain 288a. The floating gate 282a is disposed over the substrate 210, and the gate insulating layer 284 covers the floating gate 282a. The semiconductor layer 286a is disposed on the gate insulating layer 284 over the floating gate 282a. The source and drain 288a are disposed on the semiconductor layer 286a and are electrically connected to the scanning bonding pads 260 disposed on both sides of the source and drain.

  In a conventional process for forming a pixel array, conductor lines (such as scan lines and data lines), TFTs, and pixel electrodes are formed on a substrate 210. The conventional process for forming the pixel array may be a five mask process, a four mask process, or any known process for forming a pixel array. 3, 3A and 3B show a three-digit five-mask process. In FIG. 3, the scanning line 220, the scanning bonding pad 260, and the floating gate 282a of the first switching element 280a are simultaneously formed on the substrate 210 (metal 1 mask) using a five mask process. Next, a gate insulating layer 284 is formed over the substrate 210 so as to cover the scanning lines 220, the scanning bonding pads 260, and the floating gate 282a. A semiconductor layer 286a is then formed on the floating gate 282a by applying a second mask process. Thereafter, source and drain 288a are formed by plating a metal layer in a third mask process (metal 2). Next, the protective layer 300 is formed over the substrate 210 and a fourth mask process is used to define the first opening 300a and the second opening 300b. That is, a first opening 300 a that exposes the source and drain 288 a is formed on the protective layer 300 that covers the scanning line 220, and a second opening 300 b that exposes the scanning bonding pad 260 is a protection that covers the scanning bonding pad 260. A layer 300 and a gate insulating layer 284 are formed. Next, a conductor layer 310 (ITO or the like) is formed using the fifth mask so as to cover the scanning line 220 and the scanning bonding pad 260. 3, 3A, and 3B, it is noted that the source and drain 288a and the scanning bonding pad 260 can be electrically connected through the first opening 300a and the second opening 300b by the conductor layer 310. I want to be.

  That is, in FIG. 3, when a large amount of electrostatic charge is accumulated in one of the scanning bonding pads 260, the electrostatic charge can be transmitted from the scanning bonding pad 260 to the source and drain 288a of the first switching element 280a. . Then, a charge coupling effect is generated between the source and drain 288a and the floating gate 282a, so that the first switching element 280a is turned on. Accordingly, the electrostatic charge accumulated on the scan bonding pad 260 can be transmitted to the adjacent scan line 260 through the semiconductor layer 286a of the first switching element 280a. Therefore, the electrostatic charge is not accumulated on the scanning bonding pad 260, and the adjacent region of the scanning bonding pad 260 can be prevented from being damaged.

  Note also that the source and drain 288a of the first switching element 280a can be arranged asymmetrically or symmetrically. In FIG. 3, according to one embodiment of the present invention, the source and drain 288a of the first switching element 280a is coupled to the charge and drain effect between the source and drain 288a and the floating gate 282a in a limited space. For example, it is arranged asymmetrically so as to have higher electrostatic charge accumulation performance. Specifically, the length of the source (or drain) of the first switching element 280a is L1, the length of the drain (source) is L2, and L2 is longer than L1. As L2 becomes longer, the drain having the length L2 has a larger space for accumulating static charges so that a charge coupling effect can easily occur between the drain 288a and the floating gate 282a. As a result, when the electrostatic charge is accumulated, the first switching element 280a is more easily turned on, and the electrostatic charge can be transmitted from the drain having the length L2 to the source having the length L1.

  Also, when the two first switching elements 280a and 280a ′ are disposed between two adjacent scanning bonding pads 260, the source and drain 288a disposed on the floating gate 282a of the first switching element 280a ′. Especially when the length is contrary to the length of the case, the first switching element 280a ′ is preferably arranged asymmetrically. That is, the first switching element 280a ′ in FIG. 3 has a source (or drain) having a length L3, the first switching element has a drain (or source) having a length L4, and L3 is more than L4. long. As a result, the electrostatic charge moves from the drain of length L3 to the source of length L4. In summary, when two first switching elements 280a and 280a ′ connected in parallel are placed between two adjacent scan bonding pads, and the source and drain 288a are placed asymmetrically, the first switching When the device (280a, 280a ′) is quickly turned on, the transfer of electrostatic charge is bi-directional.

  FIG. 4 is an enlarged top view of the scanning bonding pad disposed at the position B shown in FIG. 4A is a cross-sectional view taken along line C-C ′ of FIG. 4, and FIG. 4B is a cross-sectional view taken along line D-D ′ of FIG. 4.

  4 and 4A, each of the second switching elements 280b includes a floating gate 282b, a gate insulating layer 284, a semiconductor layer 286b, and a source and drain 288b, according to one embodiment of the invention. The floating gate 282b is disposed over the substrate 210, and the gate insulating layer 284 covers the floating gate 282b. The semiconductor layer 286b is disposed on the gate insulating layer 284 over the floating gate 282b. The source and drain 288b are disposed on the semiconductor layer and are electrically connected to the data bonding pads 270 disposed on both side surfaces of the source and drain.

  Similarly, any known process for forming a five mask process, a four mask process, or a pixel array can be employed to manufacture the device. Take the 5 mask process as an example. 4, 4A and 4B, the floating gate 282b of the second switching element 280b is formed on the substrate 210 (metal 1 mask) using a five mask process. Next, a gate insulating layer 284 is formed over the substrate 210 so as to cover the floating gate 282b. A semiconductor layer 286b is then formed on the floating gate 282b by applying a second mask process. A metal layer formed by the scan line 220, the data bonding pad 270, and the source and drain 288a is simultaneously formed by patterning the same metal layer with a third mask (metal 2). Thereafter, the entire protective layer 300 is formed on the substrate 210, and the protective layer 300 is patterned using a fourth mask to form a third opening 300c for exposing the data bonding pad 270. . Next, a conductor layer 310 (such as ITO) is formed to cover the data lines 230 and the data bonding pads 270 using a fifth mask. It should be noted that in FIGS. 4, 4A and 4B, the source and drain 288b and the data bonding pad 270 are formed of the same metal layer so that they are electrically connected to each other.

  That is, as shown in FIG. 4, when a large amount of electrostatic charge is accumulated in one of the data bonding pads 270, the electrostatic charge is transferred from the data bonding pad 270 to the source and drain 288b of the second switching element 280b. Can be made. Then, a charge coupling effect is generated between the source and drain 288b and the floating gate 282b, so that the second switching element 280b is turned on. Accordingly, the electrostatic charge accumulated on the data bonding pad 270 can be transmitted to the adjacent data line 230 through the semiconductor layer 286b of the second switching element 280b. Therefore, the static charge is not accumulated on the data bonding pad 270, and the periphery of the data bonding pad 270 can be prevented from being damaged.

  Similarly, the source and drain 288b of the second switching element 280b can be disposed asymmetrically or symmetrically. Since the purpose, method, and effect of this asymmetrical or symmetrical arrangement have been described above, a description thereof is omitted here. In summary, two second switching elements 280b are placed between two adjacent data bonding pads 270, the source and drain 288b are placed asymmetrically, and the second switching element (280b ′) is quickly turned on. When switched, electrostatic charge can be transferred in both directions.

  In short, the placement of the first and second switching elements is accomplished using a five mask process so that no additional process is required. Also, when the first and second switching elements are respectively disposed between two adjacent scanning bonding pads and between two adjacent data bonding pads, electrostatic charge is transferred to the first switching element and / or the second switching element. By causing the charge coupling effect of the switching element, the first switching element and / or the second switching element is switched on. Thus, damage from static charges is reduced by reducing the likelihood that static charges will accumulate locally on the scan and data bonding pads. Further, the above-described TFT array substrate is mounted on the LCD panel to form an LCD panel having better antistatic protection performance.

  FIG. 5 shows an LCD panel according to a preferred embodiment of the present invention. The LCD panel 400 includes a color filter substrate 410, a TFT substrate 420, and a liquid crystal layer 430. The TFT substrate 420 may be, for example, the TFT substrate 200 shown in FIG. The liquid crystal layer 430 is disposed between the color filter substrate 410 and the TFT substrate 420.

  A common electrode (not shown) and a color filter array (not shown) are disposed on the color filter substrate 410. An electric field is generated between the common electrode and the pixel electrode (not shown) of the TFT array substrate 420 so that the liquid crystal molecules arranged between the color filter substrate 410 and the TFT array substrate 420 are rotated to change the intensity of incident light. Arise. In addition, the color filter substrate 410 completely colors the LCD panel 400. Since the present invention employs the TFT array substrate 200 shown in FIG. 2, the LCD panel 400 of the present invention has more excellent antistatic protection performance.

In summary, the TFT array substrate and the LCD panel of the present invention have the following advantages.
(1) When the first and second switching elements are disposed between two adjacent scanning bonding pads and between two adjacent data bonding pads, respectively, electrostatic charge is transferred to the first switching element and / or the second switching element. The first switching element and / or the second switching element is switched on by causing the charge coupling effect of the switching elements. Thus, damage from static charges is reduced by reducing the likelihood that static charges will accumulate locally on the scan and data bonding pads.
(2) In the limited space, when the sources and drains of the first and second switching elements are arranged asymmetrically, and electrostatic charges are accumulated on the scanning bonding pad or the data bonding pad, the first and second switching elements The switching element is quickly turned on, and the electrostatic charge can be moved to the neighboring scanning line or data line.
(3) The electrostatic charge can be transferred bidirectionally using two first switching elements connected in parallel or two second switching elements connected in parallel.
(4) The first and second switching elements are formed using a conventional 5-mask process without any additional process.
(5) The TFT array substrate having the antistatic protection performance is mounted on the LCD panel so that the LCD panel operates better because damage due to electrostatic charge is reduced.

  It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the above, the present invention includes modifications and variations of the present invention so long as they fall within the scope of the following claims and their equivalents.

  The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings, together with the description, illustrate embodiments of the invention and serve to explain the principles of the invention.

1 shows a conventional TFT array substrate. 1 shows a TFT array substrate according to an embodiment of the present invention. FIG. 3 is an enlarged top view of a scanning bonding pad disposed at a position A shown in FIG. 2. FIG. 4 is a cross-sectional view taken along line A-A ′ of FIG. 3. FIG. 4 is a cross-sectional view taken along line B-B ′ of FIG. 3. FIG. 3 is an enlarged top view of a scanning bonding pad disposed at a position B shown in FIG. 2. It is sectional drawing of the C-C 'line | wire of FIG. It is sectional drawing of the D-D 'line | wire of FIG. 1 shows an LCD panel according to an embodiment of the present invention.

Explanation of symbols

100 TFT array substrate 110 Substrate 112 Display region 114 Peripheral circuit region 120 Scan line 130 Data line 140 Pixel region 150 Pixel unit 154 Pixel electrode 160 Scan bonding pad 170 Data bonding pad 192 Inner antistatic protective ring 194 Outer antistatic protective ring 200 TFT Array substrate 210 Substrate 212 Display region 214 Peripheral circuit region 220 Scan line 230 Data line 240 Pixel region 250 Pixel unit 254 Pixel electrode 260 Scan bonding pad 270 Data bonding pad 280a First switching element 280b Second switching element 282a Floating gate 282b Floating gate 284 Gate insulating layer 286a Semiconductor layer 286b Semiconductor layer 288a Source and drain 288b Source and drain 292 inner antistatic protection ring 294 outwardly antistatic protection ring 300 protective layer 300a~300c opening 310 conductive layer 400 panel 410 color filter substrate 420 TFT array substrate 430 liquid crystal layer

Claims (15)

A substrate having a display area and a peripheral circuit area;
A plurality of scanning lines and data lines arranged on the substrate, which divides the display area into a plurality of pixel areas;
A plurality of pixel units each disposed in one of the pixel regions and driven by a scan line and a data line;
A plurality of scanning bonding pads disposed in the peripheral circuit region and electrically connected to the scanning lines;
A plurality of data bonding pads disposed in the peripheral circuit region and electrically connected to the data lines;
A plurality of first switching elements disposed in the peripheral circuit region, wherein at least one of the first switching elements is disposed between two adjacent scanning bonding pads and electrically connected to the two scanning bonding pads; A first switching element connected;
A plurality of second switching elements disposed in the peripheral circuit region, wherein at least one of the second switching elements is disposed between two adjacent data bonding pads and electrically connected to the two data bonding pads; A thin film transistor array substrate comprising a second switching element to be connected.   2. The thin film transistor array substrate of claim 1, wherein two first switching elements are disposed between two adjacent scan bonding pads.   The thin film transistor array substrate according to claim 2, wherein the two first switching elements are connected in parallel.   The thin film transistor array substrate of claim 1, wherein two second switching elements are disposed between two adjacent data bonding pads.   The thin film transistor array substrate according to claim 4, wherein two second switching elements are connected in parallel. Each first switching element is
A floating gate disposed on the substrate;
A gate insulating layer covering the floating gate;
A semiconductor layer disposed on a gate insulating layer covering the floating gate;
Comprising a source and a drain disposed on the semiconductor layer;
2. The thin film transistor array substrate of claim 1, wherein the source and drain are electrically connected to a scanning bonding pad disposed on two sides of the source and drain.   7. The thin film transistor array substrate according to claim 6, wherein the source and drain are arranged asymmetrically.   7. The thin film transistor array substrate according to claim 6, wherein the source and drain are arranged symmetrically. Each second switching element is
A floating gate disposed on the substrate;
A gate insulating layer covering the floating gate;
A semiconductor layer disposed on a gate insulating layer covering the floating gate;
Comprising a source and a drain disposed on the semiconductor layer;
2. The thin film transistor array substrate of claim 1, wherein the source and drain are electrically connected to a scanning bonding pad disposed on two sides of the source and drain.   The thin film transistor array substrate of claim 9, wherein the source and drain are asymmetrically arranged.   The thin film transistor array substrate of claim 9, wherein the source and drain are arranged symmetrically. A thin film transistor in which each pixel unit is disposed in one of the pixel regions;
The thin film transistor array substrate according to claim 1, further comprising a pixel electrode disposed in each pixel region and electrically connected to the thin film transistor.   2. The inner protection ring of claim 1, further comprising a plurality of inner protection rings disposed in the peripheral circuit region and electrically connected to scan lines and data lines between the scan bonding pad and the display region and between the data bonding pad and the display region. Thin film transistor array substrate.   A plurality of outer guard rings disposed in the peripheral circuit region and electrically connected to the scan lines and data lines between the scan bonding pads and the outside of the substrate and between the data bonding pads and the outside of the substrate; The thin film transistor array substrate according to claim 1. A color filter substrate;
A substrate having a display region and a peripheral circuit region, a plurality of scanning lines and data lines arranged on the substrate that divide the display region into a plurality of pixel regions, each arranged in one of the pixel regions and scanning A plurality of pixel units driven by lines and data lines, a plurality of scanning bonding pads arranged in the peripheral circuit region and electrically connected to the scanning lines, and arranged in the peripheral circuit region and electrically connected to the data lines A plurality of data bonding pads to be connected and at least one of the first switching elements are arranged between two adjacent scanning bonding pads and arranged in a peripheral circuit region electrically connected to the two scanning bonding pads A plurality of first switching elements and at least one of the second switching elements are two adjacent data bonding pads A thin film transistor array substrate including a plurality of second switching elements disposed in the peripheral circuit region and electrically connected to the two data bonding pads, and between the color filter substrate and the thin film transistor array substrate. A liquid crystal panel comprising a liquid crystal layer to be disposed.

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